From 392716a60844ccf051b7a3a23d07556c79057748 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 16:26:44 -0600 Subject: [PATCH] Updated global history branch predictcor with the gshare improvements. --- pipelined/src/ifu/bpred/bpred.sv | 21 ++----- .../src/ifu/bpred/speculativeglobalhistory.sv | 61 +++++++++++-------- 2 files changed, 42 insertions(+), 40 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index bdb489245..cccbe29f0 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -85,41 +85,37 @@ module bpred ( logic [3:0] WrongPredInstrClassD; -//************ new resolve issues logic BTBTargetWrongE; logic RASTargetWrongE; logic JumpOrTakenBranchE; - - logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; - // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor - twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor - globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); @@ -139,7 +135,6 @@ module bpred ( -----/\----- EXCLUDED -----/\----- */ end - // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. @@ -260,7 +255,6 @@ module bpred ( // branch class prediction wrong. assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; - // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); // If the prediction is wrong select the correct address. @@ -292,8 +286,5 @@ module bpred ( flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); - - - endmodule diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv index 47203dbdd..3ed9ba3e5 100644 --- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// globalHistoryPredictor.sv +// speculativeglobalhistory.sv // // Written: Shreya Sanghai // Email: ssanghai@hmc.edu @@ -28,7 +28,7 @@ `include "wally-config.vh" -module speculativeglobalhistory #(parameter k = 10) ( +module speculativeglobalhistory #(parameter int k = 10 ) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -36,7 +36,6 @@ module speculativeglobalhistory #(parameter k = 10) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE @@ -49,14 +48,14 @@ module speculativeglobalhistory #(parameter k = 10) ( logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:-1] GHRNextD, OldGHRD; - logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic GHRExtraF; + logic [k-1:0] GHRD, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k-1:0] GHRNextD; + logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -102,30 +101,42 @@ module speculativeglobalhistory #(parameter k = 10) ( satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; + // this version fails the regression test do to pessimistic x propagation. + // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : + // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : + // GHRF; - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - - assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; - flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - OldGHRD[k:0]; + always_comb begin + if(FlushD | DirPredictionWrongE) begin + GHRNextF = GHRNextD[k-1:0]; + end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; + else GHRNextF = GHRF; + end - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + + // use with out instruction class prediction + //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + // with instruction class prediction + assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : + WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left + GHRF[k-1:0]; + + flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + + assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed + FlushE ? GHRNextM : // branch is flushed + GHRD; + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - endmodule