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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Thomas Fleming 2021-05-04 01:14:13 -04:00
commit 39135f221e
2 changed files with 35 additions and 17 deletions
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32
wally-pipelined/testbench/testbench-imperas.sv
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@ -348,8 +348,8 @@ module testbench();
}; };
string tests64p[] = '{ string tests64p[] = '{
"rv64p/WALLY-MCAUSE", "4000", "rv64p/WALLY-MCAUSE", "3000",
"rv64p/WALLY-SCAUSE", "3000", "rv64p/WALLY-SCAUSE", "2000",
"rv64p/WALLY-MEPC", "5000", "rv64p/WALLY-MEPC", "5000",
"rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-SEPC", "4000",
"rv64p/WALLY-MTVAL", "6000", "rv64p/WALLY-MTVAL", "6000",
@ -363,18 +363,18 @@ module testbench();
}; };
string tests32p[] = '{ string tests32p[] = '{
// "rv32p/WALLY-MCAUSE", "4000", "rv32p/WALLY-MCAUSE", "3000",
// "rv32p/WALLY-SCAUSE", "3000", "rv32p/WALLY-SCAUSE", "2000",
// "rv32p/WALLY-MEPC", "5000", "rv32p/WALLY-MEPC", "5000",
// "rv32p/WALLY-SEPC", "4000", "rv32p/WALLY-SEPC", "4000",
// "rv32p/WALLY-MTVAL", "5000", "rv32p/WALLY-MTVAL", "5000",
// "rv32p/WALLY-STVAL", "4000", "rv32p/WALLY-STVAL", "4000",
// "rv32p/WALLY-MARCHID", "4000", "rv32p/WALLY-MARCHID", "4000",
// "rv32p/WALLY-MIMPID", "4000", "rv32p/WALLY-MIMPID", "4000",
// "rv32p/WALLY-MHARTID", "4000", "rv32p/WALLY-MHARTID", "4000",
// "rv32p/WALLY-MVENDORID", "4000" "rv32p/WALLY-MVENDORID", "4000",
// "rv32p/WALLY-MTVEC", "2000", "rv32p/WALLY-MTVEC", "2000",
// "rv32p/WALLY-STVEC", "2000" "rv32p/WALLY-STVEC", "2000"
}; };
string tests64periph[] = '{ string tests64periph[] = '{
@ -423,7 +423,7 @@ module testbench();
end end
//tests = {tests64a, tests}; //tests = {tests64a, tests};
//tests = tests64p; tests = tests64p;
end else begin // RV32 end else begin // RV32
// *** add the 32 bit bp tests // *** add the 32 bit bp tests
if (TESTSPERIPH) begin if (TESTSPERIPH) begin
@ -437,6 +437,8 @@ module testbench();
if (`A_SUPPORTED) tests = {tests, tests32a}; if (`A_SUPPORTED) tests = {tests, tests32a};
if (`MEM_VIRTMEM) tests = {tests, tests32mmu}; if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
end end
//tests = tests32p;
end end
end end

20
wally-pipelined/testgen/privileged/testgen-CAUSE.py
View File

@ -296,7 +296,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
author = "dottolia@hmc.edu" author = "dottolia@hmc.edu"
xlens = [32, 64] xlens = [32, 64]
testCount = 16; testCount = 8;
# setup # setup
# Change this seed to a different constant value for every test # Change this seed to a different constant value for every test
@ -336,7 +336,15 @@ for xlen in xlens:
# insert generic header # insert generic header
h = open("../testgen_header.S", "r") h = open("../testgen_header.S", "r")
for line in h: for line in h:
f.write(line) f.write(line.replace("RV_COMPLIANCE_RV64M", "RV_COMPLIANCE_RV" + str(xlen) + "M"))
# f.write(f"""
# #include "riscv_test_macros.h"
# #include "compliance_test.h"
# #include "compliance_io.h"
# 0000000080000000 <_start>:
# 80000000: 0480006f j 80000048 <reset_vector>
# """)
# We need to leave at least one bit in medeleg unset so that we have a way to get # We need to leave at least one bit in medeleg unset so that we have a way to get
# back to machine mode when the tests are complete (otherwise we'll only ever be able # back to machine mode when the tests are complete (otherwise we'll only ever be able
@ -383,6 +391,14 @@ for xlen in xlens:
lines = f""" lines = f"""
add x7, x6, x0 add x7, x6, x0
csrr x19, mtvec csrr x19, mtvec
slli a0,a0,0x1f
slli a0,a0,0x1e
slli a0,a0,0x1d
slli a0,a0,0x1c
slli a0,a0,0x1b
slli a0,a0,0x1a
slli a0,a0,0x19
""" """
# Not used — user mode traps are deprecated # Not used — user mode traps are deprecated