From 3909158619790be7400808b86825dbb55350025d Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Wed, 24 Mar 2021 13:51:25 -0400 Subject: [PATCH] re-organize privileged tests to be in rv64p to rv32p folders --- .../testbench/testbench-privileged.sv | 2 +- wally-pipelined/testgen/privileged/README.md | 15 ++ wally-pipelined/testgen/privileged/run.sh | 9 +- .../testgen/privileged/testgen-CAUSE.py | 49 +++--- .../testgen/privileged/testgen-RET.py | 157 ++++++++++++++++++ 5 files changed, 208 insertions(+), 24 deletions(-) create mode 100644 wally-pipelined/testgen/privileged/README.md create mode 100644 wally-pipelined/testgen/privileged/testgen-RET.py diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index 410dd62e1..999604480 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -40,7 +40,7 @@ module testbench(); logic [`XLEN-1:0] meminit; string tests[] = '{ - "privileged/WALLY-CAUSE-64", "0" + "rv64p/WALLY-CAUSE", "0" }; logic [`AHBW-1:0] HRDATAEXT; diff --git a/wally-pipelined/testgen/privileged/README.md b/wally-pipelined/testgen/privileged/README.md new file mode 100644 index 000000000..9220111f9 --- /dev/null +++ b/wally-pipelined/testgen/privileged/README.md @@ -0,0 +1,15 @@ +# Privileged Test Generators + +Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use + +```bash +sh run.sh NAME +``` + +For example, for `testgen-CAUSE.py`, we would run `sh run.sh CAUSE`. + +Provide -sim as the second argument to simulate the compiled tests using wally. + +```bash +sh run.sh NAME -sim +``` \ No newline at end of file diff --git a/wally-pipelined/testgen/privileged/run.sh b/wally-pipelined/testgen/privileged/run.sh index 13c7c2b0f..9d5ca4f4e 100644 --- a/wally-pipelined/testgen/privileged/run.sh +++ b/wally-pipelined/testgen/privileged/run.sh @@ -7,8 +7,11 @@ then python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" - cd ~/riscv-wally/imperas-riscv-tests - make privileged + if [[ "$2" != "-nosim" ]] + then + cd ~/riscv-wally/imperas-riscv-tests + make privileged + fi fi if [[ "$2" == "-sim" || "$2" == "-simonly" ]] @@ -18,5 +21,5 @@ then vsim -do wally-privileged.do -c fi -cd ~/riscv-wally +cd ~/riscv-wally/wally-pipelined printf "\n\n\n#####\nDone!\n#####\n\n" \ No newline at end of file diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 7cc9fa544..4bd649622 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -61,10 +61,16 @@ def writeVectors(storecmd): #lines = + + # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html + lines = f""" j _setup csrrs x31, mcause, x0 - ecall + csrrs x30, mepc, x0 + addi x30, x30, 0x100 + csrrw x0, mepc, x30 + mret _setup: li x2, 0x80000004 @@ -73,23 +79,25 @@ def writeVectors(storecmd): """ f.write(lines) - # User Software Interrupt - write(f""" - li x3, 0x8000000 - {storecmd} x2, 0(x3) - """, storecmd, True, 0, "u") + # # User Software Interrupt + # write(f""" + # li x3, 0x8000000 + # {storecmd} x2, 0(x3) + # """, storecmd, True, 0, "u") - # Supervisor Software Interrupt - write(f""" - li x3, 0x8000000 - {storecmd} x2, 0(x3) - """, storecmd, True, 0, "s") + # # A supervisor-level software interrupt is triggered on the current hart by writing 1 to its supervisor software interrupt-pending (SSIP) bit in the sip register. + # # page 58 of priv spec + # # Supervisor Software Interrupt + # write(f""" + # li x3, 0x8000000 + # {storecmd} x2, 0(x3) + # """, storecmd, True, 0, "s") - # Machine Software Interrupt - write(f""" - li x3, 0x8000000 - {storecmd} x2, 0(x3) - """, storecmd, True, 3) + # # Machine Software Interrupt + # write(f""" + # li x3, 0x8000000 + # {storecmd} x2, 0(x3) + # """, storecmd, True, 3) # User Timer Interrupt #write(f""" @@ -122,8 +130,9 @@ def writeVectors(storecmd): # Not possible in machine mode, because we can access all memory # Illegal Instruction + # . fill 1, 2, 0 outputs all 0s write(f""" - .data 00000000 + .fill 1, 2, 0 """, storecmd, False, 2) # Breakpoint @@ -212,7 +221,7 @@ def write(lines, storecmd, interrupt, code, mode = "m"): # 'Load page fault': (0, '13'), # 'Store/AMO page fault': (0, '15'), # } -author = "dottolia@hmc.edu" +author = "Domenico Ottolia (dottolia@hmc.edu)" xlens = [32, 64] numrand = 60; @@ -231,8 +240,8 @@ for xlen in xlens: storecmd = "sd" wordsize = 8 - imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/privileged/" - basename = "WALLY-CAUSE-" + str(xlen) + imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/""" + basename = "WALLY-CAUSE" fname = imperaspath + "src/" + basename + ".S" refname = imperaspath + "references/" + basename + ".reference_output" testnum = 0 diff --git a/wally-pipelined/testgen/privileged/testgen-RET.py b/wally-pipelined/testgen/privileged/testgen-RET.py new file mode 100644 index 000000000..8921cfb8e --- /dev/null +++ b/wally-pipelined/testgen/privileged/testgen-RET.py @@ -0,0 +1,157 @@ +#!/usr/bin/python3 +################################## +# testgen-CAUSE.py +# +# dottolia@hmc.edu 16 Mar 2021 +# +# Generate directed and random test vectors for RISC-V Design Validation. +################################## + +################################## +# libraries +################################## +from datetime import datetime +from random import randint +from random import seed +from enum import Enum +from random import getrandbits + +################################## +# functions +################################## + +# def computeExpected(a, b, test): +# if (test == "ADD"): +# return a + b +# elif (test == "SUB"): +# return a - b +# else: +# die("bad test name ", test) +# # exit(1) + +def randRegs(): + reg1 = randint(1,30) + reg2 = randint(1,30) + reg3 = randint(1,30) + if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): + return randRegs() + else: + return reg1, reg2, reg3 + +def writeVectors(storecmd): + global testnum + reg1, reg2, reg3 = randRegs() + + # t5 gets written with mtvec? + + # lines = f""" + + # li x{reg1}, 0 + # csrwi mtvec, 80002000 + # .data 00000000 + # j _done{testnum} + + # _trap{testnum}: + # csrrs x{reg1}, mcause, x0 + # ecall + + # _done{testnum}: + # add x0, x0, x0 + # """ + + #lines = + + + # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html + + lines = f""" + li x1, 100 + li x2, 200 + add x3, x1, x2 + add x6, x3, x3 + + """ + f.write(lines) + + expected = 600 + + if (xlen == 32): + line = formatrefstr.format(expected)+"\n" + else: + line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" + r.write(line) + +################################## +# main body +################################## + +author = "Domenico Ottolia (dottolia@hmc.edu)" +xlens = [32, 64] +numrand = 60; + +# setup +seed(0xC395D19B9173AD42) # make tests reproducible + +# generate files for each test +for xlen in xlens: + formatstrlen = str(int(xlen/4)) + formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x + if (xlen == 32): + storecmd = "sw" + wordsize = 4 + else: + storecmd = "sd" + wordsize = 8 + + imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/""" + basename = "WALLY-RET" + fname = imperaspath + "src/" + basename + ".S" + refname = imperaspath + "references/" + basename + ".reference_output" + testnum = 0 + + # print custom header part + f = open(fname, "w") + r = open(refname, "w") + line = "///////////////////////////////////////////\n" + f.write(line) + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) + + # insert generic header + # h = open("../testgen_header.S", "r") + # for line in h: + # f.write(line) + + # print directed and random test vectors + + h = open("../testgen_header.S", "r") + for line in h: + f.write(line) + + writeVectors(storecmd) + + h = open("../testgen_footer.S", "r") + for line in h: + f.write(line) + + # Finish + lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) + + + # print footer + # h = open("../testgen_footer.S", "r") + # for line in h: + # f.write(line) + + # Finish + # lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + # f.write(lines) + f.close() + r.close() +