Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e

sim/regression-wally

@@ -107,7 +107,7 @@ for test in tests32i:
   configs.append(tc)
 
 
-tests32e = ["wally32e"] 
+tests32e = ["arch32e"] 
 for test in tests32e:
   tc = TestCase(
         name=test,

testbench/testbench.sv

@@ -127,6 +127,7 @@ module testbench;
       endcase 
     end else begin // RV32
       case (TEST)
+        "arch32e":                                tests = arch32e; 
         "arch32i":                                tests = arch32i;
         "arch32priv":                             tests = arch32priv;
         "arch32c":      if (P.C_SUPPORTED) 
@@ -146,7 +147,6 @@ module testbench;
         "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
                         else                      tests = imperas32iNOc;
         "wally32i":                               tests = wally32i; 
-        "wally32e":                              tests = wally32e; 
         "wally32priv":                            tests = wally32priv;
         "wally32periph":                          tests = wally32periph;
         "embench":                                tests = embench;
@@ -321,6 +321,28 @@ module testbench;
   // Some memories are not reset, but should be zeros or set to some initial value for simulation
   ////////////////////////////////////////////////////////////////////////////////
   integer adrindex;
+  if (P.UNCORE_RAM_SUPPORTED)
+    always @(posedge clk) 
+      if (ResetMem)  // program memory is sometimes reset
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+
+  if (P.BPRED_SUPPORTED)
+    always @(posedge clk) 
+      if(reset) begin  // branch predictor must always be reset
+        for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      end
+
+  if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR))  // local history only
+    always @(posedge clk) 
+      if(reset)   // branch predictor must always be reset
+          for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+
+/*
   always @(posedge clk) begin
     if (ResetMem)  // program memory is sometimes reset
       if (P.UNCORE_RAM_SUPPORTED)
@@ -339,6 +361,7 @@ module testbench;
       end
     end
   end
+  */ 
 
   ////////////////////////////////////////////////////////////////////////////////
   // load memories with program image

testbench/tests.vh

@@ -1961,6 +1961,46 @@ string arch64zbs[] = '{
     "rv32i_m/I/src/xori-01.S"
   };
 
+  string arch32e[] = '{
+    `RISCVARCHTEST,
+    "rv32e_unratified/E/src/add-01.S",
+    "rv32e_unratified/E/src/addi-01.S",
+    "rv32e_unratified/E/src/and-01.S",
+    "rv32e_unratified/E/src/andi-01.S",
+    "rv32e_unratified/E/src/auipc-01.S",
+    "rv32e_unratified/E/src/bge-01.S",
+    "rv32e_unratified/E/src/bgeu-01.S",
+    "rv32e_unratified/E/src/blt-01.S",
+    "rv32e_unratified/E/src/bltu-01.S",
+    "rv32e_unratified/E/src/bne-01.S",
+    "rv32e_unratified/E/src/jal-01.S",
+    "rv32e_unratified/E/src/jalr-01.S",
+    "rv32e_unratified/E/src/lb-align-01.S",
+    "rv32e_unratified/E/src/lbu-align-01.S",
+    "rv32e_unratified/E/src/lh-align-01.S",
+    "rv32e_unratified/E/src/lhu-align-01.S",
+    "rv32e_unratified/E/src/lui-01.S",
+    "rv32e_unratified/E/src/lw-align-01.S",
+    "rv32e_unratified/E/src/or-01.S",
+    "rv32e_unratified/E/src/ori-01.S",
+    "rv32e_unratified/E/src/sb-align-01.S",
+    "rv32e_unratified/E/src/sh-align-01.S",
+    "rv32e_unratified/E/src/sll-01.S",
+    "rv32e_unratified/E/src/slli-01.S",
+    "rv32e_unratified/E/src/slt-01.S",
+    "rv32e_unratified/E/src/slti-01.S",
+    "rv32e_unratified/E/src/sltiu-01.S",
+    "rv32e_unratified/E/src/sltu-01.S",
+    "rv32e_unratified/E/src/sra-01.S",
+    "rv32e_unratified/E/src/srai-01.S",
+    "rv32e_unratified/E/src/srl-01.S",
+    "rv32e_unratified/E/src/srli-01.S",
+    "rv32e_unratified/E/src/sub-01.S",
+    "rv32e_unratified/E/src/sw-align-01.S",
+    "rv32e_unratified/E/src/xor-01.S",
+    "rv32e_unratified/E/src/xori-01.S"
+ };
+
  string wally64i[] = '{
     `WALLYTEST,
     "rv64i_m/I/src/WALLY-ADD.S",
@@ -2017,46 +2057,6 @@ string arch64zbs[] = '{
     "rv64i_m/privilege/src/WALLY-spi-01.S"
  };
 
- string wally32e[] = '{
-    `WALLYTEST,
-    "rv32i_m/I/src/E-add-01.S",
-    "rv32i_m/I/src/E-addi-01.S",
-    "rv32i_m/I/src/E-and-01.S",
-    "rv32i_m/I/src/E-andi-01.S",
-    "rv32i_m/I/src/E-auipc-01.S",
-    "rv32i_m/I/src/E-bge-01.S",
-    "rv32i_m/I/src/E-bgeu-01.S",
-    "rv32i_m/I/src/E-blt-01.S",
-    "rv32i_m/I/src/E-bltu-01.S",
-    "rv32i_m/I/src/E-bne-01.S",
-    "rv32i_m/I/src/E-jal-01.S",
-    "rv32i_m/I/src/E-jalr-01.S",
-    "rv32i_m/I/src/E-lb-align-01.S",
-    "rv32i_m/I/src/E-lbu-align-01.S",
-    "rv32i_m/I/src/E-lh-align-01.S",
-    "rv32i_m/I/src/E-lhu-align-01.S",
-    "rv32i_m/I/src/E-lui-01.S",
-    "rv32i_m/I/src/E-lw-align-01.S",
-    "rv32i_m/I/src/E-or-01.S",
-    "rv32i_m/I/src/E-ori-01.S",
-    "rv32i_m/I/src/E-sb-align-01.S",
-    "rv32i_m/I/src/E-sh-align-01.S",
-    "rv32i_m/I/src/E-sll-01.S",
-    "rv32i_m/I/src/E-slli-01.S",
-    "rv32i_m/I/src/E-slt-01.S",
-    "rv32i_m/I/src/E-slti-01.S",
-    "rv32i_m/I/src/E-sltiu-01.S",
-    "rv32i_m/I/src/E-sltu-01.S",
-    "rv32i_m/I/src/E-sra-01.S",
-    "rv32i_m/I/src/E-srai-01.S",
-    "rv32i_m/I/src/E-srl-01.S",
-    "rv32i_m/I/src/E-srli-01.S",
-    "rv32i_m/I/src/E-sub-01.S",
-    "rv32i_m/I/src/E-sw-align-01.S",
-    "rv32i_m/I/src/E-xor-01.S",
-    "rv32i_m/I/src/E-xori-01.S"
- };
-
  string wally32i[] = '{
     `WALLYTEST,
     "rv32i_m/I/src/WALLY-ADD.S",
@@ -2102,7 +2102,6 @@ string arch64zbs[] = '{
     "rv32i_m/privilege/src/WALLY-plic-01.S",
     "rv32i_m/privilege/src/WALLY-plic-s-01.S",
     "rv32i_m/privilege/src/WALLY-spi-01.S"
-
  };
 
  string wally32periph[] = '{

tests/riscof/Makefile

@@ -8,7 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test
 current_dir = $(shell pwd)
 #XLEN    ?= 64
 
-all: root arch32 wally32 wally32e arch64 wally64
+all: root arch32 wally32 arch32e arch64 wally64
 wally-riscv-arch-test: root wally32 wally64
 
 root:
@@ -20,10 +20,16 @@ root:
 	sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
 	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
 
+arch32e:
+	riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
+	rsync -a $(work_dir)/rv32e_unratified/ $(arch_workdir)/rv32e_unratified/ || echo "error suppressed"
+
 arch32:
 	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
 	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
 
+
 arch64:
 	riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
 	rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -55,6 +55,8 @@ class sail_cSim(pluginTemplate):
         self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
+        if "E" in ispec["ISA"]:
+            self.isa += 'e'
         if "M" in ispec["ISA"]:
             self.isa += 'm'
         if "A" in ispec["ISA"]:

tests/riscof/spike/riscof_spike.py

@@ -97,6 +97,8 @@ class spike(pluginTemplate):
       self.isa = 'rv' + self.xlen
       if "I" in ispec["ISA"]:
           self.isa += 'i'
+      if "E" in ispec["ISA"]:
+          self.isa += 'e'
       if "M" in ispec["ISA"]:
           self.isa += 'm'
       if "A" in ispec["ISA"]: