From 38e114a6c06b7e3b173c66296823c00f4dd6a394 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 15 Sep 2022 13:59:01 -0500
Subject: [PATCH] Fixed subword read to work with bigendian.

---
 pipelined/src/lsu/lsu.sv         |  2 +-
 pipelined/src/lsu/subwordread.sv | 15 +++++++++------
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index cd983c2e6..73b065f17 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -328,7 +328,7 @@ module lsu (
   // *** Ross Thompson: I think swr needs to be modified to support bigendian.  Both the subword
   // selected and the sign extension are probably wrong.  I think it should be an invertion of
   // the address bits and a different bit selected for extension.
-  subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]),
+  subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
 		.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
   subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
 
diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv
index c2c5746d9..8d5ed4de5 100644
--- a/pipelined/src/lsu/subwordread.sv
+++ b/pipelined/src/lsu/subwordread.sv
@@ -35,19 +35,22 @@ module subwordread
    input logic [`LLEN-1:0] 	ReadDataWordMuxM,
    input logic [2:0] 		PAdrM,
    input logic [2:0] 		Funct3M,
-   input logic          FpLoadStoreM, 
+   input logic              FpLoadStoreM, 
+   input logic              BigEndianM, 
    output logic [`LLEN-1:0] ReadDataM
    );
 
   logic [7:0] 				ByteM; 
   logic [15:0] 				HalfwordM;
+  logic [2:0]               PAdrSwap;
   // Funct3M[2] is the unsigned bit. mask upper bits.
   // Funct3M[1:0] is the size of the memory access.
+  assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
 
   if (`XLEN == 64) begin:swrmux
     // ByteMe mux
     always_comb
-    case(PAdrM[2:0])
+    case(PAdrSwap[2:0])
       3'b000: ByteM = ReadDataWordMuxM[7:0];
       3'b001: ByteM = ReadDataWordMuxM[15:8];
       3'b010: ByteM = ReadDataWordMuxM[23:16];
@@ -60,7 +63,7 @@ module subwordread
   
     // halfword mux
     always_comb
-    case(PAdrM[2:1])
+    case(PAdrSwap[2:1])
       2'b00: HalfwordM = ReadDataWordMuxM[15:0];
       2'b01: HalfwordM = ReadDataWordMuxM[31:16];
       2'b10: HalfwordM = ReadDataWordMuxM[47:32];
@@ -70,7 +73,7 @@ module subwordread
     logic [31:0] WordM;
     
     always_comb
-      case(PAdrM[2])
+      case(PAdrSwap[2])
         1'b0: WordM = ReadDataWordMuxM[31:0];
         1'b1: WordM = ReadDataWordMuxM[63:32];
       endcase
@@ -103,7 +106,7 @@ module subwordread
   end else begin:swrmux // 32-bit
     // byte mux
     always_comb
-    case(PAdrM[1:0])
+    case(PAdrSwap[1:0])
       2'b00: ByteM = ReadDataWordMuxM[7:0];
       2'b01: ByteM = ReadDataWordMuxM[15:8];
       2'b10: ByteM = ReadDataWordMuxM[23:16];
@@ -112,7 +115,7 @@ module subwordread
   
     // halfword mux
     always_comb
-    case(PAdrM[1])
+    case(PAdrSwap[1])
       1'b0: HalfwordM = ReadDataWordMuxM[15:0];
       1'b1: HalfwordM = ReadDataWordMuxM[31:16];
     endcase