From 3864a7f798d25b7f47cfe1efbb455feb77bccbdc Mon Sep 17 00:00:00 2001 From: James Stine Date: Mon, 3 Jun 2024 17:25:32 -0500 Subject: [PATCH] missing privileged.sv --- src/privileged/privileged.sv | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c0dffcaa6..6d73a0f5f 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -96,7 +96,12 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic InvalidateICacheM, // fence instruction output logic BigEndianM, // Use big endian in current privilege mode // Fault outputs - output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout + output logic wfiM, IntPendingM, // Stall in Memory stage for WFI until interrupt pending or timeout + // Debug scan chain + input logic DebugCapture, + input logic DebugScanEn, + input logic DebugScanIn, + output logic DebugScanOut ); logic [3:0] CauseM; // trap cause @@ -147,7 +152,8 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .EPCM, .TrapVectorM, - .CSRReadValW, .IllegalCSRAccessM, .BigEndianM); + .CSRReadValW, .IllegalCSRAccessM, .BigEndianM, + .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); // pipeline early-arriving trap sources privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,