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Add SHA instructions

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James E. Stine 2024-02-20 20:01:12 -06:00
parent 2cf1d43ec5
commit 38348f9784
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///////////////////////////////////////////
// sha256sig0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig0 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror7;
logic [31:0] ror18;
logic [31:0] sh3;
logic [31:0] exts;
assign ror7 = {rs1[6:0], rs1[31:7]};
assign ror18 = {rs1[17:0], rs1[31:18]};
assign sh3 = {3'b0, rs1[31:3]};
// Assign output to xor of 3 rotates
assign exts = ror7 ^ ror18 ^ sh3;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig1 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror17;
logic [31:0] ror19;
logic [31:0] sh10;
logic [31:0] exts;
assign ror17 = {rs1[16:0], rs1[31:17]};
assign ror19 = {rs1[18:0], rs1[31:19]};
assign sh10 = {10'b0, rs1[31:10]};
// Assign output to xor of 3 rotates
assign exts = ror17 ^ ror19 ^ sh10;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum0 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror2;
logic [31:0] ror13;
logic [31:0] ror22;
logic [31:0] exts;
assign ror2 = {rs1[1:0], rs1[31:2]};
assign ror13 = {rs1[12:0], rs1[31:13]};
assign ror22 = {rs1[21:0], rs1[31:22]};
// Assign output to xor of 3 rotates
assign exts = ror2 ^ ror13 ^ ror22;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum1 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror6;
logic [31:0] ror11;
logic [31:0] ror25;
logic [31:0] exts;
assign ror6 = {rs1[5:0], rs1[31:6]};
assign ror11 = {rs1[10:0], rs1[31:11]};
assign ror25 = {rs1[24:0], rs1[31:25]};
// Assign output to xor of 3 rotates
assign exts = ror6 ^ ror11 ^ ror25;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha512sig0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0 (input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror1;
logic [63:0] ror8;
logic [63:0] sh7;
assign ror1 = {rs1[0], rs1[63:1]};
assign ror8 = {rs1[7:0], rs1[63:8]};
assign sh7 = rs1 >> 7;
// Assign output to xor of 3 rotates
assign result = ror1 ^ ror8 ^ sh7;
endmodule

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///////////////////////////////////////////
// sha512sig0h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0h instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0h(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// RS1 Shifts
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// RS2 Shifts
logic [31:0] shift31;
logic [31:0] shift24;
// Shift rs1
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// Shift rs2
assign shift31 = rs2 << 31;
assign shift24 = rs2 << 24;
// XOR to get result
assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
endmodule

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///////////////////////////////////////////
// sha512sig0l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0l instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0l(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// rs1 operations
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// rs2 operations
logic [31:0] shift31;
logic [31:0] shift25;
logic [31:0] shift24;
// rs1 shifts
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// rs2 shifts
assign shift31 = rs2 << 31;
assign shift25 = rs2 << 25;
assign shift24 = rs2 << 24;
assign data_out = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
endmodule

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///////////////////////////////////////////
// sha512sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sig1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1 (input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror19;
logic [63:0] ror61;
logic [63:0] sh6;
assign ror19 = {rs1[18:0], rs1[63:19]};
assign ror61 = {rs1[60:0], rs1[63:61]};
assign sh6 = rs1 >> 6;
// Assign output to xor of 3 rotates
assign result = ror19 ^ ror61 ^ sh6;
endmodule

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///////////////////////////////////////////
// sha512sig1h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1h instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1h(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// rs1 shifts
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shifts
logic [31:0] shift29;
logic [31:0] shift13;
// shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// shift rs2
assign shift29 = rs2 >> 29;
assign shift13 = rs2 << 13;
// XOR Shifted registers for output
assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
endmodule

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///////////////////////////////////////////
// sha512sig1l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1l instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1l(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// rs1 shift logic
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shift logics
logic [31:0] shift29;
logic [31:0] shift26;
logic [31:0] shift13;
// Shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// Shift rs2
assign shift29 = rs2 >> 29;
assign shift26 = rs2 << 26;
assign shift13 = rs2 << 13;
assign data_out = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
endmodule

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///////////////////////////////////////////
// sha512sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0 (input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror28;
logic [63:0] ror34;
logic [63:0] ror39;
assign ror28 = {rs1[27:0], rs1[63:28]};
assign ror34 = {rs1[33:0], rs1[63:34]};
assign ror39 = {rs1[38:0], rs1[63:39]};
// Assign output to xor of 3 rotates
assign result = ror28 ^ ror34 ^ ror39;
endmodule

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///////////////////////////////////////////
// sha512sum0r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0r instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0r(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// RS1 shifts
logic [31:0] shift25;
logic [31:0] shift30;
logic [31:0] shift28;
// RS2 shifts
logic [31:0] shift7;
logic [31:0] shift2;
logic [31:0] shift4;
// Shift rs1
assign shift25 = rs1 << 25;
assign shift30 = rs1 << 30;
assign shift28 = rs1 >> 28;
// Shift rs2
assign shift7 = rs2 >> 7;
assign shift2 = rs2 >> 2;
assign shift4 = rs2 << 4;
// Set output to XOR of shifted values
assign data_out = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
endmodule

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///////////////////////////////////////////
// sha512sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1 (input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror14;
logic [63:0] ror18;
logic [63:0] ror41;
assign ror14 = {rs1[13:0], rs1[63:14]};
assign ror18 = {rs1[17:0], rs1[63:18]};
assign ror41 = {rs1[40:0], rs1[63:41]};
// Assign output to xor of 3 rotates
assign result = ror14 ^ ror18 ^ ror41;
endmodule

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///////////////////////////////////////////
// sha512sum1r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1r instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1r(input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] data_out);
// Declare logic for rs1 shifts
logic [31:0] shift1_23;
logic [31:0] shift1_14;
logic [31:0] shift1_18;
// Declare logic for rs2 shifts
logic [31:0] shift2_9;
logic [31:0] shift2_18;
logic [31:0] shift2_14;
// Shift RS1
assign shift1_23 = rs1 << 23;
assign shift1_14 = rs1 >> 14;
assign shift1_18 = rs1 >> 18;
// Shift RS2
assign shift2_9 = rs2 >> 9;
assign shift2_18 = rs2 << 18;
assign shift2_14 = rs2 << 14;
// Assign output to xor of shifts
assign data_out = shift1_23 ^ shift1_14 ^ shift1_18 ^ shift2_9 ^ shift2_18 ^ shift2_14;
endmodule