From 382d5fab0f0a97c48aefb493069e0445784374fc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Feb 2022 11:27:15 -0600 Subject: [PATCH] Cleanup. --- pipelined/src/ifu/ifu.sv | 1 - pipelined/src/lsu/lsu.sv | 25 +++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 773348faf..045dfd030 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -265,7 +265,6 @@ module ifu ( // Mux only required on instruction class miss prediction. mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate)); - // The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE. mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); end else begin : bpred diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 706633901..5ca1a7969 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -174,7 +174,8 @@ module lsu ( logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordMuxM; - logic SelUncachedAdr; + logic IgnoreRequest; + assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; if (`DMEM == `MEM_TIM) begin : dtim dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, @@ -203,25 +204,25 @@ module lsu ( .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheMemWriteData, .LSUPAdrM, .FinalAMOWriteDataM, - .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest(IgnoreRequestTLB | IgnoreRequestTrapM), .LSURWM, .CPUBusy, .CacheableM, + .ReadDataWordM, .ReadDataWordMuxM, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); assign WordOffsetAddr = LSUBusWriteCrit ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; - if(`DMEM == `MEM_CACHE) begin : dcache + logic [1:0] RW, Atomic; + assign RW = CacheableM ? LSURWM : 2'b00; // AND gate + assign Atomic = CacheableM ? LSUAtomicM : 2'b00; // AND gate cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, - .RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), - .Atomic(CacheableM ? LSUAtomicM : 2'b00), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .save, .restore, + .clk, .reset, .CPUBusy, .save, .restore, .RW, .Atomic, + .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .FinalWriteData(FinalWriteDataM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), - .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), - .ReadDataLine(ReadDataLineM), .CacheMemWriteData(DCacheMemWriteData), - .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), - .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); + .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), + .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), + .CacheMemWriteData(DCacheMemWriteData), .CacheFetchLine(DCacheFetchLine), + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, @@ -249,7 +250,7 @@ module lsu ( if (`A_SUPPORTED) begin:atomic atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, - .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest(IgnoreRequestTLB | IgnoreRequestTrapM), + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM;