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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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commit
380c9e1dde
@ -26,7 +26,6 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ieu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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// Decode stage signals
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@ -118,4 +117,3 @@ module ieu import cvw::*; #(parameter cvw_t P) (
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.FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
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.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
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endmodule
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@ -84,5 +84,3 @@ module shifter (
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assign ZShift = Z >> Offset;
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assign Y = ZShift[`XLEN-1:0];
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endmodule
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@ -1,112 +0,0 @@
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import os
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# Kevin Wan kewan@hmc.edu 10/27/2021
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def read_input(filename): #1
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"""Takes in a string filename and outputs the parsed verilog code by line into a list
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such that each element of the list is one line of verilog code as a string."""
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lineOfCode = []
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input_file = open(filename, 'r')
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for line in input_file:
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lineOfCode.append(line)
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return lineOfCode
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###################################################################################
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def ID_start(GiantString):#2
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"""takes in the list of sv file lines, outputs the location that variable names should start"""
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VarLoc = 0
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VarLineNum = None
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for lines in GiantString:
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if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
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if "[" in lines and "]" in lines:# need to account for these space
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NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear.
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if NowLoc>VarLoc:
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VarLoc = NowLoc
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VarLineNum = GiantString.index(lines) # Update this number if new record is made.
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else:
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NowLoc = lines.find('logic') + 7 # same as before.
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if NowLoc>VarLoc:
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VarLoc = NowLoc
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VarLineNum = GiantString.index(lines)
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#print("Furthest variable appears on line", VarLineNum + 1,VarLoc) # Disable this line after debugging.
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return VarLoc
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##################################################################################
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def modified_logNew(GS,SOV): #3
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Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it.
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Out = []
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for l in GS:
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lines = l.replace('\t',' ')
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if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
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if "[" in lines and "]" in lines: # the line is an extended declaration.
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EditLoc = lines.find("]") # Re-finds the string index number of ].
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VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1 # Checks where variable declaration currently is at.
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#print(VarLoc,lines[VarLoc])# VERIFIED
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NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind)
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Out.append(NewLine)# Verified0957 10272021
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else:
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EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
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VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
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NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
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Out.append(NewLine1)# Verified 1005 10272021
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else:
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Out.append(lines)
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return Out
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################################################################################
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def write_to_output(filename,GiantString,OW=True,Lines_editted=None): #4
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"""Filename is preferrably passed from the early function calls"""
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"""GiantString has all the corrected features in the code, each line is a good verilog code line"""
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newname = filename
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if not OW or OW =='f': #which means no overwrite (create a new file)
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Decomposed=filename.split('.')
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newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned.
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OutFile = open(newname,'w') # This step should create a new file.
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OutFile.writelines(GiantString)
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OutFile.close()
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print("Success! " + newname + " Now contains an aligned file!")
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return newname
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#################################################################################
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def FindCharRel(Ln):
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#returns the computer location of a character's first occurence
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for num in range(len(Ln)):
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if Ln[num] != " ":
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return num
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def Mod_Space_at(Ln,loc,diff):
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#loc is the varLoc from mln, diff is varLoc - Ind
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if diff > 0: # to delete
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NewString = Ln[:(loc-diff)] + Ln[loc:]
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if diff < 0: # to add
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NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
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if diff == 0:
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NewString = Ln
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return NewString
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'''def main_filehandler(overwrite=False):
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for filename in os.listdir():
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if ".sv" in filename:
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GiantString = read_input(filename)
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SOV = ID_start(GiantString)
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ModifiedGS = modified_logNew(GiantString,SOV)
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Newname = write_to_output(filename,ModifiedGS,overwrite)'''
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def root_filehandler(path,overwrite=False):
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for f in os.listdir(path):
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if os.path.isdir(f):
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root_filehandler(path+"/"+f)
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else:
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if ".sv" in f:
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GiantString = read_input(f)
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SOV = ID_start(GiantString)
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ModifiedGS = modified_logNew(GiantString,SOV)
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Newname = write_to_output(f,ModifiedGS,overwrite)
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def driver(overwrite=False):
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root_filehandler(os.getcwd())
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driver(True)
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@ -181,4 +181,3 @@ module decompress #(parameter XLEN)(
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endcase
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end
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endmodule
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@ -107,7 +107,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
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logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
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logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
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logic [P.XLEN+1:0] PCFExt; //
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logic [P.XLEN+1:0] PCFExt;
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logic [31:0] IROMInstrF; // Instruction from the IROM
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logic [31:0] ICacheInstrF; // Instruction from the I$
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@ -124,7 +124,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic [31:0] InstrE; // Instruction in the Execution stage
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logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
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logic BusStall; // Bus interface busy with multicycle operation
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@ -199,6 +198,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory
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////////////////////////////////////////////////////////////////////////////////////////////////
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// CommittedM tells the CPU's privileged unit the current instruction
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// in the memory stage is a memory operaton and that memory operation is either completed
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// or is partially executed. Partially completed memory operations need to prevent an interrupts.
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@ -321,7 +321,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Branch and Jump Predictor
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -341,10 +340,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign NextValidPCE = PCE;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and compressed instruction decoding.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Decode stage pipeline register and logic
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flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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@ -37,7 +37,6 @@ module irom import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] IROMInstrFFull;
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logic [31:0] RawIROMInstrF;
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logic [1:0] AdrD;
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flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
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@ -52,4 +51,3 @@ module irom import cvw::*; #(parameter cvw_t P) (
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// The spill logic will handle merging the two together.
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assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
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endmodule
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@ -71,7 +71,6 @@ module spill import cvw::*; #(parameter cvw_t P) (
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// select between PCF and PCF+2
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mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Detect spill
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////////////////////////////////////////////////////////////////////////////////////////////////////
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end
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end
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endmodule
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ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN))
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ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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endmodule
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@ -132,7 +132,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Pipeline for IEUAdr E to M
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// Zero-extend address to 34 bits for XLEN=32
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@ -320,6 +319,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Atomic operations
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/////////////////////////////////////////////////////////////////////////////////////////////
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if (P.A_SUPPORTED) begin:atomic
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atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
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.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
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@ -335,6 +335,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Subword Accesses
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/////////////////////////////////////////////////////////////////////////////////////////////
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subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
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@ -361,5 +362,4 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign LSUWriteDataM = LittleEndianWriteDataM;
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assign LittleEndianReadDataWordM = ReadDataWordMuxM;
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end
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endmodule
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@ -84,5 +84,3 @@ module mdu import cvw::*; #(parameter cvw_t P) (
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// Writeback stage pipeline register
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flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
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endmodule // mdu
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// add up partial products; this multi-input add implies CSAs and a final CPA
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assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
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endmodule
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// Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
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assign Sel = Match & Supported & AccessValid & SizeValid;
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endmodule
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@ -70,4 +70,3 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
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assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
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assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault;
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endmodule
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@ -87,4 +87,3 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) (
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// attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This
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// implementation will not detect the failure.
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endmodule
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@ -1,5 +1,3 @@
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///////////////////////////////////////////
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// csrc.sv
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//
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@ -82,7 +82,6 @@ module csri import cvw::*; #(parameter cvw_t P) (
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else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
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else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
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assign MIP_REGW = {MExtInt, 1'b0, SExtInt|MIP_REGW_writeable[9], 1'b0,
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MTimerInt, 1'b0, STIP, 1'b0,
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MSwInt, 1'b0, MIP_REGW_writeable[1], 1'b0};
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@ -112,7 +112,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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logic ExceptionM; // Memory stage instruction caused a fault
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logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
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// track the current privilege level
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privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
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.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
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@ -156,8 +155,3 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.InstrValidM, .CommittedM, .CommittedF,
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.TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
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endmodule
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@ -103,4 +103,3 @@ assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before a
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// resp logic
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assign HRESP = 0; // bridge never indicates errors
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endmodule
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