Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

This commit is contained in:
David Harris 2023-06-15 07:01:44 -07:00
commit 380c9e1dde
39 changed files with 911 additions and 1050 deletions

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@ -26,7 +26,6 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ieu import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
// Decode stage signals
@ -118,4 +117,3 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
endmodule

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@ -84,5 +84,3 @@ module shifter (
assign ZShift = Z >> Offset;
assign Y = ZShift[`XLEN-1:0];
endmodule

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@ -1,112 +0,0 @@
import os
# Kevin Wan kewan@hmc.edu 10/27/2021
def read_input(filename): #1
"""Takes in a string filename and outputs the parsed verilog code by line into a list
such that each element of the list is one line of verilog code as a string."""
lineOfCode = []
input_file = open(filename, 'r')
for line in input_file:
lineOfCode.append(line)
return lineOfCode
###################################################################################
def ID_start(GiantString):#2
"""takes in the list of sv file lines, outputs the location that variable names should start"""
VarLoc = 0
VarLineNum = None
for lines in GiantString:
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines:# need to account for these space
NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines) # Update this number if new record is made.
else:
NowLoc = lines.find('logic') + 7 # same as before.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines)
#print("Furthest variable appears on line", VarLineNum + 1,VarLoc) # Disable this line after debugging.
return VarLoc
##################################################################################
def modified_logNew(GS,SOV): #3
Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it.
Out = []
for l in GS:
lines = l.replace('\t',' ')
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines: # the line is an extended declaration.
EditLoc = lines.find("]") # Re-finds the string index number of ].
VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1 # Checks where variable declaration currently is at.
#print(VarLoc,lines[VarLoc])# VERIFIED
NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind)
Out.append(NewLine)# Verified0957 10272021
else:
EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
Out.append(NewLine1)# Verified 1005 10272021
else:
Out.append(lines)
return Out
################################################################################
def write_to_output(filename,GiantString,OW=True,Lines_editted=None): #4
"""Filename is preferrably passed from the early function calls"""
"""GiantString has all the corrected features in the code, each line is a good verilog code line"""
newname = filename
if not OW or OW =='f': #which means no overwrite (create a new file)
Decomposed=filename.split('.')
newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned.
OutFile = open(newname,'w') # This step should create a new file.
OutFile.writelines(GiantString)
OutFile.close()
print("Success! " + newname + " Now contains an aligned file!")
return newname
#################################################################################
def FindCharRel(Ln):
#returns the computer location of a character's first occurence
for num in range(len(Ln)):
if Ln[num] != " ":
return num
def Mod_Space_at(Ln,loc,diff):
#loc is the varLoc from mln, diff is varLoc - Ind
if diff > 0: # to delete
NewString = Ln[:(loc-diff)] + Ln[loc:]
if diff < 0: # to add
NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
if diff == 0:
NewString = Ln
return NewString
'''def main_filehandler(overwrite=False):
for filename in os.listdir():
if ".sv" in filename:
GiantString = read_input(filename)
SOV = ID_start(GiantString)
ModifiedGS = modified_logNew(GiantString,SOV)
Newname = write_to_output(filename,ModifiedGS,overwrite)'''
def root_filehandler(path,overwrite=False):
for f in os.listdir(path):
if os.path.isdir(f):
root_filehandler(path+"/"+f)
else:
if ".sv" in f:
GiantString = read_input(f)
SOV = ID_start(GiantString)
ModifiedGS = modified_logNew(GiantString,SOV)
Newname = write_to_output(f,ModifiedGS,overwrite)
def driver(overwrite=False):
root_filehandler(os.getcwd())
driver(True)

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@ -181,4 +181,3 @@ module decompress #(parameter XLEN)(
endcase
end
endmodule

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@ -107,7 +107,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
logic [P.XLEN+1:0] PCFExt; //
logic [P.XLEN+1:0] PCFExt;
logic [31:0] IROMInstrF; // Instruction from the IROM
logic [31:0] ICacheInstrF; // Instruction from the I$
@ -124,7 +124,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [31:0] InstrE; // Instruction in the Execution stage
logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
logic CacheableF; // PMA indicates instruction address is cacheable
logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
logic BusStall; // Bus interface busy with multicycle operation
@ -199,6 +198,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
////////////////////////////////////////////////////////////////////////////////////////////////
// Memory
////////////////////////////////////////////////////////////////////////////////////////////////
// CommittedM tells the CPU's privileged unit the current instruction
// in the memory stage is a memory operaton and that memory operation is either completed
// or is partially executed. Partially completed memory operations need to prevent an interrupts.
@ -321,7 +321,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
////////////////////////////////////////////////////////////////////////////////////////////////
// Branch and Jump Predictor
////////////////////////////////////////////////////////////////////////////////////////////////
@ -341,10 +340,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
assign NextValidPCE = PCE;
end
////////////////////////////////////////////////////////////////////////////////////////////////
// Decode stage pipeline register and compressed instruction decoding.
////////////////////////////////////////////////////////////////////////////////////////////////
// Decode stage pipeline register and logic
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);

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@ -37,7 +37,6 @@ module irom import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] IROMInstrFFull;
logic [31:0] RawIROMInstrF;
logic [1:0] AdrD;
flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
@ -52,4 +51,3 @@ module irom import cvw::*; #(parameter cvw_t P) (
// The spill logic will handle merging the two together.
assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
endmodule

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@ -71,7 +71,6 @@ module spill import cvw::*; #(parameter cvw_t P) (
// select between PCF and PCF+2
mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
////////////////////////////////////////////////////////////////////////////////////////////////////
// Detect spill
////////////////////////////////////////////////////////////////////////////////////////////////////

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@ -72,4 +72,3 @@ module amoalu import cvw::*; #(parameter cvw_t P) (
end
end
endmodule

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@ -52,4 +52,3 @@ module dtim import cvw::*; #(parameter cvw_t P) (
ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN))
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
endmodule

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@ -132,7 +132,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic SelDTIM; // Select DTIM rather than bus or D$
/////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M
// Zero-extend address to 34 bits for XLEN=32
@ -320,6 +319,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
/////////////////////////////////////////////////////////////////////////////////////////////
if (P.A_SUPPORTED) begin:atomic
atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
@ -335,6 +335,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
// Subword Accesses
/////////////////////////////////////////////////////////////////////////////////////////////
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
@ -361,5 +362,4 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign LSUWriteDataM = LittleEndianWriteDataM;
assign LittleEndianReadDataWordM = ReadDataWordMuxM;
end
endmodule

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@ -84,5 +84,3 @@ module mdu import cvw::*; #(parameter cvw_t P) (
// Writeback stage pipeline register
flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
endmodule // mdu

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@ -90,4 +90,3 @@ module mul #(parameter XLEN) (
// add up partial products; this multi-input add implies CSAs and a final CPA
assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
endmodule

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@ -50,4 +50,3 @@ module adrdec #(parameter PA_BITS) (
// Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
assign Sel = Match & Supported & AccessValid & SizeValid;
endmodule

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@ -70,4 +70,3 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault;
endmodule

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@ -87,4 +87,3 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) (
// attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This
// implementation will not detect the failure.
endmodule

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@ -1,5 +1,3 @@
///////////////////////////////////////////
// csrc.sv
//

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@ -82,7 +82,6 @@ module csri import cvw::*; #(parameter cvw_t P) (
else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
assign MIP_REGW = {MExtInt, 1'b0, SExtInt|MIP_REGW_writeable[9], 1'b0,
MTimerInt, 1'b0, STIP, 1'b0,
MSwInt, 1'b0, MIP_REGW_writeable[1], 1'b0};

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@ -112,7 +112,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
logic ExceptionM; // Memory stage instruction caused a fault
logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
// track the current privilege level
privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
@ -156,8 +155,3 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.InstrValidM, .CommittedM, .CommittedF,
.TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
endmodule

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@ -103,4 +103,3 @@ assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before a
// resp logic
assign HRESP = 0; // bridge never indicates errors
endmodule