diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c
index 04d609648..4e75086ad 100644
--- a/fpga/zsbl/spi.c
+++ b/fpga/zsbl/spi.c
@@ -31,7 +31,7 @@
 
 uint8_t spi_txrx(uint8_t byte) {
   spi_sendbyte(byte);
-  waittx();
+  waitrx();
   return spi_readbyte();
 }
 
diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h
index f9e88fa6d..5a472142f 100644
--- a/fpga/zsbl/spi.h
+++ b/fpga/zsbl/spi.h
@@ -106,7 +106,7 @@ static inline void waittx() {
 }
 
 static inline void waitrx() {
-  while(read_reg(SPI_IP) & 2) {}
+  while(!(read_reg(SPI_IP) & 2)) {}
 }
 
 static inline uint8_t spi_readbyte() {
diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv
index 1e4910faf..514e9df7b 100644
--- a/src/uncore/spi_fifo.sv
+++ b/src/uncore/spi_fifo.sv
@@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)(                 // 2^M entries of N bits
  
     assign rdata = mem[raddr];
     always_ff @(posedge PCLK)
-        if (winc & ~wfull) mem[waddr] <= wdata;
+        if (winc & wen & ~wfull) mem[waddr] <= wdata;
 
     // write and read are enabled 
     always_ff @(posedge PCLK)