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change regfile to not hold state of x0

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This commit is contained in:
Noah Boorstin 2021-01-22 15:12:33 -05:00
parent 2f24249d17
commit 379fc6d5ca
1 changed files with 2 additions and 2 deletions
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wally-pipelined/src/regfile.sv
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@ -32,7 +32,7 @@ module regfile #(parameter XLEN=32) (
input logic [XLEN-1:0] wd3, input logic [XLEN-1:0] wd3,
output logic [XLEN-1:0] rd1, rd2); output logic [XLEN-1:0] rd1, rd2);
logic [XLEN-1:0] rf[31:0]; logic [XLEN-1:0] rf[31:1];
integer i; integer i;
// three ported register file // three ported register file
@ -45,7 +45,7 @@ module regfile #(parameter XLEN=32) (
always_ff @(negedge clk or posedge reset) always_ff @(negedge clk or posedge reset)
if (reset) for(i=0; i<32; i++) rf[i] <= 0; if (reset) for(i=0; i<32; i++) rf[i] <= 0;
else if (we3) rf[a3] <= wd3; else if (we3 & (a3 != 0)) rf[a3] <= wd3;
assign #2 rd1 = (a1 != 0) ? rf[a1] : 0; assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
assign #2 rd2 = (a2 != 0) ? rf[a2] : 0; assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;