From 372904c6d90cf4274778d98e719c9fa9560c0c41 Mon Sep 17 00:00:00 2001 From: Matthew <106996253+Matthew-Otto@users.noreply.github.com> Date: Mon, 24 Jun 2024 19:45:59 -0500 Subject: [PATCH] Fix progbuf addressing, fix various syntax errors --- bin/hw_debug_test.py | 23 +++++++---- bin/openocd_tcl_wrapper.py | 6 ++- config/rv32e/config.vh | 3 ++ config/rv32gc/config.vh | 3 ++ config/rv32i/config.vh | 3 ++ config/rv32imc/config.vh | 3 ++ config/rv64i/config.vh | 3 ++ config/shared/debug.vh | 78 +++++++++++++++++++------------------- src/debug/dm.sv | 36 +++++++++--------- src/debug/dmc.sv | 1 - src/debug/dtm.sv | 2 +- src/debug/ir.sv | 2 +- src/ifu/ifu.sv | 33 ++++++++-------- src/ifu/progbuf.sv | 11 ++++-- src/lsu/lsu.sv | 2 +- src/mmu/adrdecs.sv | 4 +- src/mmu/pmachecker.sv | 4 +- src/privileged/csrd.sv | 2 +- testbench/testbench.sv | 14 ++++++- testbench/wallywrapper.sv | 21 +++++++--- 20 files changed, 154 insertions(+), 100 deletions(-) diff --git a/bin/hw_debug_test.py b/bin/hw_debug_test.py index 8a99cf7a4..2cebebf96 100755 --- a/bin/hw_debug_test.py +++ b/bin/hw_debug_test.py @@ -38,20 +38,27 @@ random_order = False def prog_buff_test(cvw): cvw.halt() - cvw.write_dmi("0x20", "0x00100073") - #cvw.write_dmi("0x21", "0xf00daedd") - #cvw.write_dmi("0x22", "0xdaede105") - #cvw.write_dmi("0x23", "0x00100073") # ebreak + pb = ["0x00840413", "0xd2e3ca40", "0x00100073"] + cvw.write_data("DCSR", hex(0x1 << 15)) + cvw.write_progbuf(pb) + cvw.exec_progbuf() - cvw.write_data("DPC", "0x00002000") # Progbuf addr cvw.resume() print() def flow_control_test(cvw): - #time.sleep(70) # wait for OpenSBI + #time.sleep(200) # wait for full boot #cvw.halt() + for _ in range(5): + time.sleep(random.randint(5,10)) + cvw.halt() + cvw.step() + cvw.step() + cvw.resume() + return + time.sleep(1) #cvw.read_data("DCSR") for _ in range(100): @@ -171,5 +178,5 @@ with OpenOCD() as cvw: cvw.reset_hart() time.sleep(1) #register_rw_test(cvw) - flow_control_test(cvw) - #prog_buff_test(cvw) + #flow_control_test(cvw) + prog_buff_test(cvw) diff --git a/bin/openocd_tcl_wrapper.py b/bin/openocd_tcl_wrapper.py index 4c1c8097e..cf5630ae8 100644 --- a/bin/openocd_tcl_wrapper.py +++ b/bin/openocd_tcl_wrapper.py @@ -115,11 +115,15 @@ class OpenOCD: self.write_dmi("0x10", "0x10000001") # ack HaveReset def write_progbuf(self, data): - #TODO query progbuf size and error is len(data) is greater + #TODO query progbuf size and error if len(data) is greater baseaddr = 0x20 for idx, instr in enumerate(data): + z = hex(baseaddr+idx) #debug self.write_dmi(hex(baseaddr+idx), instr) + def exec_progbuf(self): + self.write_dmi("0x17", hex(0x1 << 18)) + def set_haltonreset(self): self.write_dmi("0x10", "0x9") diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index e4d358782..f27102263 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -186,6 +186,9 @@ localparam logic [63:0] SDC_RANGE = 64'h0000007F; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; +// Debug program buffer support is enabled with DEBUG_SUPPORTED +localparam logic [63:0] PROGBUF_BASE = 64'h00002000; +localparam logic [63:0] PROGBUF_RANGE = 64'h0000000F; // Bus Interface width localparam AHBW = (XLEN); diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 2db15000a..035f1ecc1 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -186,6 +186,9 @@ localparam logic [63:0] SDC_RANGE = 64'h0000007F; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; +// Debug program buffer support is enabled with DEBUG_SUPPORTED +localparam logic [63:0] PROGBUF_BASE = 64'h00002000; +localparam logic [63:0] PROGBUF_RANGE = 64'h0000000F; // Bus Interface width localparam AHBW = (XLEN); diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 7c378ca56..7cf1f3403 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -186,6 +186,9 @@ localparam logic [63:0] SDC_RANGE = 64'h0000007F; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; +// Debug program buffer support is enabled with DEBUG_SUPPORTED +localparam logic [63:0] PROGBUF_BASE = 64'h00002000; +localparam logic [63:0] PROGBUF_RANGE = 64'h0000000F; // Bus Interface width localparam AHBW = (XLEN); diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index a42721b85..f79ad5b10 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -186,6 +186,9 @@ localparam logic [63:0] SDC_RANGE = 64'h0000007F; localparam logic SPI_SUPPORTED = 1; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; +// Debug program buffer support is enabled with DEBUG_SUPPORTED +localparam logic [63:0] PROGBUF_BASE = 64'h00002000; +localparam logic [63:0] PROGBUF_RANGE = 64'h0000000F; // Bus Interface width localparam AHBW = (XLEN); diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 82c58e07b..af7dad049 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -186,6 +186,9 @@ localparam logic [63:0] SDC_RANGE = 64'h0000007F; localparam logic SPI_SUPPORTED = 0; localparam logic [63:0] SPI_BASE = 64'h10040000; localparam logic [63:0] SPI_RANGE = 64'h00000FFF; +// Debug program buffer support is enabled with DEBUG_SUPPORTED +localparam logic [63:0] PROGBUF_BASE = 64'h00002000; +localparam logic [63:0] PROGBUF_RANGE = 64'h0000000F; // Bus Interface width localparam AHBW = (XLEN); diff --git a/config/shared/debug.vh b/config/shared/debug.vh index 06f1e7c28..e2ecf49cd 100755 --- a/config/shared/debug.vh +++ b/config/shared/debug.vh @@ -23,48 +23,48 @@ `define OP_FAILED 2'b10 `define OP_BUSY 2'b11 -// Debug Bus Address Width -`define ADDR_WIDTH 7 +// DMI register Address Width +`define DMI_ADDR_WIDTH 7 // Debug Module Debug Bus Register Addresses // DM Internal registers -`define DATA0 `ADDR_WIDTH'h04 -`define DATA1 `ADDR_WIDTH'h05 -`define DATA2 `ADDR_WIDTH'h06 -`define DATA3 `ADDR_WIDTH'h07 -`define DATA4 `ADDR_WIDTH'h08 -`define DATA5 `ADDR_WIDTH'h09 -`define DATA6 `ADDR_WIDTH'h0A -`define DATA7 `ADDR_WIDTH'h0B -`define DATA8 `ADDR_WIDTH'h0C -`define DATA9 `ADDR_WIDTH'h0D -`define DATA10 `ADDR_WIDTH'h0E -`define DATA11 `ADDR_WIDTH'h0F -`define DMCONTROL `ADDR_WIDTH'h10 -`define DMSTATUS `ADDR_WIDTH'h11 -`define HARTINFO `ADDR_WIDTH'h12 -`define ABSTRACTCS `ADDR_WIDTH'h16 -`define COMMAND `ADDR_WIDTH'h17 -`define ABSTRACTAUTO `ADDR_WIDTH'h18 -`define NEXTDM `ADDR_WIDTH'h1d -`define PROGBUF0 `ADDR_WIDTH'h20 -`define PROGBUF1 `ADDR_WIDTH'h21 -`define PROGBUF2 `ADDR_WIDTH'h22 -`define PROGBUF3 `ADDR_WIDTH'h23 -`define PROGBUF4 `ADDR_WIDTH'h24 -`define PROGBUF5 `ADDR_WIDTH'h25 -`define PROGBUF6 `ADDR_WIDTH'h26 -`define PROGBUF7 `ADDR_WIDTH'h27 -`define PROGBUF8 `ADDR_WIDTH'h28 -`define PROGBUF9 `ADDR_WIDTH'h29 -`define PROGBUFA `ADDR_WIDTH'h2A -`define PROGBUFB `ADDR_WIDTH'h2B -`define PROGBUFC `ADDR_WIDTH'h2C -`define PROGBUFD `ADDR_WIDTH'h2D -`define PROGBUFE `ADDR_WIDTH'h2E -`define PROGBUFF `ADDR_WIDTH'h2F -//`define dmcs2 `ADDR_WIDTH'h32 -`define SBCS `ADDR_WIDTH'h38 +`define DATA0 `DMI_ADDR_WIDTH'h04 +`define DATA1 `DMI_ADDR_WIDTH'h05 +`define DATA2 `DMI_ADDR_WIDTH'h06 +`define DATA3 `DMI_ADDR_WIDTH'h07 +`define DATA4 `DMI_ADDR_WIDTH'h08 +`define DATA5 `DMI_ADDR_WIDTH'h09 +`define DATA6 `DMI_ADDR_WIDTH'h0A +`define DATA7 `DMI_ADDR_WIDTH'h0B +`define DATA8 `DMI_ADDR_WIDTH'h0C +`define DATA9 `DMI_ADDR_WIDTH'h0D +`define DATA10 `DMI_ADDR_WIDTH'h0E +`define DATA11 `DMI_ADDR_WIDTH'h0F +`define DMCONTROL `DMI_ADDR_WIDTH'h10 +`define DMSTATUS `DMI_ADDR_WIDTH'h11 +`define HARTINFO `DMI_ADDR_WIDTH'h12 +`define ABSTRACTCS `DMI_ADDR_WIDTH'h16 +`define COMMAND `DMI_ADDR_WIDTH'h17 +`define ABSTRACTAUTO `DMI_ADDR_WIDTH'h18 +`define NEXTDM `DMI_ADDR_WIDTH'h1d +`define PROGBUF0 `DMI_ADDR_WIDTH'h20 +`define PROGBUF1 `DMI_ADDR_WIDTH'h21 +`define PROGBUF2 `DMI_ADDR_WIDTH'h22 +`define PROGBUF3 `DMI_ADDR_WIDTH'h23 +`define PROGBUF4 `DMI_ADDR_WIDTH'h24 +`define PROGBUF5 `DMI_ADDR_WIDTH'h25 +`define PROGBUF6 `DMI_ADDR_WIDTH'h26 +`define PROGBUF7 `DMI_ADDR_WIDTH'h27 +`define PROGBUF8 `DMI_ADDR_WIDTH'h28 +`define PROGBUF9 `DMI_ADDR_WIDTH'h29 +`define PROGBUFA `DMI_ADDR_WIDTH'h2A +`define PROGBUFB `DMI_ADDR_WIDTH'h2B +`define PROGBUFC `DMI_ADDR_WIDTH'h2C +`define PROGBUFD `DMI_ADDR_WIDTH'h2D +`define PROGBUFE `DMI_ADDR_WIDTH'h2E +`define PROGBUFF `DMI_ADDR_WIDTH'h2F +//`define dmcs2 `DMI_ADDR_WIDTH'h32 +`define SBCS `DMI_ADDR_WIDTH'h38 //// Register field ranges diff --git a/src/debug/dm.sv b/src/debug/dm.sv index 35d76264a..8194a6af0 100644 --- a/src/debug/dm.sv +++ b/src/debug/dm.sv @@ -77,15 +77,15 @@ module dm import cvw::*; #(parameter cvw_t P) ( localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4; // DMI Signals - logic ReqReady; - logic ReqValid; - logic [`ADDR_WIDTH-1:0] ReqAddress; - logic [31:0] ReqData; - logic [1:0] ReqOP; - logic RspReady; - logic RspValid; - logic [31:0] RspData; - logic [1:0] RspOP; + logic ReqReady; + logic ReqValid; + logic [`DMI_ADDR_WIDTH-1:0] ReqAddress; + logic [31:0] ReqData; + logic [1:0] ReqOP; + logic RspReady; + logic RspValid; + logic [31:0] RspData; + logic [1:0] RspOP; // JTAG ID for Wally: // Version [31:28] = 0x1 : 0001 @@ -94,7 +94,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( // [0] = 1 localparam JTAG_DEVICE_ID = 32'h1002AC05; - dtm #(`ADDR_WIDTH, JTAG_DEVICE_ID) dtm (.clk, .rst, .tck, .tdi, .tms, .tdo, + dtm #(`DMI_ADDR_WIDTH, JTAG_DEVICE_ID) dtm (.clk, .rst, .tck, .tdi, .tms, .tdo, .ReqReady, .ReqValid, .ReqAddress, .ReqData, .ReqOP, .RspReady, .RspValid, .RspData, .RspOP); @@ -344,17 +344,17 @@ module dm import cvw::*; #(parameter cvw_t P) ( else begin case (ReqData[`CMDTYPE]) `ACCESS_REGISTER : begin - if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)) - CmdErr <= `CMDERR_BUS; // if AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing + if (~ReqData[`TRANSFER]) + State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK; // If not transfer, exec progbuf or do nothing + else if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)) + CmdErr <= `CMDERR_BUS; // If AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing else if (InvalidRegNo) - CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing + CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing else if (ReqData[`AARWRITE] & RegReadOnly) - CmdErr <= `CMDERR_NOT_SUPPORTED; // If writing to a read only register, set CmdErr, do nothing + CmdErr <= `CMDERR_NOT_SUPPORTED; // If writing to a read only register, set CmdErr, do nothing else begin - if (ReqData[`TRANSFER]) begin - AcWrite <= ReqData[`AARWRITE]; - NewAcState <= ~ReqData[`AARWRITE] ? AC_CAPTURE : AC_SCAN; - end + AcWrite <= ReqData[`AARWRITE]; + NewAcState <= ~ReqData[`AARWRITE] ? AC_CAPTURE : AC_SCAN; State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK; end end diff --git a/src/debug/dmc.sv b/src/debug/dmc.sv index 9bcb992fa..852b77585 100644 --- a/src/debug/dmc.sv +++ b/src/debug/dmc.sv @@ -29,7 +29,6 @@ // TODO: -// Figure out what is causing resumes from stalls to error out // Calculate correct cycle timing for step // Test progbuf diff --git a/src/debug/dtm.sv b/src/debug/dtm.sv index da748fadb..de9ab86fe 100644 --- a/src/debug/dtm.sv +++ b/src/debug/dtm.sv @@ -83,7 +83,7 @@ module dtm #(parameter ADDR_WIDTH, parameter JTAG_DEVICE_ID) ( // Synchronize the edges of tck to the system clock synchronizer clksync (.clk(clk), .d(tck), .q(tcks)); - jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.tck(tcks), .tdi, .tms, .tdo, + jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.rst, .tck(tcks), .tdi, .tms, .tdo, .resetn, .UpdateDtmcs, .DtmcsIn, .DtmcsOut, .CaptureDmi, .UpdateDmi, .DmiIn, .DmiOut); diff --git a/src/debug/ir.sv b/src/debug/ir.sv index 61651c5cf..ca3328d82 100644 --- a/src/debug/ir.sv +++ b/src/debug/ir.sv @@ -51,7 +51,7 @@ module ir ( flop #(1) shift_regmsb (.clk(clockIR), .d(shift_reg[1] | captureIR), .q(shift_reg[0])); genvar i; for (i = INST_REG_WIDTH; i > 1; i = i - 1) - flop #(1) shift_reg (.clk(clockIR), .d(shift_reg[i] & ~captureIR), .q(shift_reg[i-1])); + flop #(1) shift_regi (.clk(clockIR), .d(shift_reg[i] & ~captureIR), .q(shift_reg[i-1])); // Instruction decoder // 6.1.2 diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index c763ad082..81586d7ab 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -126,7 +126,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic [31:0] IROMInstrF; // Instruction from the IROM logic [31:0] ICacheInstrF; // Instruction from the I$ - logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus + logic [31:0] InstrRawFMain; // Instruction from the IROM, I$, or bus TODO: pick a better name for this signal + logic [31:0] InstrRawF; // Instruction from ProgBuf pr InstrRawFMain (IROM, I$, bus) logic [31:0] ProgBufInstrF; // Instruction from the ProgBuf logic CompressedF, CompressedE; // The fetched instruction is compressed logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill @@ -280,7 +281,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BusStall, .BusCommitted(BusCommittedF)); mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(ShiftUncachedInstr), .d2(IROMInstrF), - .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0])); + .s({SelIROM, ~CacheableF}), .y(InstrRawFMain[31:0])); end else begin : passthrough assign IFUHADDR = PCPF; logic [1:0] BusRW; @@ -293,8 +294,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); assign CacheCommittedF = '0; - if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawF); - else assign InstrRawF = ShiftUncachedInstr; + if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawFMain); + else assign InstrRawFMain = ShiftUncachedInstr; assign IFUHBURST = 3'b0; assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0; end @@ -308,21 +309,23 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS, BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; - assign InstrRawF = IROMInstrF; + assign InstrRawFMain = IROMInstrF; end - + + // Mux between InstrRawFMain and Progbuf + if (P.DEBUG_SUPPORTED) begin + progbuf #(P) progbuf(.clk, .reset, .Addr(PCF[5:0]), .ProgBufInstrF, .ScanAddr(ProgBufAddr), .Scan(ProgBuffScanEn), .ScanIn(ProgBufScanIn)); + assign InstrRawF = SelProgBuf ? ProgBufInstrF : InstrRawFMain; + end else begin + assign InstrRawF = InstrRawFMain; + end + assign IFUCacheBusStallF = ICacheStallF | BusStall; assign IFUStallF = IFUCacheBusStallF | SelSpillNextF; assign GatedStallD = StallD & ~SelSpillNextF; - - if (P.DEBUG_SUPPORTED) begin - logic [31:0] PostSpillInstrRawFM; - progbuf #(P) progbuf(.clk, .reset, .Addr(PCNextF[3:0]), .ProgBufInstrF, .ScanAddr(ProgBufAddr), .Scan(ProgBuffScanEn), .ScanIn(ProgBufScanIn)); - assign PostSpillInstrRawFM = SelProgBuf ? ProgBufInstrF : PostSpillInstrRawF; - flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawFM, nop, InstrRawD); - end else begin - flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD); - end + + flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD); + //////////////////////////////////////////////////////////////////////////////////////////////// // PCNextF logic diff --git a/src/ifu/progbuf.sv b/src/ifu/progbuf.sv index 79bb9874a..7d30da6c8 100644 --- a/src/ifu/progbuf.sv +++ b/src/ifu/progbuf.sv @@ -28,7 +28,7 @@ module progbuf import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, - input logic [3:0] Addr, + input logic [5:0] Addr, output logic [31:0] ProgBufInstrF, input logic [3:0] ScanAddr, @@ -44,6 +44,7 @@ module progbuf import cvw::*; #(parameter cvw_t P) ( logic EnPrevClk; logic WriteProgBuf; logic [32:0] WriteData; + logic [31:0] ReadRaw; logic [ADDR_WIDTH-1:0] AddrM; flopr #(1) Scanenhist (.clk, .reset, .d(Scan), .q(EnPrevClk)); @@ -55,15 +56,17 @@ module progbuf import cvw::*; #(parameter cvw_t P) ( flopenr #(1) Scanreg (.clk, .reset, .en(Scan), .d(WriteData[i+1]), .q(WriteData[i])); end - assign AddrM = WriteProgBuf ? ScanAddr[ADDR_WIDTH-1:0] : Addr[ADDR_WIDTH-1:0]; + assign AddrM = WriteProgBuf ? ScanAddr[ADDR_WIDTH-1:0] : Addr[ADDR_WIDTH-1+2:2]; always_ff @(posedge clk) begin if (WriteProgBuf) RAM[AddrM] <= WriteData; if (reset) - ProgBufInstrF <= 0; + ReadRaw <= 0; else - ProgBufInstrF <= RAM[AddrM]; + ReadRaw <= RAM[AddrM]; end + assign ProgBufInstrF = Addr[1] ? {16'b0,ReadRaw[31:16]}: ReadRaw; // + endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 4c43b6fab..e16319012 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -252,7 +252,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]), .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM), - .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), + .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), .SelProgBuf(), .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM), .StoreAmoPageFaultM(LSUStoreAmoPageFaultM), diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index cc0561ecd..5182f1654 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -33,7 +33,7 @@ module adrdecs import cvw::*; #(parameter cvw_t P) ( input logic [P.PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWXC, input logic [1:0] Size, - output logic [12:0] SelRegions + output logic [14:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111); @@ -49,7 +49,7 @@ module adrdecs import cvw::*; #(parameter cvw_t P) ( adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[9]); adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]); adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]); - adrdec #(P.PA_BITS) progbufdec(PhysicalAddress, P.PROGBUF_BASE[P.PA_BITS-1:0], P.PROGBUF_RANGE[P.PA_BITS-1:0], P.DEBUG_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[12]); + adrdec #(P.PA_BITS) progbufdec(PhysicalAddress, P.PROGBUF_BASE[P.PA_BITS-1:0], P.PROGBUF_RANGE[P.PA_BITS-1:0], P.DEBUG_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[14]); assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected endmodule diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 813e7746e..4ee7163d5 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -46,7 +46,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( logic PMAAccessFault; logic AccessRW, AccessRWXC, AccessRX; - logic [12:0] SelRegions; + logic [14:0] SelRegions; logic AtomicAllowed; logic CacheableRegion, IdempotentRegion; @@ -73,7 +73,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-tim // Debug program buffer - assign SelProgBuf = SelRegions[12]; + assign SelProgBuf = SelRegions[14]; // Detect access faults assign PMAAccessFault = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed; diff --git a/src/privileged/csrd.sv b/src/privileged/csrd.sv index ca67d4f42..6d7432a72 100644 --- a/src/privileged/csrd.sv +++ b/src/privileged/csrd.sv @@ -86,7 +86,7 @@ module csrd import cvw::*; #(parameter cvw_t P) ( end end - flopenr #(4) DCSRreg (clk, reset, WriteDCSRM, {CSRWriteValM[`EBREAKM], CSRWriteValM[`STEP]}, {ebreakM, Step}); + flopenr #(2) DCSRreg (clk, reset, WriteDCSRM, {CSRWriteValM[`EBREAKM], CSRWriteValM[`STEP]}, {ebreakM, Step}); assign DCSR = {DebugVer, 10'b0, ebreakVS, ebreakVU, ebreakM, 1'b0, ebreakS, ebreakU, StepIE, StopCount, StopTime, Cause, V, MPrvEn, NMIP, Step, Prv}; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9f2b42a5a..da0c5ed13 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -67,6 +67,11 @@ module testbench; logic reset_ext, reset; logic ResetMem; + logic tck; + logic tdi; + logic tms; + logic tdo; + // Variables that can be overwritten with $value$plusargs at start of simulation string TEST, ElfFile; integer INSTR_LIMIT; @@ -578,7 +583,14 @@ module testbench; assign SDCIntr = 1'b0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + // Change these if testing debug + assign tck = 0; + assign tdi = 0; + assign tms = 0; + + wallypipelinedsoc #(P) dut( + .clk, .reset_ext, .reset, .tck, .tdi, .tms, .tdo, + .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 2794240be..91285f5da 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -37,7 +37,12 @@ module wallywrapper import cvw::*;( `include "parameter-defs.vh" - logic reset; + logic reset; + + logic tck; + logic tdi; + logic tms; + logic tdo; logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -63,6 +68,10 @@ module wallywrapper import cvw::*;( // instantiate device to be tested + assign tck = 0; + assign tdi = 0; + assign tms = 0; + assign GPIOIN = 0; assign UARTSin = 1; @@ -71,9 +80,11 @@ module wallywrapper import cvw::*;( assign HRDATAEXT = 0; - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr); + wallypipelinedsoc #(P) dut( + .clk, .reset_ext, .reset, .tck, .tdi, .tms, .tdo, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, + .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, + .SPIIn, .SPIOut, .SPICS, .SDCIntr + ); endmodule