From 36bbf0c50248545303d538b42d406b147c99a951 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 3 Oct 2021 11:22:34 -0400
Subject: [PATCH] Divider cleaup

---
 wally-pipelined/src/muldiv/intdivrestoring.sv | 6 +++---
 wally-pipelined/src/muldiv/muldiv.sv          | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv
index a0ddb309e..5ab9b2b8c 100644
--- a/wally-pipelined/src/muldiv/intdivrestoring.sv
+++ b/wally-pipelined/src/muldiv/intdivrestoring.sv
@@ -33,7 +33,7 @@ module intdivrestoring (
   input  logic StallM, FlushM,
   input  logic SignedDivideE, W64E,
   input  logic StartDivideE,
-  input  logic [`XLEN-1:0] XE, DE,
+  input  logic [`XLEN-1:0] SrcAE, SrcBE,
   output logic BusyE, DivDoneM,
   output logic [`XLEN-1:0] QuotM, RemM
  );
@@ -50,8 +50,8 @@ module intdivrestoring (
   // save inputs on the negative edge of the execute clock.  
   // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
   // Saving the inputs is the most hardware-efficient way to fix the issue.
-  flopen #(`XLEN) dsavereg(~clk, StartDivideE, DE, DSavedE); 
-  flopen #(`XLEN) xsavereg(~clk, StartDivideE, XE, XSavedE);
+  flopen #(`XLEN) xsavereg(~clk, StartDivideE, SrcAE, XSavedE);
+  flopen #(`XLEN) dsavereg(~clk, StartDivideE, SrcBE, DSavedE); 
 
   // Handle sign extension for W-type instructions
   generate
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index dac98f3ee..8ffe91e9e 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -62,7 +62,7 @@ module muldiv (
 	 assign DivBusyE = StartDivideE | BusyE;
 	 assign SignedDivideE = ~Funct3E[0];
 	 intdivrestoring div(.clk, .reset, .StallM, .FlushM, 
-	   .SignedDivideE, .W64E, .StartDivideE, .XE(SrcAE), .DE(SrcBE), .BusyE, .DivDoneM, .QuotM, .RemM);
+	   .SignedDivideE, .W64E, .StartDivideE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
 	 	 
 	 // Result multiplexer
 	 always_comb
@@ -86,7 +86,7 @@ module muldiv (
 	 end
 
      // Writeback stage pipeline register
-	 
+
 	 flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);	 
 
       end else begin // no M instructions supported