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Minor improvement to icache.

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This commit is contained in:
Ross Thompson 2022-01-03 22:00:35 -06:00
parent a130c03478
commit 36451bbd15
1 changed files with 25 additions and 41 deletions
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62
wally-pipelined/src/ifu/ifu.sv
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@ -118,6 +118,8 @@ module ifu (
logic IgnoreRequest;
logic CPUBusy;
logic [15:0] SpillDataBlock0;
logic [31:0] PostSpillInstrRawF;
assign PCFp2 = PCF + `XLEN'b10;
@ -136,35 +138,29 @@ module ifu (
else CurrState <= #1 NextState;
always_comb begin
NextState = STATE_SPILL_READY;
SelSpill = 0;
SelNextSpill = 0;
SpillSave = 0;
case(CurrState)
STATE_SPILL_READY: begin
if (Spill & ~(ICacheStallF | BusStall)) begin
NextState = STATE_SPILL_SPILL;
SpillSave = 1;
SelNextSpill = 1;
end else begin
NextState = STATE_SPILL_READY;
end
end
STATE_SPILL_SPILL: begin
SelSpill = 1;
if(ICacheStallF | BusStall) begin
SelNextSpill = 1;
end
if(ICacheStallF | BusStall | StallF) begin
NextState = STATE_SPILL_SPILL;
end else begin
NextState = STATE_SPILL_READY;
end
end
default: NextState = STATE_SPILL_READY;
STATE_SPILL_READY: if (Spill & ~(ICacheStallF | BusStall)) NextState = STATE_SPILL_SPILL;
else NextState = STATE_SPILL_READY;
STATE_SPILL_SPILL: if(ICacheStallF | BusStall | StallF) NextState = STATE_SPILL_SPILL;
else NextState = STATE_SPILL_READY;
default: NextState = STATE_SPILL_READY;
endcase
end
assign SelSpill = CurrState == STATE_SPILL_SPILL;
assign SelNextSpill = (CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall))) |
(CurrState == STATE_SPILL_SPILL & (ICacheStallF | BusStall));
assign SpillSave = CurrState == STATE_SPILL_READY & (Spill & ~(ICacheStallF | BusStall));
flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSave),
.reset(reset),
.d(InstrRawF[15:0]),
.q(SpillDataBlock0));
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF;
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
@ -233,17 +229,10 @@ module ifu (
logic [`PA_BITS-1:0] LocalIfuBusAdr;
logic [`PA_BITS-1:0] ICacheBusAdr;
logic SelUncachedAdr;
logic [15:0] SpillDataBlock0;
logic [31:0] PostSpillInstrRawF;
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
// *** bug: on spill the second memory request does not go through the mmu(skips tlb, pmp, and pma checkers)
// also it is possible to have any above fault on the spilled accesses.
// I think the solution is to move the spill logic into the ifu using the busfsm and ensuring
// the mmu sees the spilled address.
generate
if(`MEM_ICACHE) begin : icache
icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
@ -270,13 +259,6 @@ module ifu (
.s(SelUncachedAdr),
.y(InstrRawF));
flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSave),
.reset(reset),
.d(InstrRawF[15:0]),
.q(SpillDataBlock0));
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF;
@ -306,6 +288,8 @@ module ifu (
assign CPUBusy = StallF & ~SelNextSpill;
//assign IgnoreRequest = ITLBMissF | ExceptionM | PendingInterruptM;
// this is a difference with the dcache.
// uses interlock fsm.
assign IgnoreRequest = ITLBMissF;