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pulled swbbytemask out of subword write.

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Ross Thompson 2022-08-01 20:48:45 -05:00
parent 1ee613ae6c
commit 3612db2d70
4 changed files with 11 additions and 18 deletions
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4
pipelined/src/ebu/ahblite.sv
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@ -49,7 +49,6 @@ module ahblite (
input logic [2:0] IFUBurstType, input logic [2:0] IFUBurstType,
input logic [1:0] IFUTransType, input logic [1:0] IFUTransType,
input logic IFUTransComplete, input logic IFUTransComplete,
input logic [(`XLEN-1)/8:0] ByteMaskM,
// Signals from Data Cache // Signals from Data Cache
input logic [`PA_BITS-1:0] LSUBusAdr, input logic [`PA_BITS-1:0] LSUBusAdr,
@ -157,8 +156,7 @@ module ahblite (
assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
assign HMASTLOCK = 0; // no locking supported assign HMASTLOCK = 0; // no locking supported
assign HWRITE = (NextBusState == MEMWRITE); assign HWRITE = (NextBusState == MEMWRITE);
//assign HWSTRB = ByteMaskM; // Byte mask for HWSTRB
// Byte mask for HWSTRB
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB)); swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
// delay write data by one cycle for // delay write data by one cycle for

12
pipelined/src/lsu/lsu.sv
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@ -77,8 +77,6 @@ module lsu (
(* mark_debug = "true" *) output logic [2:0] LSUBurstType, (* mark_debug = "true" *) output logic [2:0] LSUBurstType,
(* mark_debug = "true" *) output logic [1:0] LSUTransType, (* mark_debug = "true" *) output logic [1:0] LSUTransType,
(* mark_debug = "true" *) output logic LSUTransComplete, (* mark_debug = "true" *) output logic LSUTransComplete,
output logic [(`XLEN-1)/8:0] ByteMaskM,
// page table walker // page table walker
input logic [`XLEN-1:0] SATP_REGW, // from csr input logic [`XLEN-1:0] SATP_REGW, // from csr
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -116,6 +114,7 @@ module lsu (
logic [`XLEN-1:0] LSUWriteDataM; logic [`XLEN-1:0] LSUWriteDataM;
logic [`XLEN-1:0] WriteDataM; logic [`XLEN-1:0] WriteDataM;
logic [`LLEN-1:0] ReadDataM; logic [`LLEN-1:0] ReadDataM;
logic [(`XLEN-1)/8:0] ByteMaskM;
// *** TO DO: Burst mode // *** TO DO: Burst mode
@ -277,7 +276,14 @@ module lsu (
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
.LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM); .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM);
// Compute byte masks
//swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM[2:0]), .ByteMask(ByteMaskM));
swbytemaskword #(`XLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(ByteMaskM));
// *** fix me.
//swbytemaskword #(.WORDLEN(`XLEN))
//swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// MW Pipeline Register // MW Pipeline Register

10
pipelined/src/lsu/subwordwrite.sv
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@ -34,15 +34,7 @@ module subwordwrite (
input logic [2:0] LSUPAdrM, input logic [2:0] LSUPAdrM,
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
input logic [`XLEN-1:0] AMOWriteDataM, input logic [`XLEN-1:0] AMOWriteDataM,
output logic [`XLEN-1:0] LittleEndianWriteDataM, output logic [`XLEN-1:0] LittleEndianWriteDataM);
output logic [`XLEN/8-1:0] ByteMaskM
);
// Compute byte masks
//swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
// *** fix me.
swbytemaskword #(.WORDLEN(`XLEN))
swbytemaskword (.Size(LSUFunct3M[2:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
// Replicate data for subword writes // Replicate data for subword writes
if (`XLEN == 64) begin:sww if (`XLEN == 64) begin:sww

3
pipelined/src/wally/wallypipelinedcore.sv
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@ -116,7 +116,6 @@ module wallypipelinedcore (
logic [1:0] PageType; logic [1:0] PageType;
logic sfencevmaM, wfiM, IntPendingM; logic sfencevmaM, wfiM, IntPendingM;
logic SelHPTW; logic SelHPTW;
logic [`XLEN/8-1:0] ByteMaskM;
// PMA checker signals // PMA checker signals
@ -266,7 +265,6 @@ module wallypipelinedcore (
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
.ByteMaskM,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
.PrivilegeModeW, .BigEndianM, // connects to csr .PrivilegeModeW, .BigEndianM, // connects to csr
@ -313,7 +311,6 @@ module wallypipelinedcore (
.LSUTransComplete, .LSUTransComplete,
.LSUBusAck, .LSUBusAck,
.LSUBusInit, .LSUBusInit,
.ByteMaskM,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,