Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Changes are confirmed to work on the FPGA.

Browse Source
This commit is contained in:
Rose Thompson 2024-07-23 17:39:38 -05:00
parent bfb3b63a24
commit 35efbd6a54
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/rvvi/rvvisynth.sv
View File

@ -28,7 +28,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module rvvisynth import cvw::*; #(parameter cvw_t P, module rvvisynth import cvw::*; #(parameter cvw_t P,
parameter integer MAX_CSRS = 3, parameter integer MAX_CSRS = 5,
parameter integer TOTAL_CSRS = 36)( parameter integer TOTAL_CSRS = 36)(
input logic clk, reset, input logic clk, reset,
input logic StallE, StallM, StallW, FlushE, FlushM, FlushW, input logic StallE, StallM, StallW, FlushE, FlushM, FlushW,

2
testbench/testbench.sv
View File

@ -604,7 +604,7 @@ module testbench;
end end
if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
localparam MAX_CSRS = 3; localparam MAX_CSRS = 5;
logic valid; logic valid;
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;