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Improved FPGA makefile and fixed timing constraints in clock converter.

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This commit is contained in:
Ross Thompson 2021-12-03 10:05:13 -06:00
parent 755c3e6a4c
commit 35dd1b5c9f
2 changed files with 22 additions and 4 deletions
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18
fpga/generator/Makefile
View File

@ -1,7 +1,11 @@
dst := IP dst := IP
all: FPGA
all: $(dst)/xlnx_proc_sys_reset.log \ FPGA: IP
vivado -mode batch -source wally.tcl | tee wally.log
IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr4.log \ $(dst)/xlnx_ddr4.log \
$(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_axi_clock_converter.log \
$(dst)/xlnx_ahblite_axi_bridge.log $(dst)/xlnx_ahblite_axi_bridge.log
@ -11,5 +15,13 @@ $(dst)/%.log: %.tcl
cd IP;\ cd IP;\
vivado -mode batch -source ../$*.tcl | tee $*.log vivado -mode batch -source ../$*.tcl | tee $*.log
clean: cleanIP:
rm -rf IP vivado.jou vivado.log rm -rf IP
cleanLogs:
rm -rf *.jou *.log
cleanFPGA:
rm -rf WallyFPGA.* reports sim .Xil
cleanAll: cleanIP cleanLogs cleanFPGA

8
fpga/generator/xlnx_axi_clock_converter.tcl
View File

@ -11,7 +11,13 @@ set_property board_part $boardName [current_project]
create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName] set_property -dict [list CONFIG.ACLK_ASYNC {1} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.ADDR_WIDTH {32} \
CONFIG.DATA_WIDTH {64} \
CONFIG.ID_WIDTH {4} \
CONFIG.MI_CLK.FREQ_HZ {208333333} \
CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]