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Added changed SPI controller module. New signal TransmitStartD that starts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register.

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This commit is contained in:
Jacob Pease 2024-10-30 18:45:54 -05:00
parent 4e7e311b26
commit 35c9fe7648
1 changed files with 10 additions and 9 deletions
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19
src/uncore/spi_controller.sv
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@ -34,7 +34,8 @@ module spi_controller (
// Start Transmission // Start Transmission
input logic TransmitStart, input logic TransmitStart,
input logic ResetSCLKenable, input logic TransmitStartD,
input logic ResetSCLKenable,
// Registers // Registers
input logic [11:0] SckDiv, input logic [11:0] SckDiv,
@ -168,25 +169,25 @@ module spi_controller (
SCK <= ~SCK; SCK <= ~SCK;
end end
if ((CurrState == CSSCK) & SCK) begin if ((CurrState == CSSCK) & SCK & SCLKenable) begin
CSSCKCounter <= CSSCKCounter + 8'd1; CSSCKCounter <= CSSCKCounter + 8'd1;
end else begin end else if (SCLKenable) begin
CSSCKCounter <= 8'd0; CSSCKCounter <= 8'd0;
end end
if ((CurrState == SCKCS) & SCK) begin if ((CurrState == SCKCS) & SCK & SCLKenable) begin
SCKCSCounter <= SCKCSCounter + 8'd1; SCKCSCounter <= SCKCSCounter + 8'd1;
end else begin end else if (SCLKenable) begin
SCKCSCounter <= 8'd0; SCKCSCounter <= 8'd0;
end end
if ((CurrState == INTERCS) & SCK) begin if ((CurrState == INTERCS) & SCK & SCLKenable) begin
INTERCSCounter <= INTERCSCounter + 8'd1; INTERCSCounter <= INTERCSCounter + 8'd1;
end else begin end else begin
INTERCSCounter <= 8'd0; INTERCSCounter <= 8'd0;
end end
if ((CurrState == INTERXFR) & SCK) begin if ((CurrState == INTERXFR) & SCK & SCLKenable) begin
INTERXFRCounter <= INTERXFRCounter + 8'd1; INTERXFRCounter <= INTERXFRCounter + 8'd1;
end else begin end else begin
INTERXFRCounter <= 8'd0; INTERXFRCounter <= 8'd0;
@ -259,7 +260,7 @@ module spi_controller (
always_comb begin always_comb begin
case (CurrState) case (CurrState)
INACTIVE: if (TransmitStart) INACTIVE: if (TransmitStartD)
if (~HasCSSCK) NextState = TRANSMIT; if (~HasCSSCK) NextState = TRANSMIT;
else NextState = CSSCK; else NextState = CSSCK;
else NextState = INACTIVE; else NextState = INACTIVE;
@ -293,7 +294,7 @@ module spi_controller (
HOLD: begin // HOLD mode case ----------------------------------- HOLD: begin // HOLD mode case -----------------------------------
if (CSMode == AUTOMODE) begin if (CSMode == AUTOMODE) begin
NextState = INACTIVE; NextState = INACTIVE;
end else if (TransmitStart) begin // If FIFO is written to, start again. end else if (TransmitStartD) begin // If FIFO is written to, start again.
NextState = TRANSMIT; NextState = TRANSMIT;
end else NextState = HOLD; end else NextState = HOLD;
end end