Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.

Browse Source
This commit is contained in:
Ross Thompson 2021-08-05 16:49:03 -05:00
parent 37ba6b19e5
commit 3582be4dbb
2 changed files with 21 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/linux-testgen/testvector-generation/parseNew.py
View File

@ -87,6 +87,8 @@ def PrintInstr(instr, fp):
GPR = '' GPR = ''
CSR = [] CSR = []
for key in ChangedRegisters: for key in ChangedRegisters:
# filter out csr which are not checked.
if(key in RegNumber):
if(RegNumber[key] < 32): if(RegNumber[key] < 32):
# GPR # GPR
if(HUMAN_READABLE): if(HUMAN_READABLE):

17
wally-pipelined/testbench/testbench-linux.sv
View File

@ -134,13 +134,14 @@ module testbench();
integer tempIndex; integer tempIndex;
integer processingCSR; integer processingCSR;
integer fault; integer fault;
logic TrapW;
localparam [`XLEN-1:0] MSTATUS_MASK = 64'hFFF5_FFFF;
// ----------- // -----------
// Error Macro // Error Macro
// ----------- // -----------
`define ERROR \ `define ERROR \
#10; \
$display("processed %0d instructions with %0d warnings", instrs, warningCount); \ $display("processed %0d instructions with %0d warnings", instrs, warningCount); \
$stop; $stop;
@ -148,10 +149,13 @@ module testbench();
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
end end
assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW; assign checkInstrW = (dut.hart.ieu.InstrValidW | TrapW ) & ~dut.hart.StallW;
flopenrc #(`XLEN) MemAdrWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.ieu.dp.MemAdrM, MemAdrW); flopenrc #(`XLEN) MemAdrWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
flopenrc #(`XLEN) WriteDataWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.WriteDataM, WriteDataW); flopenrc #(`XLEN) WriteDataWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.WriteDataM, WriteDataW);
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW);
// make all checks in the write back stage. // make all checks in the write back stage.
always @(negedge clk) begin always @(negedge clk) begin
@ -159,7 +163,7 @@ module testbench();
if (checkInstrW) begin if (checkInstrW) begin
// read 1 line of the trace file // read 1 line of the trace file
matchCount = $fgets(line, data_file_all); matchCount = $fgets(line, data_file_all);
if(`DEBUG_TRACE > 0) $display("line %x", line); if(`DEBUG_TRACE > 0) $display("Time %t, line %x", $time, line);
matchCount = $sscanf(line, "%x %x %s", ExpectedPCW, ExpectedInstrW, textW); matchCount = $sscanf(line, "%x %x %s", ExpectedPCW, ExpectedInstrW, textW);
//$display("matchCount %d, PCW %x ExpectedInstrW %x textW %x", matchCount, ExpectedPCW, ExpectedInstrW, textW); //$display("matchCount %d, PCW %x ExpectedInstrW %x textW %x", matchCount, ExpectedPCW, ExpectedInstrW, textW);
@ -213,7 +217,7 @@ module testbench();
end end
if (dut.hart.ieu.dp.regf.rf[RegAdr] != RegValue) begin if (dut.hart.ieu.dp.regf.rf[RegAdr] != RegValue) begin
$display("RF[%02d] does not equal expected value: %016x", RegAdr, RegValue); $display("RF[%02d]: %016x does not equal expected value: %016x", RegAdr, dut.hart.ieu.dp.regf.rf[RegAdr], RegValue);
fault = 1; fault = 1;
end end
MarkerIndex += 3; MarkerIndex += 3;
@ -271,7 +275,7 @@ module testbench();
if(`DEBUG_TRACE > 3) begin if(`DEBUG_TRACE > 3) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSR, dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRValue); $display("CSR: %s = %016x, expected = %016x", ExpectedCSR, dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRValue);
end end
if (dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW != ExpectedCSRValue) begin if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW & MSTATUS_MASK) != (ExpectedCSRValue & MSTATUS_MASK)) begin
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSR, dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRValue); $display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSR, dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRValue);
fault = 1; fault = 1;
end end
@ -452,7 +456,6 @@ module testbench();
// ----------------------- // -----------------------
// RegFile Write Hijacking // RegFile Write Hijacking
// ----------------------- // -----------------------
/* -----\/----- EXCLUDED -----\/-----
always @(PCW or dut.hart.ieu.InstrValidW) begin always @(PCW or dut.hart.ieu.InstrValidW) begin
if(dut.hart.ieu.InstrValidW && PCW != 0) begin if(dut.hart.ieu.InstrValidW && PCW != 0) begin
// Hack to compensate for how Wally's MTIME may diverge from QEMU's MTIME (and that is okay) // Hack to compensate for how Wally's MTIME may diverge from QEMU's MTIME (and that is okay)
@ -477,7 +480,6 @@ module testbench();
end else release dut.hart.ieu.dp.WriteDataW; end else release dut.hart.ieu.dp.WriteDataW;
end end
end end
-----/\----- EXCLUDED -----/\----- */
// ---------------- // ----------------
// Big Chunky Block // Big Chunky Block
@ -609,7 +611,6 @@ module testbench();
// ------------------- // -------------------
// Additional Hardware // Additional Hardware
// ------------------- // -------------------
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
// PCF stuff isn't actually checked // PCF stuff isn't actually checked
// it only exists for helping detecting duplicate instructions in PCD // it only exists for helping detecting duplicate instructions in PCD