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busybear: more progress

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This commit is contained in:
Noah Boorstin 2021-03-23 14:49:26 -04:00
parent c16605a105
commit 355961f834
2 changed files with 13 additions and 4 deletions
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2
wally-pipelined/regression/wally-busybear.do
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@ -49,6 +49,8 @@ add wave -hex /testbench_busybear/dut/hart/ifu/PCD
add wave -hex /testbench_busybear/dut/hart/ifu/InstrD add wave -hex /testbench_busybear/dut/hart/ifu/InstrD
add wave -hex /testbench_busybear/dut/hart/ifu/StallD add wave -hex /testbench_busybear/dut/hart/ifu/StallD
add wave -hex /testbench_busybear/dut/hart/ifu/FlushD add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
add wave -hex /testbench_busybear/dut/hart/ifu/StallE
add wave -hex /testbench_busybear/dut/hart/ifu/FlushE
add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
add wave /testbench_busybear/CheckInstrD add wave /testbench_busybear/CheckInstrD
add wave /testbench_busybear/lastCheckInstrD add wave /testbench_busybear/lastCheckInstrD

15
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -192,7 +192,7 @@ module testbench_busybear();
always @(dut.HRDATA) begin always @(dut.HRDATA) begin
#1; #1;
if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin if (dut.hart.MemRWM[1] && HADDR[31:3] != dut.PCF[31:3] && dut.HRDATA !== {64{1'bx}}) begin
//$display("%0t", $time); //$display("%0t", $time);
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");
@ -335,6 +335,13 @@ module testbench_busybear();
`CHECK_CSR2(STVAL, `CSRS) `CHECK_CSR2(STVAL, `CSRS)
`CHECK_CSR(STVEC) `CHECK_CSR(STVEC)
initial begin //this is just fun to make causes easier to understand
#38;
force dut.hart.priv.csr.genblk1.csrm.NextCauseM = 0;
#16;
release dut.hart.priv.csr.genblk1.csrm.NextCauseM;
end
initial begin //this is temporary until the bug can be fixed!!! initial begin //this is temporary until the bug can be fixed!!!
#18909760; #18909760;
force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004; force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004;
@ -382,10 +389,10 @@ module testbench_busybear();
logic [31:0] InstrMask; logic [31:0] InstrMask;
logic forcedInstr; logic forcedInstr;
logic [63:0] lastPCD; logic [63:0] lastPCD;
always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset) begin always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset or negedge dut.hart.ifu.StallE) begin
if(~HWRITE) begin if(~HWRITE) begin
#3; #2;
if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0) begin if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0 && ~dut.hart.ifu.StallE) begin
if (dut.hart.ifu.PCD !== lastPCD) begin if (dut.hart.ifu.PCD !== lastPCD) begin
lastCheckInstrD = CheckInstrD; lastCheckInstrD = CheckInstrD;
lastPC <= dut.hart.ifu.PCD; lastPC <= dut.hart.ifu.PCD;