mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
FIxed wallypipelinedsoc merge conflict
This commit is contained in:
David Harris
commit
352bf88ac0
@ -51,8 +51,7 @@
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// LSU microarchitectural Features
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`define DMEM 0
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`define IROM 0
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||||
`define DBUS 1
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`define IBUS 1
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||||
`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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||||
`define VIRTMEM_SUPPORTED 1
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||||
@ -53,8 +53,7 @@
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||||
// LSU microarchitectural Features
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`define DMEM 0
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`define IROM 0
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`define DBUS 1
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`define IBUS 1
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`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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`define VIRTMEM_SUPPORTED 1
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@ -52,8 +52,7 @@
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||||
// LSU microarchitectural Features
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`define DMEM 0
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`define IROM 0
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`define DBUS 1
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`define IBUS 1
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`define BUS 1
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`define DCACHE 0
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`define ICACHE 0
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`define VIRTMEM_SUPPORTED 0
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@ -51,8 +51,7 @@
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// LSU microarchitectural Features
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||||
`define DMEM 0
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`define IROM 0
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`define DBUS 1
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`define IBUS 1
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`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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`define VIRTMEM_SUPPORTED 1
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@ -52,8 +52,7 @@
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||||
// LSU microarchitectural Features
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||||
`define DMEM 0
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`define IROM 0
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`define DBUS 1
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`define IBUS 1
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||||
`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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`define VIRTMEM_SUPPORTED 1
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@ -49,12 +49,11 @@
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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// LSU microarchitectural Features
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`define DMEM 0
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`define IROM 0
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`define DBUS 1
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`define IBUS 1
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||||
`define DCACHE 1
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||||
`define ICACHE 1
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`define DMEM 1
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`define IROM 1
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||||
`define BUS 0
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`define DCACHE 0
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`define ICACHE 0
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`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define BIGENDIAN_SUPPORTED 0
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@ -53,8 +53,7 @@
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// LSU microarchitectural Features
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||||
`define DMEM 0
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`define IROM 0
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||||
`define DBUS 1
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||||
`define IBUS 1
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||||
`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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`define VIRTMEM_SUPPORTED 1
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||||
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@ -54,8 +54,7 @@
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||||
// LSU microarchitectural Features
|
||||
`define DMEM 0
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`define IROM 0
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`define DBUS 1
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||||
`define IBUS 1
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||||
`define BUS 1
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`define DCACHE 1
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`define ICACHE 1
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`define VIRTMEM_SUPPORTED 1
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||||
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@ -53,8 +53,7 @@
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||||
// LSU microarchitectural Features
|
||||
`define DMEM 0
|
||||
`define IROM 0
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define BUS 1
|
||||
`define DCACHE 1
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||||
`define ICACHE 1
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||||
`define VIRTMEM_SUPPORTED 1
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||||
|
||||
@ -53,8 +53,7 @@
|
||||
// LSU microarchitectural Features
|
||||
`define DMEM 0
|
||||
`define IROM 0
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define BUS 1
|
||||
`define DCACHE 1
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||||
`define ICACHE 1
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||||
`define VIRTMEM_SUPPORTED 1
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||||
|
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@ -53,8 +53,7 @@
|
||||
// LSU microarchitectural Features
|
||||
`define DMEM 0
|
||||
`define IROM 0
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
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||||
`define VIRTMEM_SUPPORTED 1
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||||
|
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@ -53,8 +53,7 @@
|
||||
// LSU microarchitectural Features
|
||||
`define DMEM 1
|
||||
`define IROM 1
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define BUS 0
|
||||
`define DCACHE 0
|
||||
`define ICACHE 0
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||||
`define VIRTMEM_SUPPORTED 0
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||||
|
||||
@ -366,52 +366,52 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VI
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||
@ -461,14 +461,14 @@ add wave -noupdate -group sdc /testbench/dut/SDCCmdOut
|
||||
add wave -noupdate -group sdc /testbench/dut/SDCCmdOE
|
||||
add wave -noupdate -group sdc /testbench/dut/SDCDatIn
|
||||
add wave -noupdate -group sdc /testbench/dut/SDCCLK
|
||||
add wave -noupdate -group sdc -color Gold -label {cmd fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc -color Gold -label {dat fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc -color Gold -label {clk fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_CLK
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/o_CLK
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/slow_clk_divider/i_RST
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_TIMER_OUT
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/TIMER_OUT_GT_ZERO
|
||||
add wave -noupdate -group sdc -color Gold -label {cmd fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc -color Gold -label {dat fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc -color Gold -label {clk fsm} /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/i_CLK
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/o_CLK
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/slow_clk_divider/i_RST
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/i_TIMER_OUT
|
||||
add wave -noupdate -group sdc /testbench/dut/uncore/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/TIMER_OUT_GT_ZERO
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 5} {2668546 ns} 1} {{Cursor 2} {2003 ns} 1} {{Cursor 3} {16308899 ns} 0}
|
||||
quietly wave cursor active 3
|
||||
|
||||
@ -420,27 +420,27 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
||||
|
||||
@ -56,7 +56,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} else {
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
|
||||
|
||||
@ -57,7 +57,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
#run 100 ns
|
||||
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
#force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
run 14000 ms
|
||||
#add log -recursive /*
|
||||
#do linux-wave.do
|
||||
@ -109,7 +109,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
#-- Run the Simulation
|
||||
# run 100 ns
|
||||
# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
# force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
# add log -recursive /*
|
||||
# do linux-wave.do
|
||||
# run -all
|
||||
|
||||
@ -41,9 +41,9 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate /testbench/InstrMName
|
||||
add wave -noupdate /testbench/dut/uncore/ram/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
|
||||
add wave -noupdate /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate -radix hexadecimal /testbench/PCW
|
||||
add wave -noupdate /testbench/InstrWName
|
||||
@ -1295,266 +1295,266 @@ add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATAIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWRITE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSIZE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HBURST
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HPROT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HTRANS
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HMASTLOCK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATAEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADY
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/DataAccessFaultM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/TimerIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/SwIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsIn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsOut
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/GPIOPinsEn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSin
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTSout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/PreHSELUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HSELUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HRESPUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HREADYUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRW
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWtim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWclint
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWgpio
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/MemRWuart
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/UARTIntr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/timdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clintdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpiodec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uartdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HRDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HSIZE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HWDATAIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HalfwordM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/WriteDataSubwordDuplicated
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteMaskM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/MemRWtim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HSELTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HRESPTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADYTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/busycount
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MemRWclint
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HREADCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESPCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HREADYCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/TimerIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/SwIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MTIMECMP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MTIME
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MSIP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/MemRWgpio
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HREADGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HRESPGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/HREADYGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsIn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsOut
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/GPIOPinsEn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/INPUT_VAL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/INPUT_EN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_EN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/OUTPUT_VAL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/gpio/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MemRWuart
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HREADUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HRESPUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/HREADYUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/SIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DSRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DCDb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/CTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RIb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/SOUT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/DTRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/OUT1b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/OUT2b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/INTR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/TXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/RXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/A
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/MEMWb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Din
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/Dout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/BAUDOUTb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/A
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Din
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/Dout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MEMWb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/INTR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/BAUDOUTb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DTRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/OUT1b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/OUT2b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RBR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/FCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/LCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/LSR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/IER
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MSR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/MCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SINd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SINsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DSRb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DCDb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/CTSb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RIb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/SOUTbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/loop
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/DLAB
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbaudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbaudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/baudcount
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoversampledcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txoversampledcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsreceived
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitssent
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstate
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txstate
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxshiftreg
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohead
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotail
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifohead
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifotail
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggerlevel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoentries
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoentries
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbitsexpected
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txbitsexpected
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/RXBR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxtimeoutcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxcentered
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparity
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparitybit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxstopbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxparityerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxoverrunerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxframingerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxbreak
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifohaserr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdataready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifoempty
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotriggered
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifotimeout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfifodmaready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata9
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxerrbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxfullbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/TXHR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/nexttxdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txnextbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txhrfull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txsrfull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txparity
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifoempty
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifofull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txfifodmaready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/fifoenabled
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/fifodmamodesel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/evenparitysel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxlinestatusintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/rxdataavailintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/txhremptyintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/modemstatusintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/intrpending
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uart/u/intrid
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATAIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWRITE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSIZE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HBURST
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HPROT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HTRANS
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HMASTLOCK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATAEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPEXT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADY
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/DataAccessFaultM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/TimerIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/SwIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsIn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsOut
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsEn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSin
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/PreHSELUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRW
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWtim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWclint
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWgpio
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWuart
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTIntr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Base
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Range
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HSEL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/match
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HRDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HSIZE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATAIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HalfwordM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/WriteDataSubwordDuplicated
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteMaskM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/MemRWtim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HSELTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESPTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADYTim
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/busycount
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MemRWclint
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESPCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADYCLINT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/TimerIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/SwIntM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIMECMP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIME
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MSIP
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/MemRWgpio
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESPGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADYGPIO
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsIn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsOut
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsEn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_VAL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_EN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_EN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_VAL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/entry
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memread
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memwrite
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MemRWuart
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HADDR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HWDATA
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESPUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADYUART
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DSRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DCDb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/CTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RIb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SOUT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DTRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT1b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT2b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/INTR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/TXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/A
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMWb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Din
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Dout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/BAUDOUTb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HRESETn
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/A
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Din
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Dout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMWb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/INTR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXRDYb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/BAUDOUTb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RCLK
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SIN
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUT
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RTSb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DTRb
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT1b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT2b
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RBR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/FCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LSR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLL
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/IER
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MSR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MCR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbd
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbsync
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb2
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUTbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/loop
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLAB
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbaudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbaudpulse
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudcount
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoversampledcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txoversampledcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsreceived
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitssent
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstate
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txstate
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxshiftreg
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohead
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotail
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifohead
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifotail
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggerlevel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoentries
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoentries
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsexpected
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitsexpected
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXBR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxtimeoutcnt
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxcentered
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparity
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparitybit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstopbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparityerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoverrunerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxframingerr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbreak
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohaserr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoempty
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggered
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotimeout
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifodmaready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata9
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxerrbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfullbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXHR
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/nexttxdata
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txnextbit
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhrfull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsrfull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txparity
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoempty
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifofull
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifodmaready
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifoenabled
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifodmamodesel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/evenparitysel
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxlinestatusintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataavailintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhremptyintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/modemstatusintr
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrpending
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrid
|
||||
add wave -noupdate -radix hexadecimal /testbench/it/clk
|
||||
add wave -noupdate -radix hexadecimal /testbench/it/reset
|
||||
add wave -noupdate -radix hexadecimal /testbench/it/FlushE
|
||||
|
||||
@ -52,9 +52,9 @@ add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
@ -71,7 +71,7 @@ add wave -hex /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/ram/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCW
|
||||
@ -83,7 +83,7 @@ add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/ram/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
# appearance
|
||||
|
||||
@ -40,9 +40,9 @@ add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
@ -58,7 +58,7 @@ add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/ram/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCW
|
||||
@ -70,7 +70,7 @@ add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/ram/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
@ -36,9 +36,9 @@ add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
|
||||
@ -37,9 +37,9 @@ add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
add wave -hex /testbench/InstrW
|
||||
|
||||
@ -45,7 +45,7 @@ add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave -hex /testbench/dut/core/ieu/c/InstrValidM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/ram/memwrite
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/core/WriteDataM
|
||||
add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
|
||||
add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
|
||||
@ -102,13 +102,13 @@ add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]
|
||||
# peripherals
|
||||
add wave -divider PLIC
|
||||
add wave -hex /testbench/dut/core/priv/csr/TrapM
|
||||
add wave -hex /testbench/dut/uncore/plic/plic/*
|
||||
add wave -hex /testbench/dut/uncore/plic/plic/intPriority
|
||||
add wave -hex /testbench/dut/uncore/plic/plic/pendingArray
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray
|
||||
add wave -divider UART
|
||||
add wave -hex /testbench/dut/uncore/uart/uart/u/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*
|
||||
add wave -divider GPIO
|
||||
add wave -hex /testbench/dut/uncore/gpio/gpio/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*
|
||||
#add wave -divider
|
||||
#add wave -hex /testbench/dut/core/ebu/ebu/*
|
||||
#add wave -divider
|
||||
|
||||
@ -361,61 +361,61 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VI
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqMatrix
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/priorities_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxoverrunerr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataready
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataavailintr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/RXBR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/squashRXerrIP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||
|
||||
@ -185,12 +185,12 @@ module ifu (
|
||||
assign InstrRawF = AllInstrRawF[31:0];
|
||||
|
||||
if (`IROM) begin : irom
|
||||
irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF));
|
||||
irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
|
||||
|
||||
assign {BusStall, IFUBusRead} = '0;
|
||||
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
|
||||
end
|
||||
if (`IBUS) begin : bus
|
||||
if (`BUS) begin : bus
|
||||
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
|
||||
@ -201,7 +201,9 @@ module lsu (
|
||||
// *** becomes DTIM_RAM_BASE
|
||||
|
||||
if (`DMEM) begin : dtim
|
||||
dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM),
|
||||
dtim dtim(.clk, .reset, .LSURWM,
|
||||
.IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE),
|
||||
.TrapM, .WriteDataM(LSUWriteDataM),
|
||||
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
|
||||
|
||||
// since we have a local memory the bus connections are all disabled.
|
||||
@ -211,7 +213,7 @@ module lsu (
|
||||
assign {DCacheStallM, DCacheCommittedM} = '0;
|
||||
assign {DCacheMiss, DCacheAccess} = '0;
|
||||
end
|
||||
if (`DBUS) begin : bus
|
||||
if (`BUS) begin : bus
|
||||
localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
|
||||
@ -286,7 +286,7 @@ module wallypipelinedcore (
|
||||
|
||||
// *** Ross: please make EBU conditional when only supporting internal memories
|
||||
|
||||
if(`DBUS | `IBUS) begin : ebu
|
||||
if(`BUS) begin : ebu
|
||||
ahblite ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
|
||||
|
||||
@ -88,12 +88,13 @@ module wallypipelinedsoc (
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
|
||||
);
|
||||
|
||||
if (`BUS) begin : uncore
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP,
|
||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||
.HSELEXT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
|
||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin,
|
||||
.UARTSout, .MTIME_CLINT,
|
||||
.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
|
||||
end
|
||||
|
||||
);
|
||||
endmodule
|
||||
|
||||
@ -175,13 +175,13 @@ module testbench;
|
||||
`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
|
||||
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
|
||||
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
||||
`define UART dut.uncore.uart.uart.u
|
||||
`define UART dut.uncore.uncore.uart.uart.u
|
||||
`define UART_IER `UART.IER
|
||||
`define UART_LCR `UART.LCR
|
||||
`define UART_MCR `UART.MCR
|
||||
`define UART_SCR `UART.SCR
|
||||
`define UART_IP `UART.INTR
|
||||
`define PLIC dut.uncore.plic.plic
|
||||
`define PLIC dut.uncore.uncore.plic.plic
|
||||
`define PLIC_INT_PRIORITY `PLIC.intPriority
|
||||
`define PLIC_INT_ENABLE `PLIC.intEn
|
||||
`define PLIC_THRESHOLD `PLIC.intThreshold
|
||||
@ -422,14 +422,14 @@ module testbench;
|
||||
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
|
||||
// initialize bootrom
|
||||
memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb");
|
||||
readResult = $fread(dut.uncore.bootrom.bootrom.memory.ROM,memFile);
|
||||
readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM,memFile);
|
||||
$fclose(memFile);
|
||||
// initialize RAM and ROM
|
||||
if (CHECKPOINT==0)
|
||||
memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
|
||||
else
|
||||
memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
|
||||
readResult = $fread(dut.uncore.ram.ram.memory.RAM,memFile);
|
||||
readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM,memFile);
|
||||
$fclose(memFile);
|
||||
// ---------- Ground-Zero -----------
|
||||
if (CHECKPOINT==0) begin
|
||||
@ -441,7 +441,7 @@ module testbench;
|
||||
AttemptedInstructionCount = 1; // offset needed here when running from ground zero
|
||||
// ---------- Checkpoint ----------
|
||||
end else begin
|
||||
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.memory.RAM);
|
||||
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
|
||||
traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
|
||||
interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r");
|
||||
@ -568,7 +568,7 @@ module testbench;
|
||||
if(textM.substr(0,5) == "rdtime") begin \
|
||||
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
|
||||
if(!NO_SPOOFING) \
|
||||
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
|
||||
force dut.uncore.uncore.clint.clint.MTIME = ExpectedRegValueM; \
|
||||
end \
|
||||
end \
|
||||
end \
|
||||
@ -645,7 +645,7 @@ module testbench;
|
||||
if(textW.substr(0,5) == "rdtime") begin
|
||||
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
|
||||
if(!NO_SPOOFING)
|
||||
release dut.uncore.clint.clint.MTIME;
|
||||
release dut.uncore.uncore.clint.clint.MTIME;
|
||||
end
|
||||
//if (ExpectedIEUAdrM == 'h10000005) begin
|
||||
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount);
|
||||
@ -840,7 +840,7 @@ module testbench;
|
||||
PAdr = BaseAdr + (VPN[i] << 3);
|
||||
// ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
|
||||
// by 3 (the PTE size) to get the requested 64-bit PTE.
|
||||
PTE = dut.uncore.ram.ram.memory.RAM[PAdr >> 3];
|
||||
PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3];
|
||||
PTE_R = PTE[1];
|
||||
PTE_X = PTE[3];
|
||||
if (PTE_R | PTE_X) begin
|
||||
|
||||
@ -214,7 +214,7 @@ logic [3:0] dummy;
|
||||
// the design.
|
||||
if (TEST == "coremark")
|
||||
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
|
||||
dut.uncore.ram.ram.memory.RAM[i] = 64'h0;
|
||||
dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
|
||||
|
||||
// read test vectors into memory
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
@ -223,18 +223,18 @@ logic [3:0] dummy;
|
||||
else pathname = tvpaths[1]; */
|
||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
if (TEST == "fpga") begin
|
||||
if (`FPGA) begin
|
||||
string romfilename, sdcfilename;
|
||||
romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
||||
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
||||
$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM);
|
||||
$readmemh(romfilename, dut.wallypipelinedsoc.uncore.uncore.bootrom.bootrom.memory.RAM);
|
||||
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
||||
// force sdc timers
|
||||
force dut.uncore.sdc.SDC.LimitTimers = 1;
|
||||
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
||||
end else begin
|
||||
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
|
||||
else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
|
||||
if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
|
||||
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
||||
else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
|
||||
end
|
||||
|
||||
if (riscofTest) begin
|
||||
@ -261,7 +261,7 @@ logic [3:0] dummy;
|
||||
end
|
||||
|
||||
logic [`XLEN-1:0] debugmemoryadr;
|
||||
// assign debugmemoryadr = dut.uncore.ram.ram.memory.RAM[5140];
|
||||
// assign debugmemoryadr = dut.uncore.uncore.ram.ram.memory.RAM[5140];
|
||||
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
@ -328,8 +328,8 @@ logic [3:0] dummy;
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
logic [`XLEN-1:0] sig;
|
||||
if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i];
|
||||
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i];
|
||||
if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
|
||||
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
|
||||
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
|
||||
if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
errors = errors+1;
|
||||
@ -360,10 +360,10 @@ logic [3:0] dummy;
|
||||
//pathname = tvpaths[tests[0]];
|
||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
//$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
|
||||
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
|
||||
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
|
||||
if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
|
||||
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
||||
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
|
||||
|
||||
if (riscofTest) begin
|
||||
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
|
||||
@ -459,8 +459,8 @@ module riscvassertions;
|
||||
// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
|
||||
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
//assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
|
||||
//assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
|
||||
//assert (`DCACHE == 1 & `BUS ==0) else $error("Dcache requires DBUS.");
|
||||
//assert (`ICACHE == 1 & `BUS ==0) else $error("Icache requires IBUS.");
|
||||
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user