diff --git a/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do b/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do index a932cc05b..e6e158ebd 100644 --- a/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do +++ b/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do @@ -27,7 +27,8 @@ vlib work_$2 # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -# default to config/rv64ic, but allow this to be overridden at the command line. For example: +# default to config/rv64icfd, but allow this to be overridden at the command line. For example: +# do wally-pipelined-batch.do ../config/rv32ic rv32ic switch $argc { 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} @@ -37,6 +38,13 @@ switch $argc { # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt work_$2.testbench -work work_$2 -o workopt_$2 vsim -lib work_$2 workopt_$2 +# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time +#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf +#vsim -coverage -lib work_$2 workopt_$2 run -all +#coverage report -file wally-pipelined-coverage.txt +# These aren't doing anything helpful +#coverage report -memory +#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 quit diff --git a/wally-pipelined/regression/wally-pipelined-rv64icfd.do b/wally-pipelined/regression/wally-pipelined-rv64icfd.do index 9d8ff5c67..39f62903f 100644 --- a/wally-pipelined/regression/wally-pipelined-rv64icfd.do +++ b/wally-pipelined/regression/wally-pipelined-rv64icfd.do @@ -27,7 +27,7 @@ vlib work # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -# default to config/rv64ic, but allow this to be overridden at the command line. For example: +# default to config/rv64icfd, but allow this to be overridden at the command line. For example: # do wally-pipelined.do ../config/rv32ic switch $argc { 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} diff --git a/wally-pipelined/src/fpu/FMA/tbgen/results.dat b/wally-pipelined/src/fpu/FMA/tbgen/results.dat deleted file mode 100644 index e69de29bb..000000000 diff --git a/wally-pipelined/src/fpu/FMA/tbgen/results.srt b/wally-pipelined/src/fpu/FMA/tbgen/results.srt deleted file mode 100644 index 1cfac616f..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/results.srt +++ /dev/null @@ -1,934 +0,0 @@ -3fdfffffffffffff 4340000000000001 bff0000000000001 4320000000000000 432fffffffffffff Wrong 1002971 -bed003ffc0000000 c00ffdfffffefffe bf4ffffffbfffff7 bf4effd003ffc7f9 bf4f7fe7ffffe3f8 Wrong 1006999 -3fdfffffffffffff bfd0000000000000 bcafffffffffffff bfc0000000000003 bfc0000000000007 Wrong 1021097 -b92fffdfc0000000 8020000000100006 bf74cfab3bcc97f9 3f7b3054c4336807 bf74cfab3bcc97f9 Wrong 1025125 -3fdfffffffffffff bff0000000000000 3ff0000000000001 3ca8000000000000 3fe0000000000002 Wrong 1027139 -a19ffff7ff7fffff bd0e000010000000 c03ffffffbfe0000 4030000004020000 c03ffffffbfe0000 Wrong 1031167 -3fdfffffffffffff c00ffffffffffffe c340000000000000 c340000000000002 c340000000000001 Wrong 1033181 -b801eb65455027da ffefffffffffffff ffefffc000001000 7fe0003ffffff000 ffefffc000001000 Wrong 1041237 -3f700000003fdfff bca0000000007fdf bf50400000007fff bf50400000008003 bf50400000008001 Wrong 1043251 -c12bffffffffffbe 8000000000000000 c3c0000000000000 43c0000000000000 c3c0000000000000 Wrong 104727 -3fab095e19bc680a 3fe0000000000000 be74000000010000 3f9b095b99bc680a 3f9b095919bc680a Wrong 1059363 -c040010000020000 bff00000100000fe 3fd5ca5e3cb16df4 404016ca6e3fb26c 40402c94cc7c63da Wrong 1073461 -3fdffffffffffffe 7fe0000000000001 3ff0000000000001 7fc0000000000000 7fd0000000000000 Wrong 1075475 -403000200001ffff 43effffffffffffe c1eff7dfffffffff 443000200001801e 443000200001003f Wrong 1079503 -b8bffffffff00040 bcaffffffffffffe c29d554ac7605657 4292aab5389fa9a9 c29d554ac7605657 Wrong 1089573 -36e00000000fff00 3fe0000100000006 c3fffefe00000000 43f0010200000000 c3fffefe00000000 Wrong 1091587 -3fdffffffffffffe bfe0000000000000 3cafffffffffffff bfcffffffffffffa bfcffffffffffff6 Wrong 1093601 -bce000000001fc00 3ff80cabb0668b82 b9fffffffcffffff bce80cabb0698734 bce80cabb0698754 Wrong 1097629 -3fdffffffffffffe bffffffffffffffe bff0000000000001 bff7fffffffffffe bfffffffffffffff Wrong 1099643 -3fdffffffffffffe c01ffffffffffffe 4340000000000000 c340000000000004 433ffffffffffffc Wrong 1105685 -b80fffffffff001e 593ffc07ffffffff 41c00000000007ef d15ffc07ffff003c d15ffc07ffff003d Wrong 1115755 -47effff100000000 0010000000000001 bfbfffbfffffffbf 3fb0004000000041 bfbfffbfffffffbf Wrong 1119783 -3fe0000000000000 3cafffffffffffff 3ff0000000000001 3ff0000000000002 3ff0000000000001 Wrong 1123811 -3fe0000000000000 3fe0000000000001 c340000000000000 4340000000000000 c340000000000000 Wrong 1129853 -c1f000000401ffff 3ff0000000000000 41d0060da9f8c199 c1ebfe7c9d85cf98 c1e7fcf933079f32 Wrong 1131867 -400fffff7f800000 4010000000000000 3fe0000000400000 40303fffbfc10000 40307fffbfc20000 Wrong 1137909 -2a50000000107fff 434ffffffffffffe c32ffffe01000000 43200001ff000000 c32ffffe01000000 Wrong 1143951 -3fe0000000000000 8010000000000000 4340000000000000 c340000000000000 4340000000000000 Wrong 1154021 -c34fbffffffff7fe 40100000001fffbe 406814b7cd412dec c36fc000003f776f c36fc000003f7763 Wrong 1158049 -3fe0000000000000 bfeffffffffffffe bcafffffffffffff bfd0000000000000 bfe0000000000001 Wrong 1166105 -3fe0000000000000 c00ffffffffffffe 3ff0000000000001 bff7fffffffffffd bfeffffffffffffa Wrong 1172147 -42c008fffffffffe c0200008001fffff 43effff5ffffffff 43efffb5dbdfed7e 43efffd5edeff6bf Wrong 1176175 -3fe0000000000000 c34fffffffffffff c340000000000000 c348000000000000 c350000000000000 Wrong 1178189 -c34ffefe00000000 bc4feffffffffffd c020000000000087 c02fc02202fe0087 c01fc02202fe010e Wrong 1182217 -c0003fffffffff7f 37effffffe004000 381e29836bc8d7f8 37fbd306d9996ff2 381609836c4ac7f8 Wrong 118825 -3fe0000000000001 3fd0000000000001 bff0000000000001 bfd8000000000001 bfec000000000001 Wrong 1196315 -c65000000000003d 3fe0000000000000 c7f0008000080000 c7f0008004080000 c7f0008002080000 Wrong 1198329 -c1d000803ffffffe 3feffc00000000fe bffffffeffffefff c1cffd00607000f6 c1cffd0060f000f2 Wrong 1212427 -403fdffffe000000 c011da12116127a8 7d8bfe3fae41652f fd8401c051be9ad1 7d8bfe3fae41652f Wrong 1218469 -3f1fffff7f000000 41e007fff0000000 3faa435b79a850e6 411007ffc9a31bba 411007ffe3e67734 Wrong 1224511 -c310000040001fff bfb03ffffffffffd 41cfbfbffffffffe 42d0400830f0207c 42d0401020e0207c Wrong 1230553 -39260035abdd89ad bfefffffffffffff 41efdfbfffffffff c1e0204000000001 41efdfbfffffffff Wrong 1234581 -3fe0000000000001 bffffffffffffffe 3cafffffffffffff bfefffffffffffff bfeffffffffffffe Wrong 1238609 -3fe0000000000001 c01fffffffffffff bff0000000000001 c012000000000000 c014000000000001 Wrong 1244651 -44c4c56f2310e46d c340000000000001 6dfffffffff800ff edf000000007ff01 6dfffffffff800ff Wrong 1246665 -390067d3f6bbe86d c7c4863b5c262ee4 7fef7fffffffeffe ffe0800000001002 7fef7fffffffeffe Wrong 1248679 -ffd000407fffffff 8020fffffffe0000 404136d99d2d1461 400ab7117166a2ff 404246dde5acf460 Wrong 1254721 -3fefffffffffffff 3ca0000000000001 bcafffffffffffff 395fffffffffffff bc9ffffffffffffd Wrong 1262777 -bfd0100007ffffff 3fd297ee8e336ca8 c01000000000083e c0109554343074f9 c0104aaa1a183e9b Wrong 1266805 -3fefffffffffffff 3fe0000000000001 3ff0000000000001 3ff0000000000000 3ff8000000000001 Wrong 1268819 -3fefffffffffffff 4000000000000000 c340000000000000 4340000000000002 c33ffffffffffffe Wrong 1274861 -be5bffffffffeffe c01fffffffffffff 3ff7c1136e8aa3ca 3ff7c113de8aa3ca 3ff7c113a68aa3ca Wrong 128895 -c1d3b0ae9c0eb661 801fffffffffffff ff9bffffffffc000 7f94000000004000 ff9bffffffffc000 Wrong 1295001 -42aefffffffffbfe 4040080000040000 c0000000000087fe 42ff0f800007bbec 42ff0f800007bbdc Wrong 1297015 -3fefffffffffffff bcaffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong 1299029 -4030080004000000 bfd0000000000001 74a074eb9de02cce f4af8b14621fd332 74a074eb9de02cce Wrong 1301043 -42401ffffffffbff bfefffffffffc03f be500200000003fe c2401fffffffdbde c2401fffffffdbdf Wrong 1303057 -3fefffffffffffff c00fffffffffffff bcafffffffffffff c00ffffffffffffe c00fffffffffffff Wrong 1311113 -3feffffffffffffe 3fd0000000000001 3cafffffffffffff 3fd0000000000002 3fd0000000000004 Wrong 1335281 -439fffffff0001ff c04fffffef7fffff c1d0000000300000 c3ffffffee8201fe c3ffffffee8401ff Wrong 1339309 -3feffffffffffffe 3ff0000000000000 bff0000000000001 3fdffffffffffffa bcc0000000000000 Wrong 1341323 -3feffffffffffffe 4010000000000000 4340000000000000 4340000000000004 4340000000000002 Wrong 1347365 -002fffffffdfeffe 270010000fffffff bfffffffe000003f 3ff000001fffffc1 bfffffffe000003f Wrong 1357435 -434fe000ffffffff bca0000000000001 3fa600a985274f0b bfff87fe59eb62c5 bfff2ffbb3d6c589 Wrong 1367505 -43c567cde92a1dfd b8000203fffffffe 3ee00000007fdfff 3ee00000007fdfea 3ee00000007fdff4 Wrong 1369519 -3feffffffffffffe ffe0000000000001 bff0000000000001 ffd0000000000000 ffe0000000000000 Wrong 1389659 -41f000007ffffbfe 3fef177822a30420 c0a0001040000000 41ef17789b5e3b6b 41ef17781b5db96b Wrong 1393687 -3ff0000000005000 00100001f0000000 c3f5cfc170570406 43fa303e8fa8fbfa c3f5cfc170570406 Wrong 1399729 -42c2000001ffffff 3caffffffffffffe 3fdff80000002000 3fd1180000202000 3fe0440000081000 Wrong 1403757 -4010000007f7fffe 8029b242064ab31e 3fbfffff001ffffe bfb00000ffe00002 3fbfffff001ffffe Wrong 1405771 -3ff0000000000000 3fe0000000000000 bcafffffffffffff 3fdffffffffffffe 3fdffffffffffffc Wrong 1407785 -3ff0000000000000 4000000000000000 3ff0000000000001 4004000000000000 4008000000000000 Wrong 1413827 -c02ce0c00cac853f 400fffffffffffff c36fffc0000ffffe c36fffc00010000c c36fffc000100005 Wrong 1415841 -3ff0000000000000 401ffffffffffffe c340000000000000 c34ffffffffffff8 c33ffffffffffff8 Wrong 1419869 -3ff0000000010006 8010000000000001 801f7fffffffffff 801fc00000010006 8027c00000008003 Wrong 1433967 -3ff0000000000000 bcafffffffffffff bff0000000000001 bff0000000000003 bff0000000000002 Wrong 1437995 -3ff0000000000000 bfefffffffffffff 4340000000000000 c340000000000001 433fffffffffffff Wrong 1444037 -3ff0000000000001 0010000000000000 c340000000000000 4340000000000000 c340000000000000 Wrong 1468205 -423fdfc000000000 3ca0000000000001 c00584e2101be3ef c00584d2203be3ef c00584da182be3ef Wrong 147021 -bf71bfb471d6b240 c3cefffffffffff7 41ffffc000000001 435131b70e477ca9 435131b74e46fca9 Wrong 1478275 -3ff0000000000001 3ff0000000000000 3cafffffffffffff 3ff0000000000001 3ff0000000000002 Wrong 1480289 -3ff0000000000001 400ffffffffffffe bff0000000000001 400c000000000000 4007ffffffffffff Wrong 1486331 -3d80000800003fff 401fffffffffffff 3b40000000000037 3db0000800004ffe 3db0000800005ffe Wrong 1488345 -c03c54bd6921b05d c02fe007ffffffff c0020b6d2412fdf2 407c266453c3d5f6 407c1458e69fc2f8 Wrong 149035 -3ff0000000000001 434ffffffffffffe 4340000000000000 4354000000000000 4358000000000000 Wrong 1492373 -8ea000800007fffe 7fe0000000000001 cc6000000200000f ce9000800008ffff ce9000800009ffff Wrong 1494387 -4000010000000000 bbb3ffffdfffffff 3fd4000000000000 bfdc000000000000 3fd4000000000000 Wrong 1496401 -bddfff81ffffffff bf4ffffffff7ffbe 0ceffedffffffffe 3d3fff81fff7ffdc 3d3fff81fff7ffdd Wrong 1502443 -3ff0000000000001 bfdfffffffffffff 3ff0000000000001 3c90000000000001 3fe0000000000002 Wrong 1510499 -41f03fffbfffffff c340000000000000 5a2ffdfbfffffffe da20020400000002 5a2ffdfbfffffffe Wrong 1524597 -375fe20000000000 3fe0000000000001 b46ffffffffe0010 374fe1ffffffffc2 374fe1ffffffff82 Wrong 153063 -bf7107ffffffffff 3fdeffffffffdfff c02010000ffffffe c020121007fffffc c02011080bfffffd Wrong 1532653 -bff000403fffffff 3fdf3e0be31ebee9 b802c73b4852e1e1 bfdf3e8958467aee bfdf3e8958467aef Wrong 1538695 -3fc0fffffffffff7 3cafffffffffffff bf8011ffffffffff bf8011ffffffffdd bf8011ffffffffee Wrong 1542723 -37ffffff00000006 c7e00001ffffffde 41c795c3980a9c95 41c795c3970a9c7d 41c795c3978a9c89 Wrong 1544737 -403fffffe001ffff 3e5daa9beba734ca 4023fe0e11be1e1e 4023fe0e4d1355ba 4023fe0e2f68b9ec Wrong 155077 -41fffff7ffbffffe 400fffffffffffff bf59af9a3b538749 421ffff7ffbfff30 421ffff7ffbffe62 Wrong 1554807 -4e5f3dce4e5c17a8 aeea7c211e03a2ce c00001effffffffe c00001f000000675 c00001f000000339 Wrong 1556821 -3fffffffffffffff 401ffffffffffffe 3ff0000000000001 40307ffffffffffe 4030ffffffffffff Wrong 1558835 -3fffffffffffffff bcafffffffffffff 3cafffffffffffff bcb7fffffffffffe bcaffffffffffffd Wrong 1576961 -3fffffffffffffff bfe0000000000001 bff0000000000001 bff8000000000001 c000000000000001 Wrong 1583003 -3fdfffffffffdff7 bff0000000000000 bfb503dcf633da77 bfe1503dcf632da3 bfe2a07b9ec66b4a Wrong 1585017 -3fffffffffffffff c000000000000001 4340000000000000 434ffffffffffffc 433ffffffffffffc Wrong 1589045 -40e200000000003f 4000000000000000 41cffffffffffdfe 41c0011ffffffdfe 41d00047fffffeff Wrong 159105 -3ffffffffffffffe 3caffffffffffffe c340000000000000 4340000000000000 c340000000000000 Wrong 1613213 -bfb0200001000000 3fffffffffffffff 3ec000000007fff7 bfc01ff800fffffb bfc01ff000fffff7 Wrong 1621269 -c3e76f2c56d0d8d0 c04fc00000000020 42ef800000000007 4447404e3d233736 4447404e7c233736 Wrong 1623283 -401fffffdeffffff 4010000000000001 3fdc00000fffffff 40401bffef900000 404037ffefa00000 Wrong 1627311 -bca0000dffffffff b8500000000fffee 36c9b3089edd6940 36c9b308a0dd6b00 36c9b3089fdd6a20 Wrong 1635367 -3ffffffffffffffe bfd0000000000001 bcafffffffffffff bfe0000000000001 bfe0000000000002 Wrong 1649465 -c3f23b5d47b0fea9 bfe0000000000000 d9ffffffffffdfff 59f0000000002001 d9ffffffffffdfff Wrong 1651479 -3ffffffffffffffe bff0000000000001 3ff0000000000001 bff7ffffffffffff bfeffffffffffffe Wrong 1655507 -3ffffffffffffffe c010000000000000 c340000000000000 c340000000000008 c340000000000004 Wrong 1661549 -bfbf80000001ffff 3f3fffffffefffdf 3fc573070215e3ae 3fc56f170215e566 3fc5710f0215e48a Wrong 1665577 -ba5bfffffffbffff c3eff8f4a38946a4 c03fffffbfffc000 c03fffffbf1ff150 c03fffffbf8fd8a8 Wrong 167161 -3eeffffffffffbfe bfa78bde48d46ae7 be6413896ff4d5bd bea82c7a94540ea2 bea8cd16dfd3b550 Wrong 1677661 -47f0000002000000 3cafffffffffffff c5fffdffffffe000 c5fffdfdffffdfc0 c5fffdfeffffdfe0 Wrong 1681689 -4000000000000000 3fdffffffffffffe 4340000000000000 4340000000000001 4340000000000000 Wrong 1685717 -becffffff8000003 2eb5b3f4af3d7bf6 41307fffffffffbf c13f800000000041 41307fffffffffbf Wrong 1695787 -bfd0fffff7ffffff 4340000000000001 c0b0002000001ffe c320fffff8001000 c320fffff8002000 Wrong 1699815 -c0332683837ce949 c0f000000800ffff 41e0000000000fff 41e004c9a0e35456 41e00264d071b22b Wrong 1713913 -4000000000000000 c000000000000000 bff0000000000001 c012000000000000 c014000000000000 Wrong 1728011 -50aafe7c26407d06 3ffdfff7ffffffff 0e058c435455cc58 50b94e8da43d6ba4 50b94e8da43d6ba5 Wrong 173203 -c1df000000004000 3e46552ef24d77ca 402403ffffffffff c030a1857abb38b6 c027410af576716d Wrong 1732039 -4000000000000000 c340000000000000 4340000000000000 c348000000000000 c340000000000000 Wrong 1734053 -bd6ffff800000040 c34fffffffffffff c06ffffffa000000 40cfbff8000c003f 40cf7ff80018003f Wrong 1736067 -c340000000004100 001fffffffffffff 3fb9f4a28a317ba3 bfb60b5d75ce845d 3fb9f4a28a317ba3 Wrong 1748151 -ac733af5cc6534e5 bfbfffffffffe003 be7fffffff800040 3e700000007fffc0 be7fffffff800040 Wrong 1750165 -4000000000000001 3caffffffffffffe 3ff0000000000001 3ff0000000000005 3ff0000000000003 Wrong 1752179 -c34407ffffffffff 3fd0000000000001 434ee78a270158c4 4334e38a270158c4 4349e58a270158c4 Wrong 1754193 -bef0000040002000 c00fffdffffeffff 3f94c3676ce5c5c1 3f94e3674d65c481 3f94d3675d25c521 Wrong 1756207 -4000000000000001 3fefffffffffffff c340000000000000 4340000000000002 c33ffffffffffffe Wrong 1758221 -c3faf4d1799b420e 4010000000000001 c3335809be152176 c41af4f829aebe3a c41af51ed9c23a64 Wrong 1766277 -4020fefffffffffe c01ffffffffffffe 402fc3fffffffffe c04e057ffffffffa c04a0cfffffffffa Wrong 1768291 -4000000000000001 8010000000000001 4340000000000000 c340000000000000 4340000000000000 Wrong 1782389 -3efffffffe000040 bc1000000000207f 40effffffffdc000 c0e0000000024000 40effffffffdc000 Wrong 1786417 -3f2fffddffffffff bffffffffffffffe c1e00000001003fe c1e0000000100bfe c1e00000001007fe Wrong 1796487 -4000000000000001 c010000000000000 3ff0000000000001 c01e000000000002 c01c000000000002 Wrong 1800515 -4000000000000001 c34ffffffffffffe c340000000000000 c362000000000000 c364000000000000 Wrong 1806557 -3fd0005ffffffffe c3e411c0691b2909 c34ffffff81fffff c3c42238d399afa9 c3c43238d395bfa9 Wrong 1810585 -0000000000000000 3fffffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong 18125 -c1c01f7fffffffff c0cbfffff8000000 bfe0000002000004 429c371ff7f03efe 429c371ff7f03dfe Wrong 1816627 -400fffffffffffff 3fdfffffffffffff bff0000000000001 3ff7fffffffffffe 3feffffffffffffa Wrong 1824683 -c1c0000000000fde 3fe0000000000001 41d4cbff08b3d9b1 41b997fe1167a383 41d0cbff08b3d5b9 Wrong 1826697 -b8d3ffffff000000 c3d5607787b731da ffdffffffffffffe 7fd0000000000002 ffdffffffffffffe Wrong 1828711 -400fffffffffffff 3fffffffffffffff 4340000000000000 4340000000000008 4340000000000004 Wrong 1830725 -c03f8000000000fe 4340000000000000 c1c0040000000007 c38f8000008020fe c38f8000010040fe Wrong 1838781 -c03100000001ffff bfeffffffffffffe 414fffff800fffff 4140001080100001 4150000400080000 Wrong 1862949 -402fffffe0040000 c3ea62add43fe399 c3d000001e000000 c42aa2adba58821a c42ae2adbad0821a Wrong 1864963 -4050000090000000 c00fffffffffffff 40bfffffffffbffe 40bdffffedffbffe 40befffff6ffbffe Wrong 1868991 -400fffffffffffff c01ffffffffffffe bff0000000000001 c0403ffffffffffe c0407fffffffffff Wrong 1873019 -c0377bbf63a456e8 c34fffffffffffff c0bfffffff7fefff 43977bbf63a456a7 43977bbf63a45667 Wrong 1875033 -400ffffffffffffe 3cafffffffffffff bcafffffffffffff 3ccbfffffffffffd 3cc7fffffffffffd Wrong 1891145 -3ff0000007c00000 3fd0000000000001 c02fffffffff3fff c02effffff833fff c02f7fffffc13fff Wrong 1893159 -400ffffffffffffe 3fefffffffffffff 3ff0000000000001 4011fffffffffffe 4013ffffffffffff Wrong 1897187 -bcdfffffffff7bfe 3ff0000000000000 be200ffffffffff6 be201001fffffff6 be201000fffffff6 Wrong 1899201 -400ffffffffffffe 4000000000000001 c340000000000000 c34ffffffffffff8 c33ffffffffffff8 Wrong 1903229 -c1d0000007fffeff c07fffffff03ffff bfdffffffffe7ffe 426000000781f6fe 426000000781eefe Wrong 1913299 -c013a5cd955a8eca 3e007fffff7fffff 3b0059c22188f0f5 be2442fc016834d0 be2442fc016834ce Wrong 1919341 -c02ffbfffffffbff 801ffffffffffffe c7eff7fffbffffff 47e0080004000001 c7eff7fffbffffff Wrong 1923369 -400ffffffffffffe bfd0000000000000 4340000000000000 c340000000000001 433fffffffffffff Wrong 1927397 -c030000000107ffe bfffffffffffffff c3c0800000002000 43cf7fffffffe000 c3c0800000002000 Wrong 1935453 -41c00000000fffef c01fffffffffffff 40700007fffbfffe c1effffff01ff7dd c1efffffe01fefdd Wrong 1941495 -bfe8f26bc072a863 b81ffffffff00000 381000020fffffff 3820793664331796 38247936e8331796 Wrong 1949551 -4010000000000000 3fdfffffffffffff 3cafffffffffffff 3fffffffffffffff 4000000000000000 Wrong 1963649 -4010000000000000 3ff0000000000001 bff0000000000001 400c000000000002 4008000000000002 Wrong 1969691 -3fdfffbffffffffa 4000000000000000 400080003fffffff 40003ff01ffffffe 40087ff03ffffffe Wrong 1971705 -401efffffffbffff 400c000000000fff 3fee5f5b0ddd3442 403b997d6c34044f 403c12fad86b7920 Wrong 1973719 -4010000000000000 4010000000000001 4340000000000000 4340000000000010 4340000000000008 Wrong 1975733 -381f8007fffffffe 401ffffffffffffe c3fffffefffc0000 43f0000100040000 c3fffffefffc0000 Wrong 1977747 -4010000000000000 bca0000000000000 3ff0000000000001 3ffffffffffffffd 3feffffffffffffe Wrong 1993859 -4010000000000000 bfdffffffffffffe c340000000000000 c340000000000002 c340000000000001 Wrong 1999901 -41c0007ffc000000 3c4ff80000001fff c49ef96d79f85b02 449106928607a4fe c49ef96d79f85b02 Wrong 2028097 -3f8cd1cdc67650ea c017effffffffffe 43cffdefffffffff c3c0021000000001 43cffdefffffffff Wrong 203413 -c1c1ffffffffffbf c1f20000000007fe beefdfffffffffef 43c44000000008b4 43c44000000008b5 Wrong 2040181 -4010000000000001 4000000000000001 3ff0000000000001 4021000000000002 4022000000000002 Wrong 2042195 -4010000000000001 4340000000000000 c340000000000000 435c000000000002 4358000000000002 Wrong 2048237 -4010000000000001 8010000000000000 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 2060321 -47f422d15fbfc2a7 c04000001fc00000 7fdffeffffbfffff ffd0010000400001 7fdffeffffbfffff Wrong 2064349 -4010000000000001 bcaffffffffffffe bff0000000000001 bff0000000000009 bff0000000000005 Wrong 2066363 -4010000000000001 bfeffffffffffffe 4340000000000000 434ffffffffffffc 433ffffffffffffc Wrong 2072405 -3fafffff00040000 41c000000000007f 3fb6225da8dafef7 417fffff00b513eb 417fffff016626d9 Wrong 2076433 -3fdfff80007fffff c010000000000001 c000000003fe0000 c007ffc0023f0000 c00fffc0043e0000 Wrong 2080461 -3fb00000000000fd 3648d98a332e5571 35080008e5baca0b 3608d9963332c9d7 3608d9a233373cb5 Wrong 2088517 -c3d39f1456976025 0000000000000000 7fefffffff7fffef ffe0000000800011 7fefffffff7fffef Wrong 2092545 -401fffffffffffff 0010000000000001 c340000000000000 4340000000000000 c340000000000000 Wrong 2096573 -be1ffff0ffffffff 3f5fffff00000000 3fcffffffdfbffff 3fcffffffdf80001 3fcffffffdfa0000 Wrong 2100601 -401fffffffffffff 3ff0000000000001 3cafffffffffffff 4020000000000000 4020000000000001 Wrong 2108657 -c00ffffffff7bffe 3ffffffffffffffe bfd47afa8ed01f9a c02051ebea37207c c020a3d7d47260fb Wrong 2110671 -401fffffffffffff 4010000000000000 bff0000000000001 403f7fffffffffff 403effffffffffff Wrong 2114699 -b810004000000010 401ffffffffffffe 403fff7ffffff000 c030008000001000 403fff7ffffff000 Wrong 2116713 -bf90b94940132032 7fefffffffffffff ffdfbfffffffdfff ffd1d72928024405 ffe065ca4a008901 Wrong 2122755 -002ffffffff7bfff b12b2946e3e0cc24 41aaea0575638d88 c1a515fa8a9c7278 41aaea0575638d88 Wrong 2124769 -c041c7dce2709a19 0010000000000001 3fcf7ffffff00000 bfc0800000100000 3fcf7ffffff00000 Wrong 213483 -401fffffffffffff bfdffffffffffffe 3ff0000000000001 c00bfffffffffffd c007fffffffffffd Wrong 2138867 -c34ff80000001000 bfe0000000000001 c3ff7efffffffffe c3ff7b00fffffffc c3ff7d007ffffffd Wrong 2140881 -400fdffe00000000 4000beb28ac6e8df c1df7ffff8000000 c1df7ffff3d4834d c1df7ffff5ea41a6 Wrong 2142895 -401fffffffffffff bfffffffffffffff c340000000000000 c340000000000010 c340000000000008 Wrong 2144909 -4020000000003fbe c000000000000001 c1cfefffffffff7f c1cff0000fffff7f c1cff00007ffff7f Wrong 2146923 -3fceb158f9d7dfa5 c340000000000001 c34c63caebfbfe18 c3104084a9c7d807 c3501cfb059b7d06 Wrong 2152965 -43fe690733095b3f 0010000000000000 9c0cf7eb74a0fe9b 1c0308148b5f0165 9c0cf7eb74a0fe9b Wrong 2165049 -b7e00001ffffff00 3caffffffffffffe b800000001ffffff b800000002000000 b800000001ffffff Wrong 2171091 -c3c03ffffffffbfe 8deffffe07ffffff ba5fdfffff7fffff 3a50200000800001 ba5fdfffff7fffff Wrong 2179147 -3fe0000ffffffffc bcae000000001ffe 0010040000000006 bc9e001e00001ff6 bc9e001e00001ff7 Wrong 2185189 -40c00007fc000000 c1cffffff8001fff bf1fff8000100000 c2a00007f8000e00 c2a00007f8000e01 Wrong 2191231 -c2700000003ff7ff 801fffffffffffff bdfffffe7ffffffe 3df0000180000002 bdfffffe7ffffffe Wrong 2201301 -401ffffffffffffe bcaffffffffffffe 3cafffffffffffff bcddfffffffffffc bcdbfffffffffffc Wrong 2205329 -3fc013ffffffffff 3fc000000ffffefe bfedffffffffdfff bfecfebffefea00f bfed7f5fff7f4007 Wrong 2209357 -401ffffffffffffe bfefffffffffffff bff0000000000001 c020fffffffffffe c021ffffffffffff Wrong 2211371 -38d407fffffffffe bff0000000000001 47efffffffdfdffe c7e0000000202002 47efffffffdfdffe Wrong 2213385 -bd6800000007ffff c3d8a89c08d5d92c 4000040000000800 41527e7546b68d07 41527e7586c68d07 Wrong 2215399 -401ffffffffffffe c00fffffffffffff 4340000000000000 434fffffffffffe0 433fffffffffffe0 Wrong 2217413 -c010140b934d5ff7 c03f80000003ffff c00fffffff0fffff 405f2776ca0819f0 405ea776ca0bd9f0 Wrong 2227483 -c1d000000000203f 001ffffffffffffe 001ffffffffff7bf 81ffffffffc0407c 81ffffffff80407c Wrong 2237553 -4340000000000000 3fd0000000000000 c340000000000000 c320000000000000 c338000000000000 Wrong 2241581 -3febffffffdffffe c3b0080000000fff c3f0000002000002 c3f1c0e001fe00c2 c3f0e07001ff0062 Wrong 2251651 -43dc9799aeac7b3a 3ff0000000000000 c0fff7ffffffffff 43dc9799aeac7afa 43dc9799aeac7aba Wrong 225567 -41f00000fc000000 401fffffffffffff 4366fe581a30b534 4366fe5a1a30d4b4 4366fe591a30c4f4 Wrong 2255679 -9f4ee4bea2031544 d8e0000200fffffe bfeffff00fffffff 3fe0000ff0000001 bfeffff00fffffff Wrong 2281861 -4340000000000000 c010000000000001 c340000000000000 c362000000000001 c364000000000001 Wrong 2289917 -434f8da321556224 c01b2588e50183be 427142efd04a8c6b c37ac47bc30b10c8 c37ac473219328a3 Wrong 2306029 -4340000000000001 3ca0000000000000 bff0000000000001 3fe0000000000001 0000000000000000 Wrong 2308043 -4000001000000020 c1f1000000000004 6a4fffffffdffff7 ea40000000200009 6a4fffffffdffff7 Wrong 2312071 -4340000000000001 3fe0000000000000 4340000000000000 4340000000000000 4348000000000000 Wrong 2314085 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-c1f0001fffff7ffe 3fffffffffffffff 4020000000043fff c200001fffdf7ffd c200001fffbf7ffd Wrong 2388603 -42a0020000000007 bdafe01fffffffff 3ff000000021ffff c05fc41c03ffbc0d c05fa41c03ff780d Wrong 2396659 -400c1d1b46e04d2b be4e00000000001f c02f7fff00000000 c02f7fff034b6932 c02f7fff01a5b499 Wrong 2402701 -bc1c9a8f60ba2ec4 413000000020ffff 3fe0000e00000000 3fe0000dffffe365 3fe0000dfffff1b3 Wrong 2408743 -434fffffffffffff 801fffffffffffff 4340000000000000 c340000000000000 4340000000000000 Wrong 2410757 -c2400fffffffff7f bca0000000000000 4017fffffffffff7 4018000807fffff7 4018000403fffff7 Wrong 2412771 -7f600000fbffffff c024153a49a4352e b2a0000000200002 ff94153b85f28b34 ff94153b85f28b35 Wrong 2414785 -c1ffffffffff3fff bfe0000000000000 c01fffffffe00000 41efffffff7f3fff 41effffffeff3fff Wrong 2418813 -3ecffffffffe0000 3fc0fff800000000 c0d00010000007fe c0d0000ffffbc800 c0d0000ffffde7ff Wrong 2420827 -bfdc000000080000 bfbfffffffffefe0 c035edb781f59599 c035d1b781f58da7 c035dfb781f591a0 Wrong 2426869 -434ffffffffffffe 3ca0000000000000 3cafffffffffffff 3ffffffffffffffe 3fffffffffffffff Wrong 2447009 -c06321ec0ecef83a 3cafffffffffffff 43dfffffffefff7f c3d0000000100081 43dfffffffefff7f Wrong 2449023 -434ffffffffffffe 3fdffffffffffffe bff0000000000001 433ffffffffffffc 433ffffffffffffb Wrong 2453051 -bcaffc0000000ffe c0100000001ffffb bfcffff7ffffbffe bfcffff7ffffbfbe bfcffff7ffffbfde Wrong 245707 -434ffffffffffffe 3ffffffffffffffe 4340000000000000 4361fffffffffffe 4363fffffffffffe Wrong 2459093 -c34ffffffffffc00 bbe000000000027f 43dfffffeffffbff 43d487c0c983e604 43dfffffeffffbff Wrong 2469163 -c017ff8000000000 8010000000000000 bfcfffffff820000 3fc00000007e0000 bfcfffffff820000 Wrong 2479233 -434ffffffffffffe bca0000000000001 c340000000000000 c340000000000002 c340000000000001 Wrong 2483261 -c0effaffffffffff 3f1ffbfffffffdff bfc929330a6f28fb c0202dd2b614dd51 c02060251c29bba3 Wrong 2487289 -bff007f7ffffffff bff0000000000000 3ed10000007ffffe 3ff007fa2000000f 3ff007fc4000001f Wrong 2491317 -401ffffffbfffbff 3fbfffef80000000 c00000400000007f bf121080005ddfbe bff00088420001f6 Wrong 2493331 -434ffffffffffffe c000000000000001 3cafffffffffffff c350000000000000 c360000000000000 Wrong 2495345 -bf3fffffdc000000 c00ffffffffffffe bef00000000043fe 3f5fdfffdbffff76 3f5fbfffdbfffeee Wrong 2497359 -0f2fdfefffffffff 3a7ffffffdff7fff c09c6db48153d631 4093924b7eac29cf c09c6db48153d631 Wrong 2499373 -41d47345faf3a236 bca000effffffffe 401e32064ec9ba5f 401e32063a5541a3 401e3206448f7e01 Wrong 2505415 -445ff7ffefffffff 3fdfffffffffffff 41efeffffffffff6 444ff7fff0003fde 444ff7fff0007fbe Wrong 2521527 -c01010001fffffff 3ff0000000000001 43ffffffffe1fffe c3f00000001e0002 43ffffffffe1fffe Wrong 2527569 -c1b00800ffffffff c076927c86fdafbf bf80001effffffff 42369dc72e68f605 42369dc72e68f505 Wrong 2547709 -7fe0000000000000 8010000000000001 bff0000000000001 c004000000000001 c008000000000002 Wrong 2549723 -403000000000080e bfdfffffffffffff c05dfff800000000 c00fff8000002036 c05ffff800000102 Wrong 255777 -7fe0000000000001 3fdffffffffffffe 3cafffffffffffff 7fc0000000000000 7fd0000000000000 Wrong 2592017 -3fb00000000ffffe 3fe0000000000001 413001ffdfffffff 413001ffefffffff 413001ffe7ffffff Wrong 2594031 -412007fffeffffff bfffffffffffffff 4012000040000000 c13007fdbefff7fe c13007fb7effeffe Wrong 261819 -3fc0000003f7fffe 2c00ff7fffffffff bcbffffffffe7fff 3cb0000000018001 bcbffffffffe7fff Wrong 263833 -c22000000001ffe0 176fffeffffff7fe 490ffffffff7ffff c900000000080001 490ffffffff7ffff Wrong 2644381 -ffd0007fffffffff 0010000000000001 43bff293676fa42f c3b00d6c98905bd1 43bff293676fa42f Wrong 2654451 -43412867894a0dc5 c3f94739873de8c1 3fcbffdfffffffff c74b1b82c2ed1472 c74b1b82c2ed1473 Wrong 2680633 -b7f001000000003e bfdffffffffffffe b7f00000004001ff 371ffff7ffc7bffe b7dffe0001000782 Wrong 2696745 -c01fc000ffffffff bfeff0001fffffff 406bffeffffffffe 406dfaf211f4000e 406cfd7108fa0006 Wrong 2698759 -42cf0007fffffffe bfffffffffffffff 43fffb7fffffffff 43fffb707ffbffff 43fffb783ffdffff Wrong 2702787 -c34fffffff7fbffe 37f0000000401000 40affffe0000007f c0a00001ffffff81 40affffe0000007f Wrong 2716885 -7feffffffffffffe 001fffffffffffff c340000000000000 c34ffffffffffff8 c33ffffffffffff8 Wrong 2724941 -c060003fffff7ffe 3ca0000000000001 c02000fffefffffe c02000ffff00000e c02000ffff000006 Wrong 2726955 -37e000000001ffff 434001000007ffff 38100007ffe00000 3b300100000a0020 3b300100000a0022 Wrong 2753137 -c03ffffffffffbef c00fffffffffffff c07ffffe02000000 c05ffffc04000412 c077fffe02000104 Wrong 2775291 -bca0001008000000 41c0000000000fdf 3feac3e63849250d 3feac3e5f848e4ed 3feac3e6184904fd Wrong 2777305 -3f0ff7ffffffc000 c34fffffffffffff 3feeffffffff7fff c26ff7ffffffb07f c26ff7ffffffa0ff Wrong 2781333 -bff9babb71f7f8b0 b80fffffdfffffee bb7000000000003e bb7000000000003d bb7000000000003e Wrong 2789389 -bfc3fc9335d22f67 0010000000000001 41cfffc000ffffff c1c0003fff000001 41cfffc000ffffff Wrong 2793417 -3f1fffffe0000004 426cedd14ca226b4 41e00007ffff7fff 41e1cee512fac556 41e0e776897d22aa Wrong 2795431 -c08ffffffffe001e 3ff0000000000000 c070220000000000 c092043fffff000f c094087fffff000f Wrong 2805501 -bfe200000000fffe 41fd6e4653630b63 480ffff008000000 c800000ff8000000 480ffff008000000 Wrong 281959 -4060000000080ffe 801ffffffffffffe 47fffc000fffffff c7f003fff0000001 47fffc000fffffff Wrong 2829669 -c34ffdffffff7fff 360fffffffffffbe 3f5ffffefffffffc bf50000100000004 3f5ffffefffffffc Wrong 2837725 -c3368331494c07f2 bfffffffffffffff 41d0000007ffffff 43468331594c07f9 43468331694c0801 Wrong 2841753 -405001ffffffffbf c010000000000001 bfe01ffffffffffb c0700607ffffffc0 c0700a0fffffffc0 Wrong 2847795 -c3407ffffffffffa 3fefffffffff007f c1cef00000000000 c34080000f777c3b c34080001eef7c3b Wrong 2861893 -b056edfafd7aecd8 3fe0000000000000 46fff80002000000 c6f007fffe000000 46fff80002000000 Wrong 2871963 -c34ffc00ffffffff bef38655f21f4b0d 412ff8000000003f 425383e7c313b6b4 425383e9c293b6b4 Wrong 2873977 -c07ffe0001ffffff 4000000000000000 4210080000007ffe 421007ffe0027ffc 421007fff0017ffd Wrong 2878005 -a4c1cb8f4c4a2248 3f6dfffdffffffff 43cffffffffff001 c3c0000000000fff 43cffffffffff001 Wrong 288001 -bfdfffe00fffffff 3fccf2165e6eea40 3ff0000023fffffe 3ffc61c0f4a5cd1e 3fec61c118a5cd1c Wrong 2880019 -40eaff598ceffab8 401ffffffffffffe e20ffc0000007ffe 620003ffffff8002 e20ffc0000007ffe Wrong 2884047 -be094ae83f023cb1 bcafffffffffffff c02fe000001fffff 40201fffffe00001 c02fe000001fffff Wrong 2902173 -c3ce8c81ad84b066 3e30fffffeffffff 480ffe0004000000 c80001fffc000000 480ffe0004000000 Wrong 2910229 -bfdeffffffff8000 c000000000000001 3fccc2e7f3c48eec 3ff14c2e7f3c08f0 3ff3185cfe7851de Wrong 2914257 -401618d4abc2ecba 3fe97989d3f9c41b 3deffffffffbffef 40119753370a7449 40119753370c7449 Wrong 2916271 -c7eff7fffdffffff 3fe0000000000000 45bffffff7fffe00 c7dff7fffdfbffff c7dff7fffdf7ffff Wrong 292029 -bfdce145472b2459 c1dffc3ffffffffe c3fffbfffffeffff c3fffbfffff7c886 c3fffbfffffb6443 Wrong 2934397 -431ff800000000ff 3fd0000000000000 407fffffbfffff7f 42fff800000010ff 42fff800000020ff Wrong 2938425 -3fc0dc6ed2eafe1a 9d30004000000080 402fffff7ffc0000 c020000080040000 402fffff7ffc0000 Wrong 294043 -34f746586aadaf16 3feffffffffffffe c9bffffffffbfeff 49b0000000040101 c9bffffffffbfeff Wrong 2944467 -bff00000107fffff c052f75c56a2dd94 bfd0005fffffffff 4052ef5c3a31f4cc 4052e75c0a31f4cc Wrong 2946481 -bda01000000000ff 400ffffffffffffe 3fcffe3fffffffff 3fcffe3fffdfdfff 3fcffe3fffefefff Wrong 2950509 -c02ff80000000002 119215fb360e73ac 114000200000000e 91d20d75af40f010 91d20975a740f010 Wrong 2958565 -0010000000000000 3ff0000000000001 bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong 296057 -8010000007f7ffff ffdc0ffffffffffe 3fefc00000003ffe 4002000006fd03fe 4005f80006fd0bfe Wrong 2964607 -4022e75b40b8c691 c010000000000001 bfd2ffed1d2049e5 c042fa5b2dd5e6dc c0430d5b1af30726 Wrong 2986761 -7fd03fffffbfffff 0000000000000000 3fffffff00003ffe 3ff81fff7fe01ffe 3fffffff00003ffe Wrong 2998845 -3fefff7ffffeffff 41e0001003ffffff c074811e0051b61d 41dfff9fde7ca3fb 41dfff9fb57a67fb Wrong 300085 -c047e499ddfa806a 3fdffffffffffffe b7fe0fffffffffff c037e499ddfa8068 c037e499ddfa8069 Wrong 3010929 -3fbffffefffff800 3ffffffffffffffe c340fffffffffdff 434f000000000201 c340fffffffffdff Wrong 3016971 -a440000003e00000 bf9748f93642bbe3 b7f4721d96c17b0b 37fb8de2693e84f5 b7f4721d96c17b0b Wrong 3018985 -0000000000000000 7fefffffffffffff 3cafffffffffffff 3fffffffffffffff 3cafffffffffffff Wrong 30209 -bfdfffffb0000000 401ffffffffffffe 4000000800003fff c007fffbafffdffe bfffffef5fff7ffe Wrong 304113 -bfa01fffffffffe0 bca0000000000001 c0204d08eea95a99 402fb2f71156a567 c0204d08eea95a99 Wrong 3041139 -3d2ffffbfffffffe 434e000000000003 bff0000040ffffff 408dfbfc3fefc001 408df7fc3fdf8001 Wrong 3049195 -3fffffffff7f8000 c000000000000001 c0b0000800fffffe c0b0080800ffdfde c0b0040800ffefee Wrong 3053223 -c12fc00001000000 c1e00002000003fe ffdfffffbff7ffff 7fd0000040080001 ffdfffffbff7ffff Wrong 3055237 -c1f03ffff7ffffff 41d0000000bfffff c090000001007fff c3d03ffff8c2fffe c3d03ffff8c2ffff Wrong 3061279 -8000000000000000 3ca0000000000001 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 3075377 -3fbffffffdfff7fe 3feffffffffee000 bfcffffff801ffff 3e17f35ffc004801 bfbffffff2052800 Wrong 3079405 -0010000000000000 7fe0000000000000 c340000000000000 c34ffffffffffffe c33ffffffffffffe Wrong 308141 -8000000000000000 4000000000000000 4340000000000000 c340000000000000 4340000000000000 Wrong 3087461 -c21103fffffffffe 400fffffffffffff c3e0200ffffffffe c3e020100440fffe c3e0201002207ffe Wrong 3089475 -bfb00207fffffffe c1f80bd9803691dc c3f000200000007e c3f0001ffffcfea1 c3f0001ffffe7f90 Wrong 3091489 -8000000000000000 7feffffffffffffe bcafffffffffffff bffffffffffffffe bcafffffffffffff Wrong 3099545 -8000000000000000 bcafffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong 3111629 -406ffe0000fffffe bfd0000000000001 400f499c83e9329a c04f03b31ce0b66b c04e096638c16cd6 Wrong 3113643 -c05fffffffdeffff bff0000000000001 c01000000007dfff 405f7fffffdec101 405effffffde8201 Wrong 3119685 -400040000007ffff bfa738fe57513611 c0200000000081ff c0205e5789436a5c c0202f2bc4a1f62e Wrong 3121699 -47e00010007fffff 40266ebea38fe729 c1f0001001fffffe 48166ed5130200ac 48166ed5130200ad Wrong 3139825 -bf1fffffffffefbe 4060001fff7ffffe bfb9717e7198ca76 bf6718e7158c6647 bfbd71867178c86d Wrong 3157951 -43100200003fffff b7e000000dfffffe 47ef5361de548d5b c7e0ac9e21ab72a5 47ef5361de548d5b Wrong 3163993 -7a2e9622e5ca04a5 21f6a376abef6748 bfefff80000007ff 5c35a3762db52e1a 5c35a3762db52e1b Wrong 3176077 -3f4ffffffffffe06 3fe121d0404af4cc 403ef7a477cb376d 403ef7e8ff0c3899 403ef7c6bb6bb803 Wrong 3182119 -c100007fffffffbf b3fffffffffffffe 36cfffc00000000e 36cfffc00400200e 36cfffc00200100e Wrong 3188161 -bfbffffffffb7fff 40afffffef000000 3fd000000000fe00 c07ffdffeefb7fdf c07ffbffeefb7fc0 Wrong 3194203 -0010000000000000 bca0000000000000 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 320225 -c09000003fffbfff bcafffffffffffff c02ffffffffe01ff c02ffffffffe00ff c02ffffffffe017f Wrong 322239 -c090003ffffffffb 3fefffffffffffff 41d00000003ffe00 41dffffe0037fe00 41cffffe0077fc00 Wrong 3222399 -c0200000000017ff c3e07feffffffffe 41637ffffffffffe 44107ff0000019f5 44107ff000001b2d Wrong 3230455 -380531927f4eef39 2ec0003ffffffc00 bfc7ffffffefffff 3fc8000000100001 bfc7ffffffefffff Wrong 3248581 -c010000000000ffa bfd0000000000000 3f60000000200002 3ff00400000017fa 3ff0080000001ffa Wrong 3252609 -c03000000003efff 400fbffffffbffff 704fffe7ffffffff f040001800000001 704fffe7ffffffff Wrong 3254623 -3fd00000ffffff80 bff0000000000000 bf6000000020ffff bfd0100100002080 bfd0200100004180 Wrong 3258651 -3fcffffffff7ff7f bff4691aa0d59fcd 40600007ffe00000 406feb9ee53f2f7b 405feba6e51f2f7b Wrong 3260665 -c050000100003fff 001fffffffffffff 47efffc001fffffe c7e0003ffe000002 47efffc001fffffe Wrong 3282819 -7560000001fffffe 3fc1e915aabc5c49 f5dfc0000fffffff f5dfb70b85298340 f5dfbb85ca94c19f Wrong 3284833 -401ffffe07fffffe 4010000000000001 c1f7e00000000000 c1f7dffffc00003f c1f7dffffe000020 Wrong 3300945 -40100003fffffefe 402ffffff7f7ffff ceab55d2faad3c08 4ea4aa2d0552c3f8 ceab55d2faad3c08 Wrong 3309001 -0010000000000000 bffffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong 332309 -bf9ff7ffffffffff 41e828069d05f676 401b3add2f8a8e68 c19821fc8dc14660 c19821fc8023d7c8 Wrong 3327127 -3fc000000000bfff c01ffffffffffffe bfefff9000000000 bff7ffe40000bffe bfffffc80000bffe Wrong 3337197 -beef802000000000 c000000000000001 4000000000dfffff 4000001f80ffffff 4000000fc0efffff Wrong 334323 -c1c0000003ffffff 3cafffffffffffff 3ca0000000002fff be80000003dffffe be80000003bffffe Wrong 3355323 -bdfffff8000000fe ba37ef95f9e7fcb2 ba2fc000007fffff ba2fbfffffc0837f ba2fc000002041bf Wrong 336337 -8010000000000000 3ffffffffffffffe 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 3365393 -b891000000000006 40000000003ff800 380ffffffffeffdf b8a0fc000043f7a6 b8a0f8000043f7c6 Wrong 3375463 -8010000000000000 7fefffffffffffff 4340000000000000 434ffffffffffffc 433ffffffffffffc Wrong 3377477 -8010000000000000 bca0000000000001 bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong 3389561 -c1dc00ffffffffff bfd0000000000000 bf8fffe000001000 41bc00fffffe0001 41bc00fffffc0003 Wrong 3391575 -ffd0008800000000 802b2144a835a75b 428000000000020f 4280000000003853 4280000000001d31 Wrong 3393589 -3f80001ffffefffe bfeffffffffffffe 41dfc10000000000 41dfc0fffffefffe 41dfc0ffffff7fff Wrong 3397617 -8010000000000000 c000000000000000 c340000000000000 4340000000000000 c340000000000000 Wrong 3401645 -bfe7da39e756fab8 c340000000000001 41d87200e15761ba 4337da3a183afc7c 4337da3a491efe3f Wrong 340365 -ce17bb7913b68ebe c34ffffffffffffe ffdffdffffffbfff 7fd0020000004001 ffdffdffffffbfff Wrong 3409701 -c00ffffc7fffffff 3fd7ffffdfffffff bca000400000000e bff7fffd4000037e bff7fffd4000037f Wrong 3411715 -3fbfffffefbfffff 3f600001ff7ffffe bfc000fffffffffe bfcff0fffe089fff bfbff1fffe089ffd Wrong 3417757 -3fbff7fffffffffd 47f0203ffffffffe c7fffffffe00fffe c7d7f1e40401fffe c7fdfc790000fffe Wrong 3423799 -8010000000000001 3caffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong 3425813 -41efffffffff807f 3fd0000000000001 c01feffffffff7ff 41cffffffe008081 41cffffffc018081 Wrong 3427827 -4248c62fe782eace c1effe0000004000 41dfff7ffffffffe c448c4a38484842c c448c4a38484642d Wrong 3435883 -bdcfe00ffffffffe bfdffffffffffffe bfc000000200000f bfc0000001e01fff bfc0000001f01007 Wrong 3464079 -41100008000ffffe bffffffffffffffe 3fb1baac953356d1 c1200007ee555368 c1200007dc9aa6d3 Wrong 3470121 -3dffff0000001fff 406ff08000000000 c04000000807ffff c0400000060907f7 c0400000070883fb Wrong 3472135 -bf4ff8000003ffff 400fc000000001ff bfd1000000040000 bfd17ee040040fe8 bfd13f70200407f4 Wrong 348421 -bf5fffbffffdfffe 3ca0000000000001 3f1ffffffe0003ff 3f1ffffffe0003df 3f1ffffffe0003ef Wrong 3494289 -403fffffff801000 3fe0000000000001 bff0803fffffffff 402ef7fbff801002 402deff7ff801002 Wrong 3500331 -5e78a4f96abc9de7 4000000000000001 47f8c8e01d92ead7 5e88a4f96abc9de8 5e88a4f96abc9de9 Wrong 3506373 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-bca003ffffff0000 400ac4372520559f 3fcbd9e12ac2c108 3fcbd9e12ac2c0ed 3fcbd9e12ac2c0fb Wrong 4203217 -4bb000040000003e 318ffffffffff7ff bfe0000000000017 bfeffffffffff017 bfdffffffffff02e Wrong 4209259 -bfe0000000000000 8010000000000001 c340000000000000 4340000000000000 c340000000000000 Wrong 4223357 -c03ffefffffffdff 40bc282748cfc06d bf2ffffefdfffffe c10c274607d5782a c10c274608157828 Wrong 4227385 -0000000000000000 bca0000000000001 4340000000000000 c340000000000000 4340000000000000 Wrong 42293 -bfe0000000000000 bff0000000000001 3cafffffffffffff 3fe0000000000002 3fe0000000000003 Wrong 4235441 -c3d0000007fffeff bffffffffffffffe 4343523e456566ff 43e0026a4fc8abab 43e004d497915858 Wrong 4237455 -bfe0000000000000 c010000000000000 bff0000000000001 3ff7ffffffffffff 3feffffffffffffe Wrong 4241483 -b7fef51e4b4dcbef c01ffffffffffffe bcaffffffffaffff 3ca0000000050001 bcaffffffffaffff Wrong 4243497 -b7efeffffffffff7 ffefffffffffffff ffdd4fe4b235ea5d 7fd2b01b4dca15a3 ffdd4fe4b235ea5d Wrong 4249539 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-c06905febb773604 c022a0c0b2a5ae70 3fe47dd1c6d2de46 409d236fc2abcc2e 409d24b79fc8395c Wrong 4608031 -7fdfffffffffff3e 3fd1b85566f6674c c03ffffffffffc02 7fc1b85566f666e0 7fc1b85566f666e1 Wrong 4614073 -bfffffffffffffff 4340000000000000 bff0000000000001 c34fffffffffffff c350000000000000 Wrong 4628171 -38000000fffffffd b81ffff7fff7fffe 41e1dcadee9fbd6b c1ee235211604295 41e1dcadee9fbd6b Wrong 4632199 -402fffe000007fff 801fffffffffffff 401ffff07fffffff c010000f80000001 401ffff07fffffff Wrong 4642269 -c01fc00003ffffff de8fffefffff7fff f91ffffdfc000000 7910000204000000 f91ffffdfc000000 Wrong 4644283 -bfffffffffffffff bcaffffffffffffe bcafffffffffffff 3cb7fffffffffffd 3caffffffffffffb Wrong 4646297 -bffffffffe0003ff bfdfffffffffffff 40031ade702700a8 3fc8d6f379381538 400b1ade6fa701a8 Wrong 4648311 -001fffffffffffff bfdffffffffffffe 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 465233 -bfffffffffffffff bfeffffffffffffe 3ff0000000000001 4003ffffffffffff 4007ffffffffffff Wrong 4652339 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-c000000000000001 434ffffffffffffe bcafffffffffffff c350000000000000 c360000000000000 Wrong 4839641 -c000000000000001 801fffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong 4851725 -c0e1ead1644c2360 bca0000000000001 c3dffffffffe7fff 43d0000000018001 c3dffffffffe7fff Wrong 4853739 -bea000002001ffff c1cef0dea2ce737b 400e000000000000 407f0edee0b40eda 407f2cdee0b40edb Wrong 4855753 -c000000000000001 bfffffffffffffff 3cafffffffffffff 4010000000000000 4010000000000001 Wrong 4863809 -3f30000020000000 c000000000000000 bfcfffffc001ffff bfc01fffc041ffff bfd007ffe0110000 Wrong 4865823 -c000000000000001 c010000000000001 bff0000000000001 401e000000000004 401c000000000004 Wrong 4869851 -c00fffffffffffff 3ca0000000000000 bcafffffffffffff bcc3ffffffffffff bcc7ffffffffffff Wrong 4887977 -c31feff7fffffffe 407f14dabf153af4 43c9f50da1a060a1 43a4e4d2b6c1c0b2 43c233bb7e80a07d Wrong 4892005 -c00fffffffffffff 3fe0000000000000 3ff0000000000001 bff7fffffffffffe bfeffffffffffffc Wrong 4894019 -bff080007fffffff 3fefffffffffffff 41f0002003ffffff 41f0002003defffe 41f0002003ef7fff Wrong 4896033 -c00fffffffffffff 3ffffffffffffffe c340000000000000 c340000000000008 c340000000000004 Wrong 4900061 -c00ffffffdffffee c028d9a8bea71866 ce2fffffffffffc6 4e2000000000003a ce2fffffffffffc6 Wrong 4904089 -3eb7fffffffffff0 434fffffffffffff 3fc01fffffffffef 421800000000406f 42180000000080ef Wrong 4908117 -434ffe0000000003 3f050506fa43403e c036d0c0e5df8b63 426503b6a9d22f00 426503b6a9d0c1f4 Wrong 4910131 -c020004000000040 8010000000000001 c1fffff000800000 41f0000fff800000 c1fffff000800000 Wrong 4920201 -40affffbfffffff6 c20000000003fffd c01ffdfffe000000 c2bffffc000803ef c2bffffc000807ef Wrong 4922215 -37effeffdfffffff bff0000000000000 b7efffd7ffffffff b7f7ff75efffffff b7ffff6befffffff Wrong 4932285 -4047c422625c8dfb 3ff000010003ffff 42e0000000000700 42e00000000012e2 42e0000000000cf1 Wrong 4940341 -c00fffffffffffff c340000000000001 3ff0000000000001 4360000000000000 4360000000000001 Wrong 4942355 -bfbfffffbffff7ff c34ffffffffffffe 40196d6b50f2a50c 431fffffbffff80a 431fffffbffff816 Wrong 4944369 -489fffefffffeffe b6efffffffbffffc 3fbffffffff7effe 3fa000080017f7f1 3fb800040007f3f7 Wrong 4946383 -bfefffffbfffffef 4000040ffffffffe 51d868ed5abec329 d1d79712a5413cd7 51d868ed5abec329 Wrong 4958467 -c00ffffffffffffe 3fd0000000000000 3cafffffffffffff bfeffffffffffffd bfeffffffffffffc Wrong 4960481 -c00ffffffffffffe 3feffffffffffffe bff0000000000001 c011fffffffffffe c013fffffffffffe Wrong 4966523 -c00ffffffffffffe 400ffffffffffffe 4340000000000000 434ffffffffffff0 433ffffffffffff0 Wrong 4972565 -4320037fffffffff 4010000000000001 41fdc4b3a046b212 434003807712ce81 43400380ee259d02 Wrong 4974579 -41d07fffff800000 c010ffffffbffffe bfd07fffffffffdf c1f187ffff380ffe c1f187ffff3a1ffe Wrong 4982635 -bfc003fffffff000 982fffffff7effff c7efffffbfffdfff 47e0000040002001 c7efffffbfffdfff Wrong 4994719 -c00ffffffffffffe bfd0000000000001 c340000000000000 4340000000000001 c33fffffffffffff Wrong 4996733 -bcce2e656dd76af6 c01ffffffffffffe 40582ea8ffab0667 40582ea8ffab0668 40582ea8ffab0667 Wrong 5010831 -001ffffffffffffe 3fe0000000000000 c340000000000000 4340000000000000 c340000000000000 Wrong 501485 -40000010007ffffe 3f6b3db4bb3d6728 3fd095716ec3b12b 3fd16f5fee9211ab 3fd10268aeaae16b Wrong 5018887 -c010000000000000 0000000000000000 4340000000000000 c340000000000000 4340000000000000 Wrong 5020901 -c010000000000000 3fdffffffffffffe bcafffffffffffff bffffffffffffffe bfffffffffffffff Wrong 5032985 -b8016e821e7114dc bfeffffffffffffe b7f000000001fff7 37fadd043ce129ba 37f2dd043ce029bf Wrong 50349 -3f4000100000003f 3feffffffffffffe 422ff00000007fff 422ff0000000807f 422ff0000000803f Wrong 503499 -c010000000000000 3ffffffffffffffe 3ff0000000000001 c01dfffffffffffe c01bfffffffffffe Wrong 5039027 -c010000000000000 401fffffffffffff c340000000000000 c340000000000020 c340000000000010 Wrong 5045069 -3f67c855ae00ce43 4340000000000001 43e6f149c1994369 43e6f14fb3aeaee9 43e6f14cbaa3f929 Wrong 5047083 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-c010000000000001 8010000000000001 bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong 5129657 -c010000000000001 bfd0000000000001 3ff0000000000001 3ff8000000000002 4000000000000002 Wrong 5135699 -bc58a7f283b15aa6 bfdffffffffffffe c00ff7fffffffeff 4000080000000101 c00ff7fffffffeff Wrong 5137713 -213fffc000002000 bfc39f7f419eca3b 3e1ffdffffffeffe be10020000001002 3e1ffdffffffeffe Wrong 5139727 -c010000000000001 bff0000000000000 c340000000000000 c34ffffffffffffc c33ffffffffffffc Wrong 5141741 -37ea3353806450ba bffffffffffffffe b803fffffffff7ff b80719a9c032245c b8108cd4e019102e Wrong 5143755 -c1fff7fffffffe00 c01ffffffffffffe bf38000000000040 422ff7fffffffde6 422ff7fffffffdce Wrong 5149797 -c01fffffffffffff 001ffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong 5165909 -bcaffffdf7fffffe 366ffffffe1fffff b20f000000000007 b3300000eb10000e b3300002db10000e Wrong 5169937 -bfffffffff7f7ffe c003fffffffffff6 cea3caf6c0e272a7 4eac35093f1d8d59 cea3caf6c0e272a7 Wrong 5175979 -c01fffffffffffff 401fffffffffffff 3ff0000000000001 c04fbffffffffffe c04f7ffffffffffe Wrong 5184035 -001ffffffffffffe 7feffffffffffffe bff0000000000001 401dfffffffffffc 401bfffffffffffc Wrong 519611 -bf40000804000000 3ccfffff7ffefffe be9000000fffffff be90000010003fff be90000010001fff Wrong 5200147 -c01fffffffffffff bca0000000000001 3cafffffffffffff 3cd2000000000000 3cd4000000000000 Wrong 5202161 -423c64df6ca8aa39 bcaffffffffffffe 3ff1ae3ab5f11d36 3ff1ae01ec3243e4 3ff1ae1e5111b08d Wrong 5204175 -c01fffffffffffff bfe0000000000000 bff0000000000001 400bfffffffffffe 4007fffffffffffe Wrong 5208203 -c01fffffffffffff c000000000000000 4340000000000000 4340000000000010 4340000000000008 Wrong 5214245 -bfffffffff0007ff 0010000000000001 5dbffff00003ffff ddb0000ffffc0001 5dbffff00003ffff Wrong 5234385 -bf1fffffe0ffffff bfcffffffbffff00 bf9000001ffffc00 bf9ff00020117c00 bf8ff00040117800 Wrong 5236399 -47fe17f4025a7deb b7f000000fffffef 41c000400000001f 41c0003ffe1e80dd 41c0003fff0f407e Wrong 5242441 -bca000000003fffb 4010000000000000 3fddfffffffffe00 3fddfffffffffdf0 3fddfffffffffdf8 Wrong 5252511 -3ffefffeffffffff 38100002fffffffe b81effff7fffffff 380f000a1fff9ff7 36f53fff3ff08000 Wrong 5266609 -41cbffffffffefff 801ffffffffffffe 3b3ffffffffbffff bb30000000040001 3b3ffffffffbffff Wrong 5270637 -c01ffffffffffffe bfd0000000000000 bcafffffffffffff 3ffffffffffffffe 3ffffffffffffffd Wrong 5274665 -c1c07fffffffffff bfdffffffffffffe 42db2d4be861df6a 42db2d542861df6a 42db2d500861df6a Wrong 5276679 -41cdffffc0000000 bfbff87ffffffffe 41c000000080ffff 41a1038420fa7fff 41b881c210fe3ffe Wrong 5278693 -c01ffffffffffffe bff0000000000000 3ff0000000000001 4020ffffffffffff 4021ffffffffffff Wrong 5280707 -c01ffffffffffffe c00ffffffffffffe c340000000000000 c34fffffffffffe0 c33fffffffffffe0 Wrong 5286749 -002dfffeffffffff ffefffffffffffff 3ffffffffffffbfc c02bffff0000003e c029ffff0000007f Wrong 5294805 -4713ee08a1624b47 42ddfffe00000000 47f1ffffffffffee 4a02af26d8701c7c 4a02af26d8749c7c Wrong 529681 -c383f50a0cb6ed42 41eb3dd4a3b7b79c c189841022924e71 c580fd50335fe824 c580fd50335fe825 Wrong 5302861 -ab6fffffffebffff 3ca0000000000001 4027fff000000000 c028001000000000 4027fff000000000 Wrong 5306889 -c340000000000000 3fdfffffffffffff 4340000000000000 3fe0000000000000 4330000000000000 Wrong 5310917 -bcafffc0001ffffe 3fe0000000000000 bfc000400000000f bfc0004000000017 bfc0004000000013 Wrong 5312931 -c340000000000000 8000000000000000 c340000000000000 4340000000000000 c340000000000000 Wrong 5335085 -43f017fffffffffe bcaffffffffffffe c01effffffffefff c0b01bdffffffffb c0b01fbffffffff9 Wrong 5343141 -bf9b000000000000 37effffffefff7ff 3bdfff8000000fff bbd0007ffffff001 3bdfff8000000fff Wrong 5345155 -4128574d5c8f3538 bfefffffffffffff c3ebfd9ee3d633db c3ebfd9ee3d636e6 c3ebfd9ee3d63560 Wrong 5349183 -bfdff70000000000 361c00000000003f 400fffffbbffffff c000000044000001 400fffffbbffffff Wrong 5351197 -c340000000000000 bffffffffffffffe bff0000000000001 434ffffffffffffe 434ffffffffffffd Wrong 5353211 -3ed03feffffffffe bf1ffbfff7fffffe 3fd000000000037e 3fdffffffefc24fe 3fcffffffefc287c Wrong 535723 -c340000000000000 c01ffffffffffffe 4340000000000000 4370ffffffffffff 4371ffffffffffff Wrong 5359253 -c340000000000001 3cafffffffffffff 3ff0000000000001 bff8000000000000 bff0000000000000 Wrong 5377379 -3a1001f800000000 2cd2000000000007 bfbcea2c8d11faee 3fb315d372ee0512 bfbcea2c8d11faee Wrong 5381407 -c340000000000001 3fe0000000000001 c340000000000000 c340000000000001 c348000000000001 Wrong 5383421 -bff0589b0b9001f8 4010000000000000 43e0ffffffffc000 c3ef000000004000 43e0ffffffffc000 Wrong 5391477 -3fbf800000001000 bff0000000000001 c1dfffff7fff7fff c1dfffff800f3fff c1dfffff80075fff Wrong 539751 -c0a3e45119503fad 801fffffffffffff b7ffffc07fffffff 37f0003f80000001 b7ffffc07fffffff Wrong 5409603 -c02c219606615d02 40d0000001fdfffe bfb0002800000000 c10c219649e2ab8c c10c219689e34b8d Wrong 541765 -c340000000000001 bfeffffffffffffe bcafffffffffffff 4330000000000000 4340000000000000 Wrong 5419673 -bfaffd7ffffffffe bfffffffffffffff 402ffff400000000 40207fea00000000 40301ff780000000 Wrong 5421687 -43e03ffffffefffe a51ffffffd000000 41efffffff00ffff c1e0000000ff0001 41efffffff00ffff Wrong 5423701 -c34fffffffffffff 001fffffffffffff 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong 5443841 -c34fffffffffffff 3fd0000000000001 bff0000000000001 c330000000000001 c330000000000002 Wrong 5449883 -c34fffffffffffff 3ff0000000000001 4340000000000000 c348000000000001 c340000000000001 Wrong 5455925 -c0000000007ffff6 c010000000000000 c04fffffefffffff c037ffffefc00004 c04bffffefe00002 Wrong 545793 -92e00000007fffff 3ffffffffffffffe 4aaffffffc001fff caa0000003ffe001 4aaffffffc001fff Wrong 5457939 -c03000003ffdffff 4034000000000002 3fb0100000001000 c073ff7fcffd8000 c073feff4ffd8000 Wrong 5459953 -41dffffffffffefb bfeffc0000000040 41c07ffc00000000 c1dbdc00ffffff3b c1d7bc01ffffff3b Wrong 5465995 -4acfffffffe07fff 380111a0c92fbee3 bfc020eb7964e9df 42e111a0c91ef186 42e111a0c91ef184 Wrong 5472037 -c34fffffffffffff 801ffffffffffffe c340000000000000 4340000000000000 c340000000000000 Wrong 5480093 -c1effffffffc0003 bfefffffffffffff 41df7ffffffffbff 41f3effffffdff81 41f7dffffffdff01 Wrong 5488149 -bf5ffdfeffffffff c1c00000000007fe c068f8e52e02b635 412ffd3738d69fe4 412ffc6f71ad2fcf Wrong 5502247 -43c00000000c0000 3ba03fffffffeffe c19e0000000001fe c19dfffffff7e1fe c19dfffffffbf1fe Wrong 5508289 -b80686567adb6535 3fd0000000000000 402ffffffdfe0000 c020000002020000 402ffffffdfe0000 Wrong 5518359 -c00595ebd72b467c 43cf77fffffffffe c1e9531cb30bc1e8 c3e53a2eace5781d c3e53a2eacf221ac Wrong 5520373 -c07ffbffffffefff 3feffffffffffffe 43deffffff7ffffe c3d1000000800003 43deffffff7ffffe Wrong 5524401 -c34ffffffffffffe 4000000000000000 c340000000000000 c361ffffffffffff c363ffffffffffff Wrong 5528429 -c01ffff000001ffe 419fffbfffffffff 4020088000000000 c1cfffaffe1f0ffd c1cfffaffc1dfffd Wrong 5532457 -401fffbffffffffc c0000000000100ff 3fdb0c7f1aa6dcb7 c02f938e03976683 c02f275c072ccb10 Wrong 553849 -c34ffffffffffffe bcaffffffffffffe 4340000000000000 4340000000000004 4340000000000002 Wrong 5552597 -3ff221640e87bbad bfd0000000000001 c1d70a764cfa4319 c1d70a764d1e85e1 c1d70a764d0c647d Wrong 5554611 -3ffffffffffff780 bff0000000000001 400cfefb818713c9 bfc80823f3c71dc8 3ff9fdf7030e3010 Wrong 5560653 -37efffbffbfffffe c010000000000001 426fffcfffffffff c260003000000001 426fffcfffffffff Wrong 5566695 -c3c7979fc93cf795 c01ffffdffefffff c72fffdfffffbfff 4720002000004007 c72fffdfffffbffc Wrong 5568709 -bf76a55146618ff8 c2c000001fffbffe 3fe000bffffffffe 4246a55173abf7ee 4246a55173ac17f0 Wrong 5574751 -c1e0000000100010 0000000000000000 3f9ffdffdfffffff bf90020020000001 3f9ffdffdfffffff Wrong 5578779 -b051e706ce9d287d 3ca0000000000000 401ffff7ffffc000 c010000800004000 401ffff7ffffc000 Wrong 5584821 -095fffefffffeffe 3fdffffffffffffe b85664dbd796f697 38599b2428690969 b85664dbd796f697 Wrong 5590863 -40d4374fa828b57a 3ffffffffffffffe b08008000000000f 40e4374fa828b578 40e4374fa828b579 Wrong 5596905 -3ca00000005fffff 7fefffffffffffff 7fe0043fffffffff 7fe0044000000001 7fe0044000000000 Wrong 5608989 -be10000000080010 41e00000003ffbff 3ea954e801d58acc bfffffff9b3c5816 bfffffff35e8b80f Wrong 5611003 -ffe0000000000000 801ffffffffffffe 3ff0000000000001 4011ffffffffffff 4013ffffffffffff Wrong 5619059 -00d10000fffffffe bfe0000000000001 400ff801ffffffff c00007fe00000001 400ff801ffffffff Wrong 5627115 -3f8fffdffffff7ff bfdfffe0000ffffe bfc00000002007ff bfc1fffc0023077e bfc0fffe002187be Wrong 5629129 -c4708007ffffffff b7fffffc00004000 bffffffffffffff4 3ff000000000000c bffffffffffffff4 Wrong 5641213 -c0ce6b6deff071a3 3feffffffffffffe 3f9ff00000fffffe c0ce6b6bf0f07191 c0ce6b69f1f07181 Wrong 5663367 -43dfffffffff7bff 400fffffffffffff c9e8f802949944eb 49e707fd6b66bb15 c9e8f802949944eb Wrong 5669409 -bfcff8000003ffff c0c00000007fbfff bff0000001000007 409ff6000103201d 409ff4000103001d Wrong 5671423 -be90e49a299e9782 3f5000000fc00000 401ffffffc000004 401ffffffbf78db7 401ffffffbfbc6dd Wrong 5683507 -c0c01f0000000000 3ff0001fff7fffff be12dd4b694fb5d8 c0c01f203d7f092d c0c01f203d7f0a5b Wrong 5695591 -bca0000007fefffe c1f1000003ffffff 3fe000007ffffbff 3fe000029ffffd8f 3fe000018ffffcc7 Wrong 5713717 -409ff7fffffff7ff bf836ac78348eb47 bfc2000007ffffff c03377ecd1701431 c03389ecd1781431 Wrong 571975 -ffefffffffffffff 0010000000000000 c340000000000000 c340000000000004 c340000000000002 Wrong 5721773 -3fdfffff80007fff 3fdffffffffffffe 402001ffffffffe0 402101fffc0003e0 402081fffe0001e0 Wrong 5729829 -3eb17b46105c029e 356ffff80007ffff bfcfffffe0001ffe 3fc000001fffe002 bfcfffffe0001ffe Wrong 5731843 -43f008000000003e 3fffffffffffffff c3dc8b92c412fd96 43fc7e8da77da0c8 43f8ed1b4efb4115 Wrong 5735871 -7fd4100000000000 bf2ffffe03fffffe 9e4f275405eb089b ff140ffec181fffe ff140ffec181ffff Wrong 5743927 -40013fad9f4e14d4 8027ffffffff0000 3fcffff800003ffe bfc00007ffffc002 3fcffff800003ffe Wrong 5774137 -3fd0000401ffffff c07fffe000007fff 3fafc000001fffff c05ffdec03f879fd c05ffbf003f877fd Wrong 5786221 -ffeffffffffffffe 0000000000000000 bff0000000000001 c003ffffffffffff bff0000000000001 Wrong 5788235 -c398d85aca9eff71 400fffffffffffff 41e5fab80ef2d73e c3b8d85aca471490 c3b8d85ac9ef29b0 Wrong 5808375 -b80fffffff7f7fff 8010000000000001 bf9fffffc00000ff 3f9000003fffff01 bf9fffffc00000ff Wrong 5826501 -bf1fffff8003ffff bfd0000000000000 c220800004000000 c220800003fffff8 c220800003fffffc Wrong 5832543 -ffeffffffffffffe bfe0000000000001 bff0000000000001 7fd0000000000000 7fe0000000000000 Wrong 5836571 -3812031359e6b20b c00ffffffffffffe b7f02000000003ff b832841359e6b22a b833051359e6b24a Wrong 5844627 -c1cfffffff7ffffe bfaf0e5ff2ac719c 41f89242d54a35b2 41f90e7c5512f692 41f8d05f952e9622 Wrong 5858725 -3ca0000000000000 434ffffffffffffe bcafffffffffffff 3ffffffffffffffe 3ffffffffffffffd Wrong 586073 -b81fffdff8000000 001fffffffffffff 406ffffffff9fffe c060000000060002 406ffffffff9fffe Wrong 5862753 -bfffffffffbfffbe 3ff0400003fffffe 417dd4e89ed4c2a5 417dd4e85dd4c296 417dd4e87e54c29d Wrong 5864767 -37e037ad784678e1 3fdfffffffffffff b7e000000000103f 376bd6bc233450bf b7cf90a50f734f3b Wrong 5868795 -c2700007fffffe00 415fffffe0000003 c34fffffffff7dff c3e00407effff5f1 c3e00807effff5e1 Wrong 5870809 -c01000001fffc000 c1e00000fffe0000 cf67ffe000000000 4f68002000000000 cf67ffe000000000 Wrong 5876851 -b8100000000000f6 4010000000000001 400ffdfeffffffff c000020100000001 400ffdfeffffffff Wrong 5880879 -3d80001000000800 43cffffe0000007f ffdd733b37e3b984 7fd28cc4c81c467c ffdd733b37e3b984 Wrong 5882893 -c0800000080007fe bca0000000000000 c0dfffffffe001fe 40d00000001ffe02 c0dfffffffe001fe Wrong 5899005 -279fffbfffdfffff c1f00007e0000000 47f5d4bebaf82ac1 c7fa2b414507d53f 47f5d4bebaf82ac1 Wrong 5907061 -bfcc03a8225fe071 ffeffffffffffffe ffe0000420000000 ff9fe300ed00fc86 ffd1fe342ed00fc8 Wrong 5923173 -b07eb39219723c6c bca0000000080002 b7fef7a6994454c9 37f1085966bbab37 b7fef7a6994454c9 Wrong 5925187 -bf6000002007ffff b818ec6a605f44e1 c3effffbffff8000 43e0000400008000 c3effffbffff8000 Wrong 5931229 -c050000003fff000 3cafffffffffffff 402ffffffffffdf7 402ffffffffffde7 402ffffffffffdef Wrong 5935257 -3eb9c788bafd1c8d c3cfbfffefffffff 4011ffffffffff7f c29993f99ca354f6 c29993f99ca34bf6 Wrong 5937271 -c0300000bfffffff 3fe0000000000001 401fffffe0400000 c01000018fe00000 bed9fc0000000001 Wrong 5941299 -bf90348f17f835b5 380ffffffffc001e 3fefff7dffffffff bfe0008200000001 3fefff7dffffffff Wrong 5949355 -dd32c11cf81b2b12 40002b8c7d146fad c021abbfd858aa44 dd42f428a25015a0 dd42f428a25015a1 Wrong 5955397 -c1d45d281aa37a03 3c80dfffffffffff 3fe080000000fffe 3fe07fffd50c7f66 3fe07fffea86bfb2 Wrong 596143 -41c0000000800080 40f0002fffffffff 43fa043fa875191b 43fa0443a881193b 43fa0441a87b192b Wrong 5961439 -43301fffffffffff bd2ffffffefdffff c0594b450d492733 c0734968a12722e5 c07672d142d047cb Wrong 5967481 -3fe0188bb8c96308 bfd0000000000000 bfc0000007ffff7f bfc8188bbcc962c8 bfd00c45e064b144 Wrong 5971509 -bfdffe0001fffffe 31f8000000200000 37ead068bebdb0d3 b7e52f9741424f2d 37ead068bebdb0d3 Wrong 5997691 -c03bffffffffbffe 001fffffffffffff 37f5669d69074178 b7fa996296f8be88 37f5669d69074178 Wrong 6001719 -41cfffffffffdfee d6b0004000000002 bfffff7fffffffff d890003fffffeff8 d890003fffffeff9 Wrong 6003733 -4000007fffffdfff 3fd0000000000001 4010100000010000 400410200000f800 401210100000fc00 Wrong 6007761 -3ff00000100003ff 404ffe00000003fe c30b1272065fd0c9 c30b1272065fccc9 c30b1272065fcec9 Wrong 6015817 -0000000000000000 001ffffffffffffe bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong 6041 -0020000000800100 bfe0000000000001 3f0fffff80fffffe bf0000007f000002 3f0fffff80fffffe Wrong 606213 -3ca0000000000000 bfffffffffffffff 3cafffffffffffff bc9fffffffffffff 0000000000000000 Wrong 610241 -bfd0000120000000 c000000000000000 3fc00003ff7fffff 3fe200019ff00000 3fe400021fe00000 Wrong 612255 -3ca0000000000000 c010000000000001 bff0000000000001 bff0000000000005 bff0000000000003 Wrong 616283 -3caf8000001fffff c340000000000000 3fdfffffdffeffff bffb800004201fff bff7800008203fff Wrong 618297 -be10000800000fff c34fffffffffffff ffd9db5021932540 7fd624afde6cdac0 ffd9db5021932540 Wrong 62433 -c01000007fffffde 3811953d5a433174 3e7ffdffff7fffff be70020000800001 3e7ffdffff7fffff Wrong 626353 -3fb0ffffffffffff 407000000fffffbf c0f00000000800fe c0fffde00005e0fe c0effde0000de1fc Wrong 632395 -3ca0000000000001 3ca0000000000000 bcafffffffffffff 3ca0000000000002 bcaffffffffffffe Wrong 634409 -c050000003dfffff bd6000000004000f 3fef7fffffffffde 3fef80000007ffde 3fef80000003ffde Wrong 638437 -3ca0000000000001 3fe0000000000000 3ff0000000000001 3ff0000000000002 3ff0000000000001 Wrong 640451 -3ff00101ffffffff 3fefffffffffffff c3ffffff00007ffe 43f00000ffff8002 c3ffffff00007ffe Wrong 642465 -40154b404b0501a2 380000000003fffe bfeffefffdffffff 3fe0010002000001 bfeffefffdffffff Wrong 644479 -3ca0000000000001 3ffffffffffffffe c340000000000000 4340000000000000 c340000000000000 Wrong 646493 -001eff8000000000 3801ad261b713620 beefffefff000000 3ee0001001000000 beefffefff000000 Wrong 650521 -c5b00000000ffffd 434fffffffffffff 47ddffffffffdfff c90ffffe201ffff9 c90ffffc401ffff9 Wrong 654549 -c7ffd288f3eb4dc5 480fffffffe00001 705e000000000000 f052000000000000 705e000000000000 Wrong 656563 -3ca0000000000001 7feffffffffffffe 3cafffffffffffff 7c90000000000000 7ca0000000000000 Wrong 658577 -ffe0000000038000 3c100007ffffffff 3feffe0003fffffe fc00000800038000 fc00000800038001 Wrong 662605 -0000000000000000 ffeffffffffffffe c340000000000000 c340000000000002 c340000000000000 Wrong 66461 -bfb83950c7648672 8010000000000001 fedffffc003fffff 7ed00003ffc00001 fedffffc003fffff Wrong 666633 -3ca0000000000001 bcafffffffffffff 4340000000000000 c340000000000000 4340000000000000 Wrong 670661 -3ca0000000000001 c000000000000001 bcafffffffffffff bcb8000000000002 bcc0000000000001 Wrong 682745 -3ca0000000000001 c340000000000001 3ff0000000000001 bfe0000000000003 bcb0000000000001 Wrong 688787 -3fb0000001000004 8010007efffffffe 3fbffffbffffe000 bfb0000400002000 3fbffffbffffe000 Wrong 692815 -40afffffffbeffff c1f5bb80746eb9e1 7fd7fffffbfffffe ffd8000004000002 7fd7fffffbfffffe Wrong 704899 -3cafffffffffffff 3fd0000000000000 3cafffffffffffff 3ca7ffffffffffff 3cb3ffffffffffff Wrong 706913 -c3e02000000fffff 3fdfffffffffffff c0cfffff00008000 c3d0200000100006 c3d020000010000e Wrong 708927 -3b1001fffff7ffff c3ec47dbdb9fc9e2 c19f80000000001f c19f800000001c6a c19f800000000e45 Wrong 710941 -3cafffffffffffff 3feffffffffffffe bff0000000000001 3ff0000000000001 bff0000000000000 Wrong 712955 -c1dfffffefffdfff 4010000000000001 43e0004001000000 43e0004000800000 43e0004000c00000 Wrong 721011 -3f0fffffebfffffe 7fd0000000404000 7fd0000010200000 7fd00080101fb202 7fd00040101fd901 Wrong 729067 -38c000fffffffff6 bca0000000000000 37e76291995d8252 37e76291995d424e 37e76291995d6250 Wrong 739137 -37ffc3cd8026eda0 bfe0000000000000 beab43550afc66d5 bea0000000000000 beab43550afc66d5 Wrong 745179 -3caf0000007fffff 43c3ba241e9c39cf 43efeffdffffffff 43efeffe00000000 43efeffdffffffff Wrong 747193 -bfaffffdfffffeff c000000000000000 3f4000080000001f 3fc007ff03ffff80 3fc00fff07ffff80 Wrong 751221 -3cafffffffffffff c010000000000001 3cafffffffffffff bccc000000000001 bcc8000000000001 Wrong 755249 -3fd000000fbfffff c01ffffffffffffe 3fe00000fffffefe bffbffffdf80003c bff7ffff9f80007d Wrong 757263 -bfd000080000000f b7e1fbffffffffff b800200000003ffe b7ebc0fdc0807ff8 b7fe007ee0407ffa Wrong 771361 -3caffffffffffffe 3fdffffffffffffe bcafffffffffffff b967ffffffffffff bca0000000000001 Wrong 779417 -0020000020010000 3fefffffffffffff c1dffffff0100000 41d000000ff00000 c1dffffff0100000 Wrong 781431 -3caffffffffffffe 3ffffffffffffffe 3ff0000000000001 3ff0000000000005 3ff0000000000003 Wrong 785459 -3caffffffffffffe 401fffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong 791501 -b4b6e07873102932 434ff87fffffffff 47e34d80c103eaa3 c7ecb27f3efc155d 47e34d80c103eaa3 Wrong 795529 -405000ffffff7ffe 8010000000000000 3fbfe00100000000 bfb01fff00000000 3fbfe00100000000 Wrong 805599 -43e04001fffffffe f10581b664845094 7fe6e21da5190931 ffe91de25ae6f6cf 7fe6e21da5190931 Wrong 807613 -3caffffffffffffe bfe0000000000001 4340000000000000 c340000000000000 4340000000000000 Wrong 815669 -3caffffffffffffe c340000000000000 bcafffffffffffff bffffffffffffffe bfffffffffffffff Wrong 827753 -3ffb8acd8e55074b c34ffffffffffffe 41c3d05e9bb88a09 c35b8acd8960efa2 c35b8acd846cd7fb Wrong 829767 -3fd0000000000000 3feffffffffffffe 3cafffffffffffff 3fd0000000000001 3fd0000000000003 Wrong 851921 -f4d0700000000000 4061ae8809f49782 c3effffff7ffff7f f5422a4dc23a47a6 f5422a4dc23a47a7 Wrong 855949 -3fd0000000000000 400fffffffffffff bff0000000000001 3fdffffffffffffc bcb8000000000000 Wrong 857963 -3fd0000000000000 434fffffffffffff 4340000000000000 4330000000000000 4348000000000000 Wrong 864005 -4e2c074bc1e14068 41f007ffffdfffff ffeffff000003fff 7fe0000fffffc001 ffeffff000003fff Wrong 868033 -c03ffdfff7fffffe 8000000000000000 c3ffe01000000000 43f01ff000000000 c3ffe01000000000 Wrong 872061 -bec0001fffffdffe bca0000000000000 c7ecd2b1e4c50852 47e32d4e1b3af7ae c7ecd2b1e4c50852 Wrong 878103 -4030001000000040 41efffffffffffff 42e0000000003ffa 42e0040004003ffa 42e0020002003ffa Wrong 880117 -3fd0000000000000 bfd0000000000001 3ff0000000000001 3fdc000000000002 3fee000000000002 Wrong 882131 -4020001000000003 bfdffffffffffffe bfe007ffffffffbe c011008ffffffffe c012010ffffffffa Wrong 884145 -c02fffffffff7fff bffffffffffffffe bf6ffefffffffffc 403fff8003ff7ffd 403fff0007ff7ffd Wrong 890187 -3fd0000000000000 ffe0000000000000 3cafffffffffffff ffb0000000000000 ffc0000000000000 Wrong 900257 -bfc00000fffffe00 30dffe0000000007 3fdffff00000fffe bfd0000fffff0002 3fdffff00000fffe Wrong 916369 -3fd0000000000001 3fffffffffffffff bcafffffffffffff 3fdfffffffffffff 3fdffffffffffffd Wrong 924425 -3810000040040000 4000000000000001 c7efffffffdefffe 47e0000000210002 c7efffffffdefffe Wrong 926439 -3fd0000000000001 401fffffffffffff 3ff0000000000001 4004000000000000 4008000000000001 Wrong 930467 -3feffff77fffffff bfc0003fffffffbe 40200000fffbffff 402f7fff21fc8801 401f800021f88800 Wrong 94657 -3fd0000000000001 bca0000000000001 3cafffffffffffff 3c97fffffffffffe 3cabfffffffffffe Wrong 948593 -3fd0000000000001 bfe0000000000000 bff0000000000001 bfe4000000000001 bff2000000000001 Wrong 954635 -401ffdfffff00000 bfeffffffffffffe c3400d15caf2c5ca c3400d15caf2c5d2 c3400d15caf2c5ce Wrong 956649 -3fd0000000000001 c000000000000000 4340000000000000 c340000000000000 433fffffffffffff Wrong 960677 -c3cffffffffbffbf c34fffffffffffff 43d0ed5944b60c56 472ffffffffbffbe 472ffffffffbffbf Wrong 968733 -3fd0000000000001 ffeffffffffffffe bcafffffffffffff ffc0000000000000 ffd0000000000000 Wrong 972761 -3c300000fffff7ff c2bfff0000000004 bfcbfb075ca1326a bfcbfd074cc13169 bfcbfc0754b131ea Wrong 976789 -3fdfffffffffffff 3cafffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong 984845 -c0f0e9718d9cdce9 3fd0000000000001 c01ffffffffffefd c0d0ea718d9cdcea c0d0eb718d9cdcea Wrong 986859 -3fdfffffffffffff 400fffffffffffff 3cafffffffffffff 3ffffffffffffffe 3fffffffffffffff Wrong 996929 -bffffc03ffffffff 4010000000000000 c23fdf0000000000 c23fdf00000ffe02 c23fdf000007ff01 Wrong 998943 -00114508bde544e1 3caffffffffffffe 800010000003fffe 8000000000000000 800010000003fffd Wrong w=-zero zdenorm unflw 2310057 -8010000000803fff 3ff0000000000001 000fffe07fffffff 8000000000000000 8000001f80804001 Wrong w=-zero zdenorm unflw 5246469 -b7fffff80000001f 001ffffffffffffe 800fffffffff07ff 8000000000000000 800fffffffff07ff Wrong w=-zero zdenorm unflw 5723787 -0000000000000001 c010000000000000 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong xdenorm 126881 -000454b2b3078d3e 3fdffffffffffffe c1c3ffffffdfffff 41cc000000200001 c1c3ffffffdfffff Wrong xdenorm 1476261 -000fffffffffffff 3fdfffffffffffff bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong xdenorm 151049 -000fffffffffffff 4010000000000001 c340000000000000 4340000000000000 c340000000000000 Wrong xdenorm 163133 -800f00ffffffffff 801ffffffffffffe bf4ddfffffffffff 3f42200000000001 bf4ddfffffffffff Wrong xdenorm 1784403 -000fffffffffffff bfe0000000000000 4340000000000000 c340000000000000 4340000000000000 Wrong xdenorm 187301 -000ffffffffff07f 41e7fffffdfffffe c3dffffffff77fff 43d0000000088001 c3dffffffff77fff Wrong xdenorm 1967677 -000fffffffffffff ffeffffffffffffe 3ff0000000000001 bffbfffffffffffc c007fffffffffffc Wrong xdenorm 205427 -000ffffffffffffe c34ffffffffffffe 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong xdenorm 271889 -8000000000000001 c010000000000001 bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong xdenorm 3196217 -8000000000000001 ffe0000000000001 3ff0000000000001 3fd0000000000005 3ff0000000000003 Wrong xdenorm 3202259 -800fffffffffffff 3fe0000000000000 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong xdenorm 3220385 -800fffffffffffff 401ffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong xdenorm 3232469 -800fffffffffffff bfe0000000000001 c340000000000000 4340000000000000 c340000000000000 Wrong xdenorm 3256637 -800ffffffffffffe 0010000000000000 4340000000000000 c340000000000000 4340000000000000 Wrong xdenorm 3280805 -800ffffffffffffe ffe0000000000000 bcafffffffffffff 3feffffffffffffc 3ffffffffffffffb Wrong xdenorm 3341225 -000001000000007f c001fffffffff7ff 00bffffffffffff7 00bffffedffffff6 00bfffff6ffffff7 Wrong xdenorm 4698661 -00000004000007fe ffeffffffffffffe c030000003fffeff c0100002040002fe c0300001040000fe Wrong xdenorm 5016873 -00000000000003bf bff0000000000000 0ebffffefffffefe 8eb0000100000102 0ebffffefffffefe Wrong xdenorm 5838585 -000fffffffffffff 8000000000000001 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong xdenorm ydenorm 175217 -000ffffffffffffe 000fffffffffffff c340000000000000 4340000000000000 c340000000000000 Wrong xdenorm ydenorm 211469 -800fffffffffffff 800fffffffffffff bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong xdenorm ydenorm 3244553 -800ffffffdffffff bfcffe00003ffffe 800ffff01ffffffe 7ff0000000000000 800c00302077f7ff Wrong xdenorm zdenorm w=+inf 2475205 -3fe0000000000000 000fffffffffffff bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong ydenorm 1117769 -3ff0000000000000 800ffffffffffffe 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong ydenorm 1431953 -40278f9eb19e2877 800c3f9986c3abce 380ffffff8080000 b800000007f80000 380ffffff8080000 Wrong ydenorm 1460149 -380fffff7dfffffe 8000000000000001 3757eb54c3bc586f b75814ab3c43a791 3757eb54c3bc586f Wrong ydenorm 1500429 -4000000000000001 000ffffffffffffe bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong ydenorm 1746137 -c3d02003fffffffe 000fffffffffffff 415fffffeffe0000 c150000010020000 415fffffeffe0000 Wrong ydenorm 1814613 -cbe2b464d5fb92a3 800ffffffffffffe c6dffffffffffffe 46d0000000000002 c6dffffffffffffe Wrong ydenorm 1850865 -c02fffffbfffffef 8003fffffffff800 f00ffffffdfc0000 7000000002040000 f00ffffffdfc0000 Wrong ydenorm 1858921 -bfcff800000000ff 000fffffffffffff 3fc7fefffffffffe bfc8010000000002 3fc7fefffffffffe Wrong ydenorm 2013 -4100000800020000 800fffffffffffff 5c807ffffffeffff dc8f800000010001 5c807ffffffeffff Wrong ydenorm 2128797 -7fe3795af4a2b560 000ffffffffffffe 0020008000200000 3ff3795af4a2b55e 4003795af4a2b55e Wrong ydenorm 2304015 -c3faf80eb5114084 0003d852e11515f0 3d9fffefffffe000 bd90001000002000 3d9fffefffffe000 Wrong ydenorm 2463121 -7fe0000000000001 8000000000000001 bcafffffffffffff bcb4000000000001 bcc8000000000001 Wrong ydenorm 2616185 -7fefffffffffffff 000ffffffffffffe 4340000000000000 4340000000000004 4340000000000002 Wrong ydenorm 2652437 -c010077ffffffffe 800fffffffffffff c06ffe000000000e 406001fffffffff2 c06ffe000000000e Wrong ydenorm 2896131 -400f58f62ff4033a 800fffffffffffff 401fdffffffffdff c010200000000201 401fdffffffffdff Wrong ydenorm 3035097 -bfbf0000000000fe 8000000000000001 e17fffffffff8007 6170000000007ff9 e17fffffffff8007 Wrong ydenorm 3174063 -c7fffffbfffffff7 8000000000000001 c00ffeffffff7fff 4000010000008001 c00ffeffffff7fff Wrong ydenorm 3313029 -801ffffffffffffe 000ffffffffffffe 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong ydenorm 3558737 -bcaffffffffffffe 800ffffffffffffe bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong ydenorm 3872921 -c62020000000007f 800fffffffffffff bfdfffffffffffff 3fd0000000000001 bfdfffffffffffff Wrong ydenorm 3941397 -bf2ff00000000003 000ffffffffffffe 8022000000ffffff 802200ff80ffffff 8022007fc0ffffff Wrong ydenorm 4116615 -bfd23fffffffffff 000fffffffffffff 401ffffdffffffff c010000200000001 401ffffdffffffff Wrong ydenorm 4255581 -4f70000000040001 800fffffffffffff 1fcffffe00ffffff 9fc00001ff000001 1fcffffe00ffffff Wrong ydenorm 455163 -9f90040000001fff 8000ffe4b843faad b80ff7fffffe0000 3800080000020000 b80ff7fffffe0000 Wrong ydenorm 4813459 -c7ffff0000001fff 000ffffffffffffe 401b56e379b8ab6f c014a91c86475491 401b56e379b8ab6f Wrong ydenorm 4883949 -001ffffffffffffe 0000000000000001 bcafffffffffffff 3ca0000000000001 bcafffffffffffff Wrong ydenorm 489401 -001ffffffffffffe 800ffffffffffffe 4340000000000000 c340000000000000 4340000000000000 Wrong ydenorm 525653 -bfc75f2e65f71048 0000000000000001 400ffffffffffdfe c000000000000202 400ffffffffffdfe Wrong ydenorm 5300847 -257e2d1c6ce4bd4e 800ffffffffffffe 43d3ec126aa24cbc c3dc13ed955db344 43d3ec126aa24cbc Wrong ydenorm 5337099 -c09000003fffc000 800fffffffffffff c2bffffffefffdfe 42b0000001000202 c2bffffffefffdfe Wrong ydenorm 5476065 -ffe0000000000001 800ffffffffffffe 3cafffffffffffff 3feffffffffffffe 3fffffffffffffff Wrong ydenorm 5685521 -3fadcdbdd2c3f87e 8000000000000001 402fffffffe00007 c0200000001ffff9 402fffffffe00007 Wrong ydenorm 5753997 -3fb8cfdf5b77451d 000fffffffffffff c03fefeffffffffe 4030101000000002 c03fefeffffffffe Wrong ydenorm 5929215 -c1c0008007ffffff 8000000000000001 c6b4f3502e84a07b 46bb0cafd17b5f85 c6b4f3502e84a07b Wrong ydenorm 594129 -3caffffffffffffe 800fffffffffffff 3cafffffffffffff bca0000000000001 3cafffffffffffff Wrong ydenorm 803585 -3fd0000000000000 000ffffffffffffe c340000000000000 4340000000000000 c340000000000000 Wrong ydenorm 839837 -3fd34fb8606858f1 8000000000000001 0010000000f80000 fff0000000000000 0010000000f80000 Wrong ydenorm w=-inf 2267763 -c34fdffffffbffff 0000000000000001 00000007fbffffff 801fdffe00fbffff 802fdffc01fc0000 Wrong ydenorm zdenorm 4533513 -bfbfffff007fffff 000fffffffffffff 000bffffffc00000 fff0000000000000 000a00000fb80000 Wrong ydenorm zdenorm w=-inf 1675647 -401000ffffffffff 4ba80119d03cc382 800fe0000000001e 4bc80299e1d9c74c 4bc80299e1d9c74d Wrong zdenorm 5085349 -8020007ffdffffff 9beffff7fff7fffe 000ffffffff7fffe 0000000000000000 000ffffffff7fffe Wrong zdenorm unflw 475303 diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tb b/wally-pipelined/src/fpu/FMA/tbgen/tb deleted file mode 100755 index 3e3f76226..000000000 Binary files a/wally-pipelined/src/fpu/FMA/tbgen/tb and /dev/null differ diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tb.c b/wally-pipelined/src/fpu/FMA/tbgen/tb.c deleted file mode 100644 index 85fc22358..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/tb.c +++ /dev/null @@ -1,167 +0,0 @@ -#include -#include -#include - -void main() { - FILE *fp, *fq, *fr; - int cnt=0; - char *ln; - size_t nbytes = 80; - - ln = (char *)malloc(nbytes + 1); - - // fp = fopen("tb.dat","r"); - fp = fopen("testFloat","r"); - fq = fopen("tb.v","a"); - system("cp tbhead.v tb.v"); - long k=0L; - for(; !feof(fp); k++) { - //3FDBFFFFFFFFFF7F DE608000000001FF 43CFED83C17EDBD0 DE4CE000000002F9 01 - // b68ffff8000000ff_3f9080000007ffff_b6307ffbe0080080_00001 - char ch; - int i,j,n; - char FInput1E[17]; - char FInput2E[17]; - char FInput3E[17]; - char ans[81]; - char flags[3]; - int FrmE; - long stop = 556555; - int debug = 0; - int bits = 32; - //my_string = (char *) malloc (nbytes + 1); - //bytes_read = getline (&my_string, &nbytes, stdin); - - - for(n=0; n < 1000; n++) {//613 for 10000 - if(getline(&ln,&nbytes,fp) < 0 || feof(fp)) break; - if(k == stop && debug == 1) break; - k++; - } - //fprintf(stderr,"%s\n", ln); - - if(!feof(fp)) { - - strncpy(FInput1E, ln, bits/4); FInput1E[bits/4]=0; - strncpy(FInput2E, &ln[(bits/4)+1], bits/4); FInput2E[bits/4]=0; - strncpy(FInput3E, &ln[((bits/4)+1)*2], bits/4); FInput3E[bits/4]=0; - // fprintf(stdout,"[%s]\n[%s]\n", ln,FInput3E); - strncpy(ans, &ln[((bits/4)+1)*3], bits/4); ans[bits/4]=0; - strncpy(flags,&ln[((bits/4)+1)*4], 2); flags[2]=0; - - // fprintf(stdout,"[%s]\n[%s]\n", ln,FInput3E); - if (bits == 32){ - fprintf(fq," FInput1E = 64'h%s00000000;\n",FInput1E); - fprintf(fq," FInput2E = 64'h%s00000000;\n",FInput2E); - fprintf(fq," FInput3E = 64'h%s00000000;\n",FInput3E); - fprintf(fq," ans = 64'h%s00000000;\n", ans);} - else{ - fprintf(fq," FInput1E = 64'h%s;\n",FInput1E); - fprintf(fq," FInput2E = 64'h%s;\n",FInput2E); - fprintf(fq," FInput3E = 64'h%s;\n",FInput3E); - fprintf(fq," ans = 64'h%s;\n", ans);} - fprintf(fq," flags = 5'h%s;\n", flags); - - - fprintf(fq,"#10\n"); - if (bits == 32){ -// IEEE 754-2008 section 6.3 states "When ether an input or result is NaN, this standard does not interpret the sign of a NaN." - //fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h \",FInput1E,FInput2E,FmaResultM, ans);\n"); - fprintf(fq," // IEEE 754-2008 section 6.3 states: \"When ether an input or result is NaN, this\n"); - fprintf(fq," // standard does not interpret the sign of a NaN.\"\n"); - fprintf(fq," wnan = &FmaResultM[62:55] && |FmaResultM[54:32]; \n"); - fprintf(fq," xnan = &FInput1E[62:55] && |FInput1E[54:32]; \n"); - fprintf(fq," ynan = &FInput2E[62:55] && |FInput2E[54:32]; \n"); - fprintf(fq," znan = &FInput3E[62:55] && |FInput3E[54:32]; \n"); - fprintf(fq," ansnan = &ans[62:55] && |ans[54:32]; \n"); - fprintf(fq," xnorm = ~(|FInput1E[62:55]) && |FInput1E[54:32] ? {FInput1E[50:0], 1'b0} : FInput1E; \n"); - fprintf(fq," ynorm = ~(|FInput2E[62:55]) && |FInput2E[54:32] ? {FInput2E[50:0], 1'b0} : FInput2E;\n"); - // fprintf(fq," s = ({54'b1,xnorm} + (bypsel && bypplus1)) * {54'b1,ynorm}; \n"); - // fprintf(fq," if(!(~(|FInput1E[62:55]) && |FInput1E[54:32] || ~(|FInput2E[62:55]) && |FInput2E[54:32])) begin\n"); - // not looknig at negative zero results right now - //fprintf(fq," if( (nan && (FmaResultM[62:0] != ans[62:0])) || (!nan && (FmaResultM != ans)) && !(FmaResultM == 64'h8000000000000000 && ans == 64'b0)) begin\n"); - // fprintf(fq," if( (nan && (FmaResultM[62:0] != ans[62:0])) || (!nan && (FmaResultM != ans)) ) begin\n"); - fprintf(fq," if(FmaFlagsM != flags || (!wnan && (FmaResultM != ans)) || (wnan && ansnan && ~(((xnan && (FmaResultM[62:0] == {FInput1E[62:55],1'b1,FInput1E[53:0]})) || (ynan && (FmaResultM[62:0] == {FInput2E[62:55],1'b1,FInput2E[53:0]})) || (znan && (FmaResultM[62:0] == {FInput3E[62:55],1'b1,FInput3E[53:0]})) || (FmaResultM[62:0] == ans[62:0])) ))) begin\n"); - fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h %%h Wrong \",FInput1E,FInput2E, FInput3E, FmaResultM, ans);\n"); - //fprintf(fq," $fwrite(fp, \"%%h \",s);\n"); - // fprintf(fq," $fwrite(fp, \"FmaResultM=%%d \",$signed(aligncntE));\n"); - fprintf(fq," if(FmaResultM == 64'h8000000000000000) $fwrite(fp, \"FmaResultM=-zero \");\n"); - fprintf(fq," if(~(|FInput1E[62:55]) && |FInput1E[54:32]) $fwrite(fp, \"xdenorm \");\n"); - fprintf(fq," if(~(|FInput2E[62:55]) && |FInput2E[54:32]) $fwrite(fp, \"ydenorm \");\n"); - fprintf(fq," if(~(|FInput3E[62:55]) && |FInput3E[54:32]) $fwrite(fp, \"zdenorm \");\n"); - fprintf(fq," if(FmaFlagsM[4] != 0) $fwrite(fp, \"invld \");\n"); - fprintf(fq," if(FmaFlagsM[2] != 0) $fwrite(fp, \"ovrflw \");\n"); - fprintf(fq," if(FmaFlagsM[1] != 0) $fwrite(fp, \"unflw \");\n"); - fprintf(fq," if(FmaResultM == 64'hFF80000000000000) $fwrite(fp, \"FmaResultM=-inf \");\n"); - fprintf(fq," if(FmaResultM == 64'h7F80000000000000) $fwrite(fp, \"FmaResultM=+inf \");\n"); - fprintf(fq," if(&FmaResultM[62:55] && |FmaResultM[54:32] && ~FmaResultM[54]) $fwrite(fp, \"FmaResultM=sigNaN \");\n"); - fprintf(fq," if(&FmaResultM[62:55] && |FmaResultM[54:32] && FmaResultM[54] ) $fwrite(fp, \"FmaResultM=qutNaN \");\n"); - - fprintf(fq," if(ans == 64'hFF80000000000000) $fwrite(fp, \"ans=-inf \");\n"); - fprintf(fq," if(ans == 64'h7F80000000000000) $fwrite(fp, \"ans=+inf \");\n"); - fprintf(fq," if(&ans[62:55] && |ans[54:32] && ~ans[54] ) $fwrite(fp, \"ans=sigNaN \");\n"); - fprintf(fq," if(&ans[62:55] && |ans[54:32] && ans[54]) $fwrite(fp, \"ans=qutNaN \");\n"); - }//end if bits == 32 - else{ - // IEEE 754-2008 section 6.3 states "When ether an input or result is NaN, this standard does not interpret the sign of a NaN." - //fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h \",FInput1E,FInput2E,FmaResultM, ans);\n"); - fprintf(fq," // IEEE 754-2008 section 6.3 states: \"When ether an input or result is NaN, this\n"); - fprintf(fq," // standard does not interpret the sign of a NaN.\"\n"); - fprintf(fq," wnan = &FmaResultM[62:52] && |FmaResultM[51:0]; \n"); - fprintf(fq," xnan = &FInput1E[62:52] && |FInput1E[51:0]; \n"); - fprintf(fq," ynan = &FInput2E[62:52] && |FInput2E[51:0]; \n"); - fprintf(fq," znan = &FInput3E[62:52] && |FInput3E[51:0]; \n"); - fprintf(fq," ansnan = &ans[62:52] && |ans[51:0]; \n"); - fprintf(fq," xnorm = ~(|FInput1E[62:52]) && |FInput1E[51:0] ? {FInput1E[50:0], 1'b0} : FInput1E; \n"); - fprintf(fq," ynorm = ~(|FInput2E[62:52]) && |FInput2E[51:0] ? {FInput2E[50:0], 1'b0} : FInput2E;\n"); - // fprintf(fq," s = ({54'b1,xnorm} + (bypsel && bypplus1)) * {54'b1,ynorm}; \n"); - // fprintf(fq," if(!(~(|FInput1E[62:52]) && |FInput1E[51:0] || ~(|FInput2E[62:52]) && |FInput2E[51:0])) begin\n"); - // not looknig at negative zero results right now - //fprintf(fq," if( (nan && (FmaResultM[62:0] != ans[62:0])) || (!nan && (FmaResultM != ans)) && !(FmaResultM == 64'h8000000000000000 && ans == 64'b0)) begin\n"); - // fprintf(fq," if( (nan && (FmaResultM[62:0] != ans[62:0])) || (!nan && (FmaResultM != ans)) ) begin\n"); - fprintf(fq," if((!wnan && (FmaResultM != ans)) || (wnan && ansnan && ~(((xnan && (FmaResultM[62:0] == {FInput1E[62:52],1'b1,FInput1E[50:0]})) || (ynan && (FmaResultM[62:0] == {FInput2E[62:52],1'b1,FInput2E[50:0]})) || (znan && (FmaResultM[62:0] == {FInput3E[62:52],1'b1,FInput3E[50:0]})) || (FmaResultM[62:0] == ans[62:0])) ))) begin\n"); - fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h %%h Wrong \",FInput1E,FInput2E, FInput3E, FmaResultM, ans);\n"); - //fprintf(fq," $fwrite(fp, \"%%h \",s);\n"); - fprintf(fq," $fwrite(fp, \"FmaResultM=%%d \",$signed(aligncntE));\n"); - fprintf(fq," if(FmaResultM == 64'h8000000000000000) $fwrite(fp, \"FmaResultM=-zero \");\n"); - fprintf(fq," if(~(|FInput1E[62:52]) && |FInput1E[51:0]) $fwrite(fp, \"xdenorm \");\n"); - fprintf(fq," if(~(|FInput2E[62:52]) && |FInput2E[51:0]) $fwrite(fp, \"ydenorm \");\n"); - fprintf(fq," if(~(|FInput3E[62:52]) && |FInput3E[51:0]) $fwrite(fp, \"zdenorm \");\n"); - fprintf(fq," if(FmaFlagsM[4] != 0) $fwrite(fp, \"invld \");\n"); - fprintf(fq," if(FmaFlagsM[2] != 0) $fwrite(fp, \"ovrflw \");\n"); - fprintf(fq," if(FmaFlagsM[1] != 0) $fwrite(fp, \"unflw \");\n"); - fprintf(fq," if(FmaResultM == 64'hFFF0000000000000) $fwrite(fp, \"FmaResultM=-inf \");\n"); - fprintf(fq," if(FmaResultM == 64'h7FF0000000000000) $fwrite(fp, \"FmaResultM=+inf \");\n"); - fprintf(fq," if(FmaResultM > 64'h7FF0000000000000 && FmaResultM < 64'h7FF8000000000000 ) $fwrite(fp, \"FmaResultM=sigNaN \");\n"); - fprintf(fq," if(FmaResultM > 64'hFFF8000000000000 && FmaResultM < 64'hFFF8000000000000 ) $fwrite(fp, \"FmaResultM=sigNaN \");\n"); - fprintf(fq," if(FmaResultM >= 64'h7FF8000000000000 && FmaResultM <= 64'h7FFfffffffffffff ) $fwrite(fp, \"FmaResultM=qutNaN \");\n"); - fprintf(fq," if(FmaResultM >= 64'hFFF8000000000000 && FmaResultM <= 64'hFFFfffffffffffff ) $fwrite(fp, \"FmaResultM=qutNaN \");\n"); - - fprintf(fq," if(ans == 64'hFFF0000000000000) $fwrite(fp, \"ans=-inf \");\n"); - fprintf(fq," if(ans == 64'h7FF0000000000000) $fwrite(fp, \"ans=+inf \");\n"); - fprintf(fq," if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, \"ans=sigNaN \");\n"); - fprintf(fq," if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, \"ans=sigNaN \");\n"); - fprintf(fq," if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, \"ans=qutNaN \");\n"); - fprintf(fq," if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, \"ans=qutNaN \");\n"); - }//end else - - fprintf(fq," $fwrite(fp,\"%s \");\n",flags); - - fprintf(fq," $fwrite(fp,\"%ld\\n\");\n",k); - //fprintf(fq," $stop;\n"); - // fprintf(fq," end\n"); - fprintf(fq," end\n"); - cnt++; - - //if(cnt > 100) break; - fflush(fq); - } // if(!feof(fp)) - if(k == stop && debug == 1) break; - } // for(k) - - fprintf(fq, "\t$stop;\n\tend\nendmodule"); - fclose(fq); - fclose(fp); - fprintf(stdout,"cnt = %d\n",cnt); -} - diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tb.sv b/wally-pipelined/src/fpu/FMA/tbgen/tb.sv deleted file mode 100644 index 5a8e7a868..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/tb.sv +++ /dev/null @@ -1,142 +0,0 @@ -module testbench3(); - - logic [31:0] errors=0; - logic [31:0] vectornum=0; - logic [264:0] testvectors[6133248:0]; - - logic [63:0] FInput1E,FInput2E,FInput3E; - logic [63:0] ans; - logic [7:0] flags; - logic [2:0] FrmE; - logic FmtE; - logic [63:0] FmaResultM; - logic [4:0] FmaFlagsM; -integer fp; -logic [2:0] FOpCtrlE; -logic [105:0] ProdManE; -logic [161:0] AlignedAddendE; -logic [12:0] ProdExpE; -logic AddendStickyE; -logic KillProdE; -logic XZeroE; -logic YZeroE; -logic ZZeroE; -logic XDenormE; -logic YDenormE; -logic ZDenormE; -logic XInfE; -logic YInfE; -logic ZInfE; -logic XNaNE; -logic YNaNE; -logic ZNaNE; - -logic wnan; -logic xnan; -logic ynan; -logic znan; -logic ansnan, clk; - - -assign FOpCtrlE = 3'b0; - -// nearest even - 000 -// twords zero - 001 -// down - 010 -// up - 011 -// nearest max mag - 100 -assign FrmE = 3'b011; -assign FmtE = 1'b0; - - -assign wnan = FmtE ? &FmaResultM[62:52] && |FmaResultM[51:0] : &FmaResultM[62:55] && |FmaResultM[54:32]; -assign xnan = FmtE ? &FInput1E[62:52] && |FInput1E[51:0] : &FInput1E[62:55] && |FInput1E[54:32]; -assign ynan = FmtE ? &FInput2E[62:52] && |FInput2E[51:0] : &FInput2E[62:55] && |FInput2E[54:32]; -assign znan = FmtE ? &FInput3E[62:52] && |FInput3E[51:0] : &FInput3E[62:55] && |FInput3E[54:32]; -assign ansnan = FmtE ? &ans[62:52] && |ans[51:0] : &ans[62:55] && |ans[54:32]; - // instantiate device under test -fma1 UUT1(.X(FInput1E), .Y(FInput2E), .Z(FInput3E), .*); -fma2 UUT2(.X(FInput1E), .Y(FInput2E), .Z(FInput3E), .FrmM(FrmE), .ProdManM(ProdManE), - .AlignedAddendM(AlignedAddendE), .ProdExpM(ProdExpE), .AddendStickyM(AddendStickyE),.KillProdM(KillProdE), .FOpCtrlM(FOpCtrlE), - .XZeroM(XZeroE),.YZeroM(YZeroE),.ZZeroM(ZZeroE),.XInfM(XInfE),.YInfM(YInfE),.ZInfM(ZInfE),.XNaNM(XNaNE),.YNaNM(YNaNE),.ZNaNM(ZNaNE), .FmtM(FmtE), .*); - - - // generate clock - always - begin - clk = 1; #5; clk = 0; #5; - end - // at start of test, load vectors - // and pulse reset - initial - begin - $readmemh("testFloatNoSpace", testvectors); - end - // apply test vectors on rising edge of clk -always @(posedge clk) - begin - #1; - if (FmtE==1'b1) {FInput1E, FInput2E, FInput3E, ans, flags} = testvectors[vectornum]; - else begin FInput1E = {testvectors[vectornum][135:104],32'b0}; - FInput2E = {testvectors[vectornum][103:72],32'b0}; - FInput3E = {testvectors[vectornum][71:40],32'b0}; - ans = {testvectors[vectornum][39:8],32'b0}; - flags = testvectors[vectornum][7:0]; - end - end - // check results on falling edge of clk - always @(negedge clk) begin - - // fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w"); - if((FmtE==1'b1) & (FmaFlagsM != flags[4:0] || (!wnan && (FmaResultM != ans)) || (wnan && ansnan && ~((xnan && (FmaResultM[62:0] == {FInput1E[62:52],1'b1,FInput1E[50:0]})) || (ynan && (FmaResultM[62:0] == {FInput2E[62:52],1'b1,FInput2E[50:0]})) || (znan && (FmaResultM[62:0] == {FInput3E[62:52],1'b1,FInput3E[50:0]})) || (FmaResultM[62:0] == ans[62:0]))))) begin - $display( "%h %h %h %h %h %h %h Wrong ",FInput1E,FInput2E, FInput3E, FmaResultM, ans, FmaFlagsM, flags); - if(FmaResultM == 64'h8000000000000000) $display( "FmaResultM=-zero "); - if(~(|FInput1E[62:52]) && |FInput1E[51:0]) $display( "xdenorm "); - if(~(|FInput2E[62:52]) && |FInput2E[51:0]) $display( "ydenorm "); - if(~(|FInput3E[62:52]) && |FInput3E[51:0]) $display( "zdenorm "); - if(FmaFlagsM[4] != 0) $display( "invld "); - if(FmaFlagsM[2] != 0) $display( "ovrflw "); - if(FmaFlagsM[1] != 0) $display( "unflw "); - if(FmaResultM == 64'hFFF0000000000000) $display( "FmaResultM=-inf "); - if(FmaResultM == 64'h7FF0000000000000) $display( "FmaResultM=+inf "); - if(FmaResultM > 64'h7FF0000000000000 && FmaResultM < 64'h7FF8000000000000 ) $display( "FmaResultM=sigNaN "); - if(FmaResultM > 64'hFFF8000000000000 && FmaResultM < 64'hFFF8000000000000 ) $display( "FmaResultM=sigNaN "); - if(FmaResultM >= 64'h7FF8000000000000 && FmaResultM <= 64'h7FFfffffffffffff ) $display( "FmaResultM=qutNaN "); - if(FmaResultM >= 64'hFFF8000000000000 && FmaResultM <= 64'hFFFfffffffffffff ) $display( "FmaResultM=qutNaN "); - if(ans == 64'hFFF0000000000000) $display( "ans=-inf "); - if(ans == 64'h7FF0000000000000) $display( "ans=+inf "); - if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $display( "ans=sigNaN "); - if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $display( "ans=sigNaN "); - if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $display( "ans=qutNaN "); - if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $display( "ans=qutNaN "); - errors = errors + 1; - $stop; - end - if((FmtE==1'b0)&(FmaFlagsM != flags[4:0] || (!wnan && (FmaResultM != ans)) || (wnan && ansnan && ~(((xnan && (FmaResultM[62:0] == {FInput1E[62:55],1'b1,FInput1E[53:0]})) || (ynan && (FmaResultM[62:0] == {FInput2E[62:55],1'b1,FInput2E[53:0]})) || (znan && (FmaResultM[62:0] == {FInput3E[62:55],1'b1,FInput3E[53:0]})) || (FmaResultM[62:0] == ans[62:0]))) ))) begin - $display( "%h %h %h %h %h %h %h Wrong ",FInput1E,FInput2E, FInput3E, FmaResultM, ans, FmaFlagsM, flags); - if(FmaResultM == 64'h8000000000000000) $display( "FmaResultM=-zero "); - if(~(|FInput1E[62:55]) && |FInput1E[54:32]) $display( "xdenorm "); - if(~(|FInput2E[62:55]) && |FInput2E[54:32]) $display( "ydenorm "); - if(~(|FInput3E[62:55]) && |FInput3E[54:32]) $display( "zdenorm "); - if(FmaFlagsM[4] != 0) $display( "invld "); - if(FmaFlagsM[2] != 0) $display( "ovrflw "); - if(FmaFlagsM[1] != 0) $display( "unflw "); - if(FmaResultM == 64'hFF80000000000000) $display( "FmaResultM=-inf "); - if(FmaResultM == 64'h7F80000000000000) $display( "FmaResultM=+inf "); - if(&FmaResultM[62:55] && |FmaResultM[54:32] && ~FmaResultM[54]) $display( "FmaResultM=sigNaN "); - if(&FmaResultM[62:55] && |FmaResultM[54:32] && FmaResultM[54] ) $display( "FmaResultM=qutNaN "); - if(ans == 64'hFF80000000000000) $display( "ans=-inf "); - if(ans == 64'h7F80000000000000) $display( "ans=+inf "); - if(&ans[62:55] && |ans[54:32] && ~ans[54] ) $display( "ans=sigNaN "); - if(&ans[62:55] && |ans[54:32] && ans[54]) $display( "ans=qutNaN "); - errors = errors + 1; - //if (errors == 10) - $stop; - end - vectornum = vectornum + 1; - if (testvectors[vectornum] === 194'bx) begin - $display("%d tests completed with %d errors", vectornum, errors); - $stop; - end - end -endmodule diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tb.v b/wally-pipelined/src/fpu/FMA/tbgen/tb.v deleted file mode 100644 index 89322456b..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/tb.v +++ /dev/null @@ -1,32072 +0,0 @@ - -# b7af837a135ee92b 0000000000000001 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# ydenorm -# zdenorm -# 3ca001fffff00000 0010000000000001 8010000000000000 8010000000000000 8010000000000000 01 03 Wrong -# 3c473b766ac099d4 8010000000000001 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# zdenorm -# 1c641420ab961345 8ceee6be68d6f224 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# zdenorm -# 37efffffbfffff80 800ff00000002000 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# ydenorm -# zdenorm -# 000130f47e558cd8 b7e67db1e2e6bcc6 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# zdenorm -# 028ffffdffffffbf 800fbfffdfffffff 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# ydenorm -# zdenorm -# 0000000000000001 bcaff7efffffffff 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# zdenorm -# b7affff800040000 000fffffffffffff 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# ydenorm -# zdenorm -# 800ff7ffffffefff 001fffffffffffff 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# zdenorm -# b7e0101ffffffffe 001ffffffffffffe 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# zdenorm -# 0000000000000001 802000000000043f 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# zdenorm -# 0000000000000001 3fe0000000000000 8010000000000000 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 3fe0000000000001 8010000000000000 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 3fefffffffffffff 8010000000000000 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 3feffffffffffffe 8010000000000000 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 bfd01fffdfffffff 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# zdenorm -# 0000000000000001 3fffffffffffffff 8010000000000001 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 3ffffffffffffffe 8010000000000001 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm -# 0000000000000001 b80ffffffff80003 800fffffffffffff 8010000000000000 8010000000000000 01 03 Wrong -# xdenorm `timescale 1 ns/10 ps -module tb; - - - reg [63:0] FInput1E; - reg [63:0] FInput2E; - reg [63:0] FInput3E; - reg [63:0] ans; - wire [2:0] FrmE; - wire [63:0] FmaResultM; - wire [4:0] FmaFlagsM; - reg [4:0] flags; - wire FmtE; - - wire [12:0] aligncntE; // status flags - wire [105:0] ProdManE; // other result of partial products - wire [161:0] AlignedAddendE; // wire of alignment shifter - wire [8:0] normcntE; // shift count for normalizer - wire [12:0] ProdExpE; // multiplier expoent - wire AddendStickyE; // sticky bit of addend - wire KillProdE; // FInput3E >> product - wire prodofE; // FInput1E*FInput2E out of range - wire XZeroE; - wire YZeroE; - wire ZZeroE; - wire XDenormE; - wire YDenormE; - wire ZDenormE; - wire XInfE; - wire YInfE; - wire ZInfE; - wire XNaNE; - wire YNaNE; - wire ZNaNE; - wire nanE; - wire [8:0] sumshiftE; - wire sumshiftzeroE; - wire prodinfE; - -integer fp; -reg wnan; -reg xnan; -reg ynan; -reg znan; -reg ansnan; -reg [105:0] s; // partial product 2 -reg [51:0] xnorm; -reg [51:0] ynorm; -wire [2:0] FOpCtrlE; -assign FOpCtrlE = 3'b0; -// nearest even - 000 -// twords zero - 001 -// down - 010 -// up - 011 -// nearest max mag - 100 -assign FrmE = 3'b000; -assign FmtE = 1'b1; - - -localparam period = 20; -fma1 UUT1(.*); -fma2 UUT2(.FInput1M(FInput1E), .FInput2M(FInput2E), .FInput3M(FInput3E), .FrmM(FrmE), .ProdManM(ProdManE), - .AlignedAddendM(AlignedAddendE), .ProdExpM(ProdExpE), .AddendStickyM(AddendStickyE),.KillProdM(KillProdE), .FOpCtrlM(FOpCtrlE), - .XZeroM(XZeroE),.YZeroM(YZeroE),.ZZeroM(ZZeroE),.XInfM(XInfE),.YInfM(YInfE),.ZInfM(ZInfE),.XNaNM(XNaNE),.YNaNM(YNaNE),.ZNaNM(ZNaNE), .FmtM(FmtE), .*); - - -initial - begin - fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w"); - xrf = 64'hb68ffff8000000ff; - y = 64'h3f9080000007ffff; - zrf = 64'h0000000000000000; - ans = 64'hb6307ffbe0080080; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'ha57f319ede38f755; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e00003fffbffff; - y = 64'hbfdfffffffefffff; - zrf = 64'h0000000000000000; - ans = 64'hc1d00003fff3fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h80251295103185ae; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc040000000001000; - y = 64'h802fff7fffffffc0; - zrf = 64'h0000000000000000; - ans = 64'h007fff8000001fc0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfffffffe00080; - y = 64'h3fa48edf3623f067; - zrf = 64'h0000000000000000; - ans = 64'hc1948edf360f61da; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h47fffffffff9fffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d36fa3cad3f59e; - y = 64'h802ffdfffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h84136e6cce2953e4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7f7fd5b86c89ff5; - y = 64'hc340097b5e4f0be0; - zrf = 64'h0000000000000000; - ans = 64'h4b480b93035b0b70; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc22000007fffffff; - y = 64'h24700000ffffffef; - zrf = 64'h0000000000000000; - ans = 64'ha6a00001800007ed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc3e000000ffdffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h353437f613f7e662; - y = 64'h37f1000000007fff; - zrf = 64'h0000000000000000; - ans = 64'h2d357b7575380687; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe564443115fb16; - y = 64'h3fbfffffeffbffff; - zrf = 64'h0000000000000000; - ans = 64'hffb5644426612c74; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ceec111f7d2af02; - y = 64'h39715bac743e2963; - zrf = 64'h0000000000000000; - ans = 64'h3670aeac5438df23; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h41ec86d0aa48e2a2; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400effffffffefff; - y = 64'hc7e10000000000ff; - zrf = 64'h0000000000000000; - ans = 64'hc80077fffffff876; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff007fffffffffb; - y = 64'hbe6ffffffff87fff; - zrf = 64'h0000000000000000; - ans = 64'h3e7007fffffc3e1b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03000ffffffffe0; - y = 64'h47effdfffdffffff; - zrf = 64'h0000000000000000; - ans = 64'hc82fffffddffdfbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hba2fffdffff7ffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc00000000011fe; - y = 64'h3fdfffffffffff03; - zrf = 64'h0000000000000000; - ans = 64'hbfb000000000117f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e0000020007ffe; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0400000020007ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cfdeed86c3bb69; - y = 64'h400003ffffbffffe; - zrf = 64'h0000000000000000; - ans = 64'hc1dfe6e541a5f09d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc25f117a8f103940; - y = 64'h4004e72ff4f60ee2; - zrf = 64'h0000000000000000; - ans = 64'hc2744b6155a30e59; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc01f000000080000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc513492fa35969e3; - y = 64'hbfcffdffffffffef; - zrf = 64'h0000000000000000; - ans = 64'h44f347fb105f3443; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403000000000fffe; - y = 64'h0010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0050000000010000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf6d01003ffffffff; - y = 64'h419ffffffdffefff; - zrf = 64'h0000000000000000; - ans = 64'hf8801003fefef7b6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h0010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha83100000007fffe; - y = 64'h41e0000effffffff; - zrf = 64'h0000000000000000; - ans = 64'haa21000ff0080004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc3fffffdfffffffd; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d000fffffdffff; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h020000fffffdffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d08000001fffff; - y = 64'h40200000000005ff; - zrf = 64'h0000000000000000; - ans = 64'hc40080000020062d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1a6ffffffffdffee; - y = 64'hc0dfdffffffff7ff; - zrf = 64'h0000000000000000; - ans = 64'h9b5fdffffffdf9ed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4800040080000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3eb000000000003f; - y = 64'h37ec0c2ea2e8a60d; - zrf = 64'h0000000000000000; - ans = 64'h36ac0c2ea2e8a67c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf17ffffffff7fff0; - y = 64'h001ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb1affffffff7ffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02ffffffe7fffff; - y = 64'hbfb000000007ffbe; - zrf = 64'h0000000000000000; - ans = 64'h3feffffffe8fff7b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h001ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffeffbfffffffefe; - y = 64'h41e003ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h81e001ff7fffff7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h434000080000003e; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbacc892b4c13f29c; - y = 64'h41e00000081fffff; - zrf = 64'h0000000000000000; - ans = 64'hbcbc892b5a919a96; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h50e0100000001000; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4d90100000001000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc04000010000000e; - y = 64'h3cc1ffffc0000000; - zrf = 64'h0000000000000000; - ans = 64'hbd120000dffffc0f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d40000001007fff; - y = 64'heca000001bffffff; - zrf = 64'h0000000000000000; - ans = 64'he9f000001d007fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f69ffffffffffff; - y = 64'h404716ea43fac45c; - zrf = 64'h0000000000000000; - ans = 64'h3fc2c29e573bbf8b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400327ca64d70ec7; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3cb327ca64d70ec9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd8bfff000000007f; - y = 64'hb956dbd0aee817c4; - zrf = 64'h0000000000000000; - ans = 64'h5226db19d062a0de; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc007b8561c35da43; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h405f40f41f6021f8; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe00100001fffff; - y = 64'hc24003ffffffffbf; - zrf = 64'h0000000000000000; - ans = 64'h42300500402007be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434fffffffffc003; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h400fffffffffc003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03ffffffbfffffb; - y = 64'hc02ffffffefffeff; - zrf = 64'h0000000000000000; - ans = 64'h407ffffffafffefb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40086202321a401c; - y = 64'h47f86177898dd055; - zrf = 64'h0000000000000000; - ans = 64'h481293c5d18361f7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h43e207ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43effe000fffffff; - y = 64'ha18c4acaee4cfd09; - zrf = 64'h0000000000000000; - ans = 64'ha58c49064fc37daf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h74cffffffbff7fff; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h718ffffffbff7ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5be00000ffffffbf; - y = 64'h421ffffffdffe000; - zrf = 64'h0000000000000000; - ans = 64'h5e100000feffefaf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf47ffe000000000; - y = 64'hc1ea1adf9696cf65; - zrf = 64'h0000000000000000; - ans = 64'h4143940d961184f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h348ffffffdffffdf; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0200003ffffffbf; - y = 64'h40affffbfffffff7; - zrf = 64'h0000000000000000; - ans = 64'hc0e00001ffff7fba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdf7cc18997a120; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3fbf7cc18997a120; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf70200000000003; - y = 64'hc3e0e4757c2948e7; - zrf = 64'h0000000000000000; - ans = 64'h4361063e67219b7c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dfffff7ffffe00; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hfaeffffffffff010; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41dff52055724a9e; - y = 64'h41f3fffe00000000; - zrf = 64'h0000000000000000; - ans = 64'h43e3f9323615694c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c567a7fb6402c6; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc3a567a7fb6402c7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e0000000000004; - y = 64'h388fffffffffff7e; - zrf = 64'h0000000000000000; - ans = 64'h3a7fffffffffff86; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41bfffffffffffff; - y = 64'hed6fffffffffffe8; - zrf = 64'h0000000000000000; - ans = 64'hef3fffffffffffe7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381ffffbffffffee; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h380ffffbffffffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ffffffffeffc00; - y = 64'hce70000800000001; - zrf = 64'h0000000000000000; - ans = 64'h50800007fff7fdfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1500007f0000000; - y = 64'h80201fffff7ffffe; - zrf = 64'h0000000000000000; - ans = 64'h01802007ff5fffbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1cecf3286229074; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43df400000000000; - y = 64'hbfefffffc003ffff; - zrf = 64'h0000000000000000; - ans = 64'hc3df3fffc183e7ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43dfffffffffff07; - y = 64'h80200007f7ffffff; - zrf = 64'h0000000000000000; - ans = 64'h84100007f7ffff82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80e0000001ffffe; - y = 64'hb7efffffffffffe6; - zrf = 64'h0000000000000000; - ans = 64'h400e0000001fffe6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1c0000000002003; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f500000000000fa; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3f400000000000fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hc7ffffffffefffdf; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0004000000080; - y = 64'h401ffffffffff801; - zrf = 64'h0000000000000000; - ans = 64'hc010003ffffffc80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb7f17fffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fc3945feb77579; - y = 64'hc01000100fffffff; - zrf = 64'h0000000000000000; - ans = 64'h441c39625436ba2e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40300020001fffff; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4020002000200001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcd100100000fffff; - y = 64'h381fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc5400100000ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffefffffffffdf; - y = 64'hbff8000001000000; - zrf = 64'h0000000000000000; - ans = 64'hc207f40000ff7fe7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h57f01fffffff7fff; - y = 64'h3fd00001f7ffffff; - zrf = 64'h0000000000000000; - ans = 64'h57d02001fbef7ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc870200000010000; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc87020000000ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e2fffe000000fff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe36f03e8c9d3cd8; - y = 64'hc7f9a4a35fede985; - zrf = 64'h0000000000000000; - ans = 64'h464261b53aedde07; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc180001ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fffffffef0000; - y = 64'h401b5b155998eecc; - zrf = 64'h0000000000000000; - ans = 64'hc04b5b15598a6668; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb0000400100000; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfb00004000ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc8000000400000; - y = 64'hc040000000005fff; - zrf = 64'h0000000000000000; - ans = 64'h4018000000408fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fbe26137bc2717f; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00aaa4fd557ef13; - y = 64'hc3b8917384eb32d0; - zrf = 64'h0000000000000000; - ans = 64'h43d478efdc9216d8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h33b002000007ffff; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h33b002000007ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f50000000000000; - y = 64'hc1cf9ffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc12f9ffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb3f000000ffffe00; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fffffffeffffff6; - y = 64'h3fdfffffffff0020; - zrf = 64'h0000000000000000; - ans = 64'h3fefffffefff0017; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf6fffffffffff3f; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbf6fffffffffff40; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47fffc0000000001; - y = 64'hc03fffff7fffff7f; - zrf = 64'h0000000000000000; - ans = 64'hc84ffbff800fff80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caffe000000ffff; - y = 64'h3fdffc7fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3c9ffa803800ffe3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbaa6a91cddacae08; - y = 64'h510ff80000020000; - zrf = 64'h0000000000000000; - ans = 64'hcbc6a3729676ad6e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40300000083fffff; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h40400000083fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3cd00fffff7fffff; - y = 64'hffebc7d81171f5ef; - zrf = 64'h0000000000000000; - ans = 64'hfccbe39fe8a52922; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha1407fff7fffffff; - y = 64'h41cfffbffffffffe; - zrf = 64'h0000000000000000; - ans = 64'ha3207fde8000fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc030080000ffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4150040020000000; - y = 64'h2eedc50618875049; - zrf = 64'h0000000000000000; - ans = 64'h304dcc7795977e4f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc676f7e5d9e346; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfd676f7e5d9e344; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc18aca47203438e2; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbd607ffffffffbfe; - y = 64'h4024e704bfc3d6c1; - zrf = 64'h0000000000000000; - ans = 64'hbd958e3ce5c1f03a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40664093b187b4e5; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h40764093b187b4e5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffa5cf563cae7d4; - y = 64'hbfeffbffffffffee; - zrf = 64'h0000000000000000; - ans = 64'h3ffa59a9c51e6e69; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcffffffffbffde; - y = 64'hc02fbffdffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc00fbffdfffc07dd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7fedfffffdfffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e0ff7ffffffffe; - y = 64'hc7effffffffff7ef; - zrf = 64'h0000000000000000; - ans = 64'hcbe0ff7ffffffbb5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8ad00000000041ff; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8ae0000000004200; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5dfffffffff7fffc; - y = 64'hbfffff8000010000; - zrf = 64'h0000000000000000; - ans = 64'hde0fff7ffff9001c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffefffffdfffffee; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3cd000000043fffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01d9eadf45189b8; - y = 64'h3f50000000ffffbf; - zrf = 64'h0000000000000000; - ans = 64'hbf7d9eadf62b741e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37effffeffffff00; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h380ffffeffffff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffe58b7bfa0536fd; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc190000007fffeff; - y = 64'h429455aca15996be; - zrf = 64'h0000000000000000; - ans = 64'hc43455acab846bc8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f00000000fffc0; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h44100000000fffbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47efff0008000000; - y = 64'hb1dcb0523546117f; - zrf = 64'h0000000000000000; - ans = 64'hb9dcaf6cb9e07bdb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb800003ffe000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0000000000000; - y = 64'hc1ffffffffff0008; - zrf = 64'h0000000000000000; - ans = 64'h41efffffffff0008; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41edfffffffffffe; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h420dfffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc0000000000017; - y = 64'hbfe2697f4b561495; - zrf = 64'h0000000000000000; - ans = 64'h3fb2697f4b5614b0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff3fffffbffffff; - y = 64'hbbefffeffffffdff; - zrf = 64'h0000000000000000; - ans = 64'hbbf3fff5fc0000be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1c0000007ffbffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcbd27c9d3cfce9; - y = 64'h3fbf7ffffeffffff; - zrf = 64'h0000000000000000; - ans = 64'h3f9b6332a9e97510; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404fffff000007fe; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h406fffff00000800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f000ffffff7fff; - y = 64'h22300000001fffdf; - zrf = 64'h0000000000000000; - ans = 64'h26300100001f81de; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'habc0000000000022; - y = 64'hc23ff803ffffffff; - zrf = 64'h0000000000000000; - ans = 64'h2e0ff80400000043; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbca00001ff7ffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbfffc001000000; - y = 64'h40c00000000040ff; - zrf = 64'h0000000000000000; - ans = 64'hc08fffc0010081fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c07ffffffff7fe; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc1f07ffffffff7fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf5bfffffffffffa; - y = 64'hbfe6386ce8894329; - zrf = 64'h0000000000000000; - ans = 64'h3f53715f4b781ac0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47ffffbfffefffff; - y = 64'h381001fdffffffff; - zrf = 64'h0000000000000000; - ans = 64'h402001ddfbfbff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h078fffffffff00fe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402ff000001fffff; - y = 64'h40759558e27de226; - zrf = 64'h0000000000000000; - ans = 64'h40b58a8e3622388e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb57e5a898766cf; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3fe57e5a898766ce; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb813d14cf9cc6a0f; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc01002003ffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe000010003ffff; - y = 64'heb50000000007f7e; - zrf = 64'h0000000000000000; - ans = 64'h2b40000100047f7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf020400000000100; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'hf370400000000100; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f4000400000000; - y = 64'hbf9fffbfc0000000; - zrf = 64'h0000000000000000; - ans = 64'hc7a3ffdbd7f7f800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdf7ffffefffffe; - y = 64'h3e2ffffffe007fff; - zrf = 64'h0000000000000000; - ans = 64'hbe1f7ffffd087dfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h40efdeffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40bffffff0010000; - y = 64'hc00fffbf7fffffff; - zrf = 64'h0000000000000000; - ans = 64'hc0dfffbf7001203c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80ffffffffdfeff; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbb5ffffffffdff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7efe0000000001f; - y = 64'h41cb6efdcaa9034a; - zrf = 64'h0000000000000000; - ans = 64'hc9cb538eccde5a61; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400ffffff00007ff; - y = 64'hc1e40fffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc2040ffff5f80502; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfdfffff8001ffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c001ffffffff7f; - y = 64'h43e061baf61ffb1f; - zrf = 64'h0000000000000000; - ans = 64'h45b063c72d7ebe9b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e0080000003ffe; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3b40080000003ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f9046426f60438; - y = 64'hbf7ffff7fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4189045de5dcfa79; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03ffffffc00fffe; - y = 64'h802002000007ffff; - zrf = 64'h0000000000000000; - ans = 64'h007001fffe08400e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc5b00010000003fe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3770000000000107; - y = 64'h3fd48f00324582ef; - zrf = 64'h0000000000000000; - ans = 64'h37548f0032458441; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb5affffffff7fffe; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb90ffffffff7fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0c468246a1620; - y = 64'hbf9fc40000000000; - zrf = 64'h0000000000000000; - ans = 64'hbf70a4f7e125cf36; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0200000001fffff; - y = 64'hbfc000ffffbffffe; - zrf = 64'h0000000000000000; - ans = 64'h3ff000ffffe001fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1f6c9921fedfd35; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02e0000ffffffff; - y = 64'h3f8fc00000000100; - zrf = 64'h0000000000000000; - ans = 64'hbfcdc400fe0000ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80f48a9d9dbc8c6; - y = 64'hc1c007ffffeffffe; - zrf = 64'h0000000000000000; - ans = 64'h49df584e2ea96dfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc02000003fff7fff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7feffff800010000; - y = 64'h37f21ffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h77f21ffb780090ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80c5e05644472e7; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h87fc5e05644472e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfeffffffffffaff; - y = 64'hbf800003fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3f800003fffffd7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3cbfffffffe00ffe; - y = 64'hc1cc000001000000; - zrf = 64'h0000000000000000; - ans = 64'hbe9c000000e40dfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb80fffffffc20000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb35e061abc769f3a; - y = 64'hc078000003fffffe; - zrf = 64'h0000000000000000; - ans = 64'h33e684941119bac2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0ae000000000fff; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h80ae000000000ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h643cfffffffffffe; - y = 64'h3fc000000807ffff; - zrf = 64'h0000000000000000; - ans = 64'h640d00000e8e7ffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3efffdffffdfffe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ff000000fffff80; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0114a0730d7f7a8; - y = 64'hc3dffc0000fffffe; - zrf = 64'h0000000000000000; - ans = 64'h440147ddf07c2ce2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc071f1a35952c0a4; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h8071f1a35952c0a2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf74200a147ea166; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403a793cfb1e2471; - y = 64'hbff0000100007fff; - zrf = 64'h0000000000000000; - ans = 64'hc03a793ea2b2c7eb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fd00003fffbfffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc09fffff7ffffff0; - y = 64'h3cabffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbd5bffff8ffffff1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3800008000000002; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7800008000000002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3dafffc3fffffffe; - y = 64'h480ffff800000002; - zrf = 64'h0000000000000000; - ans = 64'h45cfffbc000f0000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40cffffffffff880; - y = 64'h39100003fff00000; - zrf = 64'h0000000000000000; - ans = 64'h39f00003ffeffc40; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4190200080000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e56167e987d508; - y = 64'hc3507641c18b2d15; - zrf = 64'h0000000000000000; - ans = 64'hc545ff6e26393368; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f43652672b8c04e; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d1ffffbfe000000; - y = 64'h216898822a24af3f; - zrf = 64'h0000000000000000; - ans = 64'h1e98987f158ae1d8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c8a60ffe18c7bf; - y = 64'hc01bdaf03620c126; - zrf = 64'h0000000000000000; - ans = 64'h41f574c1d28158e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc741ffffffffffef; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3db000003ffffff7; - y = 64'h43caaa16868406bc; - zrf = 64'h0000000000000000; - ans = 64'h418aaa16f12c60c8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha220000000000bff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h39d0000007c00000; - y = 64'h37efffffe07fffff; - zrf = 64'h0000000000000000; - ans = 64'h31cfffffeffffff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc7f0000000000ffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf8fffffffffdfef; - y = 64'h7fd000000100ffff; - zrf = 64'h0000000000000000; - ans = 64'hff7000000100eff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb00000001bffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fffffffffdfdf; - y = 64'hc02fffffffffff6e; - zrf = 64'h0000000000000000; - ans = 64'hc06fffffffffdf4d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h1b6e0000000007ff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4037ab310ba6cb64; - y = 64'h7fefdffffdfffffe; - zrf = 64'h0000000000000000; - ans = 64'h00379385d9207187; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00195fa60036675; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd000003fffbfff; - y = 64'hc00fffe000000000; - zrf = 64'h0000000000000000; - ans = 64'h3fefffe07ffeffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc020000000800004; - y = 64'h43d4a4d3867e8d13; - zrf = 64'h0000000000000000; - ans = 64'hc404a4d38723b3b4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1f8f41f2ee582b0; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f0000000efffff; - y = 64'hc3d00007fffffeff; - zrf = 64'h0000000000000000; - ans = 64'hbbd0000800efff75; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h64b00000000bffff; - y = 64'h3b816cd156a62ab8; - zrf = 64'h0000000000000000; - ans = 64'h60416cd156b33c54; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h4803ffffffffefff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd7c2590b89786f; - y = 64'hc000f4df3c754c0e; - zrf = 64'h0000000000000000; - ans = 64'h3fe92df857f975ae; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f0ffffffeffffc0; - y = 64'hc003fffffff80000; - zrf = 64'h0000000000000000; - ans = 64'hbf23ffffff57ffd8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d2bbe6deae1f63; - y = 64'hffd0000000004010; - zrf = 64'h0000000000000000; - ans = 64'h03b2bbe6deae6a66; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h403000000000003f; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41cffffffff7bfff; - y = 64'h40600007fffffff8; - zrf = 64'h0000000000000000; - ans = 64'h42400007fffbdff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfff7ffffffff8; - y = 64'hb7efffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h39dfff7ffffffff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8020200007fffffe; - y = 64'hc59000000000083f; - zrf = 64'h0000000000000000; - ans = 64'h05c020000800084e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffefff8000080000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h58b00000008003fe; - y = 64'h3b6ff00001fffffe; - zrf = 64'h0000000000000000; - ans = 64'h542ff00002ff87f7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h77f34f18a693527b; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb8134f18a693527b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h42bfffffff80001e; - y = 64'h408000004000000f; - zrf = 64'h0000000000000000; - ans = 64'h435000003fc0001e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7efffffc00007ff; - y = 64'hc030000003fffffc; - zrf = 64'h0000000000000000; - ans = 64'h482fffffc80007e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbec52f80f9199ec0; - y = 64'hc3efff000007fffe; - zrf = 64'h0000000000000000; - ans = 64'h42c52ed77d1721d2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f000000407ffff; - y = 64'h8010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8410000004080000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401cc0bdc0613b09; - y = 64'hbec09901b9b2a079; - zrf = 64'h0000000000000000; - ans = 64'hbeedd3b3f0a24b73; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h8010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb00200000000ff; - y = 64'hc0000000011fffff; - zrf = 64'h0000000000000000; - ans = 64'hbfc00200012024fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fefffffffdff800; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9a5f095312a9cdc5; - y = 64'hc1f1ffffdfffffff; - zrf = 64'h0000000000000000; - ans = 64'h1c61753e9b7630ac; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc340000000000000; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h036fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e0000003fff7fe; - y = 64'h37effffbbfffffff; - zrf = 64'h0000000000000000; - ans = 64'h2fdffffbc7ffeeec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c0007dffffffff; - y = 64'hbfb3fff7fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h418400957fc0fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ef0000000000016; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3807fffffffffdff; - y = 64'h4230000000002080; - zrf = 64'h0000000000000000; - ans = 64'h3a48000000002ebf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1effffffffffc02; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h021ffffffffffc01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c0000007ffffff; - y = 64'h49103fffefffffff; - zrf = 64'h0000000000000000; - ans = 64'h4ae03ffff81ffff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81ffffffdfeffff; - y = 64'h403dfffffff80000; - zrf = 64'h0000000000000000; - ans = 64'hb86dfffffe170fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h32ee409a5f3b66fa; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3dcffffff0000000; - y = 64'hc06fffffff800800; - zrf = 64'h0000000000000000; - ans = 64'hbe4fffffef800800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2b50000200000020; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'ha800000200000020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c39e834dacb36b; - y = 64'h468f7fe000000000; - zrf = 64'h0000000000000000; - ans = 64'hc8634ff5a1f2b2f0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h391f800001000000; - y = 64'h46420003ffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3f71b803f0900020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ff3d4f7273f6526; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h407effbfffffffff; - y = 64'h3e00000040001fff; - zrf = 64'h0000000000000000; - ans = 64'h3e8effc07bff3dfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00001000000007e; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3cb0010000000080; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000003eff; - y = 64'h419ffffff8200000; - zrf = 64'h0000000000000000; - ans = 64'h01bffffff8207dfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f000000020003f; - y = 64'h3fbf800000000006; - zrf = 64'h0000000000000000; - ans = 64'hc3bf8000003f0082; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h41d1fdffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f9106b08704172; - y = 64'h43f0000000bffffe; - zrf = 64'h0000000000000000; - ans = 64'h4bf9106b099d0674; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3bddd6cd1eacf35d; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb89dd6cd1eacf35c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3810003ffdffffff; - y = 64'hc01f01d4d299b191; - zrf = 64'h0000000000000000; - ans = 64'hb83f0250d60cc15b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f00013fffffffe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc3d52e10f5566786; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403001fffffffeff; - y = 64'h402ffffdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'h407001feffdffefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb0ffff00000000; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbc70fffefffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hc03ffffeff800000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h405e1876cd43dfed; - y = 64'hb7efffffffffc006; - zrf = 64'h0000000000000000; - ans = 64'hb85e1876cd43a3c1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3fc01fffffff0000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f46ac0cb227799; - y = 64'h41c5ef5245dd848c; - zrf = 64'h0000000000000000; - ans = 64'h39cbfd80a6baabfb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcaa61d451370385; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3c8a61d451370385; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f00004000001ff; - y = 64'hc3d00bfffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h47d00c04030001ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h088fdffdfffffffe; - y = 64'hbf3000007c000000; - zrf = 64'h0000000000000000; - ans = 64'h87cfdffef707f07d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfb0010007fffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc38011ffffffffff; - y = 64'h3a60000000220000; - zrf = 64'h0000000000000000; - ans = 64'hbdf012000022263e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402feffff7fffffe; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc00feffff7ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ec36947a5606cc; - y = 64'hbfd0fffeffffffff; - zrf = 64'h0000000000000000; - ans = 64'h41cdf9fbfe921f92; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0001fffffffbf; - y = 64'hc3cffeffffffffdf; - zrf = 64'h0000000000000000; - ans = 64'hc5cfff3ffdffff5d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc312de637a398fb0; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403b5ab30b28be12; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc02b5ab30b28be11; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc040000000007f; - y = 64'h3fd0f88932487143; - zrf = 64'h0000000000000000; - ans = 64'h3fa13c6b5711938f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf8d6275431da5f5a; - y = 64'hc3f01fffffff0000; - zrf = 64'h0000000000000000; - ans = 64'h7cd653a2da3cb1a4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h434fffffff820000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3aa002007fffffff; - y = 64'hc1fe80c92278a049; - zrf = 64'h0000000000000000; - ans = 64'hbcae849a2fa3386e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4c20400000007ffe; - y = 64'hbfdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hcc10400000007ffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f778782e71a049; - y = 64'h41f0000000040004; - zrf = 64'h0000000000000000; - ans = 64'h43f778782e777e6d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f00001ffffffbf; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1cfffffff87ffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcbcb96cd6ce0e7; - y = 64'hbdf0403fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3dcc3b3456fdca1d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3810004000007fff; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb800004000007fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb816b0e6a400c9f7; - y = 64'h41d04000000003ff; - zrf = 64'h0000000000000000; - ans = 64'hb9f70baa3e90d2c9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc2b6b180a7b11fce; - y = 64'h434ffffffffe7ffe; - zrf = 64'h0000000000000000; - ans = 64'hc616b180a7b00f7a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3ca00fffffffefff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcfffe00001fffe; - y = 64'h3ffffffffffffff9; - zrf = 64'h0000000000000000; - ans = 64'hbfdfffe00001fff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381ffffffff0007f; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hb80ffffffff00080; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c508003ffffffff; - y = 64'hc9840007ffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc5e4a00d4001fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f500b2abbc6d5a; - y = 64'hc00000000200003f; - zrf = 64'h0000000000000000; - ans = 64'h440500b2ae5c8403; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1fc003ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381f83ffffffffff; - y = 64'h401020007fffffff; - zrf = 64'h0000000000000000; - ans = 64'h383fc308fc1ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc2d1fffffffffff8; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h42d1fffffffffff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c000000003fffd; - y = 64'hee8000020000007f; - zrf = 64'h0000000000000000; - ans = 64'hf05000020004007c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h44d1dac2a47ae323; - y = 64'hbf0ad596dbf9ffc8; - zrf = 64'h0000000000000000; - ans = 64'hc3edf1d4e2cf5d16; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h1dc0000200000400; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802b02a4a7567581; - y = 64'h400ffbffffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h804aff4452c18a45; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h801ffc000007ffff; - y = 64'hbfeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h001ffc000007fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4061a0ee04ab4a49; - y = 64'h395f87fffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h39d15ed28819c7f2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h488e6af849a7c8cc; - y = 64'hc3c00000801ffffe; - zrf = 64'h0000000000000000; - ans = 64'hcc5e6af93d3c6106; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hf895b944b616e64d; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc08ffffff807ffff; - y = 64'h381fdfffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'hb8bfdffff80fd7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e8ff000001fffff; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbe8ff000001fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2740d36bf6e95244; - y = 64'hb8512e32d34343c0; - zrf = 64'h0000000000000000; - ans = 64'h9fa21137ff9a0629; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd00040000003ff; - y = 64'hbfe601e4fe42b76a; - zrf = 64'h0000000000000000; - ans = 64'h3fc6023d05d6b5f4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffe0000005fffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h34ed63d731a69782; - y = 64'h37e15e6928604d26; - zrf = 64'h0000000000000000; - ans = 64'h2cdfe7805e636848; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h002ffcfffffffffe; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h802ffcffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41000000003e0000; - y = 64'hbaddffffffffff80; - zrf = 64'h0000000000000000; - ans = 64'hbbee000000743f7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40a00000020001ff; - y = 64'hc340000000800001; - zrf = 64'h0000000000000000; - ans = 64'hc3f0000002800200; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc02ffeffbfffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe85c97c592f839; - y = 64'hb7f253013ebdb741; - zrf = 64'h0000000000000000; - ans = 64'h37ebe68cf6e766e6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f00000083ffffe; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h44000000083ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe7ffffbfffffff; - y = 64'hc04f7fff00000000; - zrf = 64'h0000000000000000; - ans = 64'h40479fff01000200; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc033a9b295fcb4d4; - y = 64'hc34fffffc00fffff; - zrf = 64'h0000000000000000; - ans = 64'h4393a9b26eb32481; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfa0040000000040; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ee1b070553cb86; - y = 64'h43c02000000003ff; - zrf = 64'h0000000000000000; - ans = 64'hcbbe573d135e7aa1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbddfffffffffc03f; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3defffffffffc03e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdffff800020000; - y = 64'h40504000007fffff; - zrf = 64'h0000000000000000; - ans = 64'hc0403ffbf08103df; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h802ffb0000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcffffffffe07ff; - y = 64'h3fd5d55d6d4b65c1; - zrf = 64'h0000000000000000; - ans = 64'hbfb5d55d6d4a0ddf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc6efc00000001fff; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h46ffc00000001fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc341000000007fff; - y = 64'hffe80007ffffffff; - zrf = 64'h0000000000000000; - ans = 64'h033980088000bffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc3d45a83d3e64a25; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcaffc0000001fff; - y = 64'h37e000000003fffe; - zrf = 64'h0000000000000000; - ans = 64'hb49ffc0000081efb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe00000003fffef; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h7fefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7f0020000000fff; - y = 64'h4470000010000007; - zrf = 64'h0000000000000000; - ans = 64'hbc70020010021006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d00000010003ff; - y = 64'h40400000007effff; - zrf = 64'h0000000000000000; - ans = 64'h42200000017f03ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h402200000001ffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7efffffbfffeffe; - y = 64'hb7efe00000001fff; - zrf = 64'h0000000000000000; - ans = 64'h2fefdfffc040100e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d09308769f3f51; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h43f09308769f3f51; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5b18007fffffffff; - y = 64'h421000000004007e; - zrf = 64'h0000000000000000; - ans = 64'h5d380080000600dd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0140008000fffffe; - y = 64'hd2e0001ffffffffb; - zrf = 64'h0000000000000000; - ans = 64'h943000a0020001f8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb6a4df75cc5a8ac6; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0000000100002; - y = 64'hbfdffffff0ffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfaffffff1200002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9249d03728460383; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h1269d03728460382; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80fffffeffffffe; - y = 64'h40346972210201a4; - zrf = 64'h0000000000000000; - ans = 64'hc854697216cd4892; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffef003fffffffff; - y = 64'hc3e000000007fffc; - zrf = 64'h0000000000000000; - ans = 64'h03df0040000f8018; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h402ffffdfefffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hef3fffe000007fff; - y = 64'hffd8000000000004; - zrf = 64'h0000000000000000; - ans = 64'h2f27ffe800006004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7404000000007fe; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h37604000000007fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00fbffffc000000; - y = 64'h37e1c5f1f14e88f4; - zrf = 64'h0000000000000000; - ans = 64'hb801a2660b332da3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400fffffffffffff; - y = 64'hc1effffc00001000; - zrf = 64'h0000000000000000; - ans = 64'hc20ffffc00000fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb81fbfffffffdffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc18000001fffeffe; - y = 64'hcd4fffafffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4edfffb03fff3ffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe0c000001ffffff; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3e2c000002000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4030080000400000; - y = 64'h3feffffffffff7ef; - zrf = 64'h0000000000000000; - ans = 64'h40300800003ffbf6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f000000000004f; - y = 64'hb0d8d4e5d2e17fbc; - zrf = 64'h0000000000000000; - ans = 64'hb2d8d4e5d2e18036; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc3e4bafe2be6e7ab; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c2000000000000; - y = 64'h1b9003ffdfffffff; - zrf = 64'h0000000000000000; - ans = 64'h1f62047fdbffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f0ffffffe000000; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbf3ffffffdffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38000fffffdfffff; - y = 64'h3eb000000fffffdf; - zrf = 64'h0000000000000000; - ans = 64'h36c010000fefffde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff620e228517034; - y = 64'hd7b0007ffff00000; - zrf = 64'h0000000000000000; - ans = 64'hd7b621932f4c91dd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb2d000010001fffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434002ffffffffff; - y = 64'hb80dffffff7ffffe; - zrf = 64'h0000000000000000; - ans = 64'hbb5e059fff7fe7fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fffffffc00fff; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h404fffffffc00ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43402000003ffffe; - y = 64'h3fefbfffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'h433fff80007edfbc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h40400000000103fe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc840000fffc00000; - y = 64'h8020800000100000; - zrf = 64'h0000000000000000; - ans = 64'h087080107fce0010; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hdc6fffe800000000; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h5fbfffe800000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380ff7fffffffff7; - y = 64'h37e07fff7fffffff; - zrf = 64'h0000000000000000; - ans = 64'h30007bdf801ffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc001fff8000000; - y = 64'hc7e000000fffffee; - zrf = 64'h0000000000000000; - ans = 64'hc7b002000801ffe5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc01f672422632eb4; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc025e14360f49046; - y = 64'h412fff0000000003; - zrf = 64'h0000000000000000; - ans = 64'hc165e09456d988a3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40efbffffffffff0; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc43fbffffffffff1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffffffff00006; - y = 64'h2ff00001ffffefff; - zrf = 64'h0000000000000000; - ans = 64'hb0000001fff7f001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hdb80000000008001; - y = 64'hc8000000001fffdf; - zrf = 64'h0000000000000000; - ans = 64'h6390000000207fe1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h43c0010ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01a463c652ab793; - y = 64'hc05ffffffffeffff; - zrf = 64'h0000000000000000; - ans = 64'h408a463c6529e561; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f000ffbfffffff; - y = 64'hbfb97cb2bcb99946; - zrf = 64'h0000000000000000; - ans = 64'hc3b97e4a21f299eb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc34b6bcc142a6f56; - y = 64'hc7e4a843ca846cd5; - zrf = 64'h0000000000000000; - ans = 64'h4b41b38f9341a0c3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h43ee59a2f1155c8b; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9dd926fa6482fb5b; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h213926fa6482fb5a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe000000000fbff; - y = 64'h39cd3b5aa5703bc0; - zrf = 64'h0000000000000000; - ans = 64'h39bd3b5aa5720825; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c49fe3f310fdc0a; - y = 64'hbfd0000000000406; - zrf = 64'h0000000000000000; - ans = 64'hbc29fe3f310fe293; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h40307ff000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9daffffffdffffef; - y = 64'hbf34c1a973f2b94f; - zrf = 64'h0000000000000000; - ans = 64'h1cf4c1a972a69ead; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4cadffffffffffbf; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8c9dffffffffffbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcffc0000003fff; - y = 64'hc3e0000083ffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3bffc0107df3ffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe0000000008fff; - y = 64'h802ffffff7fffff6; - zrf = 64'h0000000000000000; - ans = 64'h801ffffff8011ff3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h3f0773142edfbe27; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h29d000000403ffff; - y = 64'h3f80003f00000000; - zrf = 64'h0000000000000000; - ans = 64'h2960003f04040fcf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38bfffefffdffffe; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hf8afffefffdfffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47effffc00000001; - y = 64'hc7e953179168449a; - zrf = 64'h0000000000000000; - ans = 64'hcfe953146705526d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffc000007ffe; - y = 64'h37ffffffdffffffa; - zrf = 64'h0000000000000000; - ans = 64'hb83fffbfe000bff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc1f000fffffffe00; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c00fffffffbffe; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h81c00fffffffbffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcebb873724572c; - y = 64'h43fffffffff007fe; - zrf = 64'h0000000000000000; - ans = 64'hc3debb8737150115; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3daffffc04000000; - y = 64'hc1dffbfffbffffff; - zrf = 64'h0000000000000000; - ans = 64'hbf9ffbfc007f807e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc7d001ffe0000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5ce0010001ffffff; - y = 64'h559000000007fe00; - zrf = 64'h0000000000000000; - ans = 64'h728001000207fe7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4d0ffffffffefff8; - y = 64'h434000000407ffff; - zrf = 64'h0000000000000000; - ans = 64'h5060000004077ffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffdb267f5c69234; - y = 64'h3e3e492b0370990d; - zrf = 64'h0000000000000000; - ans = 64'h3e4c1b285e7fc086; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hb7f00083fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe8ffbfff7ffffff; - y = 64'hb7efffffedffffff; - zrf = 64'h0000000000000000; - ans = 64'h368ffbffe6024003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40401007fffffffe; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h80401007fffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d4000000200000; - y = 64'h3ca03fffffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h4084500000207f5f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cff80000040000; - y = 64'hc30007ffffffe000; - zrf = 64'h0000000000000000; - ans = 64'h44e003fe0001e108; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc6affffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h66ef3a141ea96df4; - y = 64'ha5fe000007ffffff; - zrf = 64'h0000000000000000; - ans = 64'hccfd4672e48d5c1b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403efff800000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3efff5fffffffff; - y = 64'h3e10aaf54bbf14f4; - zrf = 64'h0000000000000000; - ans = 64'hc210aaa1f4f49a38; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h815fffbffffffbfe; - y = 64'h3fc953950e8a2680; - zrf = 64'h0000000000000000; - ans = 64'h813953626760063f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hc0045abb4860cbf3; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb26ffffffffff3ff; - y = 64'h31f0083fffffffff; - zrf = 64'h0000000000000000; - ans = 64'ha470083ffffff9fb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41fffffffffc000f; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe000000807ffff; - y = 64'hc7ffffffffffc00e; - zrf = 64'h0000000000000000; - ans = 64'h07f000000807e006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc42fffffffff7eff; - y = 64'h400af1800bf02233; - zrf = 64'h0000000000000000; - ans = 64'hc44af1800befb594; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'hbfc307b45d013179; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e67239f3caa98b; - y = 64'h4030100000007fff; - zrf = 64'h0000000000000000; - ans = 64'h442688ac2dbf27c5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc020003fefffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43df800000000000; - y = 64'hc800000007fffffd; - zrf = 64'h0000000000000000; - ans = 64'hcbef80000fbffffa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0000000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc00003ffffe000; - y = 64'h3fc00020000ffffe; - zrf = 64'h0000000000000000; - ans = 64'h3f9000240017e002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hde308000000fffff; - y = 64'hbff03ffefffffffe; - zrf = 64'h0000000000000000; - ans = 64'h5e30c1fef8103ffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h33c9eac8840374c2; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbf7fffffdfffff; - y = 64'hb15fffffff810000; - zrf = 64'h0000000000000000; - ans = 64'h312f7fffff62fc00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402e0f0ff2ae974a; - y = 64'hc010000007fbffff; - zrf = 64'h0000000000000000; - ans = 64'hc04e0f1001ae9b7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0029ab134ab9225a; - y = 64'hc1d2c16dd8a224a2; - zrf = 64'h0000000000000000; - ans = 64'h820e16c585c2b039; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h341ffc8000000000; - y = 64'hb87001fffffffe00; - zrf = 64'h0000000000000000; - ans = 64'haca0003fc7fffe00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fbefffffffffe; - y = 64'hbfe00001fff7ffff; - zrf = 64'h0000000000000000; - ans = 64'hc01fbf03f7d0207c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401395a7515be3d9; - y = 64'h8010000000040007; - zrf = 64'h0000000000000000; - ans = 64'h803395a75160c94b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffffec0000000; - y = 64'hc000000000003eff; - zrf = 64'h0000000000000000; - ans = 64'h400ffffec0007dfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h418f7ff7ffffffff; - y = 64'hb7f00000000000bf; - zrf = 64'h0000000000000000; - ans = 64'hb98f7ff800000177; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf6ffffffe000400; - y = 64'h402160aef0d05b5b; - zrf = 64'h0000000000000000; - ans = 64'hbfa160aeefba5298; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1641ffffff7ffffe; - y = 64'h47e800000000001f; - zrf = 64'h0000000000000000; - ans = 64'h1e3affffff400020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h411ffffeffffffff; - y = 64'h3e9ffc0000000020; - zrf = 64'h0000000000000000; - ans = 64'h3fcffbff00200020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fa0e39a0436d68; - y = 64'h3d3c9035c5b2e908; - zrf = 64'h0000000000000000; - ans = 64'hc14741de3814e038; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fffffdefffffe; - y = 64'h0510000f7fffffff; - zrf = 64'h0000000000000000; - ans = 64'h8540000f6f7ff001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1fc3fffffffff800; - y = 64'hc1f0000200020000; - zrf = 64'h0000000000000000; - ans = 64'ha1c40002800277ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41cfffff81ffffff; - y = 64'h402f0000000fffff; - zrf = 64'h0000000000000000; - ans = 64'h420effff85fffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4801ffffbfffffff; - y = 64'hc3c99366bccc8a8e; - zrf = 64'h0000000000000000; - ans = 64'hcbdcc5d32e1880ea; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48000000004001ff; - y = 64'h41f331de979ac49e; - zrf = 64'h0000000000000000; - ans = 64'h4a0331de97e78e7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f0ffffffbfffff; - y = 64'h4890001ff0000000; - zrf = 64'h0000000000000000; - ans = 64'h50910021eebfff80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e000008001fffe; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h881000008001fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8013a04700abd60; - y = 64'hffdfd80000000000; - zrf = 64'h0000000000000000; - ans = 64'h77f1247bea7eaff4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3eafeffff8000000; - y = 64'hca302000003fffff; - zrf = 64'h0000000000000000; - ans = 64'hc8f017effc37dffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h31fffc0000007ffe; - y = 64'h41229ed1840a7ed0; - zrf = 64'h0000000000000000; - ans = 64'h33329c7da9da47fb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hc0da7f18d03da9b8; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h00203effffffffff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fffc00000003f; - y = 64'hc11d4f929c6863da; - zrf = 64'h0000000000000000; - ans = 64'hc14d4f57fd432b42; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400ffffffff8003e; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3cbffffffff8003e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d0fffffbff7ffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d0003fffffffff; - y = 64'hbc1ffffefdfffffe; - zrf = 64'h0000000000000000; - ans = 64'hbe00003f7efdfbfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1effff800001fff; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbe9ffff800002000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e944135d63f2dd; - y = 64'h43ff7fffefffffff; - zrf = 64'h0000000000000000; - ans = 64'hcbf8df03034c5962; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca0f7fffffffffe; - y = 64'hb4bffffffff00000; - zrf = 64'h0000000000000000; - ans = 64'hb170f7fffff783fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f000000008001f; - y = 64'h30700007fc000000; - zrf = 64'h0000000000000000; - ans = 64'h32700007fc080023; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffd6b6052240005; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3cbd6b6052240005; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc02000000001ff; - y = 64'hc00ffffeffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h3fe01fff7f0001be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5580000000ffffee; - y = 64'h3ff509df8fb64af0; - zrf = 64'h0000000000000000; - ans = 64'h558509df9106e8d2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbcae035f6e1c25b3; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d3ffffff000000; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4093fffffeffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd533ffffffffffff; - y = 64'h3cafffffffbffbff; - zrf = 64'h0000000000000000; - ans = 64'hd1f3ffffffd7fd7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ecab8eca9bb4c17; - y = 64'hc0fd750edac542c0; - zrf = 64'h0000000000000000; - ans = 64'hbfd8995702b66277; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbefff8000000007f; - y = 64'h40bfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfcff8000000007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7f0008003ffffff; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb7d0008003ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe156f8e2d95e99; - y = 64'h434ffffff8000ffe; - zrf = 64'h0000000000000000; - ans = 64'hc34156f8de83a90a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c000000000001e; - y = 64'h7fde00003fffffff; - zrf = 64'h0000000000000000; - ans = 64'h83ae000040000037; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h80261e35bfb76142; - y = 64'h41cfffff0000fffe; - zrf = 64'h0000000000000000; - ans = 64'h82061e350ec66434; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41effffdfffffff6; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h41cffffdfffffff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h190294f45fbe164e; - y = 64'hbf70000005fffffe; - zrf = 64'h0000000000000000; - ans = 64'h988294f466b5f1ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h43dfff8004000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d1b3346b46a9eb; - y = 64'hbfc003fffffffff0; - zrf = 64'h0000000000000000; - ans = 64'h41a1b7a138617b84; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ed5aa8b5beebe6; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc1dd5aa8b5beebe5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434202ad5699be09; - y = 64'h307fffffc0100000; - zrf = 64'h0000000000000000; - ans = 64'h33d202ad329d64b3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h480007ffdffffffe; - y = 64'h43eff08b0c1adb83; - zrf = 64'h0000000000000000; - ans = 64'h4c00004188dfe96b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2d70d3775ee02e3a; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h2d60d3775ee02e39; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfeed9443f12e7c3; - y = 64'hc03fffffe0000000; - zrf = 64'h0000000000000000; - ans = 64'h403ed9442039a384; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43404007fffffffe; - y = 64'hdeff4f3947dd05b5; - zrf = 64'h0000000000000000; - ans = 64'he24fcc85d4991db6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf9fdfffffffffef; - y = 64'h3fe3a38b61a3da9a; - zrf = 64'h0000000000000000; - ans = 64'hbf938fe7d64236b4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3debfffffffffff; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc3cebfffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcaffe0000000008; - y = 64'h3fd00008000000ff; - zrf = 64'h0000000000000000; - ans = 64'hbc8ffe0fff000205; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc05fffffefffefff; - y = 64'h3fe8010ee8a17cd1; - zrf = 64'h0000000000000000; - ans = 64'hc058010edca0e95b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e1f29626b9ddd18; - y = 64'h30bfffdf80000000; - zrf = 64'h0000000000000000; - ans = 64'h2eef2942c595e7cc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffeffffffeffe; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3feffefffffff000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h66cefffffffffbff; - y = 64'hbee1c34e00ecb06b; - zrf = 64'h0000000000000000; - ans = 64'he5c1353390e548ae; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hba4dfffff8000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d427301514e081; - y = 64'h3fd8800000000000; - zrf = 64'h0000000000000000; - ans = 64'hc1bedc01a047f7c5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd750100fffffffff; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hd750100ffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd00000000004fe; - y = 64'hc7cffffffefffff0; - zrf = 64'h0000000000000000; - ans = 64'h07afffffff0009ec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff0004000000001; - y = 64'h3cbfffeffffffdff; - zrf = 64'h0000000000000000; - ans = 64'hbcc00037ffdfff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404ffbfffffffffc; - y = 64'hc34ffff8003fffff; - zrf = 64'h0000000000000000; - ans = 64'hc3affbf8013ff7fb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fffffdfc0000000; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3fffffdfbfffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c000001dfffffe; - y = 64'h3c00800001000000; - zrf = 64'h0000000000000000; - ans = 64'h3fd080001ff00000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffe2000000; - y = 64'h478fdfff80000000; - zrf = 64'h0000000000000000; - ans = 64'h478fdfff621e0078; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h00200003fff00000; - y = 64'hc8dffdfffffffff0; - zrf = 64'h0000000000000000; - ans = 64'h890ffe07ff6001ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d1dbffffffffffe; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3d1dbffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401e89aca33806c9; - y = 64'h381fc00007ffffff; - zrf = 64'h0000000000000000; - ans = 64'h384e4c99519401e4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403ffffffffffddf; - y = 64'h31ce00001fffffff; - zrf = 64'h0000000000000000; - ans = 64'h321e00001ffffe01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc04ffc000000fffe; - y = 64'hbfa3f7525558148b; - zrf = 64'h0000000000000000; - ans = 64'h4003f4d36b0e0942; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434fffffffd00000; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h434fffffffd00002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e0000000000082; - y = 64'h3db000003ffffeff; - zrf = 64'h0000000000000000; - ans = 64'h41a000003fffff82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcfffff00000040; - y = 64'hfd561631baa43441; - zrf = 64'h0000000000000000; - ans = 64'h7d36163109f2a699; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fffff0000007f; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h403fffff0000007f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfa0400010000000; - y = 64'hc3f00010000003ff; - zrf = 64'h0000000000000000; - ans = 64'h43a040105000140f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1600003fffffffd; - y = 64'h43fbffffffffbffe; - zrf = 64'h0000000000000000; - ans = 64'hc56c0006ffffbff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h71deffffffbffffe; - y = 64'h4060003e00000000; - zrf = 64'h0000000000000000; - ans = 64'h724f00781fbfff06; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb0d000001fffffff; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb0e000001ffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37effffffefffff0; - y = 64'h4029001bf472f471; - zrf = 64'h0000000000000000; - ans = 64'h3829001bf3aaf385; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3814000000000fff; - y = 64'h37e0001fffeffffe; - zrf = 64'h0000000000000000; - ans = 64'h30040027ffec0ffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41a0000010000000; - y = 64'hf2a00020000007ff; - zrf = 64'h0000000000000000; - ans = 64'hf4500020100027ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d004000ffffffe; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc1e004000ffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe9dfffffffffffd; - y = 64'h380afffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb6b94ffffffffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb4717e76986740; - y = 64'h47ffeffffdffffff; - zrf = 64'h0000000000000000; - ans = 64'hc7c46745b6160324; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40e9f0ae10a42de6; - y = 64'hc1df000000008000; - zrf = 64'h0000000000000000; - ans = 64'hc2d92128a01f7439; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000002000001; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0020000002000003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h320ff7fffffffc00; - y = 64'h7fe0001000000006; - zrf = 64'h0000000000000000; - ans = 64'h71fff81ff7fffc0c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h425fffffcfffffff; - y = 64'h41dffffbf7fffffe; - zrf = 64'h0000000000000000; - ans = 64'h444ffffbc800060a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4ff0fffffffdfffe; - y = 64'hd930000001000fff; - zrf = 64'h0000000000000000; - ans = 64'he9310000010e10fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe500000004001ff; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbe700000004001fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe0380000000000; - y = 64'h41affffffdfffc00; - zrf = 64'h0000000000000000; - ans = 64'h41a037fffefc7df9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00fffffc000007e; - y = 64'hc02ffffdfffffbff; - zrf = 64'h0000000000000000; - ans = 64'h404ffffdc000007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcfffffffffffff; - y = 64'hbcaffffffefffbff; - zrf = 64'h0000000000000000; - ans = 64'hbc8ffffffefffbfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'he9500000003ff7ff; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'he9700000003ff7fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f74d312c9c12e6; - y = 64'hc59138b471d0b5f9; - zrf = 64'h0000000000000000; - ans = 64'hbd99149935ac4c00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h6b10000007ffffe0; - y = 64'hb84ffffffffdffde; - zrf = 64'h0000000000000000; - ans = 64'he370000007feffce; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f8fff00001fffff; - y = 64'hbfd00000201fffff; - zrf = 64'h0000000000000000; - ans = 64'hbf6fff00405dfdfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h362fc7fffffffffe; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h364fc7fffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h550c000000000003; - y = 64'hc03fffff7ffffeff; - zrf = 64'h0000000000000000; - ans = 64'hd55bffff8fffff22; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dff8000000007f; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0001ffffffeff; - y = 64'hbfe008000000ffff; - zrf = 64'h0000000000000000; - ans = 64'h3fd008201000ff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h409dfffbffffffff; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h40bdfffc00000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43ec69813b94d362; - y = 64'hbcaffffffaffffff; - zrf = 64'h0000000000000000; - ans = 64'hc0ac69813724572f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h475703a683fd6399; - y = 64'hd6d0000000003000; - zrf = 64'h0000000000000000; - ans = 64'hde3703a683fda8a3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h390ffffffffe0006; - y = 64'h479800000000007e; - zrf = 64'h0000000000000000; - ans = 64'h40b7fffffffe8083; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381303276ef23657; - y = 64'hc4f0000000000efe; - zrf = 64'h0000000000000000; - ans = 64'hbd1303276ef24827; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe00000000f0000; - y = 64'h55ffdffffffffffc; - zrf = 64'h0000000000000000; - ans = 64'h55efe000001de1fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h367000100001fffe; - y = 64'h4340000007ffffee; - zrf = 64'h0000000000000000; - ans = 64'h39c00010080207ed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1fbfffffffdffff; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc22bfffffffdfffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h407080fd3d82dc9d; - y = 64'hc3c00000fdffffff; - zrf = 64'h0000000000000000; - ans = 64'hc44080fe438290cc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca3b763df2216f1; - y = 64'hbd50000000003ffb; - zrf = 64'h0000000000000000; - ans = 64'hba03b763df2265c8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc120000003ffffe0; - y = 64'hc06000fffbffffff; - zrf = 64'h0000000000000000; - ans = 64'h4190010000003fde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001003fffffffffd; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h036003fffffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3b10000000807ffe; - y = 64'hbe1fffff8000000f; - zrf = 64'h0000000000000000; - ans = 64'hb93fffff81010006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffb9699df82c260; - y = 64'h480ecff57c220532; - zrf = 64'h0000000000000000; - ans = 64'h481a907a18f76c15; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb10a400da0daec23; - y = 64'hc66ffbffbffffffe; - zrf = 64'h0000000000000000; - ans = 64'h378a3cc56aa6b583; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h77efff7fbfffffff; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h7b3fff7fc0000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hfc4ffffffffe00ff; - y = 64'hc80583e64223c02f; - zrf = 64'h0000000000000000; - ans = 64'h046583e64222689d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4035c0011a5256f5; - y = 64'h403bb950bcc2c81f; - zrf = 64'h0000000000000000; - ans = 64'h4082d7f5d4e4d1ba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd000800000007f; - y = 64'h463ffff7fffbffff; - zrf = 64'h0000000000000000; - ans = 64'hc620007bffde006e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4026684586bcc03f; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4386684586bcc03f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd1f7ffffffffff; - y = 64'hc01000001dffffff; - zrf = 64'h0000000000000000; - ans = 64'hbff1f80021b0fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb06fffffffffdeff; - y = 64'hbcafdfffff7fffff; - zrf = 64'h0000000000000000; - ans = 64'h2d2fdfffff7fdf20; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd0040000000007; - y = 64'h41f00000000009ff; - zrf = 64'h0000000000000000; - ans = 64'hc1d0040000000a08; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d02cdfc07b7411; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc5302cdfc07b740f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd3ffdffffffffe; - y = 64'hc1f001fdffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc1d4025d7c03fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffefffffffe0000e; - y = 64'h3c6db11b9ddefb5e; - zrf = 64'h0000000000000000; - ans = 64'hfc6db11b9dc14a4f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h391bfffffffffff6; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc010000fffffbffe; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0000ffffdffffff; - y = 64'h41fdeffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc20e0deffc41fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9ffa2f3964887701; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2e0fefdfffffffff; - y = 64'h4030000020000040; - zrf = 64'h0000000000000000; - ans = 64'h2e4fefe03fdfc07f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf743e9d43f80c40; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hff643e9d43f80c41; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e00007f0000000; - y = 64'h21bffffffff01000; - zrf = 64'h0000000000000000; - ans = 64'ha3b00007eff807fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd0000017fffffe; - y = 64'hc1f000ffffffc000; - zrf = 64'h0000000000000000; - ans = 64'h01d0010018013ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e0000080010000; - y = 64'h079fffffeeffffff; - zrf = 64'h0000000000000000; - ans = 64'h899000007780ffbb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1feffffffffc003e; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h5feffffffffc003e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3efefffffffdfff; - y = 64'h3f90100000000004; - zrf = 64'h0000000000000000; - ans = 64'hc39007f7ffffeff3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3effffff7e00000; - y = 64'h3d9ffffdfffff7ff; - zrf = 64'h0000000000000000; - ans = 64'hc19ffffdf7dff881; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f00d875c7ed339; - y = 64'h55400003fffffffc; - zrf = 64'h0000000000000000; - ans = 64'hd7400d8b5fe0aa54; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fffdff7ffffff; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h001fffdff7fffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c0000803ffffff; - y = 64'h3fcfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h43a0000803ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbee00000000007f0; - y = 64'h4030453834d7a591; - zrf = 64'h0000000000000000; - ans = 64'hbf20453834d7ada3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc0001fffffff00; - y = 64'hc170000380000000; - zrf = 64'h0000000000000000; - ans = 64'h414000238006ff00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0077fffffffff; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hffe0077fffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8a9fffffffffffff; - y = 64'h7fe0000000001080; - zrf = 64'h0000000000000000; - ans = 64'hca9000000000107f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe7aba21defbaa50; - y = 64'hfc3fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h7acaba21defbaa50; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f0000ffffdffff; - y = 64'h3fbfff0000000006; - zrf = 64'h0000000000000000; - ans = 64'h47bfff1ffefc0025; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf5ffff7fe000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38f0100000007ffe; - y = 64'h41e0000001010000; - zrf = 64'h0000000000000000; - ans = 64'h3ae01000010280ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffffffffffff2; - y = 64'h3faffff8000007ff; - zrf = 64'h0000000000000000; - ans = 64'h3fbffff8000007f2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0afffffbffffdfe; - y = 64'h3fc07ffdffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc0807ffddf0002f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h093fff7f7ffffffe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb8ed736b185958; - y = 64'h43f07dac22ee32d4; - zrf = 64'h0000000000000000; - ans = 64'h43b9b13eafd17761; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4315932d1fc6bca5; - y = 64'hbfe00000047ffffe; - zrf = 64'h0000000000000000; - ans = 64'hc305932d25d82153; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdfffff1fffffff; - y = 64'hc00aab60f8ca27b4; - zrf = 64'h0000000000000000; - ans = 64'h3ffaab603e1a80e6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3800003fdfffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f9dcc0dc84790c; - y = 64'hbfd001ffffffffc0; - zrf = 64'h0000000000000000; - ans = 64'hc7d9dffc74a00933; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hae6fff800000007e; - y = 64'hc08787cf0c729bb6; - zrf = 64'h0000000000000000; - ans = 64'h2f078770ed366a49; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01000001000000e; - y = 64'hbdbfffffdfffdffe; - zrf = 64'h0000000000000000; - ans = 64'h3ddfffffffffdffa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001fffffefff0000; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0fffffffeffffee; - y = 64'h55139bb9349e058c; - zrf = 64'h0000000000000000; - ans = 64'hd6239bb9340127b7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ef7fffffe00000; - y = 64'hc3e1db16103a3e46; - zrf = 64'h0000000000000000; - ans = 64'h3be193a9b7e77a37; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca000000008007e; - y = 64'h3810000000000880; - zrf = 64'h0000000000000000; - ans = 64'hb4c00000000808fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h406ff7fffff7ffff; - y = 64'hc03000020001ffff; - zrf = 64'h0000000000000000; - ans = 64'hc0aff803fefbfefc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41fffffc0fffffff; - y = 64'hbff125048d9f0538; - zrf = 64'h0000000000000000; - ans = 64'hc20125027190f5ca; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40101ffbffffffff; - y = 64'h4030000001fffbff; - zrf = 64'h0000000000000000; - ans = 64'h40501ffc0203fb76; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc71922783e2606; - y = 64'h5ebfffffffffb7ff; - zrf = 64'h0000000000000000; - ans = 64'h5e971922783df20d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4805e01bec624433; - y = 64'hbebfffe003fffffe; - zrf = 64'h0000000000000000; - ans = 64'hc6d5e0060f025b4c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe000fffdffffff; - y = 64'hb5ffffc007fffffe; - zrf = 64'h0000000000000000; - ans = 64'h35f000e0000043fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5b70007f80000000; - y = 64'hc3cfffffffeff7ff; - zrf = 64'h0000000000000000; - ans = 64'hdf50007f7ff7fbbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffdbaf18ce06bd; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h821fdbaf18ce06bd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0dfff77ffffffff; - y = 64'hbcff8b0a27d3ea94; - zrf = 64'h0000000000000000; - ans = 64'h3def8a8418e8c14f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40785ec8540ee022; - y = 64'h402fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h40b85ec8540ee022; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03fffdfff7ffffe; - y = 64'h3ffffffbfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc04fffdbff84000c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fbba85b3184d07; - y = 64'h8010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h041bba85b3184d09; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4a3ccc699c427a3d; - y = 64'h4000002003ffffff; - zrf = 64'h0000000000000000; - ans = 64'h4a4ccca33c48cd28; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4c3002003fffffff; - y = 64'h40dffffff0ffffff; - zrf = 64'h0000000000000000; - ans = 64'h4d200200387f0fe1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd5803ffffffffffc; - y = 64'h400fffffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'hd5a03fffffffefbb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hc80fffffffffffd6; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc346e93e17d2b781; - y = 64'h415fffffffa00000; - zrf = 64'h0000000000000000; - ans = 64'hc4b6e93e178dfbc6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0e1000000080000; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h011100000007ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb01fffff8003ffff; - y = 64'h41e1107888e2300a; - zrf = 64'h0000000000000000; - ans = 64'hb211107844a26ff4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffffff000e; - y = 64'hc034a2b24bab636b; - zrf = 64'h0000000000000000; - ans = 64'hc034a2b24baabe5e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h39e003ffffffffbf; - y = 64'h3e504000000001ff; - zrf = 64'h0000000000000000; - ans = 64'h38404410000001be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fa1ffff7fffffff; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbc51ffff7fffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cffffffe000003; - y = 64'hbd1eb76580b25d59; - zrf = 64'h0000000000000000; - ans = 64'h3efeb7657ec6e704; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc000200003fffe; - y = 64'hbb70007fbffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3b40009fc103801c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401f003fffffffff; - y = 64'hbfe8d71166319ab9; - zrf = 64'h0000000000000000; - ans = 64'hc018108a8922da45; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d6fde0000000000; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hba1fde0000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403c2c5a3b9bb39e; - y = 64'hb7efffdffffff000; - zrf = 64'h0000000000000000; - ans = 64'hb83c2c3e0f4169ec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbffffff0000007; - y = 64'hc807dfffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc7d7dffff4100004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f007ffffffffff; - y = 64'h41efffffffbffff6; - zrf = 64'h0000000000000000; - ans = 64'hc3f007ffffdfeff9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40205fffffffffff; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbce05ffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0220000000000; - y = 64'hc3afffffbf800000; - zrf = 64'h0000000000000000; - ans = 64'hc5b021ffdf7b7800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb000001fffffc0; - y = 64'h41d0804000000000; - zrf = 64'h0000000000000000; - ans = 64'h4190804021007fbe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d00010007ffffe; - y = 64'h0bd0200ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h8db020202091007b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47203fffffffff7e; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc3e03fffffffff7c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fba29d8ba0da6e3; - y = 64'h894fff7fc0000000; - zrf = 64'h0000000000000000; - ans = 64'h891a296fde570d38; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37eee003376d4ca7; - y = 64'hbd381ffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb53746e26cc966c7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h3ca0000400000100; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc357b53537b96da5; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4337b53537b96da5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3bc00000fffff000; - y = 64'hb81000001ffffff7; - zrf = 64'h0000000000000000; - ans = 64'hb3e000011ffff1f6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbfff3fffffffff; - y = 64'hb7fc000000000006; - zrf = 64'h0000000000000000; - ans = 64'hb7cbff5800000005; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd12a08d1862ac2; - y = 64'he6000000000003f6; - zrf = 64'h0000000000000000; - ans = 64'he5e12a08d1862f01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caffdfdffffffff; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbc8ffdfe00000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc50c00000003ffff; - y = 64'h480004003fffffff; - zrf = 64'h0000000000000000; - ans = 64'hcd1c0700700400fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1effffbffffbfff; - y = 64'h39a0007000000000; - zrf = 64'h0000000000000000; - ans = 64'hbba0006dfff1dffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02ffffff807fffe; - y = 64'hbff7fe641162987a; - zrf = 64'h0000000000000000; - ans = 64'h4037fe640b68ff0e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400fffff00400000; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfffffff003fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f3007ffc0000000; - y = 64'h434fffffdffffffa; - zrf = 64'h0000000000000000; - ans = 64'h429007ffaff8003d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fffffffffffff; - y = 64'hffebff8000000000; - zrf = 64'h0000000000000000; - ans = 64'h801bff7fffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3feff000003fffff; - y = 64'h4db0000ffffffffa; - zrf = 64'h0000000000000000; - ans = 64'h4daff01ff0400034; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff3fffffeffffff; - y = 64'hbfdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3fe3fffffefffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d400000000000f; - y = 64'h406ec0bcf0b3df6c; - zrf = 64'h0000000000000000; - ans = 64'h4253387616706bb2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0d5f7fefffffffff; - y = 64'h47ec8d501c4f76b7; - zrf = 64'h0000000000000000; - ans = 64'h155c1b0c95362ab4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4440f00000000000; - y = 64'hbd8c00ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc1dda50efffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37ebffffffdffffe; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb7dbffffffdffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37efe7ffffffffff; - y = 64'h44040e69405ca472; - zrf = 64'h0000000000000000; - ans = 64'h3c03ff5e716c5ef7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f25bca4820614e; - y = 64'hb7e4000000000006; - zrf = 64'h0000000000000000; - ans = 64'hbbe6f2bcda2879a8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd0000000000004; - y = 64'h318c8fccd5b02d23; - zrf = 64'h0000000000000000; - ans = 64'h316c8fccd5b02d2b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7eff77bf2b59c3c; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h47dff77bf2b59c3e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4000000210000000; - y = 64'h43c00103ffffffff; - zrf = 64'h0000000000000000; - ans = 64'h43d00106102183ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401100007fffffff; - y = 64'hc3dffffc0000003f; - zrf = 64'h0000000000000000; - ans = 64'hc400fffe5ffff020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffffffff9fffff; - y = 64'hc060000003ffffef; - zrf = 64'h0000000000000000; - ans = 64'hc270000003cfffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00d37e1e0c4506a; - y = 64'h3f8ffffffff801ff; - zrf = 64'h0000000000000000; - ans = 64'hbfad37e1e0bd0444; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f240001ffffffff; - y = 64'hc1cff8000003fffe; - zrf = 64'h0000000000000000; - ans = 64'hc103fb01ff827ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434000000ff7ffff; - y = 64'hbfdffffbdfffffff; - zrf = 64'h0000000000000000; - ans = 64'hc32ffffbffeffbdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h002e000fffffffff; - y = 64'hbfeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h802e000ffffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc000000fefffff; - y = 64'h3fb54faffd79cc78; - zrf = 64'h0000000000000000; - ans = 64'hbf854fb012b42cc4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380c3f72cc3dec98; - y = 64'hc3fffffffbffffff; - zrf = 64'h0000000000000000; - ans = 64'hbc1c3f72c8b5fe3d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caebfd21432f7f8; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbcaebfd21432f7f8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802fffdffeffffff; - y = 64'h4047cb0f60814953; - zrf = 64'h0000000000000000; - ans = 64'h8087caf794b39055; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e1001000000000; - y = 64'h37f20000003fffff; - zrf = 64'h0000000000000000; - ans = 64'h3be320120044003f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb5bffffffc1fffff; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h35bffffffc200001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h45cfdffffffbffff; - y = 64'h37e00000007fbffe; - zrf = 64'h0000000000000000; - ans = 64'h3dbfe00000fa807c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffffffffffe2; - y = 64'h972f800000003fff; - zrf = 64'h0000000000000000; - ans = 64'h176f800000003fe2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4800003fffbffffe; - y = 64'h41b000fffffffffb; - zrf = 64'h0000000000000000; - ans = 64'h49c0014003bffbf9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fee4b562439ed33; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hffefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h480ffffffc000020; - y = 64'h4094000000001ffe; - zrf = 64'h0000000000000000; - ans = 64'h48b3fffffd802012; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8e0000003fbffff; - y = 64'hc503f4d44f4bf888; - zrf = 64'h0000000000000000; - ans = 64'h3df3f4d454443066; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381ffffdfffdfffe; - y = 64'h41e2c2cc4e128c3c; - zrf = 64'h0000000000000000; - ans = 64'h3a12c2cb21e49b2d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h002d08b65157014a; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h803d08b651570148; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fd00fffffff7ffe; - y = 64'hbfe2000100000000; - zrf = 64'h0000000000000000; - ans = 64'hffc2120100ff6ffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf090b74581d0095; - y = 64'hc340101fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h425924b1e35dcdcf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fbffffff7ffff; - y = 64'h41f35be73c03f148; - zrf = 64'h0000000000000000; - ans = 64'hc233352f6d87126b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e78df1020787b47; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbe88df1020787b47; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcffffff8000ffe; - y = 64'hdb60037fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hdb40037ffbff27ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00fffeff7ffffff; - y = 64'h366ffffffeffffbe; - zrf = 64'h0000000000000000; - ans = 64'hb68fffeff700003d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb9960804588bf278; - y = 64'hc0dfffefffff0000; - zrf = 64'h0000000000000000; - ans = 64'h3a8607f9548915f2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f3ffffc001fffff; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbf4ffffc00200000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h182fffffffffffc0; - y = 64'h3fe00000001fffff; - zrf = 64'h0000000000000000; - ans = 64'h18200000001fffdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f10000000000400; - y = 64'h47fffffffdffffff; - zrf = 64'h0000000000000000; - ans = 64'h471ffffffe0007ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c40000000003ff; - y = 64'hbc10000000000ffe; - zrf = 64'h0000000000000000; - ans = 64'h3de40000000017fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f300ffff7fffffe; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbf500ffff7fffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb800000200000400; - y = 64'h2f9fffffffdffffd; - zrf = 64'h0000000000000000; - ans = 64'ha7b00001fff003fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf50000000100fff; - y = 64'hc865677a07e9dbac; - zrf = 64'h0000000000000000; - ans = 64'h47c5677a07ff588d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7f000000000013e; - y = 64'h3ff0000000002010; - zrf = 64'h0000000000000000; - ans = 64'hb7f000000000214e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4800203fffffffff; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc820203ffffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403bfffbffffffff; - y = 64'hbfc00000ffffff00; - zrf = 64'h0000000000000000; - ans = 64'hc00bfffdbfffbe3f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc340002000004000; - y = 64'hc0db3367e0423019; - zrf = 64'h0000000000000000; - ans = 64'h442b339e47125d6b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc037ff8000000000; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4057ff8000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h42c0010000080000; - y = 64'h3cd45a0cb459b7b5; - zrf = 64'h0000000000000000; - ans = 64'h3fa45b52552f2a57; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffdffc0080000000; - y = 64'h3fefffffff7fe000; - zrf = 64'h0000000000000000; - ans = 64'hffdffc007f7ff001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d0000000000060; - y = 64'h3e3a83b1571e2cf8; - zrf = 64'h0000000000000000; - ans = 64'h401a83b1571e2d98; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe00000000002ff; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e7e7cc88b1f290; - y = 64'hc3f2ac81d4039f01; - zrf = 64'h0000000000000000; - ans = 64'h3bebe683ea2b7707; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ef1fffdffffffff; - y = 64'h3f8ff7ffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'h7e91fb7e007fedff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06fefffffe00000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4801000000000fff; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc831000000000ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4f60000801ffffff; - y = 64'h41c07fe000000000; - zrf = 64'h0000000000000000; - ans = 64'h51307fe841fffbff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40faeed5df2a2899; - y = 64'h400000ffffefffff; - zrf = 64'h0000000000000000; - ans = 64'h410af084cc6d2c64; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f90f3fcc527003; - y = 64'hc7e01fffbfffffff; - zrf = 64'h0000000000000000; - ans = 64'hcfe9415de7ae15b0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403fffe000000006; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc06fffe000000004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0000020003ffe; - y = 64'hbc1ffddfffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3c0ffde03ffc3ff3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380ff7ffffffefff; - y = 64'hd00fff00000000fe; - zrf = 64'h0000000000000000; - ans = 64'hc82ff7003ffff0fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380ffffffffc007e; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbb5ffffffffc007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2310800003ffffff; - y = 64'h661000ffffefffff; - zrf = 64'h0000000000000000; - ans = 64'h4930810803efbffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4340004000020000; - y = 64'h44c00000008001ff; - zrf = 64'h0000000000000000; - ans = 64'h4810004000820400; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f3fffe00001ffff; - y = 64'hc02008000000ffff; - zrf = 64'h0000000000000000; - ans = 64'hbf7007eff802007d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ffffffbfefffff; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h454fffffbff00001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d000400000003f; - y = 64'hc1dfbfffe0000000; - zrf = 64'h0000000000000000; - ans = 64'hc3bfc07edfff807d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc000020000001f; - y = 64'hbfa00800000007fe; - zrf = 64'h0000000000000000; - ans = 64'h3f7008020100081e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcd5fffffffffe1ff; - y = 64'h4dbd2735bcda9589; - zrf = 64'h0000000000000000; - ans = 64'hdb2d2735bcda7a33; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3effffff7ffefff; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h474ffffff7ffefff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f98000000007fff; - y = 64'h41d3af2126b9069b; - zrf = 64'h0000000000000000; - ans = 64'h417d86b1ba162761; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0000fffdfffff; - y = 64'hc017d02e9840c356; - zrf = 64'h0000000000000000; - ans = 64'hbfe7d046683fbb38; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc55048c1a2236a7e; - y = 64'hbfbffe0001ffffff; - zrf = 64'h0000000000000000; - ans = 64'h452047bd170dd461; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ffc0000000003f; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4b5fc0000000003e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc002d09cd8fe7e49; - y = 64'hc27ff7fbffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4292cbe657b4a38a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404fff7fffffff7f; - y = 64'h48ab7e2aad4ec686; - zrf = 64'h0000000000000000; - ans = 64'h490b7dbcb4a410dd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3cdbf00000000000; - y = 64'h43dffffddffffffe; - zrf = 64'h0000000000000000; - ans = 64'h40cbeffe250fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc35bffffffefffff; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h034bffffffefffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fffff5fffffffe; - y = 64'h37e910297c4564f4; - zrf = 64'h0000000000000000; - ans = 64'hbbf91021a7386e1c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h995000801fffffff; - y = 64'hbfc600a072f928fd; - zrf = 64'h0000000000000000; - ans = 64'h19260150a3fe01ab; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7fc95c1023be015; - y = 64'h38000001fffff7ff; - zrf = 64'h0000000000000000; - ans = 64'hc00c95c494f3f20f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1250000fbffffffe; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hd240000fbfffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f80000003ffffef; - y = 64'h40cffffffffdfffe; - zrf = 64'h0000000000000000; - ans = 64'h4060000003feffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4806199091f39a3e; - y = 64'h3a54f1e8abc46a10; - zrf = 64'h0000000000000000; - ans = 64'h426cee1727f7af20; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fe00000000000; - y = 64'hc3cab4ec3fa6d4eb; - zrf = 64'h0000000000000000; - ans = 64'hc3fa9a3753672e16; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38a314b3956389c2; - y = 64'h41e4554078c1c962; - zrf = 64'h0000000000000000; - ans = 64'h3a983f8b5796bf4d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402f800000001ffe; - y = 64'h449000ffffe00000; - zrf = 64'h0000000000000000; - ans = 64'h44cf81f7ffc12000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cffffe001ffffe; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h01cffffe001ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c00400000000fff; - y = 64'h41dfffffbff7ffff; - zrf = 64'h0000000000000000; - ans = 64'h3df03fffdf7bffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcbc0001ff7fffffe; - y = 64'hd1c2000000001fff; - zrf = 64'h0000000000000000; - ans = 64'h5d920023f7001ffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcffc1fffffffff; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7fcffc1fffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fafffffffffff0f; - y = 64'hc3dffe0400000000; - zrf = 64'h0000000000000000; - ans = 64'hc39ffe03ffffff0f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffffffffffdd; - y = 64'h41ffffffffe7ffff; - zrf = 64'h0000000000000000; - ans = 64'hc23fffffffe7ffdc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c0000003ffffc0; - y = 64'hc00fbfffbffffffe; - zrf = 64'h0000000000000000; - ans = 64'h41dfbfffc7efff70; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e189ea1a6fff97; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf00000000017fff; - y = 64'h402000000017ffff; - zrf = 64'h0000000000000000; - ans = 64'hbf30000000197ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cffffffffffffe; - y = 64'hc7f03fffff7ffffe; - zrf = 64'h0000000000000000; - ans = 64'h49d03fffff7ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d4000000000020; - y = 64'hcb9000007ffeffff; - zrf = 64'h0000000000000000; - ans = 64'hcf7400009ffec01e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd4000000000040; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41deeffffffffffe; - y = 64'h408096dfffe807a5; - zrf = 64'h0000000000000000; - ans = 64'h427009dd8fe8d363; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd40fffffffefefff; - y = 64'h4020000000001ffb; - zrf = 64'h0000000000000000; - ans = 64'hd43ffffffff02ff4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h285fffffb0000000; - y = 64'hbcc07ffffbffffff; - zrf = 64'h0000000000000000; - ans = 64'ha5307fffd2c00009; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41dba3c9edc2d856; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0231e85f8945a25; - y = 64'hbf9ffffffff04000; - zrf = 64'h0000000000000000; - ans = 64'h3fd31e85f88af120; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff0ee9046c9330f; - y = 64'h8479e1e79766e02b; - zrf = 64'h0000000000000000; - ans = 64'h847b63d14ff91acb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3800000000008002; - y = 64'hc34fff800ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbb5fff801000fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff00010001ffffe; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h324824baaf05e670; - y = 64'hc02f1d6d391cd812; - zrf = 64'h0000000000000000; - ans = 64'hb28779c88aef6872; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3ce25f5756217be; - y = 64'hbeb8de9767c61bc6; - zrf = 64'h0000000000000000; - ans = 64'h42976e2e13caff56; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbec0fffffffffffd; - y = 64'hbff000fffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h3ec1010ffbbffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h509ffff800000040; - y = 64'hbf800002007fffff; - zrf = 64'h0000000000000000; - ans = 64'hd02ffffc00fefffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h408fffffffffffff; - y = 64'h5f8fbcc496d14669; - zrf = 64'h0000000000000000; - ans = 64'h602fbcc496d14669; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4010002000000006; - y = 64'h5e9ffc001fffffff; - zrf = 64'h0000000000000000; - ans = 64'h5ebffc401800400b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3987fed51dcf1c87; - y = 64'hbfb5383498e99ecc; - zrf = 64'h0000000000000000; - ans = 64'hb94fd2c2829010f7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd2f805130a8c11df; - y = 64'h43effffdfdfffffe; - zrf = 64'h0000000000000000; - ans = 64'hd6f8051188ba9004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha66000000008ffff; - y = 64'hb5f63e97ef44abfa; - zrf = 64'h0000000000000000; - ans = 64'h1c663e97ef512f2f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd08000fffffffe; - y = 64'hc2e50f943cb3415f; - zrf = 64'h0000000000000000; - ans = 64'h02c5b8122f921f33; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca03ffbffffffff; - y = 64'hcd52199e0ff31aad; - zrf = 64'h0000000000000000; - ans = 64'hca02620001cb6319; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402ffffffe07ffff; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h004ffffffe07ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h361ffffffffffdfb; - y = 64'h40451c57126e71b1; - zrf = 64'h0000000000000000; - ans = 64'h36751c57126e705c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe2fefffffffffff; - y = 64'hb81ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h365feffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80fffffffbfff7f; - y = 64'h4b2fffff800001ff; - zrf = 64'h0000000000000000; - ans = 64'hd34fffff7fc0017f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hba7dffffffffdfff; - y = 64'h40138c01af69c4ee; - zrf = 64'h0000000000000000; - ans = 64'hbaa2534194731512; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3a90000001020000; - y = 64'hc1cffffffffc000f; - zrf = 64'h0000000000000000; - ans = 64'hbc70000001000007; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4f1fffbfffe00000; - y = 64'hbcd02000000007ff; - zrf = 64'h0000000000000000; - ans = 64'hcc001fdfbfefe7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0007ffffffeff; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h8010007ffffffefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4047ec41418542a9; - y = 64'hbca07e0000000000; - zrf = 64'h0000000000000000; - ans = 64'hbcf8a8a5c3693c15; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca0200000000100; - y = 64'hc1c00000000ffffd; - zrf = 64'h0000000000000000; - ans = 64'hbe702000001020fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h422007ffffffffff; - y = 64'h43dfffff00000003; - zrf = 64'h0000000000000000; - ans = 64'h461007ff7fc00001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40dfe000003fffff; - y = 64'h001ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h010fe000003ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02d53f3e871e98f; - y = 64'h402000000003f7fe; - zrf = 64'h0000000000000000; - ans = 64'hc05d53f3e8792fde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0000000007bfe; - y = 64'h43c07fff80000000; - zrf = 64'h0000000000000000; - ans = 64'h45c07fff80007fde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'habfff80000ffffff; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'ha8aff80000ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802fffffffffffbf; - y = 64'h400ffff7ffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h804ffff7ffffff3e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe70000077ffffff; - y = 64'hc1efffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4070000077ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1900000000ffff6; - y = 64'hc0100000207fffff; - zrf = 64'h0000000000000000; - ans = 64'h41b00000208ffff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff00000007ffffc; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3ca00000007ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd3ad0f91e5202b24; - y = 64'h948ff7fffffffdfe; - zrf = 64'h0000000000000000; - ans = 64'h284d084e00a6e147; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434dfe591d17f337; - y = 64'h3801fffffffefffe; - zrf = 64'h0000000000000000; - ans = 64'h3b60df12205c88db; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e3fffffbfffffe; - y = 64'hc3e20000000007ff; - zrf = 64'h0000000000000000; - ans = 64'hc5d67ffffb8009fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3549284c3d5f3c48; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3209284c3d5f3c48; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc1fffdbfffffffe; - y = 64'hffe8492804aa9910; - zrf = 64'h0000000000000000; - ans = 64'h7c18490cb25d93cf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h378fff7fffbfffff; - y = 64'hc1f0000000200007; - zrf = 64'h0000000000000000; - ans = 64'hb98fff7fffffff0c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcffffffeffffe0; - y = 64'h41300023fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h41100023ff7ffece; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e1ffffbffffffe; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3ea1ffffbffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ede88c6af5824c; - y = 64'h3fdfffff82000000; - zrf = 64'h0000000000000000; - ans = 64'hc1dde88bf531d966; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81fc00000003ffe; - y = 64'h9b07b63efeb2a5b1; - zrf = 64'h0000000000000000; - ans = 64'h133786d280b56fd1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h03909fc2a7ba5daf; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h03709fc2a7ba5daf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41cfffbfffffff00; - y = 64'hbfc454db14a7766b; - zrf = 64'h0000000000000000; - ans = 64'hc1a454b26af14c79; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2bd2309c71f3442c; - y = 64'h43d0000000000009; - zrf = 64'h0000000000000000; - ans = 64'h2fb2309c71f34437; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81fffffff080000; - y = 64'he6a07fffffff7fff; - zrf = 64'h0000000000000000; - ans = 64'h5ed07fffff7fa000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc05622dd78e30c7a; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc03622dd78e30c7b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h19ba5c173102efbd; - y = 64'hc56000000047fffe; - zrf = 64'h0000000000000000; - ans = 64'h9f2a5c1731798e22; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e007fffffdffff; - y = 64'h36ffffff80008000; - zrf = 64'h0000000000000000; - ans = 64'hb8f007ffbfde401f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3bbd976272fb1d2a; - y = 64'hc06ffff80007fffe; - zrf = 64'h0000000000000000; - ans = 64'hbc3d975b0d29e641; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdffffffff00000; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfcfffffffefffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47ef7ffffffeffff; - y = 64'h3f60001fffffffef; - zrf = 64'h0000000000000000; - ans = 64'h475f803efffeffdc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h262fefbfffffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcafffc007fffffe; - y = 64'hbfdffffefffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3c9fffbf0801ffbd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3a0000000007ff0; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc390000000007fee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd00001fffffc00; - y = 64'hc1620001fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4142000440003b7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01100003fffffff; - y = 64'hc80ffffefffffbff; - zrf = 64'h0000000000000000; - ans = 64'h4830ffffb7fffbdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff00000000077fe; - y = 64'hb90000000f000000; - zrf = 64'h0000000000000000; - ans = 64'hb90000000f0077fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcac3a797cd8e4f5; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbc9c3a797cd8e4f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434fff01ffffffff; - y = 64'h403dfeffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h439dfe11e7efffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00fffffffc003ff; - y = 64'hc03fffffc03ffffe; - zrf = 64'h0000000000000000; - ans = 64'h405fffffc00003fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha2d32b1c7c92b19f; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'ha2c32b1c7c92b1a0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha640000043ffffff; - y = 64'h41f00000000fff80; - zrf = 64'h0000000000000000; - ans = 64'ha8400000440fff7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fead93e15f6bba8; - y = 64'h41c5006a9bd9854b; - zrf = 64'h0000000000000000; - ans = 64'h41c19eea30ca59a5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37efffffffff801e; - y = 64'haebffffffffe7fff; - zrf = 64'h0000000000000000; - ans = 64'ha6bffffffffe001d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff0000000107fff; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3ff0000000107fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h84bffffff0ffffff; - y = 64'h3c100040003ffffe; - zrf = 64'h0000000000000000; - ans = 64'h80e0003ff8bfe1fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7f0000007ffffee; - y = 64'hbf97fffffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h4798000007ffffe2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7dc216346ad00be1; - y = 64'hbfb5d37af4d918a8; - zrf = 64'h0000000000000000; - ans = 64'hfd88ac349d895e09; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe6fff7fffffffff; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbe6fff7ffffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff00000000002ff; - y = 64'h3e4b497c09187baf; - zrf = 64'h0000000000000000; - ans = 64'hbe4b497c091880cb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00ffbffffffbfff; - y = 64'h40e000000201ffff; - zrf = 64'h0000000000000000; - ans = 64'hc0fffc0004033f7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h21f3fe0000000000; - y = 64'hbfa7bdef23c7089e; - zrf = 64'h0000000000000000; - ans = 64'ha1adaa732ed451e4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0ecb0cf56c6bd69; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc0ecb0cf56c6bd69; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02565653da65c70; - y = 64'h402fff7fffeffffe; - zrf = 64'h0000000000000000; - ans = 64'hc065650fa806b322; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c0004000000003; - y = 64'h4eb48be91251fe77; - zrf = 64'h0000000000000000; - ans = 64'h52848c3b41f647c3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc003310bd2998fff; - y = 64'h41e00ff800000000; - zrf = 64'h0000000000000000; - ans = 64'hc1f3443345e64042; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfffdfdfffffff; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc1dfffdfe0000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0007a0c6d7de4fd; - y = 64'h4e1000400000003e; - zrf = 64'h0000000000000000; - ans = 64'hce207a4e55af9b34; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d007ff80000000; - y = 64'h41f0fffffffc0000; - zrf = 64'h0000000000000000; - ans = 64'h43d1087f77fbfe01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d0040040000000; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3e004003fffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f403ff7ffffffff; - y = 64'h3fb911d8e2d1a307; - zrf = 64'h0000000000000000; - ans = 64'h3f097613bd707829; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h274fffdffdffffff; - y = 64'hc1cff8000000007f; - zrf = 64'h0000000000000000; - ans = 64'ha92ff7e00600807d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h31f2102fde21571e; - y = 64'hbf67ffffffff7ffe; - zrf = 64'h0000000000000000; - ans = 64'hb16b1847cd317229; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff50c7f8469cefb; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc0050c7f8469cef9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43dbffffdfffffff; - y = 64'h7fefff07fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h03dbff26e000f7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fdd0802349a67aa; - y = 64'h7730000000017fff; - zrf = 64'h0000000000000000; - ans = 64'h371d0802349d2069; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h46e0000001fff000; - y = 64'hb8007ffdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbef07ffe020fef3e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc56fffffffff7fbf; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc57fffffffff7fbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffeef7a206029708; - y = 64'hbdcfa4109a3a5b22; - zrf = 64'h0000000000000000; - ans = 64'h7dce9eaa2542875b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbffffdffffff00; - y = 64'h3e2f419626e39c29; - zrf = 64'h0000000000000000; - ans = 64'h3dff419432ca38c1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f7dcd3b83b1a38; - y = 64'h7fded222c26e4b3d; - zrf = 64'h0000000000000000; - ans = 64'h03e6fbb995be62f0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha40fc000001ffffe; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'ha41fc000001fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0a000000000023f; - y = 64'h001bf55a98315677; - zrf = 64'h0000000000000000; - ans = 64'h80cbf55a98315a63; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc802c57786e11b88; - y = 64'h402007ffffeffffe; - zrf = 64'h0000000000000000; - ans = 64'hc832ceda4291c69b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4740000fe0000000; - y = 64'hbf5fffffffffdfbf; - zrf = 64'h0000000000000000; - ans = 64'hc6b0000fdfffefdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3b50004000040000; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3b70004000040000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hfa5fffffffe01ffe; - y = 64'h08e4b85713fba238; - zrf = 64'h0000000000000000; - ans = 64'hc354b85713e6fe97; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f00800007fffff; - y = 64'h3fa6e616c4e16784; - zrf = 64'h0000000000000000; - ans = 64'hc3a6f189d0fb08ec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3b6ffffffeffffc0; - y = 64'h3c7ffffe003ffffe; - zrf = 64'h0000000000000000; - ans = 64'h37fffffdff3fffce; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0200001fffffbff; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc0400001fffffbfd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e000801ffffffe; - y = 64'h376fffffffbfffde; - zrf = 64'h0000000000000000; - ans = 64'haf6000801fdffeec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc7c1babdee0743a; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03fc00000100000; - y = 64'h43efdfffffffdffe; - zrf = 64'h0000000000000000; - ans = 64'hc43fa040000fd03e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434ff7ffffffefff; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h436ff7ffffffefff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2b8a7a8d3c728052; - y = 64'hbfa86acb62809317; - zrf = 64'h0000000000000000; - ans = 64'hab4434482c1fc770; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e00002000007fe; - y = 64'hffd0008000002000; - zrf = 64'h0000000000000000; - ans = 64'hf7c00082001027fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ed16be78e120f8; - y = 64'hb97fffffffffff9e; - zrf = 64'h0000000000000000; - ans = 64'h317d16be78e1209f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfffefffffffff7f; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc01fefffffffff80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d1ffffffbfffff; - y = 64'hbfcffffefffff800; - zrf = 64'h0000000000000000; - ans = 64'h41b1ffff6fbffb82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40a0ffffbfffffff; - y = 64'hc80fffffbffffdff; - zrf = 64'h0000000000000000; - ans = 64'hc8c0ffff9dffff6e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc019377796930508; - y = 64'hcf2fffe00007fffe; - zrf = 64'h0000000000000000; - ans = 64'h4f59375e5f21bc52; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff006ffffffffff; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h402006ffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43effffdffffdfff; - y = 64'h00201fffffffbfff; - zrf = 64'h0000000000000000; - ans = 64'h04201ffefdffafdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40107fffffff0000; - y = 64'h480ffffffff80003; - zrf = 64'h0000000000000000; - ans = 64'h48307ffffffae002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43ffc03fffffffff; - y = 64'hbffc89ceeec323b9; - zrf = 64'h0000000000000000; - ans = 64'hc40c50f464837af6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03847d851769ff3; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc06847d851769ff1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e4cc95b36f21a4; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'hcb34cc95b36f21a4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd79f98b4522b366f; - y = 64'h3ff0000001010000; - zrf = 64'h0000000000000000; - ans = 64'hd79f98b45426bb3f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2030000000000090; - y = 64'hc05e2e90015c47a1; - zrf = 64'h0000000000000000; - ans = 64'ha09e2e90015c48b0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380ffff800000000; - y = 64'h3fd001fffffff800; - zrf = 64'h0000000000000000; - ans = 64'h37f001fbff7ff801; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbfff9fffffffff; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc30fffa000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h44dc65e5d161d8f2; - y = 64'h7fda6d3e1bb162b2; - zrf = 64'h0000000000000000; - ans = 64'h04c773bceef1605c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7f0000007fffeff; - y = 64'h43ed0d6b02dfccdb; - zrf = 64'h0000000000000000; - ans = 64'hcbed0d6b11668089; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7f0000000000a00; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hcb500000000009ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h406d4a7b7029484b; - y = 64'hc1cfffdfffe00000; - zrf = 64'h0000000000000000; - ans = 64'hc24d4a5e25908da6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401ffdffffffffde; - y = 64'h407ffffffffdffef; - zrf = 64'h0000000000000000; - ans = 64'h40affdfffffdffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47efdd469e302de0; - y = 64'hb80000000080001e; - zrf = 64'h0000000000000000; - ans = 64'hbfffdd469f2f1850; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfffbffc000000; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc53fffbffbfffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbbf000000007efff; - y = 64'h001fe0000007fffe; - zrf = 64'h0000000000000000; - ans = 64'hfc1fe0000017d01c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43fffffc00100000; - y = 64'hc0171459ccff2c1a; - zrf = 64'h0000000000000000; - ans = 64'hc4271456ea7f7ca7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h404ffeffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1d34898549e35148; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h5d24898549e35148; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc079c96edc9a6761; - y = 64'hc1c010007ffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4249e33919c278aa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe04390701a9d8d; - y = 64'h32980a64e11ad16b; - zrf = 64'h0000000000000000; - ans = 64'h32886fe96d861b6f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ec000008000000; - y = 64'h4020200001ffffff; - zrf = 64'h0000000000000000; - ans = 64'hc81c38000b8fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43cf77ffffffffff; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h03bf780000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfffffb7fffffe; - y = 64'hbf35a1c5c5463803; - zrf = 64'h0000000000000000; - ans = 64'h4125a1c5949a3b06; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4340607d2db01f47; - y = 64'hc7effffc00007ffe; - zrf = 64'h0000000000000000; - ans = 64'hcb40607b21a0bb11; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41cae866712069f4; - y = 64'hc02fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc20ae866712069f3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hac6bfffffeffffff; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hec6bfffffefffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc050000000000006; - y = 64'h41e0000001000000; - zrf = 64'h0000000000000000; - ans = 64'hc240000001000006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h412fd11c7ab3b025; - y = 64'hc3fffbfffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'hc53fcd22532a361d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fd83ef8d8c91fd9; - y = 64'h20a65e11c2d9c573; - zrf = 64'h0000000000000000; - ans = 64'h6090f291851e0d23; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe2ad625e1082e2; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h7fe2ad625e1082e1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4083fffffffffeff; - y = 64'h381d4e791b603cf5; - zrf = 64'h0000000000000000; - ans = 64'h38b2510bb11c252e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402000020000003f; - y = 64'h43ffefffc0000000; - zrf = 64'h0000000000000000; - ans = 64'h442ff003bdfff87e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffc7fffffffe; - y = 64'h43d0008000000800; - zrf = 64'h0000000000000000; - ans = 64'hc4100063ff2007fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80000001001ffff; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hf80000001001ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfce1e32ccf56348; - y = 64'h3ca1f66d4c8eeef3; - zrf = 64'h0000000000000000; - ans = 64'hbc80e7fa025544da; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'he6ffffffbfffffff; - y = 64'h41d000000005ffff; - zrf = 64'h0000000000000000; - ans = 64'he8dfffffc00bfffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7fffeffbfffffff; - y = 64'h2e8ffffc0003ffff; - zrf = 64'h0000000000000000; - ans = 64'ha69ffefbc02407dd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb000007ffffc00; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcaffffbffffff7f; - y = 64'hbf5000ffffffdffe; - zrf = 64'h0000000000000000; - ans = 64'h3c1000fdffdfdfbe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3400008000001ff; - y = 64'h4020000fff7ffffe; - zrf = 64'h0000000000000000; - ans = 64'hc3700017ff8801bd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h442ff0000000000f; - y = 64'h38100000001ffffc; - zrf = 64'h0000000000000000; - ans = 64'h3c4ff000003fe008; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0001ffffff000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffbaf4aab76937a; - y = 64'h400004003ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc00bb636ecde9bc9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47e099d3c7690936; - y = 64'hb17ffdffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb97098ca2a2c92a4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffedfffff0000000; - y = 64'hffeffff000000800; - zrf = 64'h0000000000000000; - ans = 64'h3fedfff0f0000f80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdffffffffbfffd; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd74ffdfffffffffe; - y = 64'h41e020001ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hd9401efe1ffdfffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbd4512fd478e497e; - y = 64'hbc0886e981ed2f8d; - zrf = 64'h0000000000000000; - ans = 64'h39602717421b4cf4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf1000000007fff0; - y = 64'h381400000000ffff; - zrf = 64'h0000000000000000; - ans = 64'hb7340000000affeb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d0bc37284221aa; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbf0000000001ff; - y = 64'h403f8f9584adf87e; - zrf = 64'h0000000000000000; - ans = 64'hc00e9318d8888ab2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e0400000000001; - y = 64'hbca0000000010ffe; - zrf = 64'h0000000000000000; - ans = 64'hbe9040000001143e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc008164611e5d5a7; - y = 64'h802fffdfffffdfff; - zrf = 64'h0000000000000000; - ans = 64'h0048162dfb9fabab; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h95c40000000000ff; - y = 64'hc07103ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h164545000000010e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37effffc3ffffffe; - y = 64'hbca0fffffffffffd; - zrf = 64'h0000000000000000; - ans = 64'hb4a0fffe01fffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha2900000009fffff; - y = 64'hb8c85070bbd9c196; - zrf = 64'h0000000000000000; - ans = 64'h1b685070bccce5fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ee1fffffffffff; - y = 64'h4110000003dfffff; - zrf = 64'h0000000000000000; - ans = 64'hc30e2000074bbffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffffffc200000; - y = 64'h6b9fffffffdfffe0; - zrf = 64'h0000000000000000; - ans = 64'h6baffffffbffffe1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe3e01e845582e7; - y = 64'hb6c009ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h36b3ec8a97683858; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40568df4bf71d4de; - y = 64'h41dffeffffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h42468d404fcbd8f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e0004000001fff; - y = 64'hecb0008000000007; - zrf = 64'h0000000000000000; - ans = 64'h64a000c002002008; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0386508df251ee3; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h00586508df251ee3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fd003ffffffffff; - y = 64'h41c007fffffbffff; - zrf = 64'h0000000000000000; - ans = 64'h01a00c01fffbfefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403fffdfffffff00; - y = 64'hdb02020000000000; - zrf = 64'h0000000000000000; - ans = 64'hdb5201edfdffff6f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc950a021bf9dee1; - y = 64'h3db0001fffdffffe; - zrf = 64'h0000000000000000; - ans = 64'hba550a2c2fd402cd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c0400000000007; - y = 64'h8010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h81e0400000000008; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e90007ffffffdff; - y = 64'h4263a6b86ea9d367; - zrf = 64'h0000000000000000; - ans = 64'h4103a755a46d4640; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc000000001008000; - y = 64'h3fafff8000200000; - zrf = 64'h0000000000000000; - ans = 64'hbfbfff800220f7fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01ffffffefffdff; - y = 64'h384ffff800100000; - zrf = 64'h0000000000000000; - ans = 64'hb87ffff7ff0ffe3f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7eb8b600079a271; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h081b8b600079a271; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4001ffffffffffff; - y = 64'hc6d00003fffffbff; - zrf = 64'h0000000000000000; - ans = 64'hc6e200047ffffb7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fd3d6f52fa881; - y = 64'h2c3fffeff7ffffff; - zrf = 64'h0000000000000000; - ans = 64'hac6fd3c7034f382a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2e3403fffffffffe; - y = 64'hc7fffffeffffffbf; - zrf = 64'h0000000000000000; - ans = 64'hb64403ff5fdfffd5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47efffffffffefc0; - y = 64'h18b03fffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h20b03ffffffff7bf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hfd4fffffdfffffef; - y = 64'h41cffffdffffffef; - zrf = 64'h0000000000000000; - ans = 64'hff2ffffde00001de; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4a0ff80000800000; - y = 64'hc3403f829e8acc09; - zrf = 64'h0000000000000000; - ans = 64'hcd603b72be242760; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e0010000003fff; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4490010000003fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f7e00003fffffff; - y = 64'h403ffffffdfbffff; - zrf = 64'h0000000000000000; - ans = 64'h3fce00003e1c3ffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40100010007fffff; - y = 64'hb7e00001ffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb80000120082000d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7c8ffffffbffffbf; - y = 64'hbfe1ff8000000000; - zrf = 64'h0000000000000000; - ans = 64'hfc81ff7ffdc00fdb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h418ffffe0fffffff; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbe3ffffe10000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43cb7d45e24373f9; - y = 64'hbf559488d625deb3; - zrf = 64'h0000000000000000; - ans = 64'hc33289cecc120933; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe0000100ffffff; - y = 64'hc03ffffffffef7ff; - zrf = 64'h0000000000000000; - ans = 64'hc030000100ff7bfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcafffffffffff82; - y = 64'hc1e001000000003f; - zrf = 64'h0000000000000000; - ans = 64'h3ea0010000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc00000004007ff; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3c800000004007ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37ee08352ef09dd4; - y = 64'h2604d5494204c82f; - zrf = 64'h0000000000000000; - ans = 64'h1e038d4ca00591eb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80f00ffffffffff; - y = 64'h401ffffffff800ff; - zrf = 64'h0000000000000000; - ans = 64'hb83f00fffff840b6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h32bfffffffff0002; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'haf7fffffffff0000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434fffffffbffeff; - y = 64'hc34fffffdffffff0; - zrf = 64'h0000000000000000; - ans = 64'hc6afffffdfbffeef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fdffffdfdffffff; - y = 64'h403ff3fffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h002ff3fdfec0bffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47eda330abe8cbed; - y = 64'h43dd1adeb484ff45; - zrf = 64'h0000000000000000; - ans = 64'h4bdaf4c6f6a96df0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf4526d7f8d80bd7; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3f2526d7f8d80bd7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3190000020000007; - y = 64'hffef800010000000; - zrf = 64'h0000000000000000; - ans = 64'hf18f80004f00002d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc009130b80fe8274; - y = 64'hb811571307061a38; - zrf = 64'h0000000000000000; - ans = 64'h382b2cb1993b60f3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3413ffffffffffe; - y = 64'hbdf7ab1d79033080; - zrf = 64'h0000000000000000; - ans = 64'h4149847bc6777048; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8000020000ffffe; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h37e0002000100000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb0020000020000; - y = 64'h4640040000000007; - zrf = 64'h0000000000000000; - ans = 64'h4600060080020088; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'he17d0c35c0de73a1; - y = 64'h63185843aaa354bd; - zrf = 64'h0000000000000000; - ans = 64'h84a6194750eee6f6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h80200000000000fe; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h00100000000000fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'haefffffffc000003; - y = 64'h3fc186e2c19646d9; - zrf = 64'h0000000000000000; - ans = 64'haed186e2bf656a82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fff5fffffffff; - y = 64'hbfafff7fffffbfff; - zrf = 64'h0000000000000000; - ans = 64'h3fdffee0027fc000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb818000000000001; - y = 64'hb7f1d3f763b137ef; - zrf = 64'h0000000000000000; - ans = 64'h301abdf31589d3e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001ffff7ffffff7f; - y = 64'hc7e000010000003e; - zrf = 64'h0000000000000000; - ans = 64'h880ffff9ffff7ffa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0600000ffffffdf; - y = 64'h7feda1b8c591f9c6; - zrf = 64'h0000000000000000; - ans = 64'h805da1ba9fad85e2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1320001ffffffff; - y = 64'h3ff4000000000004; - zrf = 64'h0000000000000000; - ans = 64'hc136800280000003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e001ffffffffff; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc1d001ffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802ffc0000000008; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h343ffffff007fffe; - y = 64'hc3d000007ffffdff; - zrf = 64'h0000000000000000; - ans = 64'hb82000007803fdbe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0003fffffffbf; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbfb0003fffffffc0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81003effffffffe; - y = 64'had7c04f924d58101; - zrf = 64'h0000000000000000; - ans = 64'h259c0bde5e259189; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43507fffdfffffff; - y = 64'h41c00003f7fffffe; - zrf = 64'h0000000000000000; - ans = 64'h45208003f7bff80d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffffffffffff0; - y = 64'h5d4ffd0000000000; - zrf = 64'h0000000000000000; - ans = 64'hdd5ffcfffffffff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48bffffbffffffff; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc8bffffbfffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e4af3f8d45e031; - y = 64'h3ca0020002000000; - zrf = 64'h0000000000000000; - ans = 64'hbe94b1d577cd70de; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802fffffff7fdfff; - y = 64'hcfaffff7ffff8000; - zrf = 64'h0000000000000000; - ans = 64'h0feffff7ff7f6020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f0000003fffffd; - y = 64'ha91000100001ffff; - zrf = 64'h0000000000000000; - ans = 64'ha1100010040203fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbfeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8f5fffffffffffff; - y = 64'h311ffffbbfffffff; - zrf = 64'h0000000000000000; - ans = 64'h808ffffbbffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fffffffffdfdf; - y = 64'h802ffffffe0007ff; - zrf = 64'h0000000000000000; - ans = 64'h806ffffffdffe7de; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020000080000040; - y = 64'h4010a7a91ae0c98e; - zrf = 64'h0000000000000000; - ans = 64'h4040a7a9a01e12a8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3feffffffe000002; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbfeffffffe000002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02e000000008000; - y = 64'hc57001ffffffff7e; - zrf = 64'h0000000000000000; - ans = 64'h45ae03c000007f1d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcfa39599be7563; - y = 64'h638f800000001ffe; - zrf = 64'h0000000000000000; - ans = 64'h636f250743579b30; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3800008100000000; - y = 64'hb810000020000080; - zrf = 64'h0000000000000000; - ans = 64'hb020008120010280; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caffff000000007; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbcaffff000000008; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0a0eb920723db732; - y = 64'h41a17037c319dc53; - zrf = 64'h0000000000000000; - ans = 64'h0bc0be16b7c15790; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdffffffe000006; - y = 64'hac64ffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h2c54fffffeb00003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcbc000000008007e; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4bd000000008007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfce00000007ffff; - y = 64'hbf19713ef8574e3d; - zrf = 64'h0000000000000000; - ans = 64'h3ef7da2b08d835a9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf27fffffffffcffe; - y = 64'hc67ff7fffffdffff; - zrf = 64'h0000000000000000; - ans = 64'h790ff7fffffdd00a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001effffffffe000; - y = 64'ha780000200000000; - zrf = 64'h0000000000000000; - ans = 64'he7af0003dfffdfff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4809b2aa55e663c2; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc819b2aa55e663c0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffffbfffffde; - y = 64'hc1d000000001fbff; - zrf = 64'h0000000000000000; - ans = 64'h420fffffc003f7dc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h372ff00000003fff; - y = 64'h7fe000fdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'h771ff1fb02003fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ebfffffbffffff; - y = 64'h560000000003fff8; - zrf = 64'h0000000000000000; - ans = 64'hddfbfffffc06fff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40000000000001ff; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc0100000000001ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h085fffff80007ffe; - y = 64'h402a11bb3168c296; - zrf = 64'h0000000000000000; - ans = 64'h089a11bac9223e16; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e62ef8919f035d; - y = 64'hb2a0001000000002; - zrf = 64'h0000000000000000; - ans = 64'h34962f0ec09794ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c0010000fffffe; - y = 64'h683dfffffffffbff; - zrf = 64'h0000000000000000; - ans = 64'hec0e01e001dffbfa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3900fffffffe000; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h43a00fffffffe002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e1fff7ffffffff; - y = 64'h2250000003fffff7; - zrf = 64'h0000000000000000; - ans = 64'ha441fff8047ffdf4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbee007fffffffffa; - y = 64'h435001001ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc2400900a00ffff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca000000000000e; - y = 64'h41df7ffffffbffff; - zrf = 64'h0000000000000000; - ans = 64'h3e8f7ffffffc001b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47d00021fffffffe; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc7f00021fffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80978bafcce324c; - y = 64'h3fcffffffffbffdf; - zrf = 64'h0000000000000000; - ans = 64'hc7e978bafccb031a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdc7fffffffffff; - y = 64'hc7ffffffffff6ffe; - zrf = 64'h0000000000000000; - ans = 64'hc7ec7fffffff7fbd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e625be6b6b5de6; - y = 64'hc0103fff00000000; - zrf = 64'h0000000000000000; - ans = 64'h38067e5402bd24a7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401e4ea4f33af325; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc03e4ea4f33af323; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca0000011000000; - y = 64'h43dfffdffffffe00; - zrf = 64'h0000000000000000; - ans = 64'hc08fffe021ffdbff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca47e03cc211f1d; - y = 64'hc3c0040000000ffe; - zrf = 64'h0000000000000000; - ans = 64'h407483234d143be1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcd00001fffffffbf; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ee889b636e67325; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbf0889b636e67325; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fa207d4382d6f3; - y = 64'h4000007ffffdfffe; - zrf = 64'h0000000000000000; - ans = 64'hc40a214e4769aef6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbc9ea0c2b4884b; - y = 64'h43f4a552574073d5; - zrf = 64'h0000000000000000; - ans = 64'hc3c277000b21a4e7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf0c000080000000; - y = 64'hc64ffffffffffc1f; - zrf = 64'h0000000000000000; - ans = 64'h456c00007ffffc9c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc2a0000000000101; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h42c0000000000103; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8341000001fffffe; - y = 64'hc3407ffffffffffd; - zrf = 64'h0000000000000000; - ans = 64'h06918800020ffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h4720000780000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1a0001000001000; - y = 64'hc803d295a14dc259; - zrf = 64'h0000000000000000; - ans = 64'h49b3d2a973e3777a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb3d757f4aa26587e; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h340757f4aa26587e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37fffffffffff5ff; - y = 64'ha190000080001ffe; - zrf = 64'h0000000000000000; - ans = 64'h99a0000080001afd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0095ffaae004771; - y = 64'hbff0040100000000; - zrf = 64'h0000000000000000; - ans = 64'h4009665442ab7263; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4030000003ffffdf; - y = 64'hc33fffffffff1fff; - zrf = 64'h0000000000000000; - ans = 64'hc380000003ff8fde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf1fe0000000ffff; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3f4fe0000000fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e3f7fffffbffffe; - y = 64'hc324000000800000; - zrf = 64'h0000000000000000; - ans = 64'hc173b0000055fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca5ec40d9224e50; - y = 64'hc3100003ffff0000; - zrf = 64'h0000000000000000; - ans = 64'hbfc5ec46543125d4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ef8000000ffffe; - y = 64'hb7e000000000007b; - zrf = 64'h0000000000000000; - ans = 64'h2fdf8000001000f1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03c99226bab2fdf; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h438c99226bab2fdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0d0000000800040; - y = 64'hb813260f6e05d589; - zrf = 64'h0000000000000000; - ans = 64'h38f3260f6e9f0652; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf10000004000003; - y = 64'hbe5efffffffdffff; - zrf = 64'h0000000000000000; - ans = 64'h3d7f000007be0005; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0000080000007; - y = 64'hc01bfffffbffffff; - zrf = 64'h0000000000000000; - ans = 64'hc21c0000dbffffeb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h9239ba76a05ecbd7; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h1589ba76a05ecbd9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47bb47c5d4f98afd; - y = 64'hbfd00000004001fe; - zrf = 64'h0000000000000000; - ans = 64'hc79b47c5d566ad79; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffffffff7ffffb; - y = 64'h0027ffffffffeffe; - zrf = 64'h0000000000000000; - ans = 64'h0237ffffff9feffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hdd2003fff7ffffff; - y = 64'h46ffffffeffffeff; - zrf = 64'h0000000000000000; - ans = 64'he43003ffeffdff82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3faffffb7ffffffe; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc30ffffb7ffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02f080000000000; - y = 64'h7fe0000020100000; - zrf = 64'h0000000000000000; - ans = 64'h801f08003e2f0800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020080ffffffffe; - y = 64'hb8107b8a10fe7835; - zrf = 64'h0000000000000000; - ans = 64'hb84083d85191086d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3810008000000fff; - y = 64'hbffd243f1bcee286; - zrf = 64'h0000000000000000; - ans = 64'hb81d25283dc7de1f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc8060448957c7df4; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4b660448957c7df3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48000000fffdffff; - y = 64'hbfeffffff7efffff; - zrf = 64'h0000000000000000; - ans = 64'hc8000000fbf5ffbe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h46700000003ffff7; - y = 64'hc1f403b660b099b6; - zrf = 64'h0000000000000000; - ans = 64'hc87403b66100a884; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e3fffffeffffffa; - y = 64'hb80e1fffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb65e1ffff0effff9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e040000fffffff; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h07d040000fffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00fffffffefffdf; - y = 64'h41e0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc1ffffffffefffdf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0107fffffffffdf; - y = 64'h3ff8ba6f4e5ae4ee; - zrf = 64'h0000000000000000; - ans = 64'hc0198042c8cdbbe2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1df80007fffffff; - y = 64'h3c7ffff7ffff7ffe; - zrf = 64'h0000000000000000; - ans = 64'hbe6f7ff89fff61fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc34ffff7feffffff; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h033ffff7ff000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2d594c653e03ade2; - y = 64'hc3e000003fffc000; - zrf = 64'h0000000000000000; - ans = 64'hb1494c65a334dda8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb800001ffe000000; - y = 64'hbfde924b4ffe25d9; - zrf = 64'h0000000000000000; - ans = 64'h37ee928870c27c6c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc049124f686bf9b3; - y = 64'hb7f000fffffff000; - zrf = 64'h0000000000000000; - ans = 64'h384913e08d626761; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffdffffffffdffff; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3fdffffffffdffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd00400000000ff; - y = 64'hc0ada76631d3f698; - zrf = 64'h0000000000000000; - ans = 64'h008daed00b606d6f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h3fe0000ffffff7ff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020c540619836fa; - y = 64'hc7f000ffefffffff; - zrf = 64'h0000000000000000; - ans = 64'hc820c64ca4d9101a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4364893437d666c6; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h8364893437d666c4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cfe0000000ffff; - y = 64'hc1d0000080400000; - zrf = 64'h0000000000000000; - ans = 64'h43afe000ff808000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbd70000fff7ffffe; - y = 64'h291fffffe0000010; - zrf = 64'h0000000000000000; - ans = 64'ha6a0000fef7ff006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f20000000001ff; - y = 64'h4012001fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc21440240000023d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80fffffffbfdfff; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h780fffffffbfdfff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe000200000ffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401650b0af16768d; - y = 64'hbe1001fe00000000; - zrf = 64'h0000000000000000; - ans = 64'hbe365377fb164379; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f9000008000ffff; - y = 64'hbfdffffffe000100; - zrf = 64'h0000000000000000; - ans = 64'hbf8000007f010076; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1effc1fffffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h05d7728ced9039cb; - y = 64'hc1eeffffff7fffff; - zrf = 64'h0000000000000000; - ans = 64'h87d6b6f885c5edc8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h39a5106aa3a32bb8; - y = 64'hbf1000fffffff7fe; - zrf = 64'h0000000000000000; - ans = 64'hb8c511bbaa4d5b5f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4070001ffffbfffe; - y = 64'hc7e00000080ffffe; - zrf = 64'h0000000000000000; - ans = 64'hc8600020080c101b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fffffffff0080; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc97ffffffff00ffe; - y = 64'hc3c002000000000f; - zrf = 64'h0000000000000000; - ans = 64'h4d5001fffff8070f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe6ef3744bfe08c; - y = 64'h4000000050000000; - zrf = 64'h0000000000000000; - ans = 64'h3ff6ef37b76bf4e4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc79feffffffeffff; - y = 64'h42b040000000ffff; - zrf = 64'h0000000000000000; - ans = 64'hca6037e000007d7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f03ffffffdffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbff0000fffffff; - y = 64'hbfd007fffffeffff; - zrf = 64'h0000000000000000; - ans = 64'hbf9ffff8100600fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0d000000001ffbf; - y = 64'hc03ba46e644e4e9c; - zrf = 64'h0000000000000000; - ans = 64'h411ba46e6451c2ba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48000000401fffff; - y = 64'hc3efffffbfff7fff; - zrf = 64'h0000000000000000; - ans = 64'hcc000000201fbf7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380ffffffeffffff; - y = 64'hb7efff00007fffff; - zrf = 64'h0000000000000000; - ans = 64'hb00ffeffff8007fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffff0000007f; - y = 64'h41c0080fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h41c0080f7fbf803f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8010e080b96f5390; - y = 64'hc1c0000fffffefff; - zrf = 64'h0000000000000000; - ans = 64'h01e0e09199effc1e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47ffffffffffffdd; - y = 64'hbfa080000000000f; - zrf = 64'h0000000000000000; - ans = 64'hc7b07ffffffffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h480dfffffff7ffff; - y = 64'hbfbffffffc0003ff; - zrf = 64'h0000000000000000; - ans = 64'hc7ddfffffc3803be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0000000007efe; - y = 64'hc3eea93f38dfa88a; - zrf = 64'h0000000000000000; - ans = 64'hc3bea93f38e09be5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4683fff7ffffffff; - y = 64'hbfbfffdfffffffe0; - zrf = 64'h0000000000000000; - ans = 64'hc653ffe40007ffeb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffffe003fe; - y = 64'h381b9635176eb14a; - zrf = 64'h0000000000000000; - ans = 64'h381b963517531e86; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc4500000005fffff; - y = 64'hc03a20ab4de47fc9; - zrf = 64'h0000000000000000; - ans = 64'h449a20ab4e8143cc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38101ffffefffffe; - y = 64'hbfc3fffff0000000; - zrf = 64'h0000000000000000; - ans = 64'hb7e427ffee9ffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfeffffffffdffde; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4710003bfffffffe; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0730003bfffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h448c88eae42cd15d; - y = 64'hc7e00000001dffff; - zrf = 64'h0000000000000000; - ans = 64'hcc7c88eae4625213; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb810bffffffffffe; - y = 64'hbfdfffff8000ffff; - zrf = 64'h0000000000000000; - ans = 64'h3800bfffbd0085fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc030588b5c2ae8f5; - y = 64'hbef5ba5fd85a7448; - zrf = 64'h0000000000000000; - ans = 64'h3f36329e27cafa0d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2a8ffff000007ffe; - y = 64'h3e0ffff800004000; - zrf = 64'h0000000000000000; - ans = 64'h28afffe80004bffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h456f400000000000; - y = 64'h924ffffffbffdfff; - zrf = 64'h0000000000000000; - ans = 64'h97cf3ffffc17e0bf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f000001fffffdf; - y = 64'h480fffff7fefffff; - zrf = 64'h0000000000000000; - ans = 64'h500fffffbfeffebd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400e00000000007e; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h003e00000000007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e1a9bf123eaa3f; - y = 64'hffefffff7ffff7ff; - zrf = 64'h0000000000000000; - ans = 64'h01e1a9becb97a98c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7b70000081fffffe; - y = 64'hbf904000000003fe; - zrf = 64'h0000000000000000; - ans = 64'hfb104000840803fb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb810100200000000; - y = 64'h37effffcffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb01010007e7fcfff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3bfffffff780000; - y = 64'h001ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h83efffffff77fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe7ffc2000000000; - y = 64'hc100000000060000; - zrf = 64'h0000000000000000; - ans = 64'h3f8ffc20000bfe8c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8020000000000ffb; - y = 64'h47f000000080003f; - zrf = 64'h0000000000000000; - ans = 64'h882000000080103a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381300ec5ae729a0; - y = 64'hc0c3975208fc137b; - zrf = 64'h0000000000000000; - ans = 64'hb8e744d2d1f394c2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40cffffffff80ffe; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3d7ffffffff80ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47effffebffffffe; - y = 64'hbf936fbdb3967862; - zrf = 64'h0000000000000000; - ans = 64'hc7936fbcf1390f5c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h45a01fffff7fffff; - y = 64'hc3c0020200000000; - zrf = 64'h0000000000000000; - ans = 64'hc9702206037fefee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38cffff800003fff; - y = 64'h3f80011fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3860011bffb82001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcfffffffffc01f; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbc7fffffffffc020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020000010040000; - y = 64'hc03000000207fffe; - zrf = 64'h0000000000000000; - ans = 64'hc0600000120c0000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc9fffbfff7fffff; - y = 64'hc1d0000003ffff80; - zrf = 64'h0000000000000000; - ans = 64'h3e7fffc0077feeff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43fffffe0001fffe; - y = 64'hb16080003ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb5707fff380103fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdfddbc012dea56; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3c9fddbc012dea56; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434352c905da85ec; - y = 64'h7fd0000020000001; - zrf = 64'h0000000000000000; - ans = 64'h032352c92c8017f9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb2cfffffffbfff80; - y = 64'hc0afffff7fffffff; - zrf = 64'h0000000000000000; - ans = 64'h338fffff7fbfff81; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06ffffffdfffff0; - y = 64'h443f000000001000; - zrf = 64'h0000000000000000; - ans = 64'hc4befffffe100ff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e8ff800000000ff; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3b4ff800000000fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffffffffff007; - y = 64'h400c899bdf7fd714; - zrf = 64'h0000000000000000; - ans = 64'hc01c899bdf7fc8d5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc5c1368ba271b92a; - y = 64'hb811ffcdc1bd41c6; - zrf = 64'h0000000000000000; - ans = 64'h3de35d27095069f1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h6480000100080000; - y = 64'hc3cca35dae1517d8; - zrf = 64'h0000000000000000; - ans = 64'he85ca35f78594468; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d00000000083ff; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc1b00000000083ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403bd37b5f01600f; - y = 64'h40110003fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h405d90ba09d04dcd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h409000003fff0000; - y = 64'hc020fffffffffffc; - zrf = 64'h0000000000000000; - ans = 64'hc0c1000043feeffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hfe6000100007fffe; - y = 64'hbd6feffffffc0000; - zrf = 64'h0000000000000000; - ans = 64'h7bdff01ff00bf7f9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fe00000007c0000; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h7fc00000007c0002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401ffffffffff800; - y = 64'hc020000000000300; - zrf = 64'h0000000000000000; - ans = 64'hc04ffffffffffdff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe004000000007fe; - y = 64'h3fdffff7ff7fffff; - zrf = 64'h0000000000000000; - ans = 64'hbdf03ffbefbf07fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d00000003efffe; - y = 64'hc02fffffafffffff; - zrf = 64'h0000000000000000; - ans = 64'hc40fffffb07dfff9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h203000000001fbff; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h202000000001fbff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h30feffffffffefff; - y = 64'h5137a780ee1f0e89; - zrf = 64'h0000000000000000; - ans = 64'h4246ea44e6ae0a41; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3cc00000000001f; - y = 64'h3ffffff8003fffff; - zrf = 64'h0000000000000000; - ans = 64'hc3dbfff90038001e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fe0000003fffe; - y = 64'h3fa47c191d152036; - zrf = 64'h0000000000000000; - ans = 64'h3fd4679d03fa9a98; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb1c0001fff7fffff; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb1b0001fff7ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0035f74d9e4a66e; - y = 64'hc1c000800000003f; - zrf = 64'h0000000000000000; - ans = 64'h41d3600fd58b75e0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fe04a50d62ff8; - y = 64'hbfc0018000000000; - zrf = 64'h0000000000000000; - ans = 64'hbfffe34757cdc40c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f08000007ffffe; - y = 64'hee9effffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hf69ff80000f7fffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb11000007ffffe00; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb10000007ffffe00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00000401ffffffe; - y = 64'h3fdfffffbfdfffff; - zrf = 64'h0000000000000000; - ans = 64'hbff0003fffef7f7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fdfebffffffffff; - y = 64'h4fafffffffffff7d; - zrf = 64'h0000000000000000; - ans = 64'h0f9febffffffff7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h00300000bfffffff; - y = 64'hc025ac1ab7310df3; - zrf = 64'h0000000000000000; - ans = 64'h8065ac1bbb424e87; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe400001fffffff; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbfd4000020000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe0001000000000; - y = 64'hb4c3fffffffbffff; - zrf = 64'h0000000000000000; - ans = 64'h74b40013fffbfffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41800000007ffbff; - y = 64'h41ccce2758e7ac2f; - zrf = 64'h0000000000000000; - ans = 64'h435cce2759ce1635; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3ce000000000002; - y = 64'h43c88b83def64702; - zrf = 64'h0000000000000000; - ans = 64'hc7a702cba106e293; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0020003ffffff800; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0020003ffffff800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402ff87ffffffffe; - y = 64'hab9f7ffffdffffff; - zrf = 64'h0000000000000000; - ans = 64'habdf789dfe0077fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80cef50bd17db40; - y = 64'hc05fffc00000000e; - zrf = 64'h0000000000000000; - ans = 64'h387cef16de76611d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d0080000fffffe; - y = 64'h381000ffffffff7f; - zrf = 64'h0000000000000000; - ans = 64'h39f0090081000f7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47effffffdfffbff; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h47effffffdfffbfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e46b2ebd63014a; - y = 64'hbec00003feffffff; - zrf = 64'h0000000000000000; - ans = 64'h46b46b33d6e7fdb6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf80040000000002; - y = 64'h3ccffff5ffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbc6003fafec00001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ecfff8008000000; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3ecfff8008000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3810410000000000; - y = 64'h3ef621b8ce00723b; - zrf = 64'h0000000000000000; - ans = 64'h37167ba1ccc5540c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d6e92ed3061ec0; - y = 64'hbfb3ffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h439ca37a87c7a66f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb0080000100000; - y = 64'hbfbff00000003fff; - zrf = 64'h0000000000000000; - ans = 64'hbf7ffff80020301e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha5a7fffffffffffe; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'ha5a7ffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3d4000ffffffffff; - y = 64'h3d47f68d8eb6b9a4; - zrf = 64'h0000000000000000; - ans = 64'h3a97f80cf78fa50f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc16ff80001fffffe; - y = 64'hc1dffffffffffdfc; - zrf = 64'h0000000000000000; - ans = 64'h435ff80001fffdfb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81f000000003fff; - y = 64'h4000000000001000; - zrf = 64'h0000000000000000; - ans = 64'hb82f000000005eff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdb6c04a6feb9f6; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3feb6c04a6feb9f6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fed24f6ded74376; - y = 64'hcc7ffffffdffffef; - zrf = 64'h0000000000000000; - ans = 64'hcc7d24f6dd04f3f8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01000000002003e; - y = 64'hc02f044788fbab9f; - zrf = 64'h0000000000000000; - ans = 64'h404f044788ff8ca1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02d8271a41fe6f3; - y = 64'h47ffffffff600000; - zrf = 64'h0000000000000000; - ans = 64'hc83d8271a38c5aba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7eed2778ed7be16; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc7fed2778ed7be14; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1fb827b7979160a; - y = 64'h3fcbb9627f4399d0; - zrf = 64'h0000000000000000; - ans = 64'hc1d7d57735568a19; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404ffffff0200000; - y = 64'hc1cde621665f3871; - zrf = 64'h0000000000000000; - ans = 64'hc22de621578a0ddf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe3fffffffffffb; - y = 64'hc03dc3321aaa5380; - zrf = 64'h0000000000000000; - ans = 64'h003299ff50aa742c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb0000ffffffe00; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbfc0000ffffffe00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d00000000efffe; - y = 64'h402ffeffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h440fff00001dff0c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb000003fbffffe; - y = 64'h79110003ffffffff; - zrf = 64'h0000000000000000; - ans = 64'hf8d1000443bc0fec; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf800000ffffefff; - y = 64'hc7f000000107ffff; - zrf = 64'h0000000000000000; - ans = 64'h478000010107f00f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc04000000000801f; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc050000000008020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8000000001fffff; - y = 64'h3fcefffffbffffff; - zrf = 64'h0000000000000000; - ans = 64'hb7defffffc3dfffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcffffdffffbfff; - y = 64'hc16907618a99b2b2; - zrf = 64'h0000000000000000; - ans = 64'h4149075ffa2367f9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7efffffdffffffc; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc80fffffdffffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40440a2b86699a62; - y = 64'hbdfffa0000000000; - zrf = 64'h0000000000000000; - ans = 64'hbe5406699e406695; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca3fffffffffeff; - y = 64'hbf02ffafb4e9241d; - zrf = 64'h0000000000000000; - ans = 64'hbbb7bf9ba2236bf3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h862000000000807f; - y = 64'h402007ffffffff80; - zrf = 64'h0000000000000000; - ans = 64'h865008000000803f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8c0000037ffffff; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb8e0000037fffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f70002000000fff; - y = 64'hbe501ffdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbdd0201e3ffc101c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h433fffffffefff80; - y = 64'h41dffffdfbffffff; - zrf = 64'h0000000000000000; - ans = 64'h452ffffdfbefff81; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401feffdffffffff; - y = 64'h7fd0000000000103; - zrf = 64'h0000000000000000; - ans = 64'h7fefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fe003fffffdffff; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h400003fffffdffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e6c4abfbae3348; - y = 64'hc3dffbfffdfffffe; - zrf = 64'h0000000000000000; - ans = 64'h47d6c1d364c272c1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41defffffefffffe; - y = 64'hc01fffffffffe004; - zrf = 64'h0000000000000000; - ans = 64'hc20efffffeffe101; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcf7fffffff87ffff; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'hcf9fffffff880000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h53598c812c3c39dd; - y = 64'h3f20000100fffffe; - zrf = 64'h0000000000000000; - ans = 64'h52898c82c69d14b1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02f00000003ffff; - y = 64'hc00814fbd82d4e31; - zrf = 64'h0000000000000000; - ans = 64'h40475453f96ee65f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbabd40046f3063; - y = 64'h959ffc00000fffff; - zrf = 64'h0000000000000000; - ans = 64'h956ab9e85c7c011c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h801010007ffffffe; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h804010007ffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h359ddddaad68456b; - y = 64'hb8000000fdfffffe; - zrf = 64'h0000000000000000; - ans = 64'hadaddddc878a34e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c90596ea75d9c9; - y = 64'h40c730520dce2fe8; - zrf = 64'h0000000000000000; - ans = 64'hc4a221cd04029cdd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff0000000000000; - y = 64'hbffbffffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'hbffbffffffffdfff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca4001000000000; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3cd4000fffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cfe7ffffffffff; - y = 64'hc0c7dd56f5c5966e; - zrf = 64'h0000000000000000; - ans = 64'h42a7cb70f48d423d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcc298ec1c2e8e2; - y = 64'h4010201000000000; - zrf = 64'h0000000000000000; - ans = 64'hbfec61fe08d53076; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dffffff8000001; - y = 64'h3fe0020000003ffe; - zrf = 64'h0000000000000000; - ans = 64'hc3d001fffbffbffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81a1948cf487bc6; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbb6a1948cf487bc6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fe20fffffffffff; - y = 64'h3d90000000000007; - zrf = 64'h0000000000000000; - ans = 64'h7d82100000000007; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h316ffffffffc0003; - y = 64'h47f001fefffffffe; - zrf = 64'h0000000000000000; - ans = 64'h397001fefffdffc0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40b49d4b49693e4c; - y = 64'h3f9fe0000001ffff; - zrf = 64'h0000000000000000; - ans = 64'h406488adfe211ee2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f5fffff7ffdffff; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h42afffff7ffe0001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03ffffffd000000; - y = 64'hbb8df851d942ba18; - zrf = 64'h0000000000000000; - ans = 64'h3bddf851d673726c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfca6a374638a9a7; - y = 64'h3694000003fffffe; - zrf = 64'h0000000000000000; - ans = 64'hb67082628f30b0ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402ffffbffffff7f; - y = 64'h4800080fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4840080dfefdffbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0c000000001fffd; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc42000000001fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ba00800003fffff; - y = 64'h3ff9a9a129c791b3; - zrf = 64'h0000000000000000; - ans = 64'h7ba9b675fac31bff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4517d68d04fb3028; - y = 64'hf67973648aee082d; - zrf = 64'h0000000000000000; - ans = 64'hfba2f5941ca565da; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5bbfffffbfff7fff; - y = 64'h3f9fffff7ffffffc; - zrf = 64'h0000000000000000; - ans = 64'h5b6fffff3fff80fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f9b338f2e03e52; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4559b338f2e03e51; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e0880000000000; - y = 64'hc8500400001ffffe; - zrf = 64'h0000000000000000; - ans = 64'h40408c2200210ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401f7fffffffe000; - y = 64'h4110000003f7ffff; - zrf = 64'h0000000000000000; - ans = 64'h413f800007d01fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d001000000ffff; - y = 64'hbfe000fbfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc1c001fc0fc1000c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38000000008001ff; - y = 64'h305ffffdfffffffb; - zrf = 64'h0000000000000000; - ans = 64'h286ffffe010003e9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38143510168bb69f; - y = 64'hbc6ffeffffefffff; - zrf = 64'h0000000000000000; - ans = 64'hb494346e6e00e7b8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06400000000000e; - y = 64'hbd00000ffffffdff; - zrf = 64'h0000000000000000; - ans = 64'h3d740013fffffd8d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d0000fffffffef; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h83c0000ffffffff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f607efffffffffe; - y = 64'hc3effeffbfffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3607e7be701fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfff00000000007f; - y = 64'hb57f6f93eb9411db; - zrf = 64'h0000000000000000; - ans = 64'h358e74174c3771c9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc000400007ffff; - y = 64'hbfb0000000fdffff; - zrf = 64'h0000000000000000; - ans = 64'hbf800040010603f6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc020007fdfffffff; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h8020007fdffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf958caed0772f21; - y = 64'h3fdffffff0000fff; - zrf = 64'h0000000000000000; - ans = 64'hbf858caec5b0e27e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h413fffffffffffbe; - y = 64'hc009e266b690362d; - zrf = 64'h0000000000000000; - ans = 64'hc159e266b69035f7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfedfffffffffffc; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hffedfffffffffffa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h57cfffffdfffffdf; - y = 64'ha1b0007fffefffff; - zrf = 64'h0000000000000000; - ans = 64'hb990007fefef7fee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fffff5fffffff; - y = 64'hc2f007bfffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc33007bfafd93ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc34f80001fffffff; - y = 64'hb7fffffe0007ffff; - zrf = 64'h0000000000000000; - ans = 64'h3b5f7ffe2807ddff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d04000007fffff; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h01d04000007fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfa03ffff7ffffff; - y = 64'hc3dfbffffffffeff; - zrf = 64'h0000000000000000; - ans = 64'h43901f7ff80fff7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha000000000000fff; - y = 64'hc7e07f0000000000; - zrf = 64'h0000000000000000; - ans = 64'h27f07f000000107e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe00020000003ff; - y = 64'h3fbffffff7fffdfe; - zrf = 64'h0000000000000000; - ans = 64'hbfb0001ffbfffafd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc030000001ffff7f; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3fb7e9782f90cc2; - y = 64'hbca0800000004000; - zrf = 64'h0000000000000000; - ans = 64'h40ac5a8c3f114323; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1df2a4105eef916; - y = 64'hc34fffffffffffe3; - zrf = 64'h0000000000000000; - ans = 64'h453f2a4105eef8fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7df000400000007e; - y = 64'hbfdfffdffffdfffe; - zrf = 64'h0000000000000000; - ans = 64'hfde0002fffbf0078; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40c794dd327440fd; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000001ff8; - y = 64'h4800020000010000; - zrf = 64'h0000000000000000; - ans = 64'h0820020000011ffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c00007fffffefe; - y = 64'h3fcffbfffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc39ffc0ffdfffdfa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2510000000000700; - y = 64'hbff00004000007fe; - zrf = 64'h0000000000000000; - ans = 64'ha510000400000efe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d3fffffffc0000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4d8ffbdfffffffff; - y = 64'hbca03ffffffffff6; - zrf = 64'h0000000000000000; - ans = 64'hca403de7bffffff5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h97ead859955088eb; - y = 64'h4a6d12c61bd00359; - zrf = 64'h0000000000000000; - ans = 64'ha26863d113b451ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd1fffdfffffffe; - y = 64'h8640000007fdffff; - zrf = 64'h0000000000000000; - ans = 64'h0621fffe08fdbefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h07cfffff0000ffff; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434000003fffbfff; - y = 64'hd29ffffffc7ffffe; - zrf = 64'h0000000000000000; - ans = 64'hd5f000003e3fbff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc346f4237b7cbfe9; - y = 64'h471000000000006f; - zrf = 64'h0000000000000000; - ans = 64'hca66f4237b7cc088; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2c4c0000003fffff; - y = 64'h230ffffc00400000; - zrf = 64'h0000000000000000; - ans = 64'h0f6bfffc8077fff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc4400000000000; - y = 64'h43cc71fdbb55b450; - zrf = 64'h0000000000000000; - ans = 64'h43a20022908c3c1b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbdeffbfffff7fffe; - y = 64'h403000000000dfff; - zrf = 64'h0000000000000000; - ans = 64'hbe2ffbfffff9bfc4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc020001001000000; - y = 64'hc34ec9a95e5b23e2; - zrf = 64'h0000000000000000; - ans = 64'h437ec9c829f11cd4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d7fffffffdffff; - y = 64'hc01ff7feffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4407f9ff3ffe007f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb245df5ba33a7f85; - y = 64'h40100000004003ff; - zrf = 64'h0000000000000000; - ans = 64'hb265df5ba392026a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06000007fffff7f; - y = 64'h43eff90000000000; - zrf = 64'h0000000000000000; - ans = 64'hc45ff900ffc7fefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc18ffc00000fffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0f1fffffffff000; - y = 64'h429effffdfffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3a16fffedfff07f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c8000000bffffff; - y = 64'hc52fff0000400000; - zrf = 64'h0000000000000000; - ans = 64'hc1bfff00183f3ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381fffffffbff7fe; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hf83fffffffbff7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h002ffffff0003fff; - y = 64'h3ff000008000003f; - zrf = 64'h0000000000000000; - ans = 64'h0030000078001fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7fca13a9dbf49e7; - y = 64'hbfe80000000001ff; - zrf = 64'h0000000000000000; - ans = 64'h37f578ebf64f7937; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47e000000800003e; - y = 64'hbfc080003ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc7b080004840005d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h8b3ffc2000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4120001fff800000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h517000001fff7ffe; - y = 64'hc1cf000000003ffe; - zrf = 64'h0000000000000000; - ans = 64'hd34f00003dff47fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380e000000000010; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hf83e00000000000f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41168636954ae162; - y = 64'hbfec00000001fffe; - zrf = 64'h0000000000000000; - ans = 64'hc113b56fc2a2ed97; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h330e000100000000; - y = 64'h43ee0000000001ff; - zrf = 64'h0000000000000000; - ans = 64'h370c2000f00001e0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802d3018ea8c241d; - y = 64'hc007fdffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0045e23fae5a7253; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffc505cc8a6e8ea; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h002c505cc8a6e8e9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbff8000001ffff; - y = 64'h3acffffffff00000; - zrf = 64'h0000000000000000; - ans = 64'hba9ff7fffff203fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80000001ffffbfe; - y = 64'h3e40880000000000; - zrf = 64'h0000000000000000; - ans = 64'hc6508800210ffbdb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d0080000000004; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc080080000000004; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41367c708f592990; - y = 64'hc00a5078d45675b0; - zrf = 64'h0000000000000000; - ans = 64'hc1527da775ba1512; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3474f322c53fb6a; - y = 64'h4c386ada422df8a5; - zrf = 64'h0000000000000000; - ans = 64'hcf91c93af32c74b4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41dffffff00003fe; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbe8ffffff00003ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0000001fdffff; - y = 64'h5ff53ac9cf7cf6c8; - zrf = 64'h0000000000000000; - ans = 64'h61f53ac9d221a8a8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb000001fffff7e; - y = 64'h3ffbad41f232c7b1; - zrf = 64'h0000000000000000; - ans = 64'h3fbbad42298d4ab5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e047fffffffffe; - y = 64'h4000003ffdfffffe; - zrf = 64'h0000000000000000; - ans = 64'h43f048411df6fffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf9e000002000000; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3c5e000002000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc53fffffff77ffff; - y = 64'hc05ffe000000003e; - zrf = 64'h0000000000000000; - ans = 64'h45affdffff7808be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1cffffffffffe1f; - y = 64'h717000005fffffff; - zrf = 64'h0000000000000000; - ans = 64'hf35000005fffff0e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402000003ffffbff; - y = 64'h403000001f800000; - zrf = 64'h0000000000000000; - ans = 64'h406000005f7ffc7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc039d0b1184126b6; - y = 64'h06ad12e793d72c70; - zrf = 64'h0000000000000000; - ans = 64'h86f77460b35b5a57; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc048000000000000; - y = 64'h434000000800003e; - zrf = 64'h0000000000000000; - ans = 64'hc39800000c00005d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06fc00001ffffff; - y = 64'h0ec040faf47bd51e; - zrf = 64'h0000000000000000; - ans = 64'h8f402078ff96ed22; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf87ffffff7fffff; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3f67ffffff7fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc70000200001fff; - y = 64'hbf29fffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3baa0003400033fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc000005fffffffff; - y = 64'h403ffffffff00002; - zrf = 64'h0000000000000000; - ans = 64'hc050005ffff7ffd0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h45f00017fffffffe; - y = 64'h47f2f5abbf28ad12; - zrf = 64'h0000000000000000; - ans = 64'h4df2f5c82faa4bcd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0dd00000000fffff; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8db0000000100000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf0d45dab53a65b8; - y = 64'h380fff7ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hb72d45659dcf90cc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbfdeba273f5031a6; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fdffffffffffdfc; - y = 64'h3cd000008000001e; - zrf = 64'h0000000000000000; - ans = 64'h7cc000007fffff1c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha0bffffdfefffffe; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h20affffdfefffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3feffff80000001e; - y = 64'hc3dffff802000000; - zrf = 64'h0000000000000000; - ans = 64'hc3dffff00201ff9d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401bb79c251f0d03; - y = 64'hbbfdf1012672bca6; - zrf = 64'h0000000000000000; - ans = 64'hbc29ef2550a601bc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffdfffffc000000f; - y = 64'h22efffffff0001ff; - zrf = 64'h0000000000000000; - ans = 64'he2dfffffbf00020f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc8b60e46a80f6d; - y = 64'hbfdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfb8b60e46a80f6b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4141058dae2059c1; - y = 64'hbf9fffff0003ffff; - zrf = 64'h0000000000000000; - ans = 64'hc0f1058d25f60d01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hca3326c13bfeba24; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4a2326c13bfeba24; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb53bffffffffc000; - y = 64'h43cfffffffffefdf; - zrf = 64'h0000000000000000; - ans = 64'hb91bffffffffb1e3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb4f0000020ffffff; - y = 64'h40095713ee956d23; - zrf = 64'h0000000000000000; - ans = 64'hb509571422d9063d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0200001e0000000; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h40100001e0000002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c00080000000ff; - y = 64'h40c000000000083f; - zrf = 64'h0000000000000000; - ans = 64'h429000800000093f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7d501ff7ffffffff; - y = 64'hbff0000004000400; - zrf = 64'h0000000000000000; - ans = 64'hfd501ff804080206; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0cfeffffffffffe; - y = 64'h4010ffffffffffde; - zrf = 64'h0000000000000000; - ans = 64'hc0f0f77fffffffdd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc06d169113d091; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3fc06d169113d091; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbd5fdffdffffffff; - y = 64'h5644b72ace1bbb6b; - zrf = 64'h0000000000000000; - ans = 64'hd3b4a27257daf2cd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381ffff7ffffeffe; - y = 64'hbf80003fffffe000; - zrf = 64'h0000000000000000; - ans = 64'hb7b0003bffefd7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3dc000000ffbffff; - y = 64'h41c68f9b37c7034c; - zrf = 64'h0000000000000000; - ans = 64'h3f968f9b4e50fa9c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ffffffdf800000; - y = 64'hbfeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h47ffffffdf7fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0000000001000; - y = 64'hbf3ffe00000001ff; - zrf = 64'h0000000000000000; - ans = 64'h3f2ffe00000021fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380a8e204e2cb7dd; - y = 64'h7fdfffcfffffffff; - zrf = 64'h0000000000000000; - ans = 64'h77fa8df878fc429a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf8f000000000100; - y = 64'hc29ffffffff04000; - zrf = 64'h0000000000000000; - ans = 64'h423efffffff0bf00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h330fc7fffffffffe; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb30fc7fffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f0000000003ffe; - y = 64'hc1d800000000000e; - zrf = 64'h0000000000000000; - ans = 64'hc3d800000000600b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e676ed17a50125; - y = 64'hbe900000000fefff; - zrf = 64'h0000000000000000; - ans = 64'h408676ed17bb619a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80010001fffffff; - y = 64'h40e01ffffff7fffe; - zrf = 64'h0000000000000000; - ans = 64'hb8f030202037f7fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc020000000000000; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4020000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h486007fffffffdff; - y = 64'h3ca000003fc00000; - zrf = 64'h0000000000000000; - ans = 64'h451008003fdfddff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81ffffffffff0fe; - y = 64'hba0dfffffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h323dfffffbfff1ed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h205043ffffffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffffdfffffff8; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc00ffffdfffffff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffffff7dff; - y = 64'h3a6000040ffffffe; - zrf = 64'h0000000000000000; - ans = 64'h3a6000040fffbefe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401bffffeffffffe; - y = 64'hb7fc497e1cedf965; - zrf = 64'h0000000000000000; - ans = 64'hb828c04e4b2b7b28; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc34fff0000007fff; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h435fff0000007ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbfc000fffffffe; - y = 64'hbff0000040007ffe; - zrf = 64'h0000000000000000; - ans = 64'hbfbfc0017f0101fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h407000003ffbfffe; - y = 64'h38042862fe8e3368; - zrf = 64'h0000000000000000; - ans = 64'h388428634f2ab547; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40f000000ff00000; - y = 64'hc1effffff0003fff; - zrf = 64'h0000000000000000; - ans = 64'hc2f0000007f01ff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dffffffff77ffe; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h43effffffff77ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb811814b7ef464dc; - y = 64'hfa807ffffbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h72a20d55d68bb521; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37efffffffe3fffe; - y = 64'h3fe000000000001b; - zrf = 64'h0000000000000000; - ans = 64'h37dfffffffe40034; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc010000001000004; - y = 64'hc0000020001ffffe; - zrf = 64'h0000000000000000; - ans = 64'h4020002001200203; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hca200000400007ff; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4a30000040000801; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f8fff7ffffefffe; - y = 64'h3fb000000087ffff; - zrf = 64'h0000000000000000; - ans = 64'h3f4fff80010efbbc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd0008000007fff; - y = 64'hc1c7099afc03c81c; - zrf = 64'h0000000000000000; - ans = 64'hc1a70a5348dc6085; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3f000000fdfffff; - y = 64'h3ffd2e23653e84e9; - zrf = 64'h0000000000000000; - ans = 64'hc3fd2e2382324c05; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf8ffbfff7ffffff; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3faffbfff7ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3dcff00fffffffff; - y = 64'hb7effff7ffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb5cff00803fbfffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h353957789e95fd88; - y = 64'h381d5abc75937d08; - zrf = 64'h0000000000000000; - ans = 64'h2d673f2091f73528; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f80080000080000; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfa008000007fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb650004000ffffff; - y = 64'hb7e00fffffffefff; - zrf = 64'h0000000000000000; - ans = 64'h2e4010404100effe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4390e6210af918da; - y = 64'h46cfffc400000000; - zrf = 64'h0000000000000000; - ans = 64'h4a70e6015b7b2447; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffffffdfef; - y = 64'h40dffffefbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h40dffffefbffdfee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401549a16416e287; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc03549a16416e287; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41fffffc00001fff; - y = 64'hc1fa652249c59e1f; - zrf = 64'h0000000000000000; - ans = 64'hc40a651efd216f4a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcfeffff6ffffffff; - y = 64'h41ffff9fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hd1ffff97001afffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbcafc000003fffff; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3ccfc00000400001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7f0000000810000; - y = 64'hc3e2c0625a54229a; - zrf = 64'h0000000000000000; - ans = 64'h3be2c0625aeb51b3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha957fffffffbfffe; - y = 64'h43cfff0000000400; - zrf = 64'h0000000000000000; - ans = 64'had37ff3ffffc031e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha464b1e64cae594f; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h2494b1e64cae594f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcedc00003ffffffe; - y = 64'h41c000000000ffff; - zrf = 64'h0000000000000000; - ans = 64'hd0ac00004001bffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01fbeffffffffff; - y = 64'h21600000003fffbf; - zrf = 64'h0000000000000000; - ans = 64'ha18fbf00007efb7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3de59209bb8a564; - y = 64'hbfd0000007fdffff; - zrf = 64'h0000000000000000; - ans = 64'h43be5920aae16a8c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7ffffffe3ffffff; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h482fffffe3fffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8a00000000002ff; - y = 64'h43dfdfffffff7ffe; - zrf = 64'h0000000000000000; - ans = 64'hbc8fdfffffff85f6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01e7d66f623cb4c; - y = 64'h787feff7fffffffe; - zrf = 64'h0000000000000000; - ans = 64'hf8ae6e20a34efbdb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47eddf042473ef08; - y = 64'hb7e00000fe000000; - zrf = 64'h0000000000000000; - ans = 64'hbfdddf05fea850ca; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf80100003ffffff; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h42d0100003ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e0000000008006; - y = 64'h7fdfffffc7fffffe; - zrf = 64'h0000000000000000; - ans = 64'h03cfffffc801000a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01ffff03fffffff; - y = 64'h3fddffffffffff7f; - zrf = 64'h0000000000000000; - ans = 64'hc00dfff13bffff7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e0000000007ffe; - y = 64'h3cae59ba3a79c7b6; - zrf = 64'h0000000000000000; - ans = 64'hc49e59ba3a7aba80; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caffff80001ffff; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbffffff800020000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbfdffffdfffffe; - y = 64'h1a8fe1ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h9a5fc21dfe01dffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3811c6a45a8e5bfc; - y = 64'hb7e48cc87315baad; - zrf = 64'h0000000000000000; - ans = 64'hb006d4b6422c9dfb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h36a0000000013ffe; - y = 64'hc170004000000200; - zrf = 64'h0000000000000000; - ans = 64'hb820004000014202; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fefffffffffff07; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h834fffffffffff06; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbfffff7fffffef; - y = 64'hc340ffffffffffbf; - zrf = 64'h0000000000000000; - ans = 64'hc310ffffbbffffb5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc003ffffff0000; - y = 64'hc800000037ffffff; - zrf = 64'h0000000000000000; - ans = 64'hc7d00400380cfffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802fffe008000000; - y = 64'hc3f00001fffffc00; - zrf = 64'h0000000000000000; - ans = 64'h042fffe407fbf901; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c6c403d1bd7bc9; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4726c403d1bd7bc8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80ffe0000001ffe; - y = 64'hbcae9296e1ac0804; - zrf = 64'h0000000000000000; - ans = 64'h44ce90adb83e0bd5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ffffffffe00003; - y = 64'haa4ffffdffdfffff; - zrf = 64'h0000000000000000; - ans = 64'h225ffffdffc00005; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h674e000000010000; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'ha73e000000010000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f5008000000007f; - y = 64'hffe0d019cec3a5a4; - zrf = 64'h0000000000000000; - ans = 64'hff40d881dbab07fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3effc0100000000; - y = 64'h417fffffff700000; - zrf = 64'h0000000000000000; - ans = 64'hc57ffc00ff7011fb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb811ffff7fffffff; - y = 64'hc0cffff0003fffff; - zrf = 64'h0000000000000000; - ans = 64'h38f1fff680243ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02f8000000007ff; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h001f800000000801; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc040000800000006; - y = 64'hb550003fffffff7e; - zrf = 64'h0000000000000000; - ans = 64'h35a00048001fff84; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffdffffef0000000; - y = 64'h37f400003fffffff; - zrf = 64'h0000000000000000; - ans = 64'hf7e3ffff95fffddf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb000040000001e; - y = 64'h426ffefffe000000; - zrf = 64'h0000000000000000; - ans = 64'h422fff07fdbfffbc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81fffffc00fffff; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h781fffffc00fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e72cba2f8f989b2; - y = 64'hc2b007fffffffff7; - zrf = 64'h0000000000000000; - ans = 64'hc132d508ca76066c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h508ffeffbffffffe; - y = 64'h3f00ffffffffbfff; - zrf = 64'h0000000000000000; - ans = 64'h4fa0ff77ddffc000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48000000027fffff; - y = 64'h4063ffff7fffffff; - zrf = 64'h0000000000000000; - ans = 64'h4873ffff831fffea; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020017ffffffffe; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h8020017ffffffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbeb00000000fbfff; - y = 64'h3fefff7ffffffffb; - zrf = 64'h0000000000000000; - ans = 64'hbeafff80001f7f7b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h002f37ebf6c8eaec; - y = 64'hc08be464f4c81c69; - zrf = 64'h0000000000000000; - ans = 64'h80cb36000706e168; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h42dfffff80000100; - y = 64'hc4befffdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc7aefffd840008f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc03ffffc00000100; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h003ffffc00000100; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c007fffffbfffe; - y = 64'h43bfff77fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h459007bbddfc000e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37ea265023bdd968; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fdfffffffbffffb; - y = 64'h3fefffe000000000; - zrf = 64'h0000000000000000; - ans = 64'h3fdfffdfffc0003c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e001fffffefffe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41500000803fffff; - y = 64'hbfadc816e2fbf1f7; - zrf = 64'h0000000000000000; - ans = 64'hc10dc817d1b3c968; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfeffdfffffffffc; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e000007fe00000; - y = 64'hbf1fffffffffffe8; - zrf = 64'h0000000000000000; - ans = 64'h411000007fdffff4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00e800000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb5665a54ce0c12; - y = 64'hbeb0000008007ffe; - zrf = 64'h0000000000000000; - ans = 64'h3e75665a5f81e46d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0300007ffffffef; - y = 64'h3fb9cc340fc29b6a; - zrf = 64'h0000000000000000; - ans = 64'hbff9cc40f5dca32f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1800000ffffffff; - y = 64'hc0bfc00000003fff; - zrf = 64'h0000000000000000; - ans = 64'h424fc001fc003ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80ffffffffffbfd; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0073e8cf3e13711; - y = 64'h802807fffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h004174b95a25e19a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37efffffffffaffe; - y = 64'h3d7ffffffffe001f; - zrf = 64'h0000000000000000; - ans = 64'h357ffffffffdb01e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e457789619128b; - y = 64'h40bff3fffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc8b44fd7c8e0c922; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8004379ab207ab5; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h27cd6fcc24e7623d; - y = 64'h401000000003efff; - zrf = 64'h0000000000000000; - ans = 64'h27ed6fcc24eea0bf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca000400003ffff; - y = 64'hc3fcb63607d6b0bc; - zrf = 64'h0000000000000000; - ans = 64'h40acb6a8e0b5fda3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hfb48000040000000; - zrf = 64'h0000000000000000; - ans = 64'hbb68000040000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc010200100000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfff863c13828ae4; - y = 64'h3fef8000000003ff; - zrf = 64'h0000000000000000; - ans = 64'hbfff0823233484a8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0409fffffffffff; - y = 64'hbfdfff0003ffffff; - zrf = 64'h0000000000000000; - ans = 64'h40309f7b0213ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb69ffff000001000; - y = 64'h43dfc00003fffffe; - zrf = 64'h0000000000000000; - ans = 64'hba8fbff024000dde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40d00000000403ff; - y = 64'h43f0000027ffffff; - zrf = 64'h0000000000000000; - ans = 64'h44d00000280403ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3e40552ef3ea764f; - y = 64'h3c200ffffffffffc; - zrf = 64'h0000000000000000; - ans = 64'h3a70658422de60c2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc0bfffe00000001e; - zrf = 64'h0000000000000000; - ans = 64'h80dfffe00000001e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfffc00000000003; - y = 64'h391001ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb91fc3f800000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc0007ffffff000; - y = 64'h381ffffffffe1ffe; - zrf = 64'h0000000000000000; - ans = 64'hb7f0007ffffefff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc010000ffffdfffe; - y = 64'hbf5fffffff800fff; - zrf = 64'h0000000000000000; - ans = 64'h3f80000fffbe07be; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3a0de408a1808afd; - y = 64'hffd00000000001fb; - zrf = 64'h0000000000000000; - ans = 64'hf9ede408a1808eb0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca5e76e4f34d231; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hfcc5e76e4f34d231; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbffdffffffff00; - y = 64'h404000000003fffb; - zrf = 64'h0000000000000000; - ans = 64'hc00ffe000007fe76; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2f40000000000027; - y = 64'hc35f7fffffffffc0; - zrf = 64'h0000000000000000; - ans = 64'hb2af80000000000c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434ffffff7ff7fff; - y = 64'h3fcfff7ffffffeff; - zrf = 64'h0000000000000000; - ans = 64'h432fff7ff7ff9f01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1000023fffffffe; - y = 64'h0010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h81200023ffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha38000000800ffff; - y = 64'h402ff7faa54f7d56; - zrf = 64'h0000000000000000; - ans = 64'ha3bff7fab54d7a26; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1db54446247aa52; - y = 64'hbfcc001fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h41b7e9d72a43174f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hb80000000000807e; - zrf = 64'h0000000000000000; - ans = 64'hf82000000000807e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dffbfefffffffe; - y = 64'hc0c0000100000100; - zrf = 64'h0000000000000000; - ans = 64'h42affc00ffbff1fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d00000000003be; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h84000000000003bd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h380154191efc4e28; - y = 64'h381000001ff7ffff; - zrf = 64'h0000000000000000; - ans = 64'h30215419419bd659; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fb6ec4483f565b4; - y = 64'h7fe657f1311c1385; - zrf = 64'h0000000000000000; - ans = 64'h7fb0016e3b91608a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hb28fffffffffe007; - zrf = 64'h0000000000000000; - ans = 64'hf2afffffffffe007; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ffffffffefffbf; - y = 64'h69a003ffffffefff; - zrf = 64'h0000000000000000; - ans = 64'he1b003fffff7edde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc038e6a7fa682c54; - y = 64'h4032e353cb91aeb8; - zrf = 64'h0000000000000000; - ans = 64'hc07d6547d23e6845; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403000001fffffdf; - y = 64'h43e2d8971b04eb4e; - zrf = 64'h0000000000000000; - ans = 64'h4422d89740b6195e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc0392c59c8e48f37; - zrf = 64'h0000000000000000; - ans = 64'h80592c59c8e48f37; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c63320494ceb76c; - y = 64'h4028000020000000; - zrf = 64'h0000000000000000; - ans = 64'h3c9ccb07059a1c4c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0201000000007ff; - y = 64'h4288c3935a34e57b; - zrf = 64'h0000000000000000; - ans = 64'hc2b8dc56ed8f26c0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c00000007fff00; - y = 64'hc01fffffffffef00; - zrf = 64'h0000000000000000; - ans = 64'h41f00000007ff680; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbcafffffffe01ffe; - zrf = 64'h0000000000000000; - ans = 64'hfccfffffffe01ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01f000001ffffff; - y = 64'hc7effffffffe0003; - zrf = 64'h0000000000000000; - ans = 64'h481f000001fe1002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4789b47aa1149764; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4439b47aa1149766; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc60fdfffffffffff; - y = 64'ha1c03fffffefffff; - zrf = 64'h0000000000000000; - ans = 64'h27e02fbffff00fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3ce000200000000; - y = 64'h001bfffffffbffff; - zrf = 64'h0000000000000000; - ans = 64'h83fa4001bffc3ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc0000800000001ff; - zrf = 64'h0000000000000000; - ans = 64'h80200800000001ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ff00000001ffefe; - y = 64'h3feffff7fff7fffe; - zrf = 64'h0000000000000000; - ans = 64'h3feffff80037fdeb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf300000000006ff; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbbf00000000006fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ff000000000002; - y = 64'hbfcffffffbfdfffe; - zrf = 64'h0000000000000000; - ans = 64'hc1defffffc1e1000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c3e4c2b39d80cb; - y = 64'h38080000001fffff; - zrf = 64'h0000000000000000; - ans = 64'h3bddd7240d940ab5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h41cfe00001ffffff; - zrf = 64'h0000000000000000; - ans = 64'h01efe00001ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe1ff7fffffffff; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e0000000006ffe; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc0a0000000006ffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f6ea4106b65a11; - y = 64'h3ec001ffffffffef; - zrf = 64'h0000000000000000; - ans = 64'h46c6ed1e4ed730c4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h480fffffffffdf00; - y = 64'h4010000000000400; - zrf = 64'h0000000000000000; - ans = 64'h482fffffffffe700; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc1d0000004000fff; - zrf = 64'h0000000000000000; - ans = 64'h81f0000004000fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h69ffffa000000000; - y = 64'hc00ffffefbffffff; - zrf = 64'h0000000000000000; - ans = 64'hea1fff9efc030bff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401000000006ffff; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3ff000000006ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1e000ffffffffff; - y = 64'h3812000000003ffe; - zrf = 64'h0000000000000000; - ans = 64'hba02012000004000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7fefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0029ddf3657c97ac; - y = 64'hbb62000400000000; - zrf = 64'h0000000000000000; - ans = 64'hfb9d19b849a90400; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h5c10000001001fff; - zrf = 64'h0000000000000000; - ans = 64'h1c30000001001fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7f02007fffffffe; - y = 64'h402000000100000f; - zrf = 64'h0000000000000000; - ans = 64'hc82020080102008d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h947ffe00000ffffe; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h945ffe00000fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc04000000047ffff; - y = 64'h3feffffffffc0007; - zrf = 64'h0000000000000000; - ans = 64'hc040000000460002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4030040000200000; - y = 64'h0017055f48beeff5; - zrf = 64'h0000000000000000; - ans = 64'h00570b20a0bf2a70; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41c0000000fdffff; - y = 64'hb81fffffffffffed; - zrf = 64'h0000000000000000; - ans = 64'hb9f0000000fdfff5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3436f8f2b2e7e21; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3336f8f2b2e7e20; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3cfffffffff7f7f; - y = 64'h40bab08b43d48199; - zrf = 64'h0000000000000000; - ans = 64'hc49ab08b43d4166b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h7fefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ffffffdff80000; - y = 64'h402fffffc00000ff; - zrf = 64'h0000000000000000; - ans = 64'hc23fffff9ff8013f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc05ffddfffffffff; - zrf = 64'h0000000000000000; - ans = 64'h807ffddfffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47e00008000ffffe; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h47d00008000ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'he8618845e92f15df; - y = 64'hbfce0fd99d7c11ae; - zrf = 64'h0000000000000000; - ans = 64'h68407870a5c4189a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h7fefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc7000000000ffee; - y = 64'hc1e0001100000000; - zrf = 64'h0000000000000000; - ans = 64'h3e6000110000fff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0cfffffdfc00000; - y = 64'hc1c0200000000040; - zrf = 64'h0000000000000000; - ans = 64'h42a01fffefbfc040; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h911f7ffffffffff0; - y = 64'h3f90ca8f09d1be5d; - zrf = 64'h0000000000000000; - ans = 64'h90c08764cdaa775b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02200003ffffffe; - y = 64'hc1d1ffffbffffffe; - zrf = 64'h0000000000000000; - ans = 64'h42043ffffffffefc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffe7ffffffffffee; - zrf = 64'h0000000000000000; - ans = 64'hc007ffffffffffee; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0000023ffffff; - y = 64'hc06ffc000000000e; - zrf = 64'h0000000000000000; - ans = 64'h405ffc0047f7000d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb2001fffffffff; - y = 64'h3fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbfa2002000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4269afb6393490b7; - y = 64'hba62478d7e1c3e1c; - zrf = 64'h0000000000000000; - ans = 64'hbcdd588bdfe3e666; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc040000000007fff; - y = 64'hc3b2a6c91c557f56; - zrf = 64'h0000000000000000; - ans = 64'h4402a6c91c56148c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06007f7fffffffe; - y = 64'hddcfff9ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h5e4007c7e817fffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc57ea73c304d054d; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc57ea73c304d054c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c086a10b8210ae; - y = 64'hbf01ffffbfffffff; - zrf = 64'h0000000000000000; - ans = 64'hc2d29774ead7ce94; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4343a987a0dad4a5; - y = 64'h40caa5c07b2b6187; - zrf = 64'h0000000000000000; - ans = 64'h44205f969ae3434d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h40b007ffffffff7e; - zrf = 64'h0000000000000000; - ans = 64'h00d007ffffffff7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e0100000000040; - y = 64'hbff0002000000001; - zrf = 64'h0000000000000000; - ans = 64'h47e0102020000042; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4403bb97ce60574a; - y = 64'h3feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4403bb97ce605749; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3a0c0007fffffffe; - y = 64'h381f800000fffffe; - zrf = 64'h0000000000000000; - ans = 64'h323b9007e0e0003d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffffffff003fff; - y = 64'hc3b0000007ffffee; - zrf = 64'h0000000000000000; - ans = 64'hc5c0000007801fed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40232b23c9417cd7; - y = 64'hba5000000000087e; - zrf = 64'h0000000000000000; - ans = 64'hba832b23c9418703; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc05fbffbffffffff; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc05fbffbffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc0000080000800; - y = 64'hb80ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h37e00000800007ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0010000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e4003fffffffff; - y = 64'hffd0007ffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h03c400e001fffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0fbffffffffffef; - y = 64'hc3cf100000000000; - zrf = 64'h0000000000000000; - ans = 64'h44db2dfffffffff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4339ff8b8ee34977; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4339ff8b8ee34979; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffffffffffff; - y = 64'h37f9fc8b9cbef88a; - zrf = 64'h0000000000000000; - ans = 64'h37f9fc8b9cbef88a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3ff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0010000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h21900001dfffffff; - y = 64'hbf20000017fffffe; - zrf = 64'h0000000000000000; - ans = 64'ha0c00001f80002cc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h41e000003fffffff; - zrf = 64'h0000000000000000; - ans = 64'h020000003fffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbf5369d33862aaac; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0300001fffffffa; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc0400001fffffff9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc06000400000007f; - y = 64'hc1d00000fff7ffff; - zrf = 64'h0000000000000000; - ans = 64'h42400040fffc005f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3fffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h001fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdffffffff000fe; - y = 64'h43dffdfffdffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3cffdfffdf001fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h41dffbffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h01fffbffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0a6000000000000; - y = 64'h43fefffffffff7ff; - zrf = 64'h0000000000000000; - ans = 64'hc4b54ffffffffa7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff60484a5536536; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc0060484a5536534; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0029954d0f0df5b3; - y = 64'h41e00000000003ff; - zrf = 64'h0000000000000000; - ans = 64'h0219954d0f0dfc17; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h3ffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h001ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc01000081fffffff; - y = 64'h308ffdffbfffffff; - zrf = 64'h0000000000000000; - ans = 64'hb0affe0ffefbdf7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc03fbffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h805fbffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2fb00ffffffdffff; - y = 64'hbd50000001fffff6; - zrf = 64'h0000000000000000; - ans = 64'had10100001fffff4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7effffffffffc1f; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb7fffffffffffc1f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb83dc63477cd3d; - y = 64'h4070007ffff80000; - zrf = 64'h0000000000000000; - ans = 64'hc0383e88229d5218; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0020000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcffffff8000100; - y = 64'hbfc000000003e000; - zrf = 64'h0000000000000000; - ans = 64'h3f9ffffff807c100; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h435f000003ffffff; - zrf = 64'h0000000000000000; - ans = 64'h037f000003ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb810000020000001; - y = 64'h47ffdfffffffff80; - zrf = 64'h0000000000000000; - ans = 64'hc01fe0003fbfff81; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h802fffefefffffff; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h803fffeff0000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd0000ffbfffffe; - y = 64'h3fbbfffffdffffff; - zrf = 64'h0000000000000000; - ans = 64'h3f9c001bf6fffdfc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0020000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43ec064c6152fc63; - y = 64'hcd3fbffffff7fffe; - zrf = 64'h0000000000000000; - ans = 64'hd13bce3fc88954d5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c3e54c4d8a3cf09; - y = 64'h415ffffffffdffe0; - zrf = 64'h0000000000000000; - ans = 64'h3dae54c4d8a1e99f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4030fffffffeffff; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h4050fffffffeffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402efffffffffff7; - y = 64'hbcafffc00001ffff; - zrf = 64'h0000000000000000; - ans = 64'hbceeffc20001eff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h400fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h002fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1a000000001fdff; - y = 64'hc7e29e108929df66; - zrf = 64'h0000000000000000; - ans = 64'h49929e10892c30d4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffeffff800007fff; - zrf = 64'h0000000000000000; - ans = 64'hc00ffff800007fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hdff0007f7fffffff; - y = 64'h37fffffffffff77f; - zrf = 64'h0000000000000000; - ans = 64'hd800007f7ffffbbe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb0000000007f7f; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfd0000000007f7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e44faf4fcc6d94; - y = 64'hb80fec0000000000; - zrf = 64'h0000000000000000; - ans = 64'h3c0442fd823a8dd0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h400ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h002ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47e0004008000000; - y = 64'hbfb85853044ed3e1; - zrf = 64'h0000000000000000; - ans = 64'hc7a858b471c70e9e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hb06003ffffffffde; - zrf = 64'h0000000000000000; - ans = 64'hf08003ffffffffde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e7518d337cc25b; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd12000ffffefffff; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hd14000ffffefffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4490000003fffefe; - y = 64'h4136bf27884c5b05; - zrf = 64'h0000000000000000; - ans = 64'h45d6bf278dfc2379; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0030000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0221db466eedfb9; - y = 64'hc3c0e83093586003; - zrf = 64'h0000000000000000; - ans = 64'h43f3249a1eb595ba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4020000000004400; - zrf = 64'h0000000000000000; - ans = 64'h0040000000004400; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4022ac23df608ace; - y = 64'h3a2cddcec5bdb7f6; - zrf = 64'h0000000000000000; - ans = 64'h3a60d80ce2bc8b14; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbffffffff60000; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h3fdffffffff60002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fefffff80000400; - y = 64'h434615f1f239d053; - zrf = 64'h0000000000000000; - ans = 64'h434615f199e20b4d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0030000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37ffe5d085a3877b; - y = 64'hc000800000003fff; - zrf = 64'h0000000000000000; - ans = 64'hb810727f84e891a6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc80ffffe00000006; - zrf = 64'h0000000000000000; - ans = 64'h882ffffe00000006; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc10001fffffefff; - y = 64'h3ccd2ded70b56965; - zrf = 64'h0000000000000000; - ans = 64'hb8ed2e27cc902da0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf700000000100ff; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfa00000000100fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f00207fffffffe; - y = 64'hc1e03effffffffff; - zrf = 64'h0000000000000000; - ans = 64'h43e0410fff7ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h401fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h003fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h403fffffff780000; - y = 64'hb400023fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb450023fffbbf66f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47ffffe000020000; - y = 64'h3fe5d02ba77755f7; - zrf = 64'h0000000000000000; - ans = 64'h47f5d015d74d0b83; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43ef0000000000ff; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h441f0000000000fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca0384aaa23be04; - y = 64'hb940005fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb5f038abfbe3bad9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h401ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h003ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40327ad957b1f5df; - y = 64'hc000006000000000; - zrf = 64'h0000000000000000; - ans = 64'hc0427b4838ca040a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hb806f9c81cbb15f4; - zrf = 64'h0000000000000000; - ans = 64'hf826f9c81cbb15f4; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37feffffffffffff; - y = 64'h47ef8000000fffff; - zrf = 64'h0000000000000000; - ans = 64'h3ffe8400000f7fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404ffefffffff000; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h439ffefffffff000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0001000200000; - y = 64'hb100003ffffffff8; - zrf = 64'h0000000000000000; - ans = 64'hb0d0005000600077; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0360000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffdb3470a5e3dd1b; - y = 64'h480f7fffffffdfff; - zrf = 64'h0000000000000000; - ans = 64'h87fac79ee34c3271; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbca0000080003fff; - zrf = 64'h0000000000000000; - ans = 64'hfcc0000080003fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3cce0ccf7d8e4a61; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d00800ffffffff; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc520080100000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f000fffffdfffe; - y = 64'h404effffffdfffff; - zrf = 64'h0000000000000000; - ans = 64'h424f01efffdc1dfc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h0360000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80f800001fffffe; - y = 64'h44e00000ffff7fff; - zrf = 64'h0000000000000000; - ans = 64'hbcff8001f9ff041c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401ffffbdfffffff; - y = 64'h43d0000000000300; - zrf = 64'h0000000000000000; - ans = 64'h43fffffbe00005ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c0000017fffffe; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc720000017fffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1feffffff7ffffe; - y = 64'h1af693ab1ab44f36; - zrf = 64'h0000000000000000; - ans = 64'h9d05df0dc1845e0e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h434fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h036fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb20643cc9d9a536b; - y = 64'h41e49085b10e049f; - zrf = 64'h0000000000000000; - ans = 64'hb3fc9ddc0081bc98; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4009ad651462b44a; - zrf = 64'h0000000000000000; - ans = 64'h0029ad651462b44a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41dff0000000003e; - y = 64'h43effff7ffffffe0; - zrf = 64'h0000000000000000; - ans = 64'h45dfeff80400001f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc09ffff000004000; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc3fffff000003ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd0200000000800; - y = 64'hdc0ffe0002000000; - zrf = 64'h0000000000000000; - ans = 64'hdbf01efe010207ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h434ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h036ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe400000080001fe; - y = 64'h14f0010000000ffe; - zrf = 64'h0000000000000000; - ans = 64'h93400100080091fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h436eff7fffffffff; - zrf = 64'h0000000000000000; - ans = 64'h038eff7fffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd883177e5f1999; - y = 64'h43e4000000000003; - zrf = 64'h0000000000000000; - ans = 64'hc3cea3dd5df6e003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e0000000800003; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h83d0000000800003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h405ffffffffffb80; - y = 64'h8015e1d67420ea5d; - zrf = 64'h0000000000000000; - ans = 64'h8085e1d67420e749; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7fe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd1000fffffffff; - y = 64'h5d310000000000ff; - zrf = 64'h0000000000000000; - ans = 64'h5d1210110000010e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc1efffdffbffffff; - zrf = 64'h0000000000000000; - ans = 64'h820fffdffbffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8a008000000007f; - y = 64'hc01ffffffc00001e; - zrf = 64'h0000000000000000; - ans = 64'h38d007fffdff008f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41ffffdfffff8000; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h01efffdfffff8002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7fe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h4000000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc340708fc64cbb8d; - y = 64'h802fc64018f098e6; - zrf = 64'h0000000000000000; - ans = 64'h038052e4afa4e3ab; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfffffbffff7ffff; - y = 64'hbd400000200000ff; - zrf = 64'h0000000000000000; - ans = 64'h3d4fffc03ff781fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02008d3baee2879; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h802008d3baee2878; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7fefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h400fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400ffe00003fffff; - y = 64'hc1e507e54ddba03c; - zrf = 64'h0000000000000000; - ans = 64'hc2050694cfb0d24b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4edffffffefffeff; - zrf = 64'h0000000000000000; - ans = 64'h0efffffffefffeff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc15000400ffffffe; - y = 64'hc0500007fffdffff; - zrf = 64'h0000000000000000; - ans = 64'h41b00048101e07f5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc6bb60a15b9ca674; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h86bb60a15b9ca672; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80a16ad02c87cd3; - y = 64'h380fffffffffe7fe; - zrf = 64'h0000000000000000; - ans = 64'hb02a16ad02c86940; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7feffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h400ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc00f7ffffffeffff; - y = 64'hf7efefffffffffbe; - zrf = 64'h0000000000000000; - ans = 64'h780f703fffff003f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h40dffffffffff806; - zrf = 64'h0000000000000000; - ans = 64'h00fffffffffff806; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h32a89b054aa778be; - y = 64'h38ee00000000000e; - zrf = 64'h0000000000000000; - ans = 64'h2ba71154f5fd013d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'haa6f0618039cfa82; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hea6f0618039cfa82; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40f007ff80000000; - y = 64'h47fffff07fffffff; - zrf = 64'h0000000000000000; - ans = 64'h490007f7bc203e00; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4010000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4020000000020006; - y = 64'hbb62b1da7ab47675; - zrf = 64'h0000000000000000; - ans = 64'hbb92b1da7ab6ccb7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc482ada40e5d82; - y = 64'hbec10c5904e0bbb5; - zrf = 64'h0000000000000000; - ans = 64'hbe95daac9db0f037; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f0fffffffffffb; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc023b435d252ab57; - y = 64'hc0efffffffbffffe; - zrf = 64'h0000000000000000; - ans = 64'h4123b435d22b42eb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37ed147aa1f43557; - y = 64'hbed00000003fffc0; - zrf = 64'h0000000000000000; - ans = 64'hb6cd147aa26886cd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h84fffbffffff0000; - zrf = 64'h0000000000000000; - ans = 64'hc51ffbffffff0000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h42a0010000000000; - y = 64'hc8000000001001ff; - zrf = 64'h0000000000000000; - ans = 64'hcab00100001002ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f00000003ffbfe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc67fefff7ffffffe; - y = 64'h3eac1d26eec725e8; - zrf = 64'h0000000000000000; - ans = 64'hc53c0f17eadb2698; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fdff7fffffdfffe; - y = 64'hbe603755dfca2a65; - zrf = 64'h0000000000000000; - ans = 64'hfe5033480a513464; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h41ffffffffbfff7f; - zrf = 64'h0000000000000000; - ans = 64'h021fffffffbfff7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47fc27499562c193; - y = 64'hbfd7fffffffff7ff; - zrf = 64'h0000000000000000; - ans = 64'hc7e51d77300a0a23; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffe000000fffe; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401ffc0000000002; - y = 64'h43cfff800000003e; - zrf = 64'h0000000000000000; - ans = 64'h43fffb8010000040; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43f7ffffffffdfff; - y = 64'hffed3e9e1f93387c; - zrf = 64'h0000000000000000; - ans = 64'h83f5eef697ae4d1d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h403fff8001000000; - zrf = 64'h0000000000000000; - ans = 64'h005fff8001000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fd004000000000f; - y = 64'h37f6cfd4cb442f48; - zrf = 64'h0000000000000000; - ans = 64'h37d6d588c077006a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf80001002000000; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e00000004007fe; - y = 64'hc0036ff67812a280; - zrf = 64'h0000000000000000; - ans = 64'hb7f36ff678606c0f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h8000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h48070394b74ce3a4; - y = 64'h480efc79a696d4b9; - zrf = 64'h0000000000000000; - ans = 64'h502648ef1c54f542; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h8020000037fffffe; - zrf = 64'h0000000000000000; - ans = 64'hc040000037fffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbc3f7fffffffffbf; - y = 64'hbca03ff7ffffffff; - zrf = 64'h0000000000000000; - ans = 64'h38effdf03fffffbd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb677ffffffffeffe; - y = 64'h415ffffffdf7fffe; - zrf = 64'h0000000000000000; - ans = 64'hb7e7fffffe79effc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc0fffffffdfffff6; - zrf = 64'h0000000000000000; - ans = 64'h811ffffffdfffff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffffdffffbff; - y = 64'h3fd00000000003ff; - zrf = 64'h0000000000000000; - ans = 64'hc00fffffe00003fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0300000ffeffffe; - y = 64'h3fffff8000001ffe; - zrf = 64'h0000000000000000; - ans = 64'hc03fff81ffd8207a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hf98fff8007ffffff; - y = 64'h3fe040003fffffff; - zrf = 64'h0000000000000000; - ans = 64'hf9803fbf440f000e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7e80001ffffffff; - y = 64'hbff0000000007ffe; - zrf = 64'h0000000000000000; - ans = 64'h47e800020000bffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d00001000001ff; - y = 64'hb7f60cb3edb38762; - zrf = 64'h0000000000000000; - ans = 64'h3bd60cb54e7ec8fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h546000000004003f; - y = 64'h400663ca353eb4a4; - zrf = 64'h0000000000000000; - ans = 64'h547663ca35444def; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfeffffffffdffff; - y = 64'hc3c800003ffffffe; - zrf = 64'h0000000000000000; - ans = 64'h43c800003ffe7ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3c000000100000f; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h03e000000100000f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c86b97bdb4310f; - y = 64'h2a1104f9c0a750d2; - zrf = 64'h0000000000000000; - ans = 64'h2de9f9e94ff2d4b0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h8010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc030000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfff000000000100; - y = 64'hbff27243af555c1b; - zrf = 64'h0000000000000000; - ans = 64'h4001deb191dab1ce; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hcf10008040000000; - zrf = 64'h0000000000000000; - ans = 64'h8f30008040000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcf800000000000; - y = 64'hbfc000000ffffffd; - zrf = 64'h0000000000000000; - ans = 64'h3f9f80001f7ffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbff0000000020fff; - y = 64'hbecc54fdffa82e36; - zrf = 64'h0000000000000000; - ans = 64'h3ecc54fdffabd529; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h8010000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc030000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1590000080200000; - y = 64'he290003ff7ffffff; - zrf = 64'h0000000000000000; - ans = 64'hb83000407822003e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h48000000040007ff; - zrf = 64'h0000000000000000; - ans = 64'h08200000040007ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h434fffffffff7dfe; - y = 64'h7fe0000000000043; - zrf = 64'h0000000000000000; - ans = 64'h033fffffffff7e84; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h407ffffffff7fff7; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h80affffffff7fff6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47fe3fffffffffff; - y = 64'h3fe12dc9c92e02e4; - zrf = 64'h0000000000000000; - ans = 64'h47f03d48c02d7ebb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h801fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc03fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb810000000003fe0; - y = 64'h9f90000100000008; - zrf = 64'h0000000000000000; - ans = 64'h17b0000100003fe9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h46abd96de2786819; - zrf = 64'h0000000000000000; - ans = 64'h06cbd96de2786819; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h60d92d2aa25c2d87; - y = 64'hbfbffe001fffffff; - zrf = 64'h0000000000000000; - ans = 64'he0a92b97e8df3265; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c0007fffdfffff; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h83f0007fffdffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfd00000407ffffe; - y = 64'hd001000000800000; - zrf = 64'h0000000000000000; - ans = 64'h4fe1000045080000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h801ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc03ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4382a3880af103a1; - y = 64'h801fffffffc08000; - zrf = 64'h0000000000000000; - ans = 64'h83b2a3880acc071f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4017ffffefffffff; - zrf = 64'h0000000000000000; - ans = 64'h0037ffffefffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hefd000800000fffe; - y = 64'h37e34d3325f0bc2f; - zrf = 64'h0000000000000000; - ans = 64'he7c34dcd8f8b2085; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hfcc0000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h413effffffffffff; - y = 64'h3ffffffdfffffffc; - zrf = 64'h0000000000000000; - ans = 64'h414efffe0ffffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc04fff0000007ffe; - zrf = 64'h0000000000000000; - ans = 64'h806fff0000007ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fbf800000000002; - y = 64'hbfb892c300fae7f4; - zrf = 64'h0000000000000000; - ans = 64'hbf883077f4f6fc55; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc7efffffdffffbff; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h449fffffdffffc01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41effffffff00002; - y = 64'hc013ffffe0000000; - zrf = 64'h0000000000000000; - ans = 64'hc213ffffdff60001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hfcc0000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0272f86e7296ddc; - y = 64'hc00fffffe1fffffe; - zrf = 64'h0000000000000000; - ans = 64'h40472f86d16cdf62; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h480ffff000000080; - zrf = 64'h0000000000000000; - ans = 64'h082ffff000000080; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc440000800000003; - y = 64'h402ffffffdfffffd; - zrf = 64'h0000000000000000; - ans = 64'hc4800007feffff81; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41f000000ffffffe; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbeb000000ffffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc21d2b9577b04a48; - y = 64'h3caffffeff7fffff; - zrf = 64'h0000000000000000; - ans = 64'hbedd2b948ddef033; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbcafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hfccfffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h46600000003ffffb; - y = 64'hc7f03ffdfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hce603ffe0040fff0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc11ff00000000003; - zrf = 64'h0000000000000000; - ans = 64'h813ff00000000003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h404ffffffe001fff; - y = 64'h3f183477e56b4fdb; - zrf = 64'h0000000000000000; - ans = 64'h3f783477e3e82091; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fe53580e079043e; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hfca53580e079043c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fcf000000400000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbcaffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hfccffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfbffffffffff7fb; - y = 64'h3f67c662a30b77d9; - zrf = 64'h0000000000000000; - ans = 64'hbf37c662a30b71e3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfff9793a2cfab94; - zrf = 64'h0000000000000000; - ans = 64'h801f9793a2cfab94; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc2a602769741e0f4; - y = 64'h41df7ffffffff800; - zrf = 64'h0000000000000000; - ans = 64'hc495aa6cbce4d3ef; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47f28f0812269bb5; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc7d28f0812269bb5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4171ffffefffffff; - y = 64'hbff0c7c76598ebc1; - zrf = 64'h0000000000000000; - ans = 64'hc172e0c0418441d2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hffefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbcaffffbfffffff7; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc340000000400020; - zrf = 64'h0000000000000000; - ans = 64'h8360000000400020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb81ffffffdffffbf; - y = 64'h4168000000000007; - zrf = 64'h0000000000000000; - ans = 64'hb997fffffe7fffd6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43d2000000000002; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc3b2000000000003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40800041ffffffff; - y = 64'hc3ced81c55396ab6; - zrf = 64'h0000000000000000; - ans = 64'hc45ed89b90ae4a40; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hffefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4003069a0d38953d; - y = 64'h40a077ffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h40b3954b909bbd9c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h43f20ac9374433ed; - zrf = 64'h0000000000000000; - ans = 64'h04120ac9374433ed; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4010618f5a6ec8f0; - y = 64'hc3ddaa7859723ef0; - zrf = 64'h0000000000000000; - ans = 64'hc3fe5f5b9e50707d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0ffffffffeffffe; - y = 64'hbfdfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h40efffffffeffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40100000020fffff; - y = 64'h3530003bffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3550003c021007ba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffefeffffffff; - y = 64'h47f0000040000fff; - zrf = 64'h0000000000000000; - ans = 64'h47fffeff7ffc1bfc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc3e0000100004000; - zrf = 64'h0000000000000000; - ans = 64'h8400000100004000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbee07fffffbffffe; - y = 64'hc008000000000ffe; - zrf = 64'h0000000000000000; - ans = 64'h3ef8bfffffa0107b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffeffffffc002000; - y = 64'hbfdffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h7fdffffffc001fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h441ed7f6a4c867c6; - y = 64'hc00fbffffffbfffe; - zrf = 64'h0000000000000000; - ans = 64'hc43e9a46b77afbf5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc0000000007fef; - y = 64'h1980000002000007; - zrf = 64'h0000000000000000; - ans = 64'h1950000002007ff7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4007810b8f74ac1d; - y = 64'hbfc856fb871d13a1; - zrf = 64'h0000000000000000; - ans = 64'hbfe1e0ac3a197c02; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h5677fffffffeffff; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hd667fffffffeffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h6f7000000001fdff; - y = 64'h1510010000000fff; - zrf = 64'h0000000000000000; - ans = 64'h4490010000020e1e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0000003ffffe000; - y = 64'hbfd1684c1780a28e; - zrf = 64'h0000000000000000; - ans = 64'h3fe168507193859e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h47fff3c7f4f5dd0a; - zrf = 64'h0000000000000000; - ans = 64'h081ff3c7f4f5dd0a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h80204000000ffffe; - y = 64'h381fffffff81fffe; - zrf = 64'h0000000000000000; - ans = 64'hf8503fffffd003fc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h95d00007ffffffff; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h15c0000800000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f0800000008000; - y = 64'h41c00000007ff800; - zrf = 64'h0000000000000000; - ans = 64'h39c08000008477c1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h413ffdffffdffffe; - y = 64'h3fbc6dc2b14b6dd5; - zrf = 64'h0000000000000000; - ans = 64'h410c6bfbd503eb5a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hde70000600000000; - zrf = 64'h0000000000000000; - ans = 64'h9e90000600000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f002000000000f; - y = 64'hb1effcfffffffffe; - zrf = 64'h0000000000000000; - ans = 64'ha9f0007fd000000d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbe4bd57690ea5405; - y = 64'hbfefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h3e4bd57690ea5405; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfcffdffff000000; - y = 64'hb7e44dc0093df58b; - zrf = 64'h0000000000000000; - ans = 64'h37c44c7b2c9af3ac; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40100000083fffff; - y = 64'h3c0dcff9f723ff06; - zrf = 64'h0000000000000000; - ans = 64'h3c2dcffa06833be8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h403ffff800000003; - zrf = 64'h0000000000000000; - ans = 64'h005ffff800000003; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dffc0000000006; - y = 64'h002ffffeffffffff; - zrf = 64'h0000000000000000; - ans = 64'h841ffbff00200005; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca01ffffffffffc; - y = 64'hbf8ffbffe0000000; - zrf = 64'h0000000000000000; - ans = 64'hbc401dfbefdffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43ebffefffffffff; - y = 64'h401fffff80003fff; - zrf = 64'h0000000000000000; - ans = 64'h441bffef900077ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h47f000021fffffff; - zrf = 64'h0000000000000000; - ans = 64'h081000021fffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4040000040200000; - y = 64'hc030003ffffff7ff; - zrf = 64'h0000000000000000; - ans = 64'hc08000404020f87e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hcc3050bc013d7cd7; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h4c3050bc013d7cd7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca371e443fc6409; - y = 64'hc3f0000004000003; - zrf = 64'h0000000000000000; - ans = 64'h40a371e448d8dd1e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8010000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3cd49ee0d5dc5dad; - y = 64'h5dd2718355e26898; - zrf = 64'h0000000000000000; - ans = 64'h5ab7c50847fefa19; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h46603fffe0000000; - zrf = 64'h0000000000000000; - ans = 64'h06803fffe0000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dffffffffffffe; - y = 64'h802fffffc8000000; - zrf = 64'h0000000000000000; - ans = 64'h041fffffc7ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h401fff7dffffffff; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc01fff7e00000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3e00000400003ff; - y = 64'hc041cb2ba6fa7627; - zrf = 64'h0000000000000000; - ans = 64'h4431cb2bee272935; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbff0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8010000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1d0003ff8000000; - y = 64'hf9f000000010003f; - zrf = 64'h0000000000000000; - ans = 64'h7bd0003ff810007f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h87fff0000000fffe; - zrf = 64'h0000000000000000; - ans = 64'hc81ff0000000fffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h308fffffffffffe7; - y = 64'hbc4fffffffefffbf; - zrf = 64'h0000000000000000; - ans = 64'hacefffffffefffa6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43c0003ffffffffc; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3d0003ffffffffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc030007ffffefffe; - y = 64'h37f1c5927efed20d; - zrf = 64'h0000000000000000; - ans = 64'hb831c620ab91ada8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbfffffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h801fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'h3111ffffffffbfff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h43c8000000ffffff; - zrf = 64'h0000000000000000; - ans = 64'h03e8000000ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffe84f73fb8db6fe; - y = 64'hbc1fffffc0000000; - zrf = 64'h0000000000000000; - ans = 64'h7c184f73caeecf07; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47e0000000010080; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc7f000000001007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc04fffffbffffffb; - y = 64'h3c7f7ffffffffdfe; - zrf = 64'h0000000000000000; - ans = 64'hbcdf7fffc0fffdf9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hbffffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h801ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37f000003fffffde; - y = 64'hc3400000000ffe00; - zrf = 64'h0000000000000000; - ans = 64'hbb400000400ffdde; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc3fb5c5330475c41; - zrf = 64'h0000000000000000; - ans = 64'h841b5c5330475c41; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h472dfffffeffffff; - y = 64'hc3448df0813db0ec; - zrf = 64'h0000000000000000; - ans = 64'hca83451178856658; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca36b7814b2d456; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'hbcb36b7814b2d456; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha4ffffefdfffffff; - y = 64'hc3e0020000000fff; - zrf = 64'h0000000000000000; - ans = 64'h28f001f7eefe0fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8020000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3feffffffffffbdf; - y = 64'hbff0077965f9c355; - zrf = 64'h0000000000000000; - ans = 64'hbff0077965f9c143; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc11ffff7fff7ffff; - y = 64'hc1adeb3cfb8c4374; - zrf = 64'h0000000000000000; - ans = 64'h42ddeb3580b589c1; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7feefffe00000000; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'hffefffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43effbfffffff7ff; - y = 64'h7fefffffff801ffe; - zrf = 64'h0000000000000000; - ans = 64'h03effbffff8027fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc000000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8020000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h32100007efffffff; - y = 64'hc78ffffff0000007; - zrf = 64'h0000000000000000; - ans = 64'hb9b00007e7fffc0a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hb7efffffbffff7fe; - zrf = 64'h0000000000000000; - ans = 64'hf80fffffbffff7fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbce98537abc2f82a; - y = 64'h41e00003ffdffffe; - zrf = 64'h0000000000000000; - ans = 64'hbed9853e0cddd8a8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffefffeffffdffff; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f8007ffffffffff; - y = 64'hc3f000401fffffff; - zrf = 64'h0000000000000000; - ans = 64'hc3800840400ffffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc00fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h802fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d4f4adbfb6a5ea; - y = 64'h3e700000000000c0; - zrf = 64'h0000000000000000; - ans = 64'hc254f4adbfb6a6e5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h408000000010ffff; - zrf = 64'h0000000000000000; - ans = 64'h00a000000010ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc015834380f2b995; - y = 64'h3f9fff0000000400; - zrf = 64'h0000000000000000; - ans = 64'hbfc5829766d6b4af; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3faffeffffffc000; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hbfcffeffffffbffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3effffffffffef7; - y = 64'hbf40445cd52bc22b; - zrf = 64'h0000000000000000; - ans = 64'h4340445cd52bc1a5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc00ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h802ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc340004000007fff; - y = 64'h4070004000000400; - zrf = 64'h0000000000000000; - ans = 64'hc3c0008001008401; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'he0d20000000003ff; - y = 64'hc34000002ffffffe; - zrf = 64'h0000000000000000; - ans = 64'h64220000360003fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h38185f449f6bf14d; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'hb8385f449f6bf14d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc341fffffffffffc; - y = 64'hbec000003ffbffff; - zrf = 64'h0000000000000000; - ans = 64'h4212000047fb7ffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8030000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc23fff7ffffffbff; - y = 64'hc8710000000000ff; - zrf = 64'h0000000000000000; - ans = 64'h4ac0ffbbfffffedf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h41dfffffc0001000; - zrf = 64'h0000000000000000; - ans = 64'h01ffffffc0001000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc8000003fffffff6; - y = 64'h7fdffffffff7dffe; - zrf = 64'h0000000000000000; - ans = 64'h87f00003fffbeff3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h32d3e44c3072f211; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'hb2f3e44c3072f212; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3efffdffeffffff; - y = 64'hc22fffffffffefbf; - zrf = 64'h0000000000000000; - ans = 64'h462fffdffeffefbf; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc010000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8030000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40700200000001fe; - y = 64'hbdffffffe0000040; - zrf = 64'h0000000000000000; - ans = 64'hbe8001ffeffe021e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h802ffbffc0000000; - zrf = 64'h0000000000000000; - ans = 64'hc04ffbffc0000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3c6fbfffffdfffff; - y = 64'h40300000009fffff; - zrf = 64'h0000000000000000; - ans = 64'h3cafc000011d7ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001000003fffffff; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h804000003ffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb80002000000007f; - y = 64'hc7e000000007fbfe; - zrf = 64'h0000000000000000; - ans = 64'h3ff002000007fd7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc01fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h803fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0204000000fffff; - y = 64'h406ffffffefffdfe; - zrf = 64'h0000000000000000; - ans = 64'hc0a03fffff8dfef9; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4809f4b95e8684c3; - y = 64'hb5a0000000000380; - zrf = 64'h0000000000000000; - ans = 64'hbdb9f4b95e868a70; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f0020000001000; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4220020000000fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc58fff8000010000; - y = 64'h3ff000080000007f; - zrf = 64'h0000000000000000; - ans = 64'hc58fff8fffc100fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc01ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h803ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfefdfbffffffffe; - y = 64'h3fb0101fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hbfafffdf7f7ffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7fdffffbfbfffffe; - zrf = 64'h0000000000000000; - ans = 64'h3ffffffbfbfffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3caffffffc00000e; - y = 64'hffefffffffe0007f; - zrf = 64'h0000000000000000; - ans = 64'hfcaffffffbe0008d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc34e3db1b794999c; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h469e3db1b794999c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e010000000001f; - y = 64'hc5b04000000fffff; - zrf = 64'h0000000000000000; - ans = 64'hc7a050400010101e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc340000000000000; - zrf = 64'h0000000000000000; - ans = 64'h8360000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fd00000001fffff; - y = 64'hc1c0010000000000; - zrf = 64'h0000000000000000; - ans = 64'h81a00100002001fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41e43c7afaf93429; - y = 64'hc3dffff8000ffffe; - zrf = 64'h0000000000000000; - ans = 64'hc5d43c75ebe493a6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h1d60000000000000; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'ha0b0000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfe0000007fffffb; - y = 64'hb7e000000000200e; - zrf = 64'h0000000000000000; - ans = 64'h37d000000800200a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc340000000000001; - zrf = 64'h0000000000000000; - ans = 64'h8360000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4c6000000ffffe00; - y = 64'hb4cfbffff7fffffe; - zrf = 64'h0000000000000000; - ans = 64'hc13fc00017bffbfe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3b40018000000000; - y = 64'h3ea0400000000100; - zrf = 64'h0000000000000000; - ans = 64'h39f0418600000101; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41cf871987a4786c; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc52f871987a4786b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4261d11be1f2a3c5; - y = 64'h3caf800000000080; - zrf = 64'h0000000000000000; - ans = 64'h3f2189d7726ad97e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc34fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h836fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'ha6d00ffffc000000; - y = 64'hc1e0002080000000; - zrf = 64'h0000000000000000; - ans = 64'h28c010209c7ff7e0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc770000000001c00; - y = 64'h450fffebfffffffe; - zrf = 64'h0000000000000000; - ans = 64'hcc8fffec000037fd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc000000100002000; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h4360000100001fff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43dfffff40000000; - y = 64'h3c700000003fffff; - zrf = 64'h0000000000000000; - ans = 64'h405fffff407ffffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc34ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h836ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc504000080000000; - y = 64'hc030000200400000; - zrf = 64'h0000000000000000; - ans = 64'h4544000300501002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h4cdffeffff7fffff; - zrf = 64'h0000000000000000; - ans = 64'h0cfffeffff7fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3dff8000000007e; - y = 64'h3fd0008000000002; - zrf = 64'h0000000000000000; - ans = 64'hc3bff8ffc0000082; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc80e00000000001f; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h07fe00000000001f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4038c1f6b59a2712; - y = 64'hc1effe0000000ffe; - zrf = 64'h0000000000000000; - ans = 64'hc238c06a962ed9ce; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffe0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3f0fffffdfffffdf; - y = 64'hc2a0000000000402; - zrf = 64'h0000000000000000; - ans = 64'hc1bfffffe00007e2; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7fd007fbffffffff; - y = 64'h400bfffffffefffe; - zrf = 64'h0000000000000000; - ans = 64'h7fec0df8fffeff7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h402fc000000007ff; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'h801fc00000000800; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400c000003fffffe; - y = 64'h43c0000000020002; - zrf = 64'h0000000000000000; - ans = 64'h43dc000004038002; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffe0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc000000000000001; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h16dff0001ffffffe; - y = 64'h3fb500ae0796659d; - zrf = 64'h0000000000000000; - ans = 64'h16a4f62dc5934871; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7fdfffffdf800000; - zrf = 64'h0000000000000000; - ans = 64'h3fffffffdf800000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40111e45b8b5ab55; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h80111e45b8b5ab54; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hba0007fffffeffff; - y = 64'h3ca0000008000200; - zrf = 64'h0000000000000000; - ans = 64'hb6b00800080301ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffefffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc00fffffffffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1dfc7ffffffffff; - y = 64'hc3cff00000000fff; - zrf = 64'h0000000000000000; - ans = 64'h45bfb81c00000fe3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h47ffffffffffdff0; - y = 64'h3f9fdffffffffbff; - zrf = 64'h0000000000000000; - ans = 64'h47afdfffffffdc10; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1fffffe000001ff; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h01fffffe000001fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hba6fffffbf7fffff; - y = 64'hc00fffffbdffffff; - zrf = 64'h0000000000000000; - ans = 64'h3a8fffff7d800084; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hffeffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc00ffffffffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7e003ffffffff7f; - y = 64'hdeafffffeffffffd; - zrf = 64'h0000000000000000; - ans = 64'h56a003fff7fdff7e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h03efffffffffff04; - y = 64'h3dafff7ffffffffa; - zrf = 64'h0000000000000000; - ans = 64'h01afff7ffffffeff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h381ff000000000ff; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hf81ff000000000ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43fe000000004000; - y = 64'h3fdfffc000000400; - zrf = 64'h0000000000000000; - ans = 64'h43edffc4000043c0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hfff0000000000000; - zrf = 64'h0000000000000000; - ans = 64'hc010000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h378b1c4beaf19830; - y = 64'hc1d00000000081ff; - zrf = 64'h0000000000000000; - ans = 64'hb96b1c4beaf27474; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbf8e00000000000e; - y = 64'h342fffffffc01fff; - zrf = 64'h0000000000000000; - ans = 64'hb3cdffffffc41e0d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7febdc9a99e7a82d; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d003fffffffffb; - y = 64'h47effffff0000001; - zrf = 64'h0000000000000000; - ans = 64'hcbd003fff7fdfffb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h406000001fffbfff; - y = 64'h3f20020000080000; - zrf = 64'h0000000000000000; - ans = 64'h3f900200200bbff8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'hc0f01fff00000000; - zrf = 64'h0000000000000000; - ans = 64'h81101fff00000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001fffefffffefff; - y = 64'h40ac0001fffffffe; - zrf = 64'h0000000000000000; - ans = 64'h00dbfff3fffef1fe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7ffffffff80000f; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h40fffe000001fffe; - y = 64'hc28ffffeffffff7f; - zrf = 64'h0000000000000000; - ans = 64'hc39ffdff0011ff7c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1f010e938b5ded1; - y = 64'h400dfffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc20e1fb54a5501c5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h415ffffffffffe1f; - y = 64'hd96f7f7fffffffff; - zrf = 64'h0000000000000000; - ans = 64'hdadf7f7ffffffe25; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hef00000ffffc0000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h7ffc000000000000; - y = 64'hbab0002007ffffff; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000000; - y = 64'h7ffc000000000000; - zrf = 64'h0000000000000000; - ans = 64'h7ff8000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3eefffffffffffed; - y = 64'h43efe8e5002721cc; - zrf = 64'h0000000000000000; - ans = 64'h42efe8e5002721ba; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h51f00008003ffffe; - y = 64'hc470040000000001; - zrf = 64'h0000000000000000; - ans = 64'hd670040802400ffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ca0020000000000; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h41d0040040000000; - y = 64'hbe4ffffffffbffef; - zrf = 64'h0000000000000000; - ans = 64'hc03004003ffdff77; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'h0000000000000000; - zrf = 64'h0000000000000000; - ans = 64'h0000000000000000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1ca0de3d0d15dd1; - y = 64'h3fffffffe03ffffe; - zrf = 64'h0000000000000000; - ans = 64'hc1da0de3b6f795c6; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'hb8d09a33206c9699; - zrf = 64'h0000000000000000; - ans = 64'hf8f09a33206c969a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4340800000000020; - y = 64'h3f5fec0000000000; - zrf = 64'h0000000000000000; - ans = 64'h42b075b000000020; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdffff800100000; - y = 64'h10dfffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h90cffff8000fffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h439fbffffffbffff; - y = 64'hbf8454fd38ef0ba0; - zrf = 64'h0000000000000000; - ans = 64'hc3342c533e7aa2e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfdf7fffffffffbe; - y = 64'hc3f8cd30846286fc; - zrf = 64'h0000000000000000; - ans = 64'h43e869fbc250fcad; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc010102396a7802c; - y = 64'hc0200000000007bf; - zrf = 64'h0000000000000000; - ans = 64'h4040102396a787f3; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0258dbcf58dfc04; - y = 64'h3da000000001007f; - zrf = 64'h0000000000000000; - ans = 64'hbdd58dbcf58f558a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'h43400000000001f8; - zrf = 64'h0000000000000000; - ans = 64'h03600000000001fa; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43e000000009ffff; - y = 64'h407059db2c4f6829; - zrf = 64'h0000000000000000; - ans = 64'h446059db2c59a051; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbca5daf2cc8924e1; - y = 64'hc03000007ffffefe; - zrf = 64'h0000000000000000; - ans = 64'h3ce5daf37b60b9e5; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfc000000000043f; - y = 64'hc2c084efd4d351ba; - zrf = 64'h0000000000000000; - ans = 64'h429084efd4d3561d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hdc1fffffffffffaf; - y = 64'hc34ffffffdffc000; - zrf = 64'h0000000000000000; - ans = 64'h5f7ffffffdffbfb0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h418effffffffff7f; - y = 64'h0010000000000000; - zrf = 64'h0000000000000000; - ans = 64'h01aeffffffffff7f; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1c000000200007e; - y = 64'hbf000001ffffffbf; - zrf = 64'h0000000000000000; - ans = 64'h40d000020200007e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hae31fbffffffffff; - y = 64'h1801c2793142b19f; - zrf = 64'h0000000000000000; - ans = 64'h8643f657b91eb725; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'h403fffffffffc1ff; - zrf = 64'h0000000000000000; - ans = 64'h005fffffffffc201; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd0000fffdfffff; - y = 64'hbb5fffffff81ffff; - zrf = 64'h0000000000000000; - ans = 64'h7b40000fffa0ffc0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h2c8000080000ffff; - y = 64'hf0000000010001ff; - zrf = 64'h0000000000000000; - ans = 64'hdc9000080101027e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e7ff7fffffffff; - y = 64'h43ff8acf4be4e380; - zrf = 64'h0000000000000000; - ans = 64'h3bf7a79d4dae7b0c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3cfffffffefe000; - y = 64'h37efff0001fffffe; - zrf = 64'h0000000000000000; - ans = 64'hbbcfff0001efe07e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffd7ad4237371282; - y = 64'h001fffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hc007ad4237371281; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h001e6a23746179de; - y = 64'h4b3fffffbfffffe0; - zrf = 64'h0000000000000000; - ans = 64'h0b6e6a23378d32d7; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc1a0000080fffffe; - y = 64'hc00feffbfffffffe; - zrf = 64'h0000000000000000; - ans = 64'h41bfeffd017edfbb; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h480000000008fffe; - y = 64'h001637e790e69de2; - zrf = 64'h0000000000000000; - ans = 64'h082637e790f31d52; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3400ffffffefffe; - y = 64'h001ffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h83700ffffffefffc; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc050000003ffdfff; - y = 64'h3fc000009ffffffe; - zrf = 64'h0000000000000000; - ans = 64'hc0200000a3ffe024; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc02fffffffffffff; - y = 64'h4030000000080000; - zrf = 64'h0000000000000000; - ans = 64'hc07000000007ffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb7effef800000000; - y = 64'h47efff7ffffeffff; - zrf = 64'h0000000000000000; - ans = 64'hbfeffe78041f0007; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h400fffffc3ffffff; - y = 64'h3ca0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3cbfffffc3ffffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfefb80000000000; - y = 64'hbfd9c346f3f0115d; - zrf = 64'h0000000000000000; - ans = 64'h3fd9894f944b3536; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbfb007fffffffbfe; - y = 64'h3fffff0000000007; - zrf = 64'h0000000000000000; - ans = 64'hbfc0077fbffffc01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'h7fe8764cdc1ba128; - zrf = 64'h0000000000000000; - ans = 64'h4008764cdc1ba12a; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h419ffffffdfdffff; - y = 64'hc01fffffffff0000; - zrf = 64'h0000000000000000; - ans = 64'hc1cffffffdfcffff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hbffffffc000003fe; - y = 64'h3ca0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hbcaffffc000003ff; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3ffffffbffe00000; - y = 64'h402ffffbfefffffe; - zrf = 64'h0000000000000000; - ans = 64'h403ffff7fee08023; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hd1bfffffffffffff; - y = 64'h4373dd6bcb6fc58e; - zrf = 64'h0000000000000000; - ans = 64'hd543dd6bcb6fc58d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hb8cfffffffbefffe; - y = 64'h3cafffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'hb58fffffffbefffd; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc0a684d24f5ca22b; - y = 64'hc34ffffeffffffff; - zrf = 64'h0000000000000000; - ans = 64'h440684d19b360fb0; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h37e2e713ec3308f4; - y = 64'h4010000000001fdf; - zrf = 64'h0000000000000000; - ans = 64'h3802e713ec332e9c; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fffff80000001ff; - y = 64'hbffffc0000000040; - zrf = 64'h0000000000000000; - ans = 64'hc00ffb801000023e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43cffdff7fffffff; - y = 64'h3caffffffffffffe; - zrf = 64'h0000000000000000; - ans = 64'h408ffdff7ffffffe; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4014daa7249b383d; - y = 64'hc804080000000000; - zrf = 64'h0000000000000000; - ans = 64'hc82a1bbe415453e8; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h43cffc00000000fe; - y = 64'h43c1ffffffffffff; - zrf = 64'h0000000000000000; - ans = 64'h47a1fdc00000008e; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h6b4848a9a8c0dcd5; - y = 64'h480ffffffffbdfff; - zrf = 64'h0000000000000000; - ans = 64'h736848a9a8bdbb77; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h3fc9e8c6d2ecf933; - y = 64'h3fd0000000000000; - zrf = 64'h0000000000000000; - ans = 64'h3fa9e8c6d2ecf933; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h4037ab91bff33a68; - y = 64'h3dbfdffffffffff7; - zrf = 64'h0000000000000000; - ans = 64'h3e0793e62e334727; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hffeffffffffbfefe; - y = 64'h3c503ffffeffffff; - zrf = 64'h0000000000000000; - ans = 64'hfc503ffffefdf77b; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'h0010000000000001; - y = 64'h400fffffffff7bff; - zrf = 64'h0000000000000000; - ans = 64'h002fffffffff7c01; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc92bffffffffff7e; - y = 64'h3cc00007fffe0000; - zrf = 64'h0000000000000000; - ans = 64'hc5fc000dfffc7f7d; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); xrf = 64'hc3d00000201fffff; - y = 64'h3fd0000000000001; - zrf = 64'h0000000000000000; - ans = 64'hc3b0000020200000; - rn = 1; - rz = 0; - rm = 0; - rp = 0; - earlyres = 64'b0; - earlyressel = 0; - bypsel= 2'b0; - bypplus1 = 0; - byppostnorm = 0; -#10 - $fwrite(fp, "%h %h %h %h ",xrf,y,w, ans); - if(w != ans) $fwrite(fp, " Wrong"); - $fwrite(fp,"\n"); $stop; - end -endmodule \ No newline at end of file diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tbgen b/wally-pipelined/src/fpu/FMA/tbgen/tbgen deleted file mode 100755 index 9006e592e..000000000 Binary files a/wally-pipelined/src/fpu/FMA/tbgen/tbgen and /dev/null differ diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tbhead.v b/wally-pipelined/src/fpu/FMA/tbgen/tbhead.v deleted file mode 100644 index 6aa89e3b5..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/tbhead.v +++ /dev/null @@ -1,69 +0,0 @@ -`timescale 1 ns/10 ps -module tb; - - - reg [63:0] FInput1E; - reg [63:0] FInput2E; - reg [63:0] FInput3E; - reg [63:0] ans; - wire [2:0] FrmE; - wire [63:0] FmaResultM; - wire [4:0] FmaFlagsM; - reg [4:0] flags; - wire FmtE; - - wire [12:0] aligncntE; // status flags - wire [105:0] ProdManE; // other result of partial products - wire [161:0] AlignedAddendE; // wire of alignment shifter - wire [8:0] normcntE; // shift count for normalizer - wire [12:0] ProdExpE; // multiplier expoent - wire AddendStickyE; // sticky bit of addend - wire KillProdE; // FInput3E >> product - wire prodofE; // FInput1E*FInput2E out of range - wire XZeroE; - wire YZeroE; - wire ZZeroE; - wire XDenormE; - wire YDenormE; - wire ZDenormE; - wire XInfE; - wire YInfE; - wire ZInfE; - wire XNaNE; - wire YNaNE; - wire ZNaNE; - wire nanE; - wire [8:0] sumshiftE; - wire sumshiftzeroE; - wire prodinfE; - -integer fp; -reg wnan; -reg xnan; -reg ynan; -reg znan; -reg ansnan; -reg [105:0] s; // partial product 2 -reg [51:0] xnorm; -reg [51:0] ynorm; -wire [2:0] FOpCtrlE; -assign FOpCtrlE = 3'b0; -// nearest even - 000 -// twords zero - 001 -// down - 010 -// up - 011 -// nearest max mag - 100 -assign FrmE = 3'b000; -assign FmtE = 1'b1; - - -localparam period = 20; -fma1 UUT1(.*); -fma2 UUT2(.FInput1M(FInput1E), .FInput2M(FInput2E), .FInput3M(FInput3E), .FrmM(FrmE), .ProdManM(ProdManE), - .AlignedAddendM(AlignedAddendE), .ProdExpM(ProdExpE), .AddendStickyM(AddendStickyE),.KillProdM(KillProdE), .FOpCtrlM(FOpCtrlE), - .XZeroM(XZeroE),.YZeroM(YZeroE),.ZZeroM(ZZeroE),.XInfM(XInfE),.YInfM(YInfE),.ZInfM(ZInfE),.XNaNM(XNaNE),.YNaNM(YNaNE),.ZNaNM(ZNaNE), .FmtM(FmtE), .*); - - -initial - begin - fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w"); diff --git a/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh b/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh deleted file mode 100755 index 5f12e143c..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh +++ /dev/null @@ -1,3 +0,0 @@ -testfloat_gen f32_mulAdd -tininessafter -n 6133248 -rmax -seed 113355 -level 1 > testFloat -tr -d ' ' < testFloat > testFloatNoSpace - diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk b/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk deleted file mode 100755 index 3675cab5a..000000000 --- a/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk +++ /dev/null @@ -1 +0,0 @@ -awk 'BEGIN {FS = " "; OFS = "_"} {if ($3 == "0000000000000000") print $1, $2, $4;}' testFloat | head -n 1000 > testMini \ No newline at end of file diff --git a/wally-pipelined/src/fpu/build_temp/fcsr.sv b/wally-pipelined/src/fpu/build_temp/fcsr.sv deleted file mode 100644 index 64f3f7b92..000000000 --- a/wally-pipelined/src/fpu/build_temp/fcsr.sv +++ /dev/null @@ -1,29 +0,0 @@ -`include "../../config/rv64icfd/wally-config.vh" - -module fcsr( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic write, - input logic [4:0] flags, - output logic [31:0] readData); - - //register I/O assignment - logic [31:0] regInput; - logic [31:0] regOutput; - - //no L instruction support - //only last 8 bits used for FCSR - - //latching input to write signal - //AND clk and write and remove latch - //for clk-based write - assign regInput = (write) ? {24'h0,frm,flags} : regInput; - - floprc #(32) (.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput)); - - assign readData = regOutput; - - -endmodule diff --git a/wally-pipelined/src/fpu/build_temp/fctrl.sv b/wally-pipelined/src/fpu/build_temp/fctrl.sv deleted file mode 100644 index 13451165d..000000000 --- a/wally-pipelined/src/fpu/build_temp/fctrl.sv +++ /dev/null @@ -1,143 +0,0 @@ -`include "../../config/rv64icfd/wally-config.vh" - -module fctrl ( - input logic [6:0] Funct7D, - input logic [6:0] OpD, - input logic [4:0] Rs2D, - input logic [4:0] Rs1D, - input logic [2:0] FrmW, - output logic WriteEnD, - output logic DivSqrtStartD, - output logic [2:0] regSelD, - output logic [2:0] writeSelD, - output logic [3:0] OpCtrlD, - output logic FmtD, - output logic WriteIntD); - - - - //precision is taken directly from instruction - assign FmtD = Funct7D[0]; - - //all subsequent logic is based on the table present - //in Section 5 of Wally Architecture Specification - - //write is enabled for all fp instruciton op codes - //sans fp load - logic isFP, isFPLD; - always_comb begin - //case statement is easier to modify - //in case of errors - case(OpD) - //fp instructions sans load - 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1000011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1000111 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1001011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1001111 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b0100111 : begin isFP = 1'b1; isFPLD = 1'b0; end - //fp load - 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b1; end - default : begin isFP = 1'b0; isFPLD = 1'b0; end - endcase - end - - assign WriteEnD = isFP & ~isFPLD; - - //useful intermediary signals - // - //(mult only not supported in current datapath) - //set third FMA operand to zero in this case - //(or equivalent) - logic isAddSub, isFMA, isMult, isDivSqrt, isCvt, isCmp, isFPSTR; - - always_comb begin - //checks all but FMA/store/load - if(OpD == 7'b1010011) begin - case(Funct7D) - //compare - 7'b10100?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b1; isFPSTR = 1'b0; end - //div/sqrt - 7'b0?011?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b1; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //add/sub - 7'b0000??? : begin isAddSub = 1'b1; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //mult - 7'b00010?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b1; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //convert (not precision) - 7'b110?0?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end - //convert (precision) - 7'b010000? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end - endcase - end - //FMA/store/load - else begin - case(OpD) - //4 FMA instructions - 7'b1000011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1000111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1001011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1001111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //store (load already found) - 7'b0100111 : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b1; end - endcase - end - end - - //register is chosen based on operation performed - //---- - //write selection is chosen in the same way as - //register selection - // - - // reg/write sel logic and assignment - // - // 3'b000 = add/sub/cvt - // 3'b001 = sign - // 3'b010 = fma - // 3'b011 = cmp - // 3'b100 = div/sqrt - // - //reg select - - //this value is used enough to be shorthand - logic isSign; - assign isSign = ~Funct7D[6] & ~Funct7D[5] & Funct7D[4] & ~Funct7D[3] & ~Funct7D[2]; - - - assign regSelD[2] = isDivSqrt & ~isFMA; - assign regSelD[1] = isFMA | isCmp; - //AND of Funct7 for sign - assign regSelD[0] = isCmp | isSign; - - //write select - assign writeSelD[2] = isDivSqrt & ~isFMA; - assign writeSelD[1] = isFMA | isCmp; - //AND of Funct7 for sign - assign writeSelD[0] = isCmp | isSign; - - //if op is div/sqrt - start div/sqrt - assign DivSqrtStartD = isDivSqrt & ~isFMA; - - //operation control for each fp operation - //has to be expanded over standard to account for - //integrated fpadd/cvt - // - //will integrate FMA opcodes into design later - // - //conversion instructions will - //also need to be added later as I find the opcode - //version I used for this repo - - assign OpCtrlD[3] = 1'b0; - //if is positive sign injection OR is precision convert - assign OpCtrlD[2] = (isSign & ~FrmW[0]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); - //if is precision convert OR is sign xor - assign OpCtrlD[1] = (isSign & FrmW[1]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); - //if is sqrt OR is sub OR is single-precision cmp OR negation - assign OpCtrlD[0] = (isDivSqrt & ~isFMA & Funct7D[6]) | (isAddSub & ~isFMA & Funct7D[2]) | (isCmp & ~isFMA & Funct7D[0]) | (isSign & FrmW[0]); - - //write to integer source if conv to int occurs - //AND of Funct7 for int results - assign WriteIntD = isCvt & (Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); - -endmodule diff --git a/wally-pipelined/src/fpu/build_temp/fputop.sv b/wally-pipelined/src/fpu/build_temp/fputop.sv deleted file mode 100644 index 3b29e4da5..000000000 --- a/wally-pipelined/src/fpu/build_temp/fputop.sv +++ /dev/null @@ -1,65 +0,0 @@ -`include "../../config/rv64icfd/wally-config.vh" - -module fputop ( - input logic [2:0] FrmW, - input logic reset, - input logic clear, - input logic clk, - input logic [31:0] InstrD, - input logic [`XLEN-1:0] SrcAE, - input logic [`XLEN-1:0] SrcAW, - output logic [31:0] FSROutW, - output logic DivSqrtDoneE, - output logic FInvalInstrD, - output logic [`XLEN-1:0] FPUResultW); - - /*fctrl (); - - //regfile instantiation and decode stage - - //write signal mux - - //address signal mux - - //parallel floating-point registers are - //used for modularity and future performance - //comparisons between operation sets - freg1adr (); - - freg2adr (); - - freg2adr (); - - freg2adr (); - - freg3adr (); - - //can easily be merged into privledged core - //if necessary - fcsr (); - - //E pipe and execution stage - - fpdivsqrt (); - - fma1 (); - - fpaddcvt1 (); - - fpcmp1 (); - - fpsign (); - - //M pipe and memory stage - - fma2 (); - - fpaddcvt2 (); - - fpcmp2 (); - - //W pipe and writeback stage - - //flag signal mux -*/ -endmodule diff --git a/wally-pipelined/src/fpu/build_temp/freg.sv b/wally-pipelined/src/fpu/build_temp/freg.sv deleted file mode 100644 index 282610869..000000000 --- a/wally-pipelined/src/fpu/build_temp/freg.sv +++ /dev/null @@ -1,513 +0,0 @@ -`include "../../config/rv64icfd/wally-config.vh" - -module freg1adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //this could be done with: - // - //assign readData = regOutput[adr1]; - // - //but always_comb allows for finer control - - - //address decoder - //only 1 for this fp register set - //used with fpsign - //defaults to outputting zeroes - always_comb begin - case(adr1) - 5'b00000 : readData = regOutput[0]; - 5'b00001 : readData = regOutput[1]; - 5'b00010 : readData = regOutput[2]; - 5'b00011 : readData = regOutput[3]; - 5'b00100 : readData = regOutput[4]; - 5'b00101 : readData = regOutput[5]; - 5'b00110 : readData = regOutput[6]; - 5'b00111 : readData = regOutput[7]; - 5'b01000 : readData = regOutput[8]; - 5'b01001 : readData = regOutput[9]; - 5'b01010 : readData = regOutput[10]; - 5'b01011 : readData = regOutput[11]; - 5'b01100 : readData = regOutput[12]; - 5'b01101 : readData = regOutput[13]; - 5'b01110 : readData = regOutput[14]; - 5'b01111 : readData = regOutput[15]; - 5'b10000 : readData = regOutput[16]; - 5'b10001 : readData = regOutput[17]; - 5'b10010 : readData = regOutput[18]; - 5'b10011 : readData = regOutput[19]; - 5'b10100 : readData = regOutput[20]; - 5'b10101 : readData = regOutput[21]; - 5'b10110 : readData = regOutput[22]; - 5'b10111 : readData = regOutput[23]; - 5'b11000 : readData = regOutput[24]; - 5'b11001 : readData = regOutput[25]; - 5'b11010 : readData = regOutput[26]; - 5'b11011 : readData = regOutput[27]; - 5'b11100 : readData = regOutput[28]; - 5'b11101 : readData = regOutput[29]; - 5'b11110 : readData = regOutput[30]; - 5'b11111 : readData = regOutput[31]; - default : readData = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01000 : regInput[9] = writeData; - 5'b01001 : regInput[10] = writeData; - 5'b01010 : regInput[11] = writeData; - 5'b01111 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11000 : regInput[25] = writeData; - 5'b11001 : regInput[26] = writeData; - 5'b11010 : regInput[27] = writeData; - 5'b11111 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//******** -//formatting separation -//******** -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -module freg2adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [4:0] adr2, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData1, - output logic [`XLEN-1:0] readData2); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //address decoder - //2 are used for this fp register set - //used with fpadd/cvt, fpdiv/sqrt, and fpcmp - //defaults to outputting zeroes - always_comb begin - - //adderss 1 decoder - case(adr1) - 5'b00000 : readData1 = regOutput[0]; - 5'b00001 : readData1 = regOutput[1]; - 5'b00010 : readData1 = regOutput[2]; - 5'b00011 : readData1 = regOutput[3]; - 5'b00100 : readData1 = regOutput[4]; - 5'b00101 : readData1 = regOutput[5]; - 5'b00110 : readData1 = regOutput[6]; - 5'b00111 : readData1 = regOutput[7]; - 5'b01000 : readData1 = regOutput[8]; - 5'b01001 : readData1 = regOutput[9]; - 5'b01010 : readData1 = regOutput[10]; - 5'b01011 : readData1 = regOutput[11]; - 5'b01100 : readData1 = regOutput[12]; - 5'b01101 : readData1 = regOutput[13]; - 5'b01110 : readData1 = regOutput[14]; - 5'b01111 : readData1 = regOutput[15]; - 5'b10000 : readData1 = regOutput[16]; - 5'b10001 : readData1 = regOutput[17]; - 5'b10010 : readData1 = regOutput[18]; - 5'b10011 : readData1 = regOutput[19]; - 5'b10100 : readData1 = regOutput[20]; - 5'b10101 : readData1 = regOutput[21]; - 5'b10110 : readData1 = regOutput[22]; - 5'b10111 : readData1 = regOutput[23]; - 5'b11000 : readData1 = regOutput[24]; - 5'b11001 : readData1 = regOutput[25]; - 5'b11010 : readData1 = regOutput[26]; - 5'b11011 : readData1 = regOutput[27]; - 5'b11100 : readData1 = regOutput[28]; - 5'b11101 : readData1 = regOutput[29]; - 5'b11110 : readData1 = regOutput[30]; - 5'b11111 : readData1 = regOutput[31]; - default : readData1 = `XLEN'h0; - endcase - - //address 2 decoder - case(adr2) - 5'b00000 : readData2 = regOutput[0]; - 5'b00001 : readData2 = regOutput[1]; - 5'b00010 : readData2 = regOutput[2]; - 5'b00011 : readData2 = regOutput[3]; - 5'b00100 : readData2 = regOutput[4]; - 5'b00101 : readData2 = regOutput[5]; - 5'b00110 : readData2 = regOutput[6]; - 5'b00111 : readData2 = regOutput[7]; - 5'b01000 : readData2 = regOutput[8]; - 5'b01001 : readData2 = regOutput[9]; - 5'b01010 : readData2 = regOutput[10]; - 5'b01011 : readData2 = regOutput[11]; - 5'b01100 : readData2 = regOutput[12]; - 5'b01101 : readData2 = regOutput[13]; - 5'b01110 : readData2 = regOutput[14]; - 5'b01111 : readData2 = regOutput[15]; - 5'b10000 : readData2 = regOutput[16]; - 5'b10001 : readData2 = regOutput[17]; - 5'b10010 : readData2 = regOutput[18]; - 5'b10011 : readData2 = regOutput[19]; - 5'b10100 : readData2 = regOutput[20]; - 5'b10101 : readData2 = regOutput[21]; - 5'b10110 : readData2 = regOutput[22]; - 5'b10111 : readData2 = regOutput[23]; - 5'b11000 : readData2 = regOutput[24]; - 5'b11001 : readData2 = regOutput[25]; - 5'b11010 : readData2 = regOutput[26]; - 5'b11011 : readData2 = regOutput[27]; - 5'b11100 : readData2 = regOutput[28]; - 5'b11101 : readData2 = regOutput[29]; - 5'b11110 : readData2 = regOutput[30]; - 5'b11111 : readData2 = regOutput[31]; - default : readData2 = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01000 : regInput[9] = writeData; - 5'b01001 : regInput[10] = writeData; - 5'b01010 : regInput[11] = writeData; - 5'b01111 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11000 : regInput[25] = writeData; - 5'b11001 : regInput[26] = writeData; - 5'b11010 : regInput[27] = writeData; - 5'b11111 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//******** -//formatting separation -//******** -///////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -module freg3adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [4:0] adr2, - input logic [4:0] adr3, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData1, - output logic [`XLEN-1:0] readData2, - output logic [`XLEN-1:0] readData3); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) reg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //address decoder - //3 are used for this fp register set - //used exclusively for fma - //defaults to outputting zeroes - always_comb begin - - //adderss 1 decoder - case(adr1) - 5'b00000 : readData1 = regOutput[0]; - 5'b00001 : readData1 = regOutput[1]; - 5'b00010 : readData1 = regOutput[2]; - 5'b00011 : readData1 = regOutput[3]; - 5'b00100 : readData1 = regOutput[4]; - 5'b00101 : readData1 = regOutput[5]; - 5'b00110 : readData1 = regOutput[6]; - 5'b00111 : readData1 = regOutput[7]; - 5'b01000 : readData1 = regOutput[8]; - 5'b01001 : readData1 = regOutput[9]; - 5'b01010 : readData1 = regOutput[10]; - 5'b01011 : readData1 = regOutput[11]; - 5'b01100 : readData1 = regOutput[12]; - 5'b01101 : readData1 = regOutput[13]; - 5'b01110 : readData1 = regOutput[14]; - 5'b01111 : readData1 = regOutput[15]; - 5'b10000 : readData1 = regOutput[16]; - 5'b10001 : readData1 = regOutput[17]; - 5'b10010 : readData1 = regOutput[18]; - 5'b10011 : readData1 = regOutput[19]; - 5'b10100 : readData1 = regOutput[20]; - 5'b10101 : readData1 = regOutput[21]; - 5'b10110 : readData1 = regOutput[22]; - 5'b10111 : readData1 = regOutput[23]; - 5'b11000 : readData1 = regOutput[24]; - 5'b11001 : readData1 = regOutput[25]; - 5'b11010 : readData1 = regOutput[26]; - 5'b11011 : readData1 = regOutput[27]; - 5'b11100 : readData1 = regOutput[28]; - 5'b11101 : readData1 = regOutput[29]; - 5'b11110 : readData1 = regOutput[30]; - 5'b11111 : readData1 = regOutput[31]; - default : readData1 = `XLEN'h0; - endcase - - //address 2 decoder - case(adr2) - 5'b00000 : readData2 = regOutput[0]; - 5'b00001 : readData2 = regOutput[1]; - 5'b00010 : readData2 = regOutput[2]; - 5'b00011 : readData2 = regOutput[3]; - 5'b00100 : readData2 = regOutput[4]; - 5'b00101 : readData2 = regOutput[5]; - 5'b00110 : readData2 = regOutput[6]; - 5'b00111 : readData2 = regOutput[7]; - 5'b01000 : readData2 = regOutput[8]; - 5'b01001 : readData2 = regOutput[9]; - 5'b01010 : readData2 = regOutput[10]; - 5'b01011 : readData2 = regOutput[11]; - 5'b01100 : readData2 = regOutput[12]; - 5'b01101 : readData2 = regOutput[13]; - 5'b01110 : readData2 = regOutput[14]; - 5'b01111 : readData2 = regOutput[15]; - 5'b10000 : readData2 = regOutput[16]; - 5'b10001 : readData2 = regOutput[17]; - 5'b10010 : readData2 = regOutput[18]; - 5'b10011 : readData2 = regOutput[19]; - 5'b10100 : readData2 = regOutput[20]; - 5'b10101 : readData2 = regOutput[21]; - 5'b10110 : readData2 = regOutput[22]; - 5'b10111 : readData2 = regOutput[23]; - 5'b11000 : readData2 = regOutput[24]; - 5'b11001 : readData2 = regOutput[25]; - 5'b11010 : readData2 = regOutput[26]; - 5'b11011 : readData2 = regOutput[27]; - 5'b11100 : readData2 = regOutput[28]; - 5'b11101 : readData2 = regOutput[29]; - 5'b11110 : readData2 = regOutput[30]; - 5'b11111 : readData2 = regOutput[31]; - default : readData2 = `XLEN'h0; - endcase - - //address 3 decoder - case(adr3) - 5'b00000 : readData3 = regOutput[0]; - 5'b00001 : readData3 = regOutput[1]; - 5'b00010 : readData3 = regOutput[2]; - 5'b00011 : readData3 = regOutput[3]; - 5'b00100 : readData3 = regOutput[4]; - 5'b00101 : readData3 = regOutput[5]; - 5'b00110 : readData3 = regOutput[6]; - 5'b00111 : readData3 = regOutput[7]; - 5'b01000 : readData3 = regOutput[8]; - 5'b01001 : readData3 = regOutput[9]; - 5'b01010 : readData3 = regOutput[10]; - 5'b01011 : readData3 = regOutput[11]; - 5'b01100 : readData3 = regOutput[12]; - 5'b01101 : readData3 = regOutput[13]; - 5'b01110 : readData3 = regOutput[14]; - 5'b01111 : readData3 = regOutput[15]; - 5'b10000 : readData3 = regOutput[16]; - 5'b10001 : readData3 = regOutput[17]; - 5'b10010 : readData3 = regOutput[18]; - 5'b10011 : readData3 = regOutput[19]; - 5'b10100 : readData3 = regOutput[20]; - 5'b10101 : readData3 = regOutput[21]; - 5'b10110 : readData3 = regOutput[22]; - 5'b10111 : readData3 = regOutput[23]; - 5'b11000 : readData3 = regOutput[24]; - 5'b11001 : readData3 = regOutput[25]; - 5'b11010 : readData3 = regOutput[26]; - 5'b11011 : readData3 = regOutput[27]; - 5'b11100 : readData3 = regOutput[28]; - 5'b11101 : readData3 = regOutput[29]; - 5'b11110 : readData3 = regOutput[30]; - 5'b11111 : readData3 = regOutput[31]; - default : readData3 = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01000 : regInput[9] = writeData; - 5'b01001 : regInput[10] = writeData; - 5'b01010 : regInput[11] = writeData; - 5'b01111 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11000 : regInput[25] = writeData; - 5'b11001 : regInput[26] = writeData; - 5'b11010 : regInput[27] = writeData; - 5'b11111 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule diff --git a/wally-pipelined/src/fpu/convert_inputs_div.sv b/wally-pipelined/src/fpu/convert_inputs_div.sv index 0d4d72949..5ee88ca6a 100755 --- a/wally-pipelined/src/fpu/convert_inputs_div.sv +++ b/wally-pipelined/src/fpu/convert_inputs_div.sv @@ -21,30 +21,26 @@ module convert_inputs_div (Float1, Float2b, op1, op2, op_type, P); // Test if the input exponent is zero, because if it is then the // exponent of the converted number should be zero. - assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] | - op1[58] | op1[57] | op1[56] | op1[55]); - assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] | - op2[58] | op2[57] | op2[56] | op2[55]); - assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] & - op1[58] & op1[57] & op1[56] & op1[55]); - assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] & - op2[58] & op2[57] & op2[56] &op2[55]); + assign Zexp1 = ~(|op1[30:23]); + assign Zexp2 = ~(|op2[30:23]); + assign Oexp1 = (&op1[30:23]); + assign Oexp2 = (&op2[30:23]); // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]} + assign Float1[62:29] = P ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]} : op1[62:29]; assign Float1[28:0] = op1[28:0] & {29{~P}}; // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]} + assign Float2[62:29] = P ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]} : op2[62:29]; assign Float2[28:0] = op2[28:0] & {29{~P}}; // Set the sign of Float1 based on its original sign - assign Float1[63] = op1[63]; - assign Float2[63] = op2[63]; + assign Float1[63] = P ? op1[31] : op1[63]; + assign Float2[63] = P ? op2[31] : op2[63]; // For sqrt, assign Float2 same as Float1 for simplicity assign Float2b = op_type ? Float1 : Float2; -endmodule // convert_inputs +endmodule // convert_inputs \ No newline at end of file diff --git a/wally-pipelined/src/fpu/dev/' b/wally-pipelined/src/fpu/dev/' deleted file mode 100644 index 6d70def0b..000000000 --- a/wally-pipelined/src/fpu/dev/' +++ /dev/null @@ -1,50 +0,0 @@ -`include "../../config/rv64icfd/wally-config.vh" - -module fputop ( - input logic [2:0] FrmW, - input logic reset, - input logic clear, - input logic clk, - input logic [31:0] InstrD, - input logic [`XLEN-1:0] SrcAE, - input logic [`XLEN-1:0] SrcAW, - output logic [31:0] FSROutW, - output logic DivSqrtDoneE, - output logic FInvalInstrD, - output logic [`XLEN-1:0] FPUResultW); - - fctrl (); - - //regfile instantiation and decode stage - freg3adr (); - - //can easily be merged into privledged core - //if necessary - //fcsr (); - - //E pipe and execution stage - - fpdivsqrt (); - - //fma1 (); - - fpaddcvt1 fpadd1 (); - - fpcmp1 cmp1 (); - - fpusgn (); - - //M pipe and memory stage - - //fma2 (); - - fpaddcvt2 fpadd2 (); - - fpcmp2 cmp2 (); - - //W pipe and writeback stage - - //flag signal mux - - //result mux -endmodule diff --git a/wally-pipelined/src/fpu/dev/adder.v b/wally-pipelined/src/fpu/dev/adder.v deleted file mode 100755 index 3d4124af6..000000000 --- a/wally-pipelined/src/fpu/dev/adder.v +++ /dev/null @@ -1,758 +0,0 @@ -// The following module make up the basic building blocks that -// are used by the cla64, cla_sub64, and cla52. - -module INVBLOCK ( GIN, GOUT ); - - input GIN; - output GOUT; - - assign GOUT = ~ GIN; - -endmodule // INVBLOCK - - -module XXOR1 ( A, B, GIN, SUM ); - - input A; - input B; - input GIN; - output SUM; - - assign SUM = ( ~ (A ^ B)) ^ GIN; - -endmodule // XXOR1 - - -module BLOCK0 ( A, B, POUT, GOUT ); - - input A; - input B; - output POUT; - output GOUT; - - assign POUT = ~ (A | B); - assign GOUT = ~ (A & B); - -endmodule // BLOCK0 - - -module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 | PIN2); - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1 - - -module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 & PIN2); - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule // BLOCK2 - - -module BLOCK1A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1A - - -module BLOCK2A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule - -module PRESTAGE_64 ( A, B, CIN, POUT, GOUT ); - - input [0:63] A; - input [0:63] B; - input CIN; - - output [0:63] POUT; - output [0:64] GOUT; - - BLOCK0 U10 (A[0] , B[0] , POUT[0] , GOUT[1] ); - BLOCK0 U11 (A[1] , B[1] , POUT[1] , GOUT[2] ); - BLOCK0 U12 (A[2] , B[2] , POUT[2] , GOUT[3] ); - BLOCK0 U13 (A[3] , B[3] , POUT[3] , GOUT[4] ); - BLOCK0 U14 (A[4] , B[4] , POUT[4] , GOUT[5] ); - BLOCK0 U15 (A[5] , B[5] , POUT[5] , GOUT[6] ); - BLOCK0 U16 (A[6] , B[6] , POUT[6] , GOUT[7] ); - BLOCK0 U17 (A[7] , B[7] , POUT[7] , GOUT[8] ); - BLOCK0 U18 (A[8] , B[8] , POUT[8] , GOUT[9] ); - BLOCK0 U19 (A[9] , B[9] , POUT[9] , GOUT[10] ); - BLOCK0 U110 (A[10] , B[10] , POUT[10] , GOUT[11] ); - BLOCK0 U111 (A[11] , B[11] , POUT[11] , GOUT[12] ); - BLOCK0 U112 (A[12] , B[12] , POUT[12] , GOUT[13] ); - BLOCK0 U113 (A[13] , B[13] , POUT[13] , GOUT[14] ); - BLOCK0 U114 (A[14] , B[14] , POUT[14] , GOUT[15] ); - BLOCK0 U115 (A[15] , B[15] , POUT[15] , GOUT[16] ); - BLOCK0 U116 (A[16] , B[16] , POUT[16] , GOUT[17] ); - BLOCK0 U117 (A[17] , B[17] , POUT[17] , GOUT[18] ); - BLOCK0 U118 (A[18] , B[18] , POUT[18] , GOUT[19] ); - BLOCK0 U119 (A[19] , B[19] , POUT[19] , GOUT[20] ); - BLOCK0 U120 (A[20] , B[20] , POUT[20] , GOUT[21] ); - BLOCK0 U121 (A[21] , B[21] , POUT[21] , GOUT[22] ); - BLOCK0 U122 (A[22] , B[22] , POUT[22] , GOUT[23] ); - BLOCK0 U123 (A[23] , B[23] , POUT[23] , GOUT[24] ); - BLOCK0 U124 (A[24] , B[24] , POUT[24] , GOUT[25] ); - BLOCK0 U125 (A[25] , B[25] , POUT[25] , GOUT[26] ); - BLOCK0 U126 (A[26] , B[26] , POUT[26] , GOUT[27] ); - BLOCK0 U127 (A[27] , B[27] , POUT[27] , GOUT[28] ); - BLOCK0 U128 (A[28] , B[28] , POUT[28] , GOUT[29] ); - BLOCK0 U129 (A[29] , B[29] , POUT[29] , GOUT[30] ); - BLOCK0 U130 (A[30] , B[30] , POUT[30] , GOUT[31] ); - BLOCK0 U131 (A[31] , B[31] , POUT[31] , GOUT[32] ); - BLOCK0 U132 (A[32] , B[32] , POUT[32] , GOUT[33] ); - BLOCK0 U133 (A[33] , B[33] , POUT[33] , GOUT[34] ); - BLOCK0 U134 (A[34] , B[34] , POUT[34] , GOUT[35] ); - BLOCK0 U135 (A[35] , B[35] , POUT[35] , GOUT[36] ); - BLOCK0 U136 (A[36] , B[36] , POUT[36] , GOUT[37] ); - BLOCK0 U137 (A[37] , B[37] , POUT[37] , GOUT[38] ); - BLOCK0 U138 (A[38] , B[38] , POUT[38] , GOUT[39] ); - BLOCK0 U139 (A[39] , B[39] , POUT[39] , GOUT[40] ); - BLOCK0 U140 (A[40] , B[40] , POUT[40] , GOUT[41] ); - BLOCK0 U141 (A[41] , B[41] , POUT[41] , GOUT[42] ); - BLOCK0 U142 (A[42] , B[42] , POUT[42] , GOUT[43] ); - BLOCK0 U143 (A[43] , B[43] , POUT[43] , GOUT[44] ); - BLOCK0 U144 (A[44] , B[44] , POUT[44] , GOUT[45] ); - BLOCK0 U145 (A[45] , B[45] , POUT[45] , GOUT[46] ); - BLOCK0 U146 (A[46] , B[46] , POUT[46] , GOUT[47] ); - BLOCK0 U147 (A[47] , B[47] , POUT[47] , GOUT[48] ); - BLOCK0 U148 (A[48] , B[48] , POUT[48] , GOUT[49] ); - BLOCK0 U149 (A[49] , B[49] , POUT[49] , GOUT[50] ); - BLOCK0 U150 (A[50] , B[50] , POUT[50] , GOUT[51] ); - BLOCK0 U151 (A[51] , B[51] , POUT[51] , GOUT[52] ); - BLOCK0 U152 (A[52] , B[52] , POUT[52] , GOUT[53] ); - BLOCK0 U153 (A[53] , B[53] , POUT[53] , GOUT[54] ); - BLOCK0 U154 (A[54] , B[54] , POUT[54] , GOUT[55] ); - BLOCK0 U155 (A[55] , B[55] , POUT[55] , GOUT[56] ); - BLOCK0 U156 (A[56] , B[56] , POUT[56] , GOUT[57] ); - BLOCK0 U157 (A[57] , B[57] , POUT[57] , GOUT[58] ); - BLOCK0 U158 (A[58] , B[58] , POUT[58] , GOUT[59] ); - BLOCK0 U159 (A[59] , B[59] , POUT[59] , GOUT[60] ); - BLOCK0 U160 (A[60] , B[60] , POUT[60] , GOUT[61] ); - BLOCK0 U161 (A[61] , B[61] , POUT[61] , GOUT[62] ); - BLOCK0 U162 (A[62] , B[62] , POUT[62] , GOUT[63] ); - BLOCK0 U163 (A[63] , B[63] , POUT[63] , GOUT[64] ); - INVBLOCK U2 (CIN , GOUT[0] ); - -endmodule // PRESTAGE_64 - - -module DBLC_0_64 ( PIN, GIN, POUT, GOUT ); - - input [0:63] PIN; - input [0:64] GIN; - - output [0:62] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , GOUT[1] ); - BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , POUT[0] , GOUT[2] ); - BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , POUT[1] , GOUT[3] ); - BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , POUT[2] , GOUT[4] ); - BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , POUT[3] , GOUT[5] ); - BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , POUT[4] , GOUT[6] ); - BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , POUT[5] , GOUT[7] ); - BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , POUT[6] , GOUT[8] ); - BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , POUT[7] , GOUT[9] ); - BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , POUT[8] , GOUT[10] ); - BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , POUT[9] , GOUT[11] ); - BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , POUT[10] , GOUT[12] ); - BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , POUT[11] , GOUT[13] ); - BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , POUT[12] , GOUT[14] ); - BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , POUT[13] , GOUT[15] ); - BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , POUT[14] , GOUT[16] ); - BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , POUT[15] , GOUT[17] ); - BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , POUT[16] , GOUT[18] ); - BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , POUT[17] , GOUT[19] ); - BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , POUT[18] , GOUT[20] ); - BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , POUT[19] , GOUT[21] ); - BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , POUT[20] , GOUT[22] ); - BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , POUT[21] , GOUT[23] ); - BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , POUT[22] , GOUT[24] ); - BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , POUT[23] , GOUT[25] ); - BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , POUT[24] , GOUT[26] ); - BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , POUT[25] , GOUT[27] ); - BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , POUT[26] , GOUT[28] ); - BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , POUT[27] , GOUT[29] ); - BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , POUT[28] , GOUT[30] ); - BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , POUT[29] , GOUT[31] ); - BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , POUT[30] , GOUT[32] ); - BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , POUT[31] , GOUT[33] ); - BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , POUT[32] , GOUT[34] ); - BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , POUT[33] , GOUT[35] ); - BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , POUT[34] , GOUT[36] ); - BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , POUT[35] , GOUT[37] ); - BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , POUT[36] , GOUT[38] ); - BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , POUT[37] , GOUT[39] ); - BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , POUT[38] , GOUT[40] ); - BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , POUT[39] , GOUT[41] ); - BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , POUT[40] , GOUT[42] ); - BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , POUT[41] , GOUT[43] ); - BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , POUT[42] , GOUT[44] ); - BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , POUT[43] , GOUT[45] ); - BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , POUT[44] , GOUT[46] ); - BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , POUT[45] , GOUT[47] ); - BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , POUT[46] , GOUT[48] ); - BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , POUT[47] , GOUT[49] ); - BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , POUT[48] , GOUT[50] ); - BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , POUT[49] , GOUT[51] ); - BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , POUT[50] , GOUT[52] ); - BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , POUT[51] , GOUT[53] ); - BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , POUT[52] , GOUT[54] ); - BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , POUT[53] , GOUT[55] ); - BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , POUT[54] , GOUT[56] ); - BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , POUT[55] , GOUT[57] ); - BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , POUT[56] , GOUT[58] ); - BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , POUT[57] , GOUT[59] ); - BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , POUT[58] , GOUT[60] ); - BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , POUT[59] , GOUT[61] ); - BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , POUT[60] , GOUT[62] ); - BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , POUT[61] , GOUT[63] ); - BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , POUT[62] , GOUT[64] ); - -endmodule // DBLC_0_64 - - -module DBLC_1_64 ( PIN, GIN, POUT, GOUT ); - - input [0:62] PIN; - input [0:64] GIN; - - output [0:60] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , GOUT[2] ); - BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , GOUT[3] ); - BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , POUT[0] , GOUT[4] ); - BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , POUT[1] , GOUT[5] ); - BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , POUT[2] , GOUT[6] ); - BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , POUT[3] , GOUT[7] ); - BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , POUT[4] , GOUT[8] ); - BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , POUT[5] , GOUT[9] ); - BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , POUT[6] , GOUT[10] ); - BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , POUT[7] , GOUT[11] ); - BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , POUT[8] , GOUT[12] ); - BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , POUT[9] , GOUT[13] ); - BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , POUT[10] , GOUT[14] ); - BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , POUT[11] , GOUT[15] ); - BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , POUT[12] , GOUT[16] ); - BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , POUT[13] , GOUT[17] ); - BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , POUT[14] , GOUT[18] ); - BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , POUT[15] , GOUT[19] ); - BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , POUT[16] , GOUT[20] ); - BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , POUT[17] , GOUT[21] ); - BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , POUT[18] , GOUT[22] ); - BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , POUT[19] , GOUT[23] ); - BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , POUT[20] , GOUT[24] ); - BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , POUT[21] , GOUT[25] ); - BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , POUT[22] , GOUT[26] ); - BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , POUT[23] , GOUT[27] ); - BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , POUT[24] , GOUT[28] ); - BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , POUT[25] , GOUT[29] ); - BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , POUT[26] , GOUT[30] ); - BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , POUT[27] , GOUT[31] ); - BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , POUT[28] , GOUT[32] ); - BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , POUT[29] , GOUT[33] ); - BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , POUT[30] , GOUT[34] ); - BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , POUT[31] , GOUT[35] ); - BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , POUT[32] , GOUT[36] ); - BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , POUT[33] , GOUT[37] ); - BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , POUT[34] , GOUT[38] ); - BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , POUT[35] , GOUT[39] ); - BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , POUT[36] , GOUT[40] ); - BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , POUT[37] , GOUT[41] ); - BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , POUT[38] , GOUT[42] ); - BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , POUT[39] , GOUT[43] ); - BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , POUT[40] , GOUT[44] ); - BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , POUT[41] , GOUT[45] ); - BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , POUT[42] , GOUT[46] ); - BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , POUT[43] , GOUT[47] ); - BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , POUT[44] , GOUT[48] ); - BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , POUT[45] , GOUT[49] ); - BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , POUT[46] , GOUT[50] ); - BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , POUT[47] , GOUT[51] ); - BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , POUT[48] , GOUT[52] ); - BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , POUT[49] , GOUT[53] ); - BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , POUT[50] , GOUT[54] ); - BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , POUT[51] , GOUT[55] ); - BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , POUT[52] , GOUT[56] ); - BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , POUT[53] , GOUT[57] ); - BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , POUT[54] , GOUT[58] ); - BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , POUT[55] , GOUT[59] ); - BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , POUT[56] , GOUT[60] ); - BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , POUT[57] , GOUT[61] ); - BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , POUT[58] , GOUT[62] ); - BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , POUT[59] , GOUT[63] ); - BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , POUT[60] , GOUT[64] ); - -endmodule // DBLC_1_64 - - -module DBLC_2_64 ( PIN, GIN, POUT, GOUT ); - - input [0:60] PIN; - input [0:64] GIN; - - output [0:56] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , GOUT[4] ); - BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , GOUT[5] ); - BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , GOUT[6] ); - BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , GOUT[7] ); - BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , POUT[0] , GOUT[8] ); - BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , POUT[1] , GOUT[9] ); - BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , POUT[2] , GOUT[10] ); - BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , POUT[3] , GOUT[11] ); - BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , POUT[4] , GOUT[12] ); - BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , POUT[5] , GOUT[13] ); - BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , POUT[6] , GOUT[14] ); - BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , POUT[7] , GOUT[15] ); - BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , POUT[8] , GOUT[16] ); - BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , POUT[9] , GOUT[17] ); - BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , POUT[10] , GOUT[18] ); - BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , POUT[11] , GOUT[19] ); - BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , POUT[12] , GOUT[20] ); - BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , POUT[13] , GOUT[21] ); - BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , POUT[14] , GOUT[22] ); - BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , POUT[15] , GOUT[23] ); - BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , POUT[16] , GOUT[24] ); - BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , POUT[17] , GOUT[25] ); - BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , POUT[18] , GOUT[26] ); - BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , POUT[19] , GOUT[27] ); - BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , POUT[20] , GOUT[28] ); - BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , POUT[21] , GOUT[29] ); - BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , POUT[22] , GOUT[30] ); - BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , POUT[23] , GOUT[31] ); - BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , POUT[24] , GOUT[32] ); - BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , POUT[25] , GOUT[33] ); - BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , POUT[26] , GOUT[34] ); - BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , POUT[27] , GOUT[35] ); - BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , POUT[28] , GOUT[36] ); - BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , POUT[29] , GOUT[37] ); - BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , POUT[30] , GOUT[38] ); - BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , POUT[31] , GOUT[39] ); - BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , POUT[32] , GOUT[40] ); - BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , POUT[33] , GOUT[41] ); - BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , POUT[34] , GOUT[42] ); - BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , POUT[35] , GOUT[43] ); - BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , POUT[36] , GOUT[44] ); - BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , POUT[37] , GOUT[45] ); - BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , POUT[38] , GOUT[46] ); - BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , POUT[39] , GOUT[47] ); - BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , POUT[40] , GOUT[48] ); - BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , POUT[41] , GOUT[49] ); - BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , POUT[42] , GOUT[50] ); - BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , POUT[43] , GOUT[51] ); - BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , POUT[44] , GOUT[52] ); - BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , POUT[45] , GOUT[53] ); - BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , POUT[46] , GOUT[54] ); - BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , POUT[47] , GOUT[55] ); - BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , POUT[48] , GOUT[56] ); - BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , POUT[49] , GOUT[57] ); - BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , POUT[50] , GOUT[58] ); - BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , POUT[51] , GOUT[59] ); - BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , POUT[52] , GOUT[60] ); - BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , POUT[53] , GOUT[61] ); - BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , POUT[54] , GOUT[62] ); - BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , POUT[55] , GOUT[63] ); - BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , POUT[56] , GOUT[64] ); - -endmodule // DBLC_2_64 - - -module DBLC_3_64 ( PIN, GIN, POUT, GOUT ); - - input [0:56] PIN; - input [0:64] GIN; - - output [0:48] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , GOUT[8] ); - BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , GOUT[9] ); - BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , GOUT[10] ); - BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , GOUT[11] ); - BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , GOUT[12] ); - BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , GOUT[13] ); - BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , GOUT[14] ); - BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , GOUT[15] ); - BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , POUT[0] , GOUT[16] ); - BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , POUT[1] , GOUT[17] ); - BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , POUT[2] , GOUT[18] ); - BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , POUT[3] , GOUT[19] ); - BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , POUT[4] , GOUT[20] ); - BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , POUT[5] , GOUT[21] ); - BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , POUT[6] , GOUT[22] ); - BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , POUT[7] , GOUT[23] ); - BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , POUT[8] , GOUT[24] ); - BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , POUT[9] , GOUT[25] ); - BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , POUT[10] , GOUT[26] ); - BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , POUT[11] , GOUT[27] ); - BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , POUT[12] , GOUT[28] ); - BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , POUT[13] , GOUT[29] ); - BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , POUT[14] , GOUT[30] ); - BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , POUT[15] , GOUT[31] ); - BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , POUT[16] , GOUT[32] ); - BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , POUT[17] , GOUT[33] ); - BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , POUT[18] , GOUT[34] ); - BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , POUT[19] , GOUT[35] ); - BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , POUT[20] , GOUT[36] ); - BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , POUT[21] , GOUT[37] ); - BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , POUT[22] , GOUT[38] ); - BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , POUT[23] , GOUT[39] ); - BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , POUT[24] , GOUT[40] ); - BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , POUT[25] , GOUT[41] ); - BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , POUT[26] , GOUT[42] ); - BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , POUT[27] , GOUT[43] ); - BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , POUT[28] , GOUT[44] ); - BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , POUT[29] , GOUT[45] ); - BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , POUT[30] , GOUT[46] ); - BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , POUT[31] , GOUT[47] ); - BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , POUT[32] , GOUT[48] ); - BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , POUT[33] , GOUT[49] ); - BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , POUT[34] , GOUT[50] ); - BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , POUT[35] , GOUT[51] ); - BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , POUT[36] , GOUT[52] ); - BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , POUT[37] , GOUT[53] ); - BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , POUT[38] , GOUT[54] ); - BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , POUT[39] , GOUT[55] ); - BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , POUT[40] , GOUT[56] ); - BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , POUT[41] , GOUT[57] ); - BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , POUT[42] , GOUT[58] ); - BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , POUT[43] , GOUT[59] ); - BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , POUT[44] , GOUT[60] ); - BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , POUT[45] , GOUT[61] ); - BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , POUT[46] , GOUT[62] ); - BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , POUT[47] , GOUT[63] ); - BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , POUT[48] , GOUT[64] ); - -endmodule // DBLC_3_64 - - -module DBLC_4_64 ( PIN, GIN, POUT, GOUT ); - - input [0:48] PIN; - input [0:64] GIN; - - output [0:32] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , GOUT[16] ); - BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , GOUT[17] ); - BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , GOUT[18] ); - BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , GOUT[19] ); - BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , GOUT[20] ); - BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , GOUT[21] ); - BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , GOUT[22] ); - BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , GOUT[23] ); - BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , GOUT[24] ); - BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , GOUT[25] ); - BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , GOUT[26] ); - BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , GOUT[27] ); - BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , GOUT[28] ); - BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , GOUT[29] ); - BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , GOUT[30] ); - BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , GOUT[31] ); - BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , POUT[0] , GOUT[32] ); - BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , POUT[1] , GOUT[33] ); - BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , POUT[2] , GOUT[34] ); - BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , POUT[3] , GOUT[35] ); - BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , POUT[4] , GOUT[36] ); - BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , POUT[5] , GOUT[37] ); - BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , POUT[6] , GOUT[38] ); - BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , POUT[7] , GOUT[39] ); - BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , POUT[8] , GOUT[40] ); - BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , POUT[9] , GOUT[41] ); - BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , POUT[10] , GOUT[42] ); - BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , POUT[11] , GOUT[43] ); - BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , POUT[12] , GOUT[44] ); - BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , POUT[13] , GOUT[45] ); - BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , POUT[14] , GOUT[46] ); - BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , POUT[15] , GOUT[47] ); - BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , POUT[16] , GOUT[48] ); - BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , POUT[17] , GOUT[49] ); - BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , POUT[18] , GOUT[50] ); - BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , POUT[19] , GOUT[51] ); - BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , POUT[20] , GOUT[52] ); - BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , POUT[21] , GOUT[53] ); - BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , POUT[22] , GOUT[54] ); - BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , POUT[23] , GOUT[55] ); - BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , POUT[24] , GOUT[56] ); - BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , POUT[25] , GOUT[57] ); - BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , POUT[26] , GOUT[58] ); - BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , POUT[27] , GOUT[59] ); - BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , POUT[28] , GOUT[60] ); - BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , POUT[29] , GOUT[61] ); - BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , POUT[30] , GOUT[62] ); - BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , POUT[31] , GOUT[63] ); - BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , POUT[32] , GOUT[64] ); - -endmodule // DBLC_4_64 - - -module DBLC_5_64 ( PIN, GIN, POUT, GOUT ); - - input [0:32] PIN; - input [0:64] GIN; - - output [0:0] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - INVBLOCK U116 (GIN[16] , GOUT[16] ); - INVBLOCK U117 (GIN[17] , GOUT[17] ); - INVBLOCK U118 (GIN[18] , GOUT[18] ); - INVBLOCK U119 (GIN[19] , GOUT[19] ); - INVBLOCK U120 (GIN[20] , GOUT[20] ); - INVBLOCK U121 (GIN[21] , GOUT[21] ); - INVBLOCK U122 (GIN[22] , GOUT[22] ); - INVBLOCK U123 (GIN[23] , GOUT[23] ); - INVBLOCK U124 (GIN[24] , GOUT[24] ); - INVBLOCK U125 (GIN[25] , GOUT[25] ); - INVBLOCK U126 (GIN[26] , GOUT[26] ); - INVBLOCK U127 (GIN[27] , GOUT[27] ); - INVBLOCK U128 (GIN[28] , GOUT[28] ); - INVBLOCK U129 (GIN[29] , GOUT[29] ); - INVBLOCK U130 (GIN[30] , GOUT[30] ); - INVBLOCK U131 (GIN[31] , GOUT[31] ); - BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , GOUT[32] ); - BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , GOUT[33] ); - BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , GOUT[34] ); - BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , GOUT[35] ); - BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , GOUT[36] ); - BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , GOUT[37] ); - BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , GOUT[38] ); - BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , GOUT[39] ); - BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , GOUT[40] ); - BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , GOUT[41] ); - BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , GOUT[42] ); - BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , GOUT[43] ); - BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , GOUT[44] ); - BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , GOUT[45] ); - BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , GOUT[46] ); - BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , GOUT[47] ); - BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , GOUT[48] ); - BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , GOUT[49] ); - BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , GOUT[50] ); - BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , GOUT[51] ); - BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , GOUT[52] ); - BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , GOUT[53] ); - BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , GOUT[54] ); - BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , GOUT[55] ); - BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , GOUT[56] ); - BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , GOUT[57] ); - BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , GOUT[58] ); - BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , GOUT[59] ); - BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , GOUT[60] ); - BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , GOUT[61] ); - BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , GOUT[62] ); - BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , GOUT[63] ); - BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , POUT[0] , GOUT[64] ); - -endmodule // DBLC_5_64 - - -module XORSTAGE_64 ( A, B, PBIT, CARRY, SUM, COUT ); - - input [0:63] A; - input [0:63] B; - input PBIT; - input [0:64] CARRY; - - output [0:63] SUM; - output COUT; - - XXOR1 U20 (A[0] , B[0] , CARRY[0] , SUM[0] ); - XXOR1 U21 (A[1] , B[1] , CARRY[1] , SUM[1] ); - XXOR1 U22 (A[2] , B[2] , CARRY[2] , SUM[2] ); - XXOR1 U23 (A[3] , B[3] , CARRY[3] , SUM[3] ); - XXOR1 U24 (A[4] , B[4] , CARRY[4] , SUM[4] ); - XXOR1 U25 (A[5] , B[5] , CARRY[5] , SUM[5] ); - XXOR1 U26 (A[6] , B[6] , CARRY[6] , SUM[6] ); - XXOR1 U27 (A[7] , B[7] , CARRY[7] , SUM[7] ); - XXOR1 U28 (A[8] , B[8] , CARRY[8] , SUM[8] ); - XXOR1 U29 (A[9] , B[9] , CARRY[9] , SUM[9] ); - XXOR1 U210 (A[10] , B[10] , CARRY[10] , SUM[10] ); - XXOR1 U211 (A[11] , B[11] , CARRY[11] , SUM[11] ); - XXOR1 U212 (A[12] , B[12] , CARRY[12] , SUM[12] ); - XXOR1 U213 (A[13] , B[13] , CARRY[13] , SUM[13] ); - XXOR1 U214 (A[14] , B[14] , CARRY[14] , SUM[14] ); - XXOR1 U215 (A[15] , B[15] , CARRY[15] , SUM[15] ); - XXOR1 U216 (A[16] , B[16] , CARRY[16] , SUM[16] ); - XXOR1 U217 (A[17] , B[17] , CARRY[17] , SUM[17] ); - XXOR1 U218 (A[18] , B[18] , CARRY[18] , SUM[18] ); - XXOR1 U219 (A[19] , B[19] , CARRY[19] , SUM[19] ); - XXOR1 U220 (A[20] , B[20] , CARRY[20] , SUM[20] ); - XXOR1 U221 (A[21] , B[21] , CARRY[21] , SUM[21] ); - XXOR1 U222 (A[22] , B[22] , CARRY[22] , SUM[22] ); - XXOR1 U223 (A[23] , B[23] , CARRY[23] , SUM[23] ); - XXOR1 U224 (A[24] , B[24] , CARRY[24] , SUM[24] ); - XXOR1 U225 (A[25] , B[25] , CARRY[25] , SUM[25] ); - XXOR1 U226 (A[26] , B[26] , CARRY[26] , SUM[26] ); - XXOR1 U227 (A[27] , B[27] , CARRY[27] , SUM[27] ); - XXOR1 U228 (A[28] , B[28] , CARRY[28] , SUM[28] ); - XXOR1 U229 (A[29] , B[29] , CARRY[29] , SUM[29] ); - XXOR1 U230 (A[30] , B[30] , CARRY[30] , SUM[30] ); - XXOR1 U231 (A[31] , B[31] , CARRY[31] , SUM[31] ); - XXOR1 U232 (A[32] , B[32] , CARRY[32] , SUM[32] ); - XXOR1 U233 (A[33] , B[33] , CARRY[33] , SUM[33] ); - XXOR1 U234 (A[34] , B[34] , CARRY[34] , SUM[34] ); - XXOR1 U235 (A[35] , B[35] , CARRY[35] , SUM[35] ); - XXOR1 U236 (A[36] , B[36] , CARRY[36] , SUM[36] ); - XXOR1 U237 (A[37] , B[37] , CARRY[37] , SUM[37] ); - XXOR1 U238 (A[38] , B[38] , CARRY[38] , SUM[38] ); - XXOR1 U239 (A[39] , B[39] , CARRY[39] , SUM[39] ); - XXOR1 U240 (A[40] , B[40] , CARRY[40] , SUM[40] ); - XXOR1 U241 (A[41] , B[41] , CARRY[41] , SUM[41] ); - XXOR1 U242 (A[42] , B[42] , CARRY[42] , SUM[42] ); - XXOR1 U243 (A[43] , B[43] , CARRY[43] , SUM[43] ); - XXOR1 U244 (A[44] , B[44] , CARRY[44] , SUM[44] ); - XXOR1 U245 (A[45] , B[45] , CARRY[45] , SUM[45] ); - XXOR1 U246 (A[46] , B[46] , CARRY[46] , SUM[46] ); - XXOR1 U247 (A[47] , B[47] , CARRY[47] , SUM[47] ); - XXOR1 U248 (A[48] , B[48] , CARRY[48] , SUM[48] ); - XXOR1 U249 (A[49] , B[49] , CARRY[49] , SUM[49] ); - XXOR1 U250 (A[50] , B[50] , CARRY[50] , SUM[50] ); - XXOR1 U251 (A[51] , B[51] , CARRY[51] , SUM[51] ); - XXOR1 U252 (A[52] , B[52] , CARRY[52] , SUM[52] ); - XXOR1 U253 (A[53] , B[53] , CARRY[53] , SUM[53] ); - XXOR1 U254 (A[54] , B[54] , CARRY[54] , SUM[54] ); - XXOR1 U255 (A[55] , B[55] , CARRY[55] , SUM[55] ); - XXOR1 U256 (A[56] , B[56] , CARRY[56] , SUM[56] ); - XXOR1 U257 (A[57] , B[57] , CARRY[57] , SUM[57] ); - XXOR1 U258 (A[58] , B[58] , CARRY[58] , SUM[58] ); - XXOR1 U259 (A[59] , B[59] , CARRY[59] , SUM[59] ); - XXOR1 U260 (A[60] , B[60] , CARRY[60] , SUM[60] ); - XXOR1 U261 (A[61] , B[61] , CARRY[61] , SUM[61] ); - XXOR1 U262 (A[62] , B[62] , CARRY[62] , SUM[62] ); - XXOR1 U263 (A[63] , B[63] , CARRY[63] , SUM[63] ); - BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , COUT ); - -endmodule // XORSTAGE_64 - - -module DBLCTREE_64 ( PIN, GIN, GOUT, POUT ); - - input [0:63] PIN; - input [0:64] GIN; - - output [0:64] GOUT; - output [0:0] POUT; - - wire [0:62] INTPROP_0; - wire [0:64] INTGEN_0; - wire [0:60] INTPROP_1; - wire [0:64] INTGEN_1; - wire [0:56] INTPROP_2; - wire [0:64] INTGEN_2; - wire [0:48] INTPROP_3; - wire [0:64] INTGEN_3; - wire [0:32] INTPROP_4; - wire [0:64] INTGEN_4; - - DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) ); - DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) ); - DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) ); - DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) ); - DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) ); - DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .POUT(POUT) , .GOUT(GOUT) ); - -endmodule // DBLCTREE_64 - - -module DBLCADDER_64_64 ( OPA, OPB, CIN, SUM, COUT ); - - input [0:63] OPA; - input [0:63] OPB; - input CIN; - - output [0:63] SUM; - output COUT; - - wire [0:63] INTPROP; - wire [0:64] INTGEN; - wire [0:0] PBIT; - wire [0:64] CARRY; - - PRESTAGE_64 U1 (OPA , OPB , CIN , INTPROP , INTGEN ); - DBLCTREE_64 U2 (INTPROP , INTGEN , CARRY , PBIT ); - XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , CARRY[0:64] , SUM , COUT ); - -endmodule diff --git a/wally-pipelined/src/fpu/dev/bk128.v b/wally-pipelined/src/fpu/dev/bk128.v deleted file mode 100755 index 4c856a470..000000000 --- a/wally-pipelined/src/fpu/dev/bk128.v +++ /dev/null @@ -1,620 +0,0 @@ -// Brent-Kung Carry-save Prefix Adder - -module bk128 (cout, sum, a, b, cin); - - input [127:0] a, b; - input cin; - - output [127:0] sum; - output cout; - - wire [128:0] p,g,t; - wire [127:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - assign t[1]=p[1]; - assign t[2]=p[2]; - assign t[3]=p[3]^g[2]; - assign t[4]=p[4]; - assign t[5]=p[5]^g[4]; - assign t[6]=p[6]; - assign t[7]=p[7]^g[6]; - assign t[8]=p[8]; - assign t[9]=p[9]^g[8]; - assign t[10]=p[10]; - assign t[11]=p[11]^g[10]; - assign t[12]=p[12]; - assign t[13]=p[13]^g[12]; - assign t[14]=p[14]; - assign t[15]=p[15]^g[14]; - assign t[16]=p[16]; - assign t[17]=p[17]^g[16]; - assign t[18]=p[18]; - assign t[19]=p[19]^g[18]; - assign t[20]=p[20]; - assign t[21]=p[21]^g[20]; - assign t[22]=p[22]; - assign t[23]=p[23]^g[22]; - assign t[24]=p[24]; - assign t[25]=p[25]^g[24]; - assign t[26]=p[26]; - assign t[27]=p[27]^g[26]; - assign t[28]=p[28]; - assign t[29]=p[29]^g[28]; - assign t[30]=p[30]; - assign t[31]=p[31]^g[30]; - assign t[32]=p[32]; - assign t[33]=p[33]^g[32]; - assign t[34]=p[34]; - assign t[35]=p[35]^g[34]; - assign t[36]=p[36]; - assign t[37]=p[37]^g[36]; - assign t[38]=p[38]; - assign t[39]=p[39]^g[38]; - assign t[40]=p[40]; - assign t[41]=p[41]^g[40]; - assign t[42]=p[42]; - assign t[43]=p[43]^g[42]; - assign t[44]=p[44]; - assign t[45]=p[45]^g[44]; - assign t[46]=p[46]; - assign t[47]=p[47]^g[46]; - assign t[48]=p[48]; - assign t[49]=p[49]^g[48]; - assign t[50]=p[50]; - assign t[51]=p[51]^g[50]; - assign t[52]=p[52]; - assign t[53]=p[53]^g[52]; - assign t[54]=p[54]; - assign t[55]=p[55]^g[54]; - assign t[56]=p[56]; - assign t[57]=p[57]^g[56]; - assign t[58]=p[58]; - assign t[59]=p[59]^g[58]; - assign t[60]=p[60]; - assign t[61]=p[61]^g[60]; - assign t[62]=p[62]; - assign t[63]=p[63]^g[62]; - assign t[64]=p[64]; - assign t[65]=p[65]^g[64]; - assign t[66]=p[66]; - assign t[67]=p[67]^g[66]; - assign t[68]=p[68]; - assign t[69]=p[69]^g[68]; - assign t[70]=p[70]; - assign t[71]=p[71]^g[70]; - assign t[72]=p[72]; - assign t[73]=p[73]^g[72]; - assign t[74]=p[74]; - assign t[75]=p[75]^g[74]; - assign t[76]=p[76]; - assign t[77]=p[77]^g[76]; - assign t[78]=p[78]; - assign t[79]=p[79]^g[78]; - assign t[80]=p[80]; - assign t[81]=p[81]^g[80]; - assign t[82]=p[82]; - assign t[83]=p[83]^g[82]; - assign t[84]=p[84]; - assign t[85]=p[85]^g[84]; - assign t[86]=p[86]; - assign t[87]=p[87]^g[86]; - assign t[88]=p[88]; - assign t[89]=p[89]^g[88]; - assign t[90]=p[90]; - assign t[91]=p[91]^g[90]; - assign t[92]=p[92]; - assign t[93]=p[93]^g[92]; - assign t[94]=p[94]; - assign t[95]=p[95]^g[94]; - assign t[96]=p[96]; - assign t[97]=p[97]^g[96]; - assign t[98]=p[98]; - assign t[99]=p[99]^g[98]; - assign t[100]=p[100]; - assign t[101]=p[101]^g[100]; - assign t[102]=p[102]; - assign t[103]=p[103]^g[102]; - assign t[104]=p[104]; - assign t[105]=p[105]^g[104]; - assign t[106]=p[106]; - assign t[107]=p[107]^g[106]; - assign t[108]=p[108]; - assign t[109]=p[109]^g[108]; - assign t[110]=p[110]; - assign t[111]=p[111]^g[110]; - assign t[112]=p[112]; - assign t[113]=p[113]^g[112]; - assign t[114]=p[114]; - assign t[115]=p[115]^g[114]; - assign t[116]=p[116]; - assign t[117]=p[117]^g[116]; - assign t[118]=p[118]; - assign t[119]=p[119]^g[118]; - assign t[120]=p[120]; - assign t[121]=p[121]^g[120]; - assign t[122]=p[122]; - assign t[123]=p[123]^g[122]; - assign t[124]=p[124]; - assign t[125]=p[125]^g[124]; - assign t[126]=p[126]; - assign t[127]=p[127]^g[126]; - assign t[128]=p[128]; - - // prefix tree - brent_kung_cs prefix_tree(c, p[127:0], g[127:0]); - - // post-computation - assign sum=p[128:1]^c; - assign cout=g[128]|(p[128]&c[127]); - -endmodule - -module brent_kung_cs (c, p, g); - - input [127:0] p; - input [127:0] g; - output [128:1] c; - - - // parallel-prefix, Brent-Kung - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]}); - - black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]}); - black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]}); - black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]}); - black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]}); - black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]}); - black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]}); - black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]}); - black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]}); - - black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]}); - black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]}); - black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]}); - black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]}); - black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]}); - black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]}); - black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]}); - black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]}); - - black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]}); - black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]}); - black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]}); - black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]}); - black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]}); - black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]}); - black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]}); - black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]}); - - black b_65_64 (G_65_64, P_65_64, {g[65],g[64]}, {p[65],p[64]}); - black b_67_66 (G_67_66, P_67_66, {g[67],g[66]}, {p[67],p[66]}); - black b_69_68 (G_69_68, P_69_68, {g[69],g[68]}, {p[69],p[68]}); - black b_71_70 (G_71_70, P_71_70, {g[71],g[70]}, {p[71],p[70]}); - black b_73_72 (G_73_72, P_73_72, {g[73],g[72]}, {p[73],p[72]}); - black b_75_74 (G_75_74, P_75_74, {g[75],g[74]}, {p[75],p[74]}); - black b_77_76 (G_77_76, P_77_76, {g[77],g[76]}, {p[77],p[76]}); - black b_79_78 (G_79_78, P_79_78, {g[79],g[78]}, {p[79],p[78]}); - - black b_81_80 (G_81_80, P_81_80, {g[81],g[80]}, {p[81],p[80]}); - black b_83_82 (G_83_82, P_83_82, {g[83],g[82]}, {p[83],p[82]}); - black b_85_84 (G_85_84, P_85_84, {g[85],g[84]}, {p[85],p[84]}); - black b_87_86 (G_87_86, P_87_86, {g[87],g[86]}, {p[87],p[86]}); - black b_89_88 (G_89_88, P_89_88, {g[89],g[88]}, {p[89],p[88]}); - black b_91_90 (G_91_90, P_91_90, {g[91],g[90]}, {p[91],p[90]}); - black b_93_92 (G_93_92, P_93_92, {g[93],g[92]}, {p[93],p[92]}); - black b_95_94 (G_95_94, P_95_94, {g[95],g[94]}, {p[95],p[94]}); - - black b_97_96 (G_97_96, P_97_96, {g[97],g[96]}, {p[97],p[96]}); - black b_99_98 (G_99_98, P_99_98, {g[99],g[98]}, {p[99],p[98]}); - black b_101_100 (G_101_100, P_101_100, {g[101],g[100]}, {p[101],p[100]}); - black b_103_102 (G_103_102, P_103_102, {g[103],g[102]}, {p[103],p[102]}); - black b_105_104 (G_105_104, P_105_104, {g[105],g[104]}, {p[105],p[104]}); - black b_107_106 (G_107_106, P_107_106, {g[107],g[106]}, {p[107],p[106]}); - black b_109_108 (G_109_108, P_109_108, {g[109],g[108]}, {p[109],p[108]}); - black b_111_110 (G_111_110, P_111_110, {g[111],g[110]}, {p[111],p[110]}); - - black b_113_112 (G_113_112, P_113_112, {g[113],g[112]}, {p[113],p[112]}); - black b_115_114 (G_115_114, P_115_114, {g[115],g[114]}, {p[115],p[114]}); - black b_117_116 (G_117_116, P_117_116, {g[117],g[116]}, {p[117],p[116]}); - black b_119_118 (G_119_118, P_119_118, {g[119],g[118]}, {p[119],p[118]}); - black b_121_120 (G_121_120, P_121_120, {g[121],g[120]}, {p[121],p[120]}); - black b_123_122 (G_123_122, P_123_122, {g[123],g[122]}, {p[123],p[122]}); - black b_125_124 (G_125_124, P_125_124, {g[125],g[124]}, {p[125],p[124]}); - black b_127_126 (G_127_126, P_127_126, {g[127],g[126]}, {p[127],p[126]}); - - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12}); - black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16}); - black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20}); - black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24}); - black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28}); - - black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32}); - black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36}); - black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40}); - black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44}); - black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48}); - black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52}); - black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56}); - black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60}); - - black b_67_64 (G_67_64, P_67_64, {G_67_66,G_65_64}, {P_67_66,P_65_64}); - black b_71_68 (G_71_68, P_71_68, {G_71_70,G_69_68}, {P_71_70,P_69_68}); - black b_75_72 (G_75_72, P_75_72, {G_75_74,G_73_72}, {P_75_74,P_73_72}); - black b_79_76 (G_79_76, P_79_76, {G_79_78,G_77_76}, {P_79_78,P_77_76}); - black b_83_80 (G_83_80, P_83_80, {G_83_82,G_81_80}, {P_83_82,P_81_80}); - black b_87_84 (G_87_84, P_87_84, {G_87_86,G_85_84}, {P_87_86,P_85_84}); - black b_91_88 (G_91_88, P_91_88, {G_91_90,G_89_88}, {P_91_90,P_89_88}); - black b_95_92 (G_95_92, P_95_92, {G_95_94,G_93_92}, {P_95_94,P_93_92}); - - black b_99_96 (G_99_96, P_99_96, {G_99_98,G_97_96}, {P_99_98,P_97_96}); - black b_103_100 (G_103_100, P_103_100, {G_103_102,G_101_100}, {P_103_102,P_101_100}); - black b_107_104 (G_107_104, P_107_104, {G_107_106,G_105_104}, {P_107_106,P_105_104}); - black b_111_108 (G_111_108, P_111_108, {G_111_110,G_109_108}, {P_111_110,P_109_108}); - black b_115_112 (G_115_112, P_115_112, {G_115_114,G_113_112}, {P_115_114,P_113_112}); - black b_119_116 (G_119_116, P_119_116, {G_119_118,G_117_116}, {P_119_118,P_117_116}); - black b_123_120 (G_123_120, P_123_120, {G_123_122,G_121_120}, {P_123_122,P_121_120}); - black b_127_124 (G_127_124, P_127_124, {G_127_126,G_125_124}, {P_127_126,P_125_124}); - - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8}); - black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16}); - black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24}); - black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32}); - black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40}); - black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48}); - black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56}); - - black b_71_64 (G_71_64, P_71_64, {G_71_68,G_67_64}, {P_71_68,P_67_64}); - black b_79_72 (G_79_72, P_79_72, {G_79_76,G_75_72}, {P_79_76,P_75_72}); - black b_87_80 (G_87_80, P_87_80, {G_87_84,G_83_80}, {P_87_84,P_83_80}); - black b_95_88 (G_95_88, P_95_88, {G_95_92,G_91_88}, {P_95_92,P_91_88}); - black b_103_96 (G_103_96, P_103_96, {G_103_100,G_99_96}, {P_103_100,P_99_96}); - black b_111_104 (G_111_104, P_111_104, {G_111_108,G_107_104}, {P_111_108,P_107_104}); - black b_119_112 (G_119_112, P_119_112, {G_119_116,G_115_112}, {P_119_116,P_115_112}); - black b_127_120 (G_127_120, P_127_120, {G_127_124,G_123_120}, {P_127_124,P_123_120}); - - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8); - black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16}); - black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32}); - black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48}); - black b_79_64 (G_79_64, P_79_64, {G_79_72,G_71_64}, {P_79_72,P_71_64}); - black b_95_80 (G_95_80, P_95_80, {G_95_88,G_87_80}, {P_95_88,P_87_80}); - black b_111_96 (G_111_96, P_111_96, {G_111_104,G_103_96}, {P_111_104,P_103_96}); - black b_127_112 (G_127_112, P_127_112, {G_127_120,G_119_112}, {P_127_120,P_119_112}); - - - // Stage 5: Generates G/P pairs that span 16 bits - grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16); - black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32}); - black b_95_64 (G_95_64, P_95_64, {G_95_80,G_79_64}, {P_95_80,P_79_64}); - black b_127_96 (G_127_96, P_127_96, {G_127_112,G_111_96}, {P_127_112,P_111_96}); - - // Stage 6: Generates G/P pairs that span 32 bits - grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32); - black b_127_64 (G_127_64, P_127_64, {G_127_96,G_95_64}, {P_127_96,P_95_64}); - - // Stage 7: Generates G/P pairs that span 64 bits - grey g_127_0 (G_127_0, {G_127_64,G_63_0}, P_127_64); - - // Stage 8: Generates G/P pairs that span 32 bits - grey g_95_0 (G_95_0, {G_95_64,G_63_0}, P_95_64); - - // Stage 9: Generates G/P pairs that span 16 bits - grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32); - grey g_79_0 (G_79_0, {G_79_64,G_63_0}, P_79_64); - grey g_111_0 (G_111_0, {G_111_96,G_95_0}, P_111_96); - - // Stage 10: Generates G/P pairs that span 8 bits - grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16); - grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32); - grey g_55_0 (G_55_0, {G_55_48,G_47_0}, P_55_48); - grey g_71_0 (G_71_0, {G_71_64,G_63_0}, P_71_64); - grey g_87_0 (G_87_0, {G_87_80,G_79_0}, P_87_80); - grey g_103_0 (G_103_0, {G_103_96,G_95_0}, P_103_96); - grey g_119_0 (G_119_0, {G_119_112,G_111_0}, P_119_112); - - // Stage 11: Generates G/P pairs that span 4 bits - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16); - grey g_27_0 (G_27_0, {G_27_24,G_23_0}, P_27_24); - grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32); - grey g_43_0 (G_43_0, {G_43_40,G_39_0}, P_43_40); - grey g_51_0 (G_51_0, {G_51_48,G_47_0}, P_51_48); - grey g_59_0 (G_59_0, {G_59_56,G_55_0}, P_59_56); - grey g_67_0 (G_67_0, {G_67_64,G_63_0}, P_67_64); - grey g_75_0 (G_75_0, {G_75_72,G_71_0}, P_75_72); - grey g_83_0 (G_83_0, {G_83_80,G_79_0}, P_83_80); - grey g_91_0 (G_91_0, {G_91_88,G_87_0}, P_91_88); - grey g_99_0 (G_99_0, {G_99_96,G_95_0}, P_99_96); - grey g_107_0 (G_107_0, {G_107_104,G_103_0}, P_107_104); - grey g_115_0 (G_115_0, {G_115_112,G_111_0}, P_115_112); - grey g_123_0 (G_123_0, {G_123_120,G_119_0}, P_123_120); - - // Stage 12: Generates G/P pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12); - grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16); - grey g_21_0 (G_21_0, {G_21_20,G_19_0}, P_21_20); - grey g_25_0 (G_25_0, {G_25_24,G_23_0}, P_25_24); - grey g_29_0 (G_29_0, {G_29_28,G_27_0}, P_29_28); - grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32); - grey g_37_0 (G_37_0, {G_37_36,G_35_0}, P_37_36); - grey g_41_0 (G_41_0, {G_41_40,G_39_0}, P_41_40); - grey g_45_0 (G_45_0, {G_45_44,G_43_0}, P_45_44); - grey g_49_0 (G_49_0, {G_49_48,G_47_0}, P_49_48); - grey g_53_0 (G_53_0, {G_53_52,G_51_0}, P_53_52); - grey g_57_0 (G_57_0, {G_57_56,G_55_0}, P_57_56); - grey g_61_0 (G_61_0, {G_61_60,G_59_0}, P_61_60); - grey g_65_0 (G_65_0, {G_65_64,G_63_0}, P_65_64); - grey g_69_0 (G_69_0, {G_69_68,G_67_0}, P_69_68); - grey g_73_0 (G_73_0, {G_73_72,G_71_0}, P_73_72); - grey g_77_0 (G_77_0, {G_77_76,G_75_0}, P_77_76); - grey g_81_0 (G_81_0, {G_81_80,G_79_0}, P_81_80); - grey g_85_0 (G_85_0, {G_85_84,G_83_0}, P_85_84); - grey g_89_0 (G_89_0, {G_89_88,G_87_0}, P_89_88); - grey g_93_0 (G_93_0, {G_93_92,G_91_0}, P_93_92); - grey g_97_0 (G_97_0, {G_97_96,G_95_0}, P_97_96); - grey g_101_0 (G_101_0, {G_101_100,G_99_0}, P_101_100); - grey g_105_0 (G_105_0, {G_105_104,G_103_0}, P_105_104); - grey g_109_0 (G_109_0, {G_109_108,G_107_0}, P_109_108); - grey g_113_0 (G_113_0, {G_113_112,G_111_0}, P_113_112); - grey g_117_0 (G_117_0, {G_117_116,G_115_0}, P_117_116); - grey g_121_0 (G_121_0, {G_121_120,G_119_0}, P_121_120); - grey g_125_0 (G_125_0, {G_125_124,G_123_0}, P_125_124); - - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]); - grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]); - grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]); - grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]); - grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]); - grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]); - grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]); - grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]); - grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]); - grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]); - grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]); - grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]); - grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]); - grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]); - grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]); - grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]); - grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]); - grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]); - grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]); - grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]); - grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]); - grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]); - grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]); - grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]); - grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]); - grey g_64_0 (G_64_0, {g[64],G_63_0}, p[64]); - grey g_66_0 (G_66_0, {g[66],G_65_0}, p[66]); - grey g_68_0 (G_68_0, {g[68],G_67_0}, p[68]); - grey g_70_0 (G_70_0, {g[70],G_69_0}, p[70]); - grey g_72_0 (G_72_0, {g[72],G_71_0}, p[72]); - grey g_74_0 (G_74_0, {g[74],G_73_0}, p[74]); - grey g_76_0 (G_76_0, {g[76],G_75_0}, p[76]); - grey g_78_0 (G_78_0, {g[78],G_77_0}, p[78]); - grey g_80_0 (G_80_0, {g[80],G_79_0}, p[80]); - grey g_82_0 (G_82_0, {g[82],G_81_0}, p[82]); - grey g_84_0 (G_84_0, {g[84],G_83_0}, p[84]); - grey g_86_0 (G_86_0, {g[86],G_85_0}, p[86]); - grey g_88_0 (G_88_0, {g[88],G_87_0}, p[88]); - grey g_90_0 (G_90_0, {g[90],G_89_0}, p[90]); - grey g_92_0 (G_92_0, {g[92],G_91_0}, p[92]); - grey g_94_0 (G_94_0, {g[94],G_93_0}, p[94]); - grey g_96_0 (G_96_0, {g[96],G_95_0}, p[96]); - grey g_98_0 (G_98_0, {g[98],G_97_0}, p[98]); - grey g_100_0 (G_100_0, {g[100],G_99_0}, p[100]); - grey g_102_0 (G_102_0, {g[102],G_101_0}, p[102]); - grey g_104_0 (G_104_0, {g[104],G_103_0}, p[104]); - grey g_106_0 (G_106_0, {g[106],G_105_0}, p[106]); - grey g_108_0 (G_108_0, {g[108],G_107_0}, p[108]); - grey g_110_0 (G_110_0, {g[110],G_109_0}, p[110]); - grey g_112_0 (G_112_0, {g[112],G_111_0}, p[112]); - grey g_114_0 (G_114_0, {g[114],G_113_0}, p[114]); - grey g_116_0 (G_116_0, {g[116],G_115_0}, p[116]); - grey g_118_0 (G_118_0, {g[118],G_117_0}, p[118]); - grey g_120_0 (G_120_0, {g[120],G_119_0}, p[120]); - grey g_122_0 (G_122_0, {g[122],G_121_0}, p[122]); - grey g_124_0 (G_124_0, {g[124],G_123_0}, p[124]); - grey g_126_0 (G_126_0, {g[126],G_125_0}, p[126]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - assign c[15]=G_14_0; - assign c[16]=G_15_0; - assign c[17]=G_16_0; - - assign c[18]=G_17_0; - assign c[19]=G_18_0; - assign c[20]=G_19_0; - assign c[21]=G_20_0; - assign c[22]=G_21_0; - assign c[23]=G_22_0; - assign c[24]=G_23_0; - assign c[25]=G_24_0; - - assign c[26]=G_25_0; - assign c[27]=G_26_0; - assign c[28]=G_27_0; - assign c[29]=G_28_0; - assign c[30]=G_29_0; - assign c[31]=G_30_0; - assign c[32]=G_31_0; - assign c[33]=G_32_0; - - assign c[34]=G_33_0; - assign c[35]=G_34_0; - assign c[36]=G_35_0; - assign c[37]=G_36_0; - assign c[38]=G_37_0; - assign c[39]=G_38_0; - assign c[40]=G_39_0; - assign c[41]=G_40_0; - - assign c[42]=G_41_0; - assign c[43]=G_42_0; - assign c[44]=G_43_0; - assign c[45]=G_44_0; - assign c[46]=G_45_0; - assign c[47]=G_46_0; - assign c[48]=G_47_0; - assign c[49]=G_48_0; - - assign c[50]=G_49_0; - assign c[51]=G_50_0; - assign c[52]=G_51_0; - assign c[53]=G_52_0; - assign c[54]=G_53_0; - assign c[55]=G_54_0; - assign c[56]=G_55_0; - assign c[57]=G_56_0; - - assign c[58]=G_57_0; - assign c[59]=G_58_0; - assign c[60]=G_59_0; - assign c[61]=G_60_0; - assign c[62]=G_61_0; - assign c[63]=G_62_0; - assign c[64]=G_63_0; - assign c[65]=G_64_0; - - assign c[66]=G_65_0; - assign c[67]=G_66_0; - assign c[68]=G_67_0; - assign c[69]=G_68_0; - assign c[70]=G_69_0; - assign c[71]=G_70_0; - assign c[72]=G_71_0; - assign c[73]=G_72_0; - - assign c[74]=G_73_0; - assign c[75]=G_74_0; - assign c[76]=G_75_0; - assign c[77]=G_76_0; - assign c[78]=G_77_0; - assign c[79]=G_78_0; - assign c[80]=G_79_0; - assign c[81]=G_80_0; - - assign c[82]=G_81_0; - assign c[83]=G_82_0; - assign c[84]=G_83_0; - assign c[85]=G_84_0; - assign c[86]=G_85_0; - assign c[87]=G_86_0; - assign c[88]=G_87_0; - assign c[89]=G_88_0; - - assign c[90]=G_89_0; - assign c[91]=G_90_0; - assign c[92]=G_91_0; - assign c[93]=G_92_0; - assign c[94]=G_93_0; - assign c[95]=G_94_0; - assign c[96]=G_95_0; - assign c[97]=G_96_0; - - assign c[98]=G_97_0; - assign c[99]=G_98_0; - assign c[100]=G_99_0; - assign c[101]=G_100_0; - assign c[102]=G_101_0; - assign c[103]=G_102_0; - assign c[104]=G_103_0; - assign c[105]=G_104_0; - - assign c[106]=G_105_0; - assign c[107]=G_106_0; - assign c[108]=G_107_0; - assign c[109]=G_108_0; - assign c[110]=G_109_0; - assign c[111]=G_110_0; - assign c[112]=G_111_0; - assign c[113]=G_112_0; - - assign c[114]=G_113_0; - assign c[115]=G_114_0; - assign c[116]=G_115_0; - assign c[117]=G_116_0; - assign c[118]=G_117_0; - assign c[119]=G_118_0; - assign c[120]=G_119_0; - assign c[121]=G_120_0; - - assign c[122]=G_121_0; - assign c[123]=G_122_0; - assign c[124]=G_123_0; - assign c[125]=G_124_0; - assign c[126]=G_125_0; - assign c[127]=G_126_0; - assign c[128]=G_127_0; - -endmodule // brent_kung_cs - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule // black - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule // grey - diff --git a/wally-pipelined/src/fpu/dev/bk13.v b/wally-pipelined/src/fpu/dev/bk13.v deleted file mode 100755 index e47493e11..000000000 --- a/wally-pipelined/src/fpu/dev/bk13.v +++ /dev/null @@ -1,120 +0,0 @@ -// Brent-Kung Carry-save Prefix Adder - -module exp_add (cout, sum, a, b, cin); - input [12:0] a, b; - input cin; - output [12:0] sum; - output cout; - - wire [13:0] p,g,t; - wire [12:0] c; - -// pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - assign t[1]=p[1]; - assign t[2]=p[2]; - assign t[3]=p[3]^g[2]; - assign t[4]=p[4]; - assign t[5]=p[5]^g[4]; - assign t[6]=p[6]; - assign t[7]=p[7]^g[6]; - assign t[8]=p[8]; - assign t[9]=p[9]^g[8]; - assign t[10]=p[10]; - assign t[11]=p[11]^g[10]; - assign t[12]=p[12]; - assign t[13]=p[13]; - -// prefix tree - brent_kung_cs prefix_tree(c, p[12:0], g[12:0]); - -// post-computation - assign sum=p[13:1]^c; - assign cout=g[13]|(p[13]&c[12]); - -endmodule - -module brent_kung_cs (c, p, g); - - input [13:0] p; - input [13:0] g; - output [13:1] c; - - - // parallel-prefix, Brent-Kung - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - - // Stage 4: Generates G/P pairs that span 8 bits - - // Stage 5: Generates G/P pairs that span 4 bits - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - - // Stage 6: Generates G/P pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - -endmodule - - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule diff --git a/wally-pipelined/src/fpu/dev/bk14.v b/wally-pipelined/src/fpu/dev/bk14.v deleted file mode 100755 index 5e1eb5a6d..000000000 --- a/wally-pipelined/src/fpu/dev/bk14.v +++ /dev/null @@ -1,109 +0,0 @@ -// Brent-Kung Prefix Adder - -module add (cout, sum, a, b, cin); - input [13:0] a, b; - input cin; - output [13:0] sum; - output cout; - - wire [14:0] p,g; - wire [13:0] c; - -// pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - -// prefix tree - brent_kung prefix_tree(c, p[13:0], g[13:0]); - -// post-computation - assign sum=p[14:1]^c; - assign cout=g[14]|(p[14]&c[13]); - -endmodule - -module brent_kung (c, p, g); - - input [13:0] p; - input [13:0] g; - output [14:1] c; - - - // parallel-prefix, Brent-Kung - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - - // Stage 4: Generates G/P pairs that span 8 bits - - // Stage 5: Generates G/P pairs that span 4 bits - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - - // Stage 6: Generates G/P pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12); - - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - -endmodule - - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule diff --git a/wally-pipelined/src/fpu/dev/bk15.v b/wally-pipelined/src/fpu/dev/bk15.v deleted file mode 100755 index 3e79c6740..000000000 --- a/wally-pipelined/src/fpu/dev/bk15.v +++ /dev/null @@ -1,155 +0,0 @@ -// Kogge-Stone Prefix Adder -module bk15 (cout, sum, a, b, cin); - - input [14:0] a, b; - input cin; - - output [14:0] sum; - output cout; - - wire [15:0] p,g; - wire [15:1] h,c; - - // pre-computation - assign p={a|b,1'b1}; - assign g={a&b, cin}; - - // prefix tree - kogge_stone prefix_tree(h, c, p[14:0], g[14:0]); - - // post-computation - assign h[15]=g[15]|c[15]; - assign sum=p[15:1]^h|g[15:1]&c; - assign cout=p[15]&h[15]; - -endmodule // bk15 - -module kogge_stone (h, c, p, g); - - input [14:0] p; - input [14:0] g; - - output [15:1] h; - output [15:1] c; - - // parallel-prefix, Kogge-Stone - - // Stage 1: Generates G/P pairs that span 1 bits - rgry g_1_0 (H_1_0, {g[1],g[0]}); - rblk b_2_1 (H_2_1, I_2_1, {g[2],g[1]}, {p[1],p[0]}); - rblk b_3_2 (H_3_2, I_3_2, {g[3],g[2]}, {p[2],p[1]}); - rblk b_4_3 (H_4_3, I_4_3, {g[4],g[3]}, {p[3],p[2]}); - rblk b_5_4 (H_5_4, I_5_4, {g[5],g[4]}, {p[4],p[3]}); - rblk b_6_5 (H_6_5, I_6_5, {g[6],g[5]}, {p[5],p[4]}); - rblk b_7_6 (H_7_6, I_7_6, {g[7],g[6]}, {p[6],p[5]}); - rblk b_8_7 (H_8_7, I_8_7, {g[8],g[7]}, {p[7],p[6]}); - - rblk b_9_8 (H_9_8, I_9_8, {g[9],g[8]}, {p[8],p[7]}); - rblk b_10_9 (H_10_9, I_10_9, {g[10],g[9]}, {p[9],p[8]}); - rblk b_11_10 (H_11_10, I_11_10, {g[11],g[10]}, {p[10],p[9]}); - rblk b_12_11 (H_12_11, I_12_11, {g[12],g[11]}, {p[11],p[10]}); - rblk b_13_12 (H_13_12, I_13_12, {g[13],g[12]}, {p[12],p[11]}); - rblk b_14_13 (H_14_13, I_14_13, {g[14],g[13]}, {p[13],p[12]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_2_0 (H_2_0, {H_2_1,g[0]}, I_2_1); - grey g_3_0 (H_3_0, {H_3_2,H_1_0}, I_3_2); - black b_4_1 (H_4_1, I_4_1, {H_4_3,H_2_1}, {I_4_3,I_2_1}); - black b_5_2 (H_5_2, I_5_2, {H_5_4,H_3_2}, {I_5_4,I_3_2}); - black b_6_3 (H_6_3, I_6_3, {H_6_5,H_4_3}, {I_6_5,I_4_3}); - black b_7_4 (H_7_4, I_7_4, {H_7_6,H_5_4}, {I_7_6,I_5_4}); - black b_8_5 (H_8_5, I_8_5, {H_8_7,H_6_5}, {I_8_7,I_6_5}); - black b_9_6 (H_9_6, I_9_6, {H_9_8,H_7_6}, {I_9_8,I_7_6}); - - black b_10_7 (H_10_7, I_10_7, {H_10_9,H_8_7}, {I_10_9,I_8_7}); - black b_11_8 (H_11_8, I_11_8, {H_11_10,H_9_8}, {I_11_10,I_9_8}); - black b_12_9 (H_12_9, I_12_9, {H_12_11,H_10_9}, {I_12_11,I_10_9}); - black b_13_10 (H_13_10, I_13_10, {H_13_12,H_11_10}, {I_13_12,I_11_10}); - black b_14_11 (H_14_11, I_14_11, {H_14_13,H_12_11}, {I_14_13,I_12_11}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_4_0 (H_4_0, {H_4_1,g[0]}, I_4_1); - grey g_5_0 (H_5_0, {H_5_2,H_1_0}, I_5_2); - grey g_6_0 (H_6_0, {H_6_3,H_2_0}, I_6_3); - grey g_7_0 (H_7_0, {H_7_4,H_3_0}, I_7_4); - black b_8_1 (H_8_1, I_8_1, {H_8_5,H_4_1}, {I_8_5,I_4_1}); - black b_9_2 (H_9_2, I_9_2, {H_9_6,H_5_2}, {I_9_6,I_5_2}); - black b_10_3 (H_10_3, I_10_3, {H_10_7,H_6_3}, {I_10_7,I_6_3}); - black b_11_4 (H_11_4, I_11_4, {H_11_8,H_7_4}, {I_11_8,I_7_4}); - - black b_12_5 (H_12_5, I_12_5, {H_12_9,H_8_5}, {I_12_9,I_8_5}); - black b_13_6 (H_13_6, I_13_6, {H_13_10,H_9_6}, {I_13_10,I_9_6}); - black b_14_7 (H_14_7, I_14_7, {H_14_11,H_10_7}, {I_14_11,I_10_7}); - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_8_0 (H_8_0, {H_8_1,g[0]}, I_8_1); - grey g_9_0 (H_9_0, {H_9_2,H_1_0}, I_9_2); - grey g_10_0 (H_10_0, {H_10_3,H_2_0}, I_10_3); - grey g_11_0 (H_11_0, {H_11_4,H_3_0}, I_11_4); - grey g_12_0 (H_12_0, {H_12_5,H_4_0}, I_12_5); - grey g_13_0 (H_13_0, {H_13_6,H_5_0}, I_13_6); - grey g_14_0 (H_14_0, {H_14_7,H_6_0}, I_14_7); - - // Final Stage: Apply c_k+1=p_k&H_k_0 - assign c[1]=g[0]; - - assign h[1]=H_1_0; assign c[2]=p[1]&H_1_0; - assign h[2]=H_2_0; assign c[3]=p[2]&H_2_0; - assign h[3]=H_3_0; assign c[4]=p[3]&H_3_0; - assign h[4]=H_4_0; assign c[5]=p[4]&H_4_0; - assign h[5]=H_5_0; assign c[6]=p[5]&H_5_0; - assign h[6]=H_6_0; assign c[7]=p[6]&H_6_0; - assign h[7]=H_7_0; assign c[8]=p[7]&H_7_0; - assign h[8]=H_8_0; assign c[9]=p[8]&H_8_0; - - assign h[9]=H_9_0; assign c[10]=p[9]&H_9_0; - assign h[10]=H_10_0; assign c[11]=p[10]&H_10_0; - assign h[11]=H_11_0; assign c[12]=p[11]&H_11_0; - assign h[12]=H_12_0; assign c[13]=p[12]&H_12_0; - assign h[13]=H_13_0; assign c[14]=p[13]&H_13_0; - assign h[14]=H_14_0; assign c[15]=p[14]&H_14_0; - -endmodule // kogge_stone - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule // black - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule // grey - -// reduced Black cell -module rblk(hout, iout, gin, pin); - - input [1:0] gin, pin; - output hout, iout; - - assign iout=pin[1]&pin[0]; - assign hout=gin[1]|gin[0]; - -endmodule // rblk - -// reduced Grey cell -module rgry(hout, gin); - - input[1:0] gin; - output hout; - - assign hout=gin[1]|gin[0]; - -endmodule // rgry diff --git a/wally-pipelined/src/fpu/dev/cla12.v b/wally-pipelined/src/fpu/dev/cla12.v deleted file mode 100755 index 46b8ba99f..000000000 --- a/wally-pipelined/src/fpu/dev/cla12.v +++ /dev/null @@ -1,331 +0,0 @@ -// This module implements a 12-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla12 (S, CO, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - output CO; - - wire [0:63] A,B,Q; - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO = Q[12]; - -endmodule //cla52 - -// This module implements a 12-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub12 (S, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - - wire [0:63] A,B,Q,Bbar; - wire CO; - wire LOGIC0; - wire VDD; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign VDD = 1; - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO_12 = Q[12]; - -endmodule //cla_sub52 diff --git a/wally-pipelined/src/fpu/dev/cla52.v b/wally-pipelined/src/fpu/dev/cla52.v deleted file mode 100755 index 6cc55faf5..000000000 --- a/wally-pipelined/src/fpu/dev/cla52.v +++ /dev/null @@ -1,408 +0,0 @@ -// This module implements a 52-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla52 (S, CO, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - output CO; - - wire [0:63] A,B,Q; - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO = Q[52]; - -endmodule //cla52 - -// This module implements a 52-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub52 (S, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - - wire [0:63] A,B,Q,Bbar; - wire LOGIC0; - wire CIN; - wire CO_52; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , Bbar , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO_52 = Q[52]; - -endmodule //cla_sub52 diff --git a/wally-pipelined/src/fpu/dev/cla64.v b/wally-pipelined/src/fpu/dev/cla64.v deleted file mode 100755 index a0809e9d1..000000000 --- a/wally-pipelined/src/fpu/dev/cla64.v +++ /dev/null @@ -1,420 +0,0 @@ -// This module implements a 64-bit carry lookehead adder/subtractor. -// It is used to perform the primary addition in the floating point -// adder - -module cla64 (S, X, Y, Sub); - - input [63:0] X; - input [63:0] Y; - input Sub; - output [63:0] S; - wire CO; - wire [0:63] A,B,Q, Bbar; - - DBLCADDER_64_64 U1 (A , Bbar , Sub , Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = B ^ {64{Sub}}; - -endmodule // cla64 - -// This module performs 64-bit subtraction. It is used to get the two's complement -// of main addition or subtraction in the floating point adder. - -module cla_sub64 (S, X, Y); - - input [63:0] X; - input [63:0] Y; - - output [63:0] S; - - wire CO; - wire VDD = 1'b1; - wire [0:63] A,B,Q, Bbar; - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = ~B; - -endmodule // cla_sub64 \ No newline at end of file diff --git a/wally-pipelined/src/fpu/dev/convert_inputs.v b/wally-pipelined/src/fpu/dev/convert_inputs.v deleted file mode 100755 index e5dc96d79..000000000 --- a/wally-pipelined/src/fpu/dev/convert_inputs.v +++ /dev/null @@ -1,61 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// the operation type (op_type) and the result precision (P). -// Based on the operation and precision , it conditionally -// converts single precision values to double precision values -// and modifies the sign of op1. The converted operands are Float1 -// and Float2. - -module convert_inputs(Float1, Float2, op1, op2, op_type, P); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [3:0] op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - - output [63:0] Float1; // Converted 1st input operand - output [63:0] Float2; // Converted 2nd input operand - - wire conv_SP; // Convert from SP to DP - wire negate; // Operation is negation - wire abs_val; // Operation is absolute value - wire Zexp1; // One if the exponent of op1 is zero - wire Zexp2; // One if the exponent of op2 is zero - wire Oexp1; // One if the exponent of op1 is all ones - wire Oexp2; // One if the exponent of op2 is all ones - - // Convert from single precision to double precision if (op_type is 11X - // and P is 0) or (op_type is not 11X and P is one). - assign conv_SP = (op_type[2]&op_type[1]) ^ P; - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] | - op1[58] | op1[57] | op1[56] | op1[55]); - assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] | - op2[58] | op2[57] | op2[56] | op2[55]); - assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] & - op1[58] & op1[57] & op1[56] & op1[55]); - assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] & - op2[58] & op2[57] & op2[56] &op2[55]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = conv_SP ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~conv_SP}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = conv_SP ? {op2[62], - {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~conv_SP}}; - - // Set the sign of Float1 based on its original sign and if the operation - // is negation (op_type = 101) or absolute value (op_type = 100) - - assign negate = op_type[2] & ~op_type[1] & op_type[0]; - assign abs_val = op_type[2] & ~op_type[1] & ~op_type[0]; - assign Float1[63] = (op1[63] ^ negate) & ~abs_val; - assign Float2[63] = op2[63]; - -endmodule // convert_inputs - diff --git a/wally-pipelined/src/fpu/dev/convert_inputs_div.v b/wally-pipelined/src/fpu/dev/convert_inputs_div.v deleted file mode 100755 index c4538c6e0..000000000 --- a/wally-pipelined/src/fpu/dev/convert_inputs_div.v +++ /dev/null @@ -1,51 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// and the result precision (P). Based on the operation and precision, -// it conditionally converts single precision values to double -// precision values and modifies the sign of op1. -// The converted operands are Float1 and Float2. - -module convert_inputs_div (Float1, Float2b, op1, op2, op_type, P); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input P; // Result Precision (0 for double, 1 for single) - input op_type; // Operation - - output [63:0] Float1; // Converted 1st input operand - output [63:0] Float2b; // Converted 2nd input operand - - wire [63:0] Float2; - wire Zexp1; // One if the exponent of op1 is zero - wire Zexp2; // One if the exponent of op2 is zero - wire Oexp1; // One if the exponent of op1 is all ones - wire Oexp2; // One if the exponent of op2 is all ones - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] | - op1[58] | op1[57] | op1[56] | op1[55]); - assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] | - op2[58] | op2[57] | op2[56] | op2[55]); - assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] & - op1[58] & op1[57] & op1[56] & op1[55]); - assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] & - op2[58] & op2[57] & op2[56] &op2[55]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~P}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~P}}; - - // Set the sign of Float1 based on its original sign - assign Float1[63] = op1[63]; - assign Float2[63] = op2[63]; - - // For sqrt, assign Float2 same as Float1 for simplicity - assign Float2b = op_type ? Float1 : Float2; - -endmodule // convert_inputs diff --git a/wally-pipelined/src/fpu/dev/exception.v b/wally-pipelined/src/fpu/dev/exception.v deleted file mode 100755 index d1d767dd7..000000000 --- a/wally-pipelined/src/fpu/dev/exception.v +++ /dev/null @@ -1,120 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. - -module exception (Ztype, Invalid, Denorm, ANorm, BNorm, Sub, A, B, op_type); - - input [63:0] A; // 1st input operand (op1) - input [63:0] B; // 2nd input operand (op2) - input [3:0] op_type; // Function opcode - output [3:0] Ztype; // Indicates type of result (Z) - output Invalid; // Invalid operation exception - output Denorm; // Denormalized input - output ANorm; // A is not zero or Denorm - output BNorm; // B is not zero or Denorm - output Sub; // The effective operation is subtraction - wire AzeroM; // '1' if the mantissa of A is zero - wire BzeroM; // '1' if the mantissa of B is zero - wire AzeroE; // '1' if the exponent of A is zero - wire BzeroE; // '1' if the exponent of B is zero - wire AonesE; // '1' if the exponent of A is all ones - wire BonesE; // '1' if the exponent of B is all ones - wire ADenorm; // '1' if A is a denomalized number - wire BDenorm; // '1' if B is a denomalized number - wire AInf; // '1' if A is infinite - wire BInf; // '1' if B is infinite - wire AZero; // '1' if A is 0 - wire BZero; // '1' if B is 0 - wire ANaN; // '1' if A is a not-a-number - wire BNaN; // '1' if B is a not-a-number - wire ASNaN; // '1' if A is a signalling not-a-number - wire BSNaN; // '1' if B is a signalling not-a-number - wire ZQNaN; // '1' if result Z is a quiet NaN - wire ZPInf; // '1' if result Z positive infnity - wire ZNInf; // '1' if result Z negative infnity - wire add_sub; // '1' if operation is add or subtract - wire converts; // See if there are any converts - - parameter [51:0] fifty_two_zeros = 52'h0000000000000; // Use parameter? - - - // Is this instruction a convert - assign converts = ~(~op_type[1] & ~op_type[2]); - - // Determine if mantissas are all zeros - assign AzeroM = (A[51:0] == fifty_two_zeros); - assign BzeroM = (B[51:0] == fifty_two_zeros); - - // Determine if exponents are all ones or all zeros - assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]; - assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]; - assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]); - assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]); - - // Determine special cases. Note: Zero is not really a special case. - assign ADenorm = AzeroE & ~AzeroM; - assign BDenorm = BzeroE & ~BzeroM; - assign AInf = AonesE & AzeroM; - assign BInf = BonesE & BzeroM; - assign ANaN = AonesE & ~AzeroM; - assign BNaN = BonesE & ~BzeroM; - assign ASNaN = ANaN & ~A[51]; - assign BSNaN = BNaN & ~B[51]; - assign AZero = AzeroE & AzeroM; - assign BZero = BzeroE & BzeroE; - - // A and B are normalized if their exponents are not zero. - assign ANorm = ~AzeroE; - assign BNorm = ~BzeroE; - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite and the "effective operation" is - // subtraction). - assign add_sub = ~op_type[2] & ~op_type[1]; - assign Invalid = (ASNaN | BSNaN | - (add_sub & AInf & BInf & (A[63]^B[63]^op_type[0]))) & ~converts; - - // The Denorm flag is set if (A is denormlized and the operation is not integer - // conversion ) or (if B is normalized and the operation is addition or subtraction). - assign Denorm = ADenorm&(op_type[2]|~op_type[1]) | BDenorm & add_sub; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN and the operation uses B). - assign ZQNaN = Invalid | ANaN | (BNaN & add_sub); - - // The result is +Inf if ((A is +Inf) or (B is -Inf and the operation is - // subtraction) or (B is +Inf and the operation is addition)) and (the - // result is not a quiet NaN). - assign ZPInf = (AInf&A[63] | add_sub&BInf&(~B[63]^op_type[0]))&~ZQNaN; - - // The result is -Inf if ((A is -Inf) or (B is +Inf and the operation is - // subtraction) or (B is -Inf and the operation is addition)) and the - // result is not a quiet NaN. - assign ZNInf = (AInf&~A[63] | add_sub&BInf&(B[63]^op_type[0]))&~ZQNaN; - - // Set the type of the result as follows: - // (needs optimization - got lazy or was late) - // Ztype Result - // 0000 Normal - // 0001 Quiet NaN - // 0010 Negative Infinity - // 0011 Positive Infinity - // 0100 +Bzero and +Azero (and vice-versa) - // 0101 +Bzero and -Azero (and vice-versa) - // 1000 Convert SP to DP (and vice-versa) - - assign Ztype[0] = ((ZQNaN | ZPInf) & ~(~op_type[2] & op_type[1])) | - ((AZero & BZero & (A[63]^B[63]^op_type[0])) - & ~converts); - assign Ztype[1] = ((ZNInf | ZPInf) & ~(~op_type[2] & op_type[1])) | - (((AZero & BZero & A[63] & B[63] & ~op_type[0]) | - (AZero & BZero & A[63] & ~B[63] & op_type[0])) - & ~converts); - assign Ztype[2] = ((AZero & BZero & ~op_type[1] & ~op_type[2]) - & ~converts); - assign Ztype[3] = (op_type[1] & op_type[2] & ~op_type[0]); - - // Determine if the effective operation is subtraction - assign Sub = ~(op_type[3] & ~op_type[0]) & ( (op_type[3] & op_type[0]) | (add_sub & (A[63]^B[63]^op_type[0])) ); - -endmodule // exception - diff --git a/wally-pipelined/src/fpu/dev/exception_div.v b/wally-pipelined/src/fpu/dev/exception_div.v deleted file mode 100755 index b074c4e60..000000000 --- a/wally-pipelined/src/fpu/dev/exception_div.v +++ /dev/null @@ -1,96 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. - -module exception_div (Ztype, Invalid, Denorm, ANorm, BNorm, A, B, op_type); - - input [63:0] A; // 1st input operand (op1) - input [63:0] B; // 2nd input operand (op2) - input op_type; // Determine operation - - output [2:0] Ztype; // Indicates type of result (Z) - output Invalid; // Invalid operation exception - output Denorm; // Denormalized input - output ANorm; // A is not zero or Denorm - output BNorm; // B is not zero or Denorm - - wire AzeroM; // '1' if the mantissa of A is zero - wire BzeroM; // '1' if the mantissa of B is zero - wire AzeroE; // '1' if the exponent of A is zero - wire BzeroE; // '1' if the exponent of B is zero - wire AonesE; // '1' if the exponent of A is all ones - wire BonesE; // '1' if the exponent of B is all ones - wire ADenorm; // '1' if A is a denomalized number - wire BDenorm; // '1' if B is a denomalized number - wire AInf; // '1' if A is infinite - wire BInf; // '1' if B is infinite - wire AZero; // '1' if A is 0 - wire BZero; // '1' if B is 0 - wire ANaN; // '1' if A is a not-a-number - wire BNaN; // '1' if B is a not-a-number - wire ASNaN; // '1' if A is a signalling not-a-number - wire BSNaN; // '1' if B is a signalling not-a-number - wire ZQNaN; // '1' if result Z is a quiet NaN - wire ZInf; // '1' if result Z is an infnity - wire square_root; // '1' if square root operation - wire Zero; // '1' if result is zero - - parameter [51:0] fifty_two_zeros = 52'h0; // Use parameter? - - // Determine if mantissas are all zeros - assign AzeroM = (A[51:0] == fifty_two_zeros); - assign BzeroM = (B[51:0] == fifty_two_zeros); - - // Determine if exponents are all ones or all zeros - assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]; - assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]; - assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]); - assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]); - - // Determine special cases. Note: Zero is not really a special case. - assign ADenorm = AzeroE & ~AzeroM; - assign BDenorm = BzeroE & ~BzeroM; - assign AInf = AonesE & AzeroM; - assign BInf = BonesE & BzeroM; - assign ANaN = AonesE & ~AzeroM; - assign BNaN = BonesE & ~BzeroM; - assign ASNaN = ANaN & A[50]; - assign BSNaN = ANaN & A[50]; - assign AZero = AzeroE & AzeroM; - assign BZero = BzeroE & BzeroE; - - // A and B are normalized if their exponents are not zero. - assign ANorm = ~AzeroE; - assign BNorm = ~BzeroE; - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite) - assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) | - (A[63] & op_type); - - // The Denorm flag is set if A is denormlized or if B is normalized - assign Denorm = ADenorm | BDenorm; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN). - assign ZQNaN = Invalid | ANaN | BNaN; - - // The result is zero - assign Zero = (AZero | BInf)&~op_type | AZero&op_type; - - // The result is +Inf if ((A is Inf) or (B is 0)) and (the - // result is not a quiet NaN). - assign ZInf = (AInf | BZero)&~ZQNaN&~op_type | AInf&op_type&~ZQNaN; - - // Set the type of the result as follows: - // Ztype Result - // 000 Normal - // 001 Quiet NaN - // 010 Infinity - // 011 Zero - // 110 DivZero - assign Ztype[0] = ZQNaN | Zero; - assign Ztype[1] = ZInf | Zero; - assign Ztype[2] = BZero&~op_type; - -endmodule // exception - diff --git a/wally-pipelined/src/fpu/dev/fctrl.sv b/wally-pipelined/src/fpu/dev/fctrl.sv deleted file mode 100755 index 175fb37ac..000000000 --- a/wally-pipelined/src/fpu/dev/fctrl.sv +++ /dev/null @@ -1,148 +0,0 @@ - -module fctrl ( - input logic [6:0] Funct7D, - input logic [6:0] OpD, - input logic [4:0] Rs2D, - input logic [4:0] Rs1D, - input logic [2:0] FrmW, - output logic WriteEnD, - output logic DivSqrtStartD, - //output logic [2:0] regSelD, - output logic [2:0] WriteSelD, - output logic [2:0] OpCtrlD, - output logic FmtD, - output logic WriteIntD); - - - - //precision is taken directly from instruction - assign FmtD = Funct7D[0]; - - //all subsequent logic is based on the table present - //in Section 5 of Wally Architecture Specification - - //write is enabled for all fp instruciton op codes - //sans fp load - logic isFP, isFPLD; - always_comb begin - //case statement is easier to modify - //in case of errors - case(OpD) - //fp instructions sans load - 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1000011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1000111 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1001011 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b1001111 : begin isFP = 1'b1; isFPLD = 1'b0; end - 7'b0100111 : begin isFP = 1'b1; isFPLD = 1'b0; end - //fp load - 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b1; end - default : begin isFP = 1'b0; isFPLD = 1'b0; end - endcase - end - - assign WriteEnD = isFP & ~isFPLD; - - //useful intermediary signals - // - //(mult only not supported in current datapath) - //set third FMA operand to zero in this case - //(or equivalent) - logic isAddSub, isFMA, isMult, isDivSqrt, isCvt, isCmp, isFPSTR; - - always_comb begin - //checks all but FMA/store/load - if(OpD == 7'b1010011) begin - case(Funct7D) - //compare - 7'b10100?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b1; isFPSTR = 1'b0; end - //div/sqrt - 7'b0?011?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b1; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //add/sub - 7'b0000??? : begin isAddSub = 1'b1; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //mult - 7'b00010?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b1; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //convert (not precision) - 7'b110?0?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end - //convert (precision) - 7'b010000? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end - endcase - end - //FMA/store/load - else begin - case(OpD) - //4 FMA instructions - 7'b1000011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1000111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1001011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - 7'b1001111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end - //store (load already found) - 7'b0100111 : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b1; end - endcase - end - end - - //register is chosen based on operation performed - //---- - //write selection is chosen in the same way as - //register selection - // - - // reg/write sel logic and assignment - // - // 3'b000 = add/sub/cvt - // 3'b001 = sign - // 3'b010 = fma - // 3'b011 = cmp - // 3'b100 = div/sqrt - // - //reg select - - //this value is used enough to be shorthand - logic isSign; - assign isSign = ~Funct7D[6] & ~Funct7D[5] & Funct7D[4] & ~Funct7D[3] & ~Funct7D[2]; - - //write select - assign WriteSelD[2] = isDivSqrt & ~isFMA; - assign WriteSelD[1] = isFMA | isCmp; - //AND of Funct7 for sign - assign WriteSelD[0] = isCmp | isSign; - - //if op is div/sqrt - start div/sqrt - assign DivSqrtStartD = isDivSqrt & ~isFMA; - - //operation control for each fp operation - //has to be expanded over standard to account for - //integrated fpadd/cvt - // - //will integrate FMA opcodes into design later - // - //conversion instructions will - //also need to be added later as I find the opcode - //version I used for this repo - - //let's do separate SOP for each type of operation -// assign OpCtrlD[3] = 1'b0; -// -// - - //add/cvt chooses unsigned conversion here - assign OpCtrlD[3] = (isAddSub & Rs2D[0]) | (isFMA & 1'b0) | (isDivSqrt & 1'b0) | (isCmp & 1'b0) | (isSign & 1'b0); - //add/cvt chooses FP/int or int/FP conversion - assign OpCtrlD[2] = (isAddSub & (Funct7D[6] & Funct7D[5] & ~Funct7D[4])) | (isFMA & 1'b0) | (isDivSqrt & 1'b0) | (isCmp & 1'b0) | (isSign & 1'b0); - //compare chooses equals - //sign chooses sgnjx - //add/cvt can chooses between abs/neg functions, but they aren't used in the - //wally-spec - assign OpCtrlD[1] = (isAddSub & 1'b0) | (isFMA & 1'b0) | (isDivSqrt & 1'b0) | (isCmp & FrmW[2]) | (isSign & FrmW[1]); - //divide chooses between div/sqrt - //compare chooses between LT and LE - //sign chooses between sgnj and sgnjn - //add/cvt chooses between add/sub or single-precision conversion - assign OpCtrlD[0] = (isAddSub & (Funct7D[2] | Funct7D[0])) | (isFMA & 1'b0) | (isDivSqrt & Funct7D[5]) | (isCmp & FrmW[1]) | (isSign & FrmW[0]); - - //write to integer source if conv to int occurs - //AND of Funct7 for int results - assign WriteIntD = isCvt & (Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); - -endmodule diff --git a/wally-pipelined/src/fpu/dev/fpadd_denorm.v b/wally-pipelined/src/fpu/dev/fpadd_denorm.v deleted file mode 100755 index e3919f28e..000000000 --- a/wally-pipelined/src/fpu/dev/fpadd_denorm.v +++ /dev/null @@ -1,274 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - - -module fpadd (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [2:0] rm; // Rounding mode - specify values - input [3:0] op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - - wire [63:0] Float1; - wire [63:0] Float2; - wire [63:0] IntValue; - wire [11:0] exp1, exp2; - wire [11:0] exp_diff1, exp_diff2; - wire [10:0] exponent, exp_pre; - wire [11:0] exp_shift; - wire [63:0] Result; - wire [51:0] mantissaA; - wire [56:0] mantissaA1; - wire [63:0] mantissaA3; - wire [51:0] mantissaB; - wire [56:0] mantissaB1, mantissaB2; - wire [63:0] mantissaB3; - wire [63:0] sum, sum_tc, sum_corr, sum_norm, sum_norm_w_bypass; - wire [5:0] align_shift; - wire [5:0] norm_shift, norm_shift_denorm; - wire [3:0] sel_inv; - wire op1_Norm, op2_Norm; - wire opA_Norm, opB_Norm; - wire Invalid; - wire DenormIn, DenormIO; - wire [4:0] FlagsIn; - wire exp_valid; - wire exp_gt63; - wire Sticky_out; - wire signA, sign_corr; - wire corr_sign; - wire zeroB; - wire convert; - wire swap; - wire sub; - wire [10:0] exponent_postsum; - wire mantissa_comp; - wire mantissa_comp_sum; - wire mantissa_comp_sum_tc; - wire Float1_sum_comp; - wire Float2_sum_comp; - wire Float1_sum_tc_comp; - wire Float2_sum_tc_comp; - wire [5:0] ZP_mantissaA; - wire [5:0] ZP_mantissaB; - wire ZV_mantissaA; - wire ZV_mantissaB; - wire normal_underflow; - wire normal_overflow; - - // Convert the input operands to their appropriate forms based on - // the orignal operands, the op_type , and their precision P. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - - convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P); - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if op1 and op2 are not zero or denormalized. - // sub is one if the effective operation is subtaction. - - exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, sub, - Float1, Float2, op_type); - - // Perform Exponent Subtraction (used for alignment). For performance - // both exponent subtractions are performed in parallel. This was - // changed to a behavior level to allow the tools to try to optimize - // the two parallel additions. The input values are zero-extended to 12 - // bits prior to performing the addition. - - assign exp1 = {1'b0, Float1[62:52]}; - assign exp2 = {1'b0, Float2[62:52]}; - assign exp_diff1 = exp1 - exp2; - assign exp_diff2 = DenormIn ? ({Float2[63], exp2[10:0]} - {Float1[63], exp1[10:0]}): exp2 - exp1; - - // The second operand (B) should be set to zero, if op_type does not - // specify addition or subtraction - assign zeroB = op_type[2] | op_type[1]; - - // Swapped operands if zeroB is not one and exp1 < exp2. - // Swapping causes exp2 to be used for the result exponent. - // Only the exponent of the larger operand is used to determine - // the final result. - assign swap = exp_diff1[11] & ~zeroB; - assign exponent = swap ? exp2[10:0] : exp1[10:0]; - assign exponent_postsum = swap ? exp2[10:0] : exp1[10:0]; - assign mantissaA = swap ? Float2[51:0] : Float1[51:0]; - assign mantissaB = swap ? Float1[51:0] : Float2[51:0]; - assign signA = swap ? Float2[63] : Float1[63]; - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - // modified to 52 bits to detect leading zeroes on denormalized mantissas - lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA); - lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB); - - // Denormalized exponents created by subtracting the leading zeroes from the original exponents - assign exp1_denorm = swap ? (exp1 - ZP_mantissaB) : (exp1 - ZP_mantissaA); - assign exp2_denorm = swap ? (exp2 - ZP_mantissaA) : (exp2 - ZP_mantissaB); - - // Finds normal underflow result to determine whether to round final exponent down - // Comparison between each float and the resulting sum of the primary cla adder/subtractor and cla subtractor - assign Float1_sum_comp = (Float1[51:0] > sum[51:0]) ? 1'b0 : 1'b1; - assign Float2_sum_comp = (Float2[51:0] > sum[51:0]) ? 1'b0 : 1'b1; - assign Float1_sum_tc_comp = (Float1[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1; - assign Float2_sum_tc_comp = (Float2[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1; - - // Determines the correct Float value to compare based on swap result - assign mantissa_comp_sum = swap ? Float2_sum_comp : Float1_sum_comp; - assign mantissa_comp_sum_tc = swap ? Float2_sum_tc_comp : Float1_sum_tc_comp; - - // Determines the correct comparison result based on operation and sign of resulting sum - assign mantissa_comp = (op_type[0] ^ sum[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum; - - // If the signs are different and both operands aren't denormalized - // the normal underflow bit is needed and therefore updated. - assign normal_underflow = ((Float1[63] ~^ Float2[63]) & (opA_Norm | opB_Norm)) ? mantissa_comp : 1'b0; - - // Determine the alignment shift and limit it to 63. If any bit from - // exp_shift[6] to exp_shift[11] is one, then shift is set to all ones. - assign exp_shift = swap ? exp_diff2 : exp_diff1; - assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9] - | exp_shift[8] | exp_shift[7] | exp_shift[6]; - assign align_shift = exp_shift | {6{exp_gt63}}; - - // Unpack the 52-bit mantissas to 57-bit numbers of the form. - // 001.M[51]M[50] ... M[1]M[0]00 - // Unless the number has an exponent of zero, in which case it - // is unpacked as - // 000.00 ... 00 - // This effectively flushes denormalized values to zero. - // The three bits of to the left of the binary point prevent overflow - // and loss of sign information. The two bits to the right of the - // original mantissa form the "guard" and "round" bits that are used - // to round the result. - assign opA_Norm = swap ? op2_Norm : op1_Norm; - assign opB_Norm = swap ? op1_Norm : op2_Norm; - assign mantissaA1 = {2'h0, opA_Norm, mantissaA[51:0]&{52{opA_Norm}}, 2'h0}; - assign mantissaB1 = {2'h0, opB_Norm, mantissaB[51:0]&{52{opB_Norm}}, 2'h0}; - - // Perform mantissa alignment using a 57-bit barrel shifter - // If any of the bits shifted out are one, Sticky_out is set. - // The size of the barrel shifter could be reduced by two bits - // by not adding the leading two zeros until after the shift. - barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift); - - // Place either the sign-extened 32-bit value or the original 64-bit value - // into IntValue (to be used for integer to floating point conversion) - assign IntValue [31:0] = op1[31:0]; - assign IntValue [63:32] = op_type[0] ? {32{op1[31]}} : op1[63:32]; - - // If doing an integer to floating point conversion, mantissaA3 is set to - // IntVal and the prenomalized exponent is set to 1084. Otherwise, - // mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero, - // and the exponent value is left unchanged. - // Under denormalized cases, the exponent before the rounder is set to 1 - // if the normal shift value is 11. - assign convert = ~op_type[2] & op_type[1]; - assign mantissaA3 = (op_type[3]) ? (op_type[0] ? Float1 : ~Float1) : (DenormIn ? ({12'h0, mantissaA}) : (convert ? IntValue : {mantissaA1, 7'h0})); - assign exp_pre = DenormIn ? - ((norm_shift == 6'b001011) ? 11'b00000000001 : (swap ? exp2_denorm : exp1_denorm)) - : (convert ? 11'b10000111100 : exponent); - - // Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to - // 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six - // zeros. - assign mantissaB3[63:7] = (op_type[3]) ? (57'h0) : (DenormIn ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}}); - assign mantissaB3[6] = (op_type[3]) ? (1'b0) : (DenormIn ? mantissaB[6] : Sticky_out & ~zeroB); - assign mantissaB3[5:0] = (op_type[3]) ? (6'h01) : (DenormIn ? mantissaB[5:0] : 6'h0); - - // The sign of the result needs to be corrected if the true - // operation is subtraction and the input operands were swapped. - assign corr_sign = ~op_type[2]&~op_type[1]&op_type[0]&swap; - - // 64-bit Mantissa Adder/Subtractor - cla64 add1 (sum, mantissaA3, mantissaB3, sub); - - // 64-bit Mantissa Subtractor - to get the two's complement of the - // result when the sign from the adder/subtractor is negative. - cla_sub64 sub1 (sum_tc, mantissaB3, mantissaA3); - - // Determine the correct sign of the result - assign sign_corr = ((corr_sign ^ signA) & ~convert) ^ sum[63]; - - // If the sum is negative, use its two complement instead. - // This value has to be 64-bits to correctly handle the - // case 10...00 - assign sum_corr = (DenormIn & (opA_Norm | opB_Norm) & ( ( (Float1[63] ~^ Float2[63]) & op_type[0] ) | ((Float1[63] ^ Float2[63]) & ~op_type[0]) )) - ? (sum[63] ? sum : sum_tc) : ( (op_type[3]) ? sum : (sum[63] ? sum_tc : sum)); - - // Finds normal underflow result to determine whether to round final exponent down - assign normal_overflow = (DenormIn & (sum == 16'h0) & (opA_Norm | opB_Norm) & ~op_type[0]) ? 1'b1 : (sum[63] ? sum_tc[52] : sum[52]); - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - lz64 lzd1 (norm_shift, exp_valid, sum_corr); - - assign norm_shift_denorm = (DenormIn & ( (~opA_Norm & ~opB_Norm) | normal_underflow)) ? (6'h00) : (norm_shift); - - // Barell shifter used for normalization. It takes as inputs the - // the corrected sum and the amount by which the sum should - // be right shifted. It outputs the normalized sum. - barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm); - - assign sum_norm_w_bypass = (op_type[3]) ? (op_type[0] ? ~sum_corr : sum_corr) : (sum_norm); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. If the result is a single precision number, the actual - // mantissa is in the upper 23 bits and the lower 29 bits are zero. - // At this point, normalization has already been performed, so we know - // exactly where the rounding point is. The rounding units also - // handles special cases and set the exception flags. - - // Changed DenormIO -> Denorm and FlagsIn -> Flags in order to - // help in processor reservation station detection of load/stores. In - // other words, the processor would like to know ahead of time that - // if the result is an exception then don't load or store. - rounder round1 (Result, DenormIO, FlagsIn, rm, P, OvEn, UnEn, exp_valid, - sel_inv, Invalid, DenormIn, convert, sign_corr, exp_pre, norm_shift, sum_norm_w_bypass, - exponent_postsum, op1_Norm, op2_Norm, Float1[63:52], Float2[63:52], - normal_overflow, normal_underflow, swap, op_type, sum); - - // Store the final result and the exception flags in registers. - assign AS_Result = Result; - assign {Denorm, Flags} = {DenormIO, FlagsIn}; - -endmodule // fpadd - - diff --git a/wally-pipelined/src/fpu/dev/fpdiv.v b/wally-pipelined/src/fpu/dev/fpdiv.v deleted file mode 100755 index da437a69f..000000000 --- a/wally-pipelined/src/fpu/dev/fpdiv.v +++ /dev/null @@ -1,248 +0,0 @@ -// -// File name : fpdiv -// Title : Floating-Point Divider/Square-Root -// project : FPU -// Library : fpdiv -// Author(s) : James E. Stine, Jr. -// Purpose : definition of main unit to floating-point div/sqrt -// notes : -// -// Copyright Oklahoma State University -// -// Basic Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Exponent Logic -// Step 4: Divide/Sqrt using Goldschmidt -// Step 5: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 6: Round the result.// -// Step 7: Put quotient/remainder onto output. -// - -`timescale 1ps/1ps -module fpdiv (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [1:0] rm; // Rounding mode - specify values - input op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - - input start; - input reset; - input clk; - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - output done; - - supply1 vdd; - supply0 vss; - - wire [63:0] Float1; - wire [63:0] Float2; - wire [63:0] IntValue; - - wire [12:0] exp1, exp2, expF; - wire [12:0] exp_diff, bias; - wire [13:0] exp_sqrt; - wire [12:0] exp_s; - wire [12:0] exp_c; - - wire [10:0] exponent, exp_pre; - wire [63:0] Result; - wire [52:0] mantissaA; - wire [52:0] mantissaB; - wire [63:0] sum, sum_tc, sum_corr, sum_norm; - - wire [5:0] align_shift; - wire [5:0] norm_shift; - wire [2:0] sel_inv; - wire op1_Norm, op2_Norm; - wire opA_Norm, opB_Norm; - wire Invalid; - wire DenormIn, DenormIO; - wire [4:0] FlagsIn; - wire exp_gt63; - wire Sticky_out; - wire signResult, sign_corr; - wire corr_sign; - wire zeroB; - wire convert; - wire swap; - wire sub; - - wire [63:0] q1, qm1, qp1, q0, qm0, qp0; - wire [63:0] rega_out, regb_out, regc_out, regd_out; - wire [127:0] regr_out; - wire [2:0] sel_muxa, sel_muxb; - wire sel_muxr; - wire load_rega, load_regb, load_regc, load_regd, load_regr; - - wire donev, sel_muxrv, sel_muxsv; - wire [1:0] sel_muxav, sel_muxbv; - wire load_regav, load_regbv, load_regcv; - wire load_regrv, load_regsv; - - // Convert the input operands to their appropriate forms based on - // the orignal operands, the op_type , and their precision P. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - convert_inputs_div divconv1 (Float1, Float2, op1, op2, op_type, P); - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if op1 and op2 are not zero or denormalized. - // sub is one if the effective operation is subtaction. - exception_div divexc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, - Float1, Float2, op_type); - - // Determine Sign/Mantissa - assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type; - assign mantissaA = {vdd, Float1[51:0]}; - assign mantissaB = {vdd, Float2[51:0]}; - // Perform Exponent Subtraction - expA - expB + Bias - assign exp1 = {2'b0, Float1[62:52]}; - assign exp2 = {2'b0, Float2[62:52]}; - // bias : DP = 2^{11-1}-1 = 1023 - assign bias = {3'h0, 10'h3FF}; - // Divide exponent - csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c); - exp_add explogic1 (exp_cout1, {open, exp_diff}, - {vss, exp_s}, {vss, exp_c}, 1'b1); - // Sqrt exponent (check if exponent is odd) - assign exp_odd = Float1[52] ? vss : vdd; - exp_add explogic2 (exp_cout2, exp_sqrt, - {vss, exp1}, {4'h0, 10'h3ff}, exp_odd); - // Choose correct exponent - assign expF = op_type ? exp_sqrt[13:1] : exp_diff; - - // Main Goldschmidt/Division Routine - divconv goldy (q1, qm1, qp1, q0, qm0, qp0, - rega_out, regb_out, regc_out, regd_out, - regr_out, mantissaB, mantissaA, - sel_muxa, sel_muxb, sel_muxr, - reset, clk, - load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, P, op_type, exp_odd); - - // FSM : control divider - fsm control (done, load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. The rounding units also handles special cases and - // set the exception flags. - rounder_div divround1 (Result, DenormIO, FlagsIn, - rm, P, OvEn, UnEn, expF, - sel_inv, Invalid, DenormIn, signResult, - q1, qm1, qp1, q0, qm0, qp0, regr_out); - - // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, done, Result, AS_Result); - flopenr #(1) regb (clk, reset, done, DenormIO, Denorm); - flopenr #(5) regc (clk, reset, done, FlagsIn, Flags); - -endmodule // fpadd - -// -// Brent-Kung Prefix Adder -// (yes, it is 14 bits as my generator is broken for 13 bits :( -// assume, synthesizer will delete stuff not needed ) -// -module exp_add (cout, sum, a, b, cin); - - input [13:0] a, b; - input cin; - - output [13:0] sum; - output cout; - - wire [14:0] p,g; - wire [13:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - - // prefix tree - brent_kung prefix_tree(c, p[13:0], g[13:0]); - - // post-computation - assign sum=p[14:1]^c; - assign cout=g[14]|(p[14]&c[13]); - -endmodule // exp_add - -module brent_kung (c, p, g); - - input [13:0] p; - input [13:0] g; - output [14:1] c; - - // parallel-prefix, Brent-Kung - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - - // Stage 4: Generates G/P pairs that span 8 bits - - // Stage 5: Generates G/P pairs that span 4 bits - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - - // Stage 6: Generates G/P pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12); - - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - -endmodule // brent_kung - diff --git a/wally-pipelined/src/fpu/dev/fpuaddcvt1.sv b/wally-pipelined/src/fpu/dev/fpuaddcvt1.sv deleted file mode 100755 index 2ff45ce42..000000000 --- a/wally-pipelined/src/fpu/dev/fpuaddcvt1.sv +++ /dev/null @@ -1,200 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - - -module fpuaddcvt1 (sum, sum_tc, sel_inv, exponent_postsum, corr_sign, op1_Norm, op2_Norm, opA_Norm, opB_Norm, Invalid, DenormIn, convert, swap, normal_overflow, signA, Float1, Float2, exp1_denorm, exp2_denorm, exponent, op1, op2, rm, op_type, Pin, OvEn, UnEn); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [2:0] rm; // Rounding mode - specify values - input [3:0] op_type; // Function opcode - input Pin; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - - wire P; - assign P = Pin | op_type[2]; - - wire [63:0] IntValue; - wire [11:0] exp1, exp2; - wire [11:0] exp_diff1, exp_diff2; - wire [11:0] exp_shift; - wire [51:0] mantissaA; - wire [56:0] mantissaA1; - wire [63:0] mantissaA3; - wire [51:0] mantissaB; - wire [56:0] mantissaB1, mantissaB2; - wire [63:0] mantissaB3; - wire exp_gt63; - wire Sticky_out; - wire sub; - wire zeroB; - wire [5:0] align_shift; - - output [63:0] Float1; - output [63:0] Float2; - output [10:0] exponent; - output [10:0] exponent_postsum; - output [10:0] exp1_denorm, exp2_denorm; - output [63:0] sum, sum_tc; - output [3:0] sel_inv; - output corr_sign; - output signA; - output op1_Norm, op2_Norm; - output opA_Norm, opB_Norm; - output Invalid; - output DenormIn; -// output exp_valid; - output convert; - output swap; - output normal_overflow; - wire [5:0] ZP_mantissaA; - wire [5:0] ZP_mantissaB; - wire ZV_mantissaA; - wire ZV_mantissaB; - - // Convert the input operands to their appropriate forms based on - // the orignal operands, the op_type , and their precision P. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - - convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P); - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if op1 and op2 are not zero or denormalized. - // sub is one if the effective operation is subtaction. - - exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, sub, - Float1, Float2, op_type); - - // Perform Exponent Subtraction (used for alignment). For performance - // both exponent subtractions are performed in parallel. This was - // changed to a behavior level to allow the tools to try to optimize - // the two parallel additions. The input values are zero-extended to 12 - // bits prior to performing the addition. - - assign exp1 = {1'b0, Float1[62:52]}; - assign exp2 = {1'b0, Float2[62:52]}; - assign exp_diff1 = exp1 - exp2; - assign exp_diff2 = DenormIn ? ({Float2[63], exp2[10:0]} - {Float1[63], exp1[10:0]}): exp2 - exp1; - - // The second operand (B) should be set to zero, if op_type does not - // specify addition or subtraction - assign zeroB = op_type[2] | op_type[1]; - - // Swapped operands if zeroB is not one and exp1 < exp2. - // Swapping causes exp2 to be used for the result exponent. - // Only the exponent of the larger operand is used to determine - // the final result. - assign swap = exp_diff1[11] & ~zeroB; - assign exponent = swap ? exp2[10:0] : exp1[10:0]; - assign exponent_postsum = swap ? exp2[10:0] : exp1[10:0]; - assign mantissaA = swap ? Float2[51:0] : Float1[51:0]; - assign mantissaB = swap ? Float1[51:0] : Float2[51:0]; - assign signA = swap ? Float2[63] : Float1[63]; - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - // modified to 52 bits to detect leading zeroes on denormalized mantissas - lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA); - lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB); - - // Denormalized exponents created by subtracting the leading zeroes from the original exponents - assign exp1_denorm = swap ? (exp1 - ZP_mantissaB) : (exp1 - ZP_mantissaA); - assign exp2_denorm = swap ? (exp2 - ZP_mantissaA) : (exp2 - ZP_mantissaB); - - // Determine the alignment shift and limit it to 63. If any bit from - // exp_shift[6] to exp_shift[11] is one, then shift is set to all ones. - assign exp_shift = swap ? exp_diff2 : exp_diff1; - assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9] - | exp_shift[8] | exp_shift[7] | exp_shift[6]; - assign align_shift = exp_shift | {6{exp_gt63}}; - - // Unpack the 52-bit mantissas to 57-bit numbers of the form. - // 001.M[51]M[50] ... M[1]M[0]00 - // Unless the number has an exponent of zero, in which case it - // is unpacked as - // 000.00 ... 00 - // This effectively flushes denormalized values to zero. - // The three bits of to the left of the binary point prevent overflow - // and loss of sign information. The two bits to the right of the - // original mantissa form the "guard" and "round" bits that are used - // to round the result. - assign opA_Norm = swap ? op2_Norm : op1_Norm; - assign opB_Norm = swap ? op1_Norm : op2_Norm; - assign mantissaA1 = {2'h0, opA_Norm, mantissaA[51:0]&{52{opA_Norm}}, 2'h0}; - assign mantissaB1 = {2'h0, opB_Norm, mantissaB[51:0]&{52{opB_Norm}}, 2'h0}; - - // Perform mantissa alignment using a 57-bit barrel shifter - // If any of the bits shifted out are one, Sticky_out is set. - // The size of the barrel shifter could be reduced by two bits - // by not adding the leading two zeros until after the shift. - barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift); - - // Place either the sign-extened 32-bit value or the original 64-bit value - // into IntValue (to be used for integer to floating point conversion) - assign IntValue [31:0] = op1[31:0]; - assign IntValue [63:32] = op_type[0] ? {32{op1[31]}} : op1[63:32]; - - // If doing an integer to floating point conversion, mantissaA3 is set to - // IntVal and the prenomalized exponent is set to 1084. Otherwise, - // mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero, - // and the exponent value is left unchanged. - // Under denormalized cases, the exponent before the rounder is set to 1 - // if the normal shift value is 11. - assign convert = ~op_type[2] & op_type[1]; - assign mantissaA3 = (op_type[3]) ? (op_type[0] ? Float1 : ~Float1) : (DenormIn ? ({12'h0, mantissaA}) : (convert ? IntValue : {mantissaA1, 7'h0})); - - // Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to - // 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six - // zeros. - assign mantissaB3[63:7] = (op_type[3]) ? (57'h0) : (DenormIn ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}}); - assign mantissaB3[6] = (op_type[3]) ? (1'b0) : (DenormIn ? mantissaB[6] : Sticky_out & ~zeroB); - assign mantissaB3[5:0] = (op_type[3]) ? (6'h01) : (DenormIn ? mantissaB[5:0] : 6'h0); - - // The sign of the result needs to be corrected if the true - // operation is subtraction and the input operands were swapped. - assign corr_sign = ~op_type[2]&~op_type[1]&op_type[0]&swap; - - // 64-bit Mantissa Adder/Subtractor - cla64 add1 (sum, mantissaA3, mantissaB3, sub); - - // 64-bit Mantissa Subtractor - to get the two's complement of the - // result when the sign from the adder/subtractor is negative. - cla_sub64 sub1 (sum_tc, mantissaB3, mantissaA3); - - // Finds normal underflow result to determine whether to round final exponent down - assign normal_overflow = (DenormIn & (sum == 16'h0) & (opA_Norm | opB_Norm) & ~op_type[0]) ? 1'b1 : (sum[63] ? sum_tc[52] : sum[52]); - -endmodule // fpadd - - diff --git a/wally-pipelined/src/fpu/dev/fpuaddcvt2.sv b/wally-pipelined/src/fpu/dev/fpuaddcvt2.sv deleted file mode 100755 index 4ab2fa944..000000000 --- a/wally-pipelined/src/fpu/dev/fpuaddcvt2.sv +++ /dev/null @@ -1,156 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - - -module fpuaddcvt2sv (AS_Result, Flags, Denorm, sum, sum_tc, sel_inv, exponent_postsum, corr_sign, op1_Norm, op2_Norm, opA_Norm, opB_Norm, Invalid, DenormIn, exp_valid, convert, swap, normal_overflow, signA, Float1, Float2, exp1_denorm, exp2_denorm, exponent, op1, op2, rm, op_type, Pin, OvEn, UnEn); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [2:0] rm; // Rounding mode - specify values - input [3:0] op_type; // Function opcode - input Pin; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - input [63:0] sum, sum_tc; - input [63:0] Float1; - input [63:0] Float2; - input [10:0] exp1_denorm, exp2_denorm; - input [10:0] exponent, exponent_postsum; //exp_pre; - input exp_valid; - input [3:0] sel_inv; - input op1_Norm, op2_Norm; - input opA_Norm, opB_Norm; - input Invalid; - input DenormIn; - input signA; - input corr_sign; - input convert; - input swap; - input normal_overflow; - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - - wire P; - assign P = Pin | op_type[2]; - - wire [10:0] exp_pre; - wire [63:0] Result; - wire [63:0] sum_norm, sum_norm_w_bypass; - wire [5:0] norm_shift, norm_shift_denorm; - wire DenormIO; - wire [4:0] FlagsIn; - wire Sticky_out; - wire sign_corr; - wire zeroB; - wire [10:0] exponent_postsum; - wire mantissa_comp; - wire mantissa_comp_sum; - wire mantissa_comp_sum_tc; - wire Float1_sum_comp; - wire Float2_sum_comp; - wire Float1_sum_tc_comp; - wire Float2_sum_tc_comp; - wire normal_underflow; - wire [63:0] sum_corr; - - //exponent value pre-rounding with considerations for denormalized - //cases/conversion cases - assign exp_pre = DenormIn ? - ((norm_shift == 6'b001011) ? 11'b00000000001 : (swap ? exp2_denorm : exp1_denorm)) - : (convert ? 11'b10000111100 : exponent); - - - // Finds normal underflow result to determine whether to round final exponent down - // Comparison between each float and the resulting sum of the primary cla adder/subtractor and cla subtractor - assign Float1_sum_comp = (Float1[51:0] > sum[51:0]) ? 1'b0 : 1'b1; - assign Float2_sum_comp = (Float2[51:0] > sum[51:0]) ? 1'b0 : 1'b1; - assign Float1_sum_tc_comp = (Float1[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1; - assign Float2_sum_tc_comp = (Float2[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1; - - // Determines the correct Float value to compare based on swap result - assign mantissa_comp_sum = swap ? Float2_sum_comp : Float1_sum_comp; - assign mantissa_comp_sum_tc = swap ? Float2_sum_tc_comp : Float1_sum_tc_comp; - - // Determines the correct comparison result based on operation and sign of resulting sum - assign mantissa_comp = (op_type[0] ^ sum[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum; - - // If the signs are different and both operands aren't denormalized - // the normal underflow bit is needed and therefore updated. - assign normal_underflow = ((Float1[63] ~^ Float2[63]) & (opA_Norm | opB_Norm)) ? mantissa_comp : 1'b0; - - // Determine the correct sign of the result - assign sign_corr = ((corr_sign ^ signA) & ~convert) ^ sum[63]; - - // If the sum is negative, use its two complement instead. - // This value has to be 64-bits to correctly handle the - // case 10...00 - assign sum_corr = (DenormIn & (opA_Norm | opB_Norm) & ( ( (Float1[63] ~^ Float2[63]) & op_type[0] ) | ((Float1[63] ^ Float2[63]) & ~op_type[0]) )) - ? (sum[63] ? sum : sum_tc) : ( (op_type[3]) ? sum : (sum[63] ? sum_tc : sum)); - - // Finds normal underflow result to determine whether to round final exponent down - assign normal_overflow = (DenormIn & (sum == 16'h0) & (opA_Norm | opB_Norm) & ~op_type[0]) ? 1'b1 : (sum[63] ? sum_tc[52] : sum[52]); - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - lz64 lzd1 (norm_shift, exp_valid, sum_corr); - - assign norm_shift_denorm = (DenormIn & ( (~opA_Norm & ~opB_Norm) | normal_underflow)) ? (6'h00) : (norm_shift); - - // Barell shifter used for normalization. It takes as inputs the - // the corrected sum and the amount by which the sum should - // be right shifted. It outputs the normalized sum. - barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm); - - assign sum_norm_w_bypass = (op_type[3]) ? (op_type[0] ? ~sum_corr : sum_corr) : (sum_norm); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. If the result is a single precision number, the actual - // mantissa is in the upper 23 bits and the lower 29 bits are zero. - // At this point, normalization has already been performed, so we know - // exactly where the rounding point is. The rounding units also - // handles special cases and set the exception flags. - - // Changed DenormIO -> Denorm and FlagsIn -> Flags in order to - // help in processor reservation station detection of load/stores. In - // other words, the processor would like to know ahead of time that - // if the result is an exception then don't load or store. - rounder round1 (Result, DenormIO, FlagsIn, rm, P, OvEn, UnEn, exp_valid, - sel_inv, Invalid, DenormIn, convert, sign_corr, exp_pre, norm_shift, sum_norm_w_bypass, - exponent_postsum, op1_Norm, op2_Norm, Float1[63:52], Float2[63:52], - normal_overflow, normal_underflow, swap, op_type, sum); - - // Store the final result and the exception flags in registers. - assign AS_Result = Result; - assign {Denorm, Flags} = {DenormIO, FlagsIn}; - -endmodule // fpadd - - diff --git a/wally-pipelined/src/fpu/dev/fpucmp1.sv b/wally-pipelined/src/fpu/dev/fpucmp1.sv deleted file mode 100755 index a7bafd2d8..000000000 --- a/wally-pipelined/src/fpu/dev/fpucmp1.sv +++ /dev/null @@ -1,235 +0,0 @@ -// -// File name : fpcomp.v -// Title : Floating-Point Comparator -// project : FPU -// Library : fpcomp -// Author(s) : James E. Stine -// Purpose : definition of main unit to floating-point comparator -// notes : -// -// Copyright Oklahoma State University -// -// Floating Point Comparator (Algorithm) -// -// 1.) Performs sign-extension if the inputs are 32-bit integers. -// 2.) Perform a magnitude comparison on the lower 63 bits of the inputs -// 3.) Check for special cases (+0=-0, unordered, and infinite values) -// and correct for sign bits -// -// This module takes 64-bits inputs op1 and op2, VSS, and VDD -// signals, and a 2-bit signal Sel that indicates the type of -// operands being compared as indicated below. -// Sel Description -// 00 double precision numbers -// 01 single precision numbers -// 10 half precision numbers -// 11 (unused) -// -// The comparator produces a 2-bit signal FCC, which -// indicates the result of the comparison: -// -// fcc decscription -// 00 A = B -// 01 A < B -// 10 A > B -// 11 A and B are unordered (i.e., A or B is NaN) -// -// It also produces an invalid operation flag, which is one -// if either of the input operands is a signaling NaN per 754 - -module fpucmp1 (w, x, ANaN, BNaN, Azero, Bzero, op1, op2, Sel); - - input logic [63:0] op1; - input logic [63:0] op2; - input logic [1:0] Sel; - - output logic [7:0] w, x; - output logic ANaN, BNaN; - output logic Azero, Bzero; - - // Perform magnitude comparison between the 63 least signficant bits - // of the input operands. Only LT and EQ are returned, since GT can - // be determined from these values. - magcompare64b_1 magcomp2 (w, x, {~op1[63], op1[62:0]}, {~op2[63], op2[62:0]}); - - // Determine final values based on output of magnitude comparison, - // sign bits, and special case testing. - exception_cmp_1 exc1 (ANaN, BNaN, Azero, Bzero, op1, op2, Sel); - -endmodule // fpcomp - -module magcompare2b (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - // Determine if A < B using a minimized sum-of-products expression - assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; - // Determine if A > B using a minimized sum-of-products expression - assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; - -endmodule // magcompare2b - -// 2-bit magnitude comparator -// This module compares two 2-bit values A and B. LT is '1' if A < B -// and GT is '1'if A > B. LT and GT are both '0' if A = B. However, -// this version actually incorporates don't cares into the equation to -// simplify the optimization - -module magcompare2c (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - assign LT = B[1] | (!A[1]&B[0]); - assign GT = A[1] | (!B[1]&A[0]); - -endmodule // magcompare2b - -// This module compares two 64-bit values A and B. LT is '1' if A < B -// and EQ is '1'if A = B. LT and GT are both '0' if A > B. -// This structure was modified so -// that it only does a strict magnitdude comparison, and only -// returns flags for less than (LT) and eqaual to (EQ). It uses a tree -// of 63 2-bit magnitude comparators, followed by one OR gates. -// -// J. E. Stine and M. J. Schulte, "A combined two's complement and -// floating-point comparator," 2005 IEEE International Symposium on -// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. -// doi: 10.1109/ISCAS.2005.1464531 - -module magcompare64b_1 (w, x, A, B); - - input logic [63:0] A; - input logic [63:0] B; - - logic [31:0] s; - logic [31:0] t; - logic [15:0] u; - logic [15:0] v; - output logic [7:0] w; - output logic [7:0] x; - - magcompare2b mag1(s[0], t[0], A[1:0], B[1:0]); - magcompare2b mag2(s[1], t[1], A[3:2], B[3:2]); - magcompare2b mag3(s[2], t[2], A[5:4], B[5:4]); - magcompare2b mag4(s[3], t[3], A[7:6], B[7:6]); - magcompare2b mag5(s[4], t[4], A[9:8], B[9:8]); - magcompare2b mag6(s[5], t[5], A[11:10], B[11:10]); - magcompare2b mag7(s[6], t[6], A[13:12], B[13:12]); - magcompare2b mag8(s[7], t[7], A[15:14], B[15:14]); - magcompare2b mag9(s[8], t[8], A[17:16], B[17:16]); - magcompare2b magA(s[9], t[9], A[19:18], B[19:18]); - magcompare2b magB(s[10], t[10], A[21:20], B[21:20]); - magcompare2b magC(s[11], t[11], A[23:22], B[23:22]); - magcompare2b magD(s[12], t[12], A[25:24], B[25:24]); - magcompare2b magE(s[13], t[13], A[27:26], B[27:26]); - magcompare2b magF(s[14], t[14], A[29:28], B[29:28]); - magcompare2b mag10(s[15], t[15], A[31:30], B[31:30]); - magcompare2b mag11(s[16], t[16], A[33:32], B[33:32]); - magcompare2b mag12(s[17], t[17], A[35:34], B[35:34]); - magcompare2b mag13(s[18], t[18], A[37:36], B[37:36]); - magcompare2b mag14(s[19], t[19], A[39:38], B[39:38]); - magcompare2b mag15(s[20], t[20], A[41:40], B[41:40]); - magcompare2b mag16(s[21], t[21], A[43:42], B[43:42]); - magcompare2b mag17(s[22], t[22], A[45:44], B[45:44]); - magcompare2b mag18(s[23], t[23], A[47:46], B[47:46]); - magcompare2b mag19(s[24], t[24], A[49:48], B[49:48]); - magcompare2b mag1A(s[25], t[25], A[51:50], B[51:50]); - magcompare2b mag1B(s[26], t[26], A[53:52], B[53:52]); - magcompare2b mag1C(s[27], t[27], A[55:54], B[55:54]); - magcompare2b mag1D(s[28], t[28], A[57:56], B[57:56]); - magcompare2b mag1E(s[29], t[29], A[59:58], B[59:58]); - magcompare2b mag1F(s[30], t[30], A[61:60], B[61:60]); - magcompare2b mag20(s[31], t[31], A[63:62], B[63:62]); - - magcompare2c mag21(u[0], v[0], t[1:0], s[1:0]); - magcompare2c mag22(u[1], v[1], t[3:2], s[3:2]); - magcompare2c mag23(u[2], v[2], t[5:4], s[5:4]); - magcompare2c mag24(u[3], v[3], t[7:6], s[7:6]); - magcompare2c mag25(u[4], v[4], t[9:8], s[9:8]); - magcompare2c mag26(u[5], v[5], t[11:10], s[11:10]); - magcompare2c mag27(u[6], v[6], t[13:12], s[13:12]); - magcompare2c mag28(u[7], v[7], t[15:14], s[15:14]); - magcompare2c mag29(u[8], v[8], t[17:16], s[17:16]); - magcompare2c mag2A(u[9], v[9], t[19:18], s[19:18]); - magcompare2c mag2B(u[10], v[10], t[21:20], s[21:20]); - magcompare2c mag2C(u[11], v[11], t[23:22], s[23:22]); - magcompare2c mag2D(u[12], v[12], t[25:24], s[25:24]); - magcompare2c mag2E(u[13], v[13], t[27:26], s[27:26]); - magcompare2c mag2F(u[14], v[14], t[29:28], s[29:28]); - magcompare2c mag30(u[15], v[15], t[31:30], s[31:30]); - - magcompare2c mag31(w[0], x[0], v[1:0], u[1:0]); - magcompare2c mag32(w[1], x[1], v[3:2], u[3:2]); - magcompare2c mag33(w[2], x[2], v[5:4], u[5:4]); - magcompare2c mag34(w[3], x[3], v[7:6], u[7:6]); - magcompare2c mag35(w[4], x[4], v[9:8], u[9:8]); - magcompare2c mag36(w[5], x[5], v[11:10], u[11:10]); - magcompare2c mag37(w[6], x[6], v[13:12], u[13:12]); - magcompare2c mag38(w[7], x[7], v[15:14], u[15:14]); - -endmodule // magcompare64b - -// This module takes 64-bits inputs A and B, two magnitude comparison -// flags LT_mag and EQ_mag, and a 2-bit signal Sel that indicates the type of -// operands being compared as indicated below. -// Sel Description -// 00 double precision numbers -// 01 single precision numbers -// 10 half precision numbers -// 11 bfloat precision numbers -// -// The comparator produces a 2-bit signal fcc, which -// indicates the result of the comparison as follows: -// fcc decscription -// 00 A = B -// 01 A < B -// 10 A > B -// 11 A and B are unordered (i.e., A or B is NaN) -// It also produces a invalid operation flag, which is one -// if either of the input operands is a signaling NaN. - -module exception_cmp_1 (ANaN, BNaN, Azero, Bzero, A, B, Sel); - - input logic [63:0] A; - input logic [63:0] B; - input logic [1:0] Sel; - - logic dp, sp, hp; - - output logic ANaN; - output logic BNaN; - output logic Azero; - output logic Bzero; - logic [62:0] sixtythreezeros = 63'h0; - - assign dp = !Sel[1]&!Sel[0]; - assign sp = !Sel[1]&Sel[0]; - assign hp = Sel[1]&!Sel[0]; - - // Test if A or B is NaN. - assign ANaN = (A[62]&A[61]&A[60]&A[59]&A[58]) & - ((sp&A[57]&A[56]&A[55]&(A[54]|A[53])) | - (dp&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]&(A[51]|A[50])) | - (hp&(A[57]|A[56]))); - - assign BNaN = (B[62]&B[61]&B[60]&B[59]&B[58]) & - ((sp&B[57]&B[56]&B[55]&(B[54]|B[53])) | - (dp&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]&(B[51]|B[50])) | - (hp&(B[57]|B[56]))); - - // Test if A is +0 or -0 when viewed as a floating point number (i.e, - // the 63 least siginficant bits of A are zero). - // Depending on how this synthesizes, it may work better to replace - // this with assign Azero = ~(A[62] | A[61] | ... | A[0]) - assign Azero = (A[62:0] == sixtythreezeros); - assign Bzero = (B[62:0] == sixtythreezeros); - -endmodule // exception_cmp diff --git a/wally-pipelined/src/fpu/dev/fpucmp2.sv b/wally-pipelined/src/fpu/dev/fpucmp2.sv deleted file mode 100755 index fe81e37fe..000000000 --- a/wally-pipelined/src/fpu/dev/fpucmp2.sv +++ /dev/null @@ -1,226 +0,0 @@ -// -// File name : fpcomp.v -// Title : Floating-Point Comparator -// project : FPU -// Library : fpcomp -// Author(s) : James E. Stine -// Purpose : definition of main unit to floating-point comparator -// notes : -// -// Copyright Oklahoma State University -// -// Floating Point Comparator (Algorithm) -// -// 1.) Performs sign-extension if the inputs are 32-bit integers. -// 2.) Perform a magnitude comparison on the lower 63 bits of the inputs -// 3.) Check for special cases (+0=-0, unordered, and infinite values) -// and correct for sign bits -// -// This module takes 64-bits inputs op1 and op2, VSS, and VDD -// signals, and a 2-bit signal Sel that indicates the type of -// operands being compared as indicated below. -// Sel Description -// 00 double precision numbers -// 01 single precision numbers -// 10 half precision numbers -// 11 (unused) -// -// The comparator produces a 2-bit signal FCC, which -// indicates the result of the comparison: -// -// fcc decscription -// 00 A = B -// 01 A < B -// 10 A > B -// 11 A and B are unordered (i.e., A or B is NaN) -// -// It also produces an invalid operation flag, which is one -// if either of the input operands is a signaling NaN per 754 - -module fpucmp2 (Invalid, FCC, ANaN, BNaN, Azero, Bzero, w, x, Sel, op1, op2); - - input logic [63:0] op1; - input logic [63:0] op2; - input logic [1:0] Sel; - input logic [7:0] w, x; - input logic ANaN, BNaN; - input logic Azero, Bzero; - - output logic Invalid; // Invalid Operation - output logic [1:0] FCC; // Condition Codes - - logic LT; // magnitude op1 < magnitude op2 - logic EQ; // magnitude op1 = magnitude op2 - - // Perform magnitude comparison between the 63 least signficant bits - // of the input operands. Only LT and EQ are returned, since GT can - // be determined from these values. - magcompare64b_2 magcomp2 (LT, EQ, w, x); - - // Determine final values based on output of magnitude comparison, - // sign bits, and special case testing. - exception_cmp_2 exc2 (.invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ), .ANaN(ANaN), .BNaN(BNaN), .Azero(Azero), .Bzero(Bzero), .Sel(Sel), .A(op1), .B(op2)); - - -endmodule // fpcomp - -/*module magcompare2b (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - // Determine if A < B using a minimized sum-of-products expression - assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; - // Determine if A > B using a minimized sum-of-products expression - assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; - -endmodule*/ // magcompare2b - -// 2-bit magnitude comparator -// This module compares two 2-bit values A and B. LT is '1' if A < B -// and GT is '1'if A > B. LT and GT are both '0' if A = B. However, -// this version actually incorporates don't cares into the equation to -// simplify the optimization - -module magcompare2c (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - assign LT = B[1] | (!A[1]&B[0]); - assign GT = A[1] | (!B[1]&A[0]); - -endmodule // magcompare2b - -// This module compares two 64-bit values A and B. LT is '1' if A < B -// and EQ is '1'if A = B. LT and GT are both '0' if A > B. -// This structure was modified so -// that it only does a strict magnitdude comparison, and only -// returns flags for less than (LT) and eqaual to (EQ). It uses a tree -// of 63 2-bit magnitude comparators, followed by one OR gates. -// -// J. E. Stine and M. J. Schulte, "A combined two's complement and -// floating-point comparator," 2005 IEEE International Symposium on -// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. -// doi: 10.1109/ISCAS.2005.1464531 - -module magcompare64b_2 (LT, EQ, w, x); - - input logic [7:0] w; - input logic [7:0] x; - logic [3:0] y; - logic [3:0] z; - logic [1:0] a; - logic [1:0] b; - logic GT; - - output logic LT; - output logic EQ; - - magcompare2c mag39(y[0], z[0], x[1:0], w[1:0]); - magcompare2c mag3A(y[1], z[1], x[3:2], w[3:2]); - magcompare2c mag3B(y[2], z[2], x[5:4], w[5:4]); - magcompare2c mag3C(y[3], z[3], x[7:6], w[7:6]); - - magcompare2c mag3D(a[0], b[0], z[1:0], y[1:0]); - magcompare2c mag3E(a[1], b[1], z[3:2], y[3:2]); - - magcompare2c mag3F(LT, GT, b[1:0], a[1:0]); - - assign EQ = ~(LT | GT); - -endmodule // magcompare64b - -// This module takes 64-bits inputs A and B, two magnitude comparison -// flags LT_mag and EQ_mag, and a 2-bit signal Sel that indicates the type of -// operands being compared as indicated below. -// Sel Description -// 00 double precision numbers -// 01 single precision numbers -// 10 half precision numbers -// 11 bfloat precision numbers -// -// The comparator produces a 2-bit signal fcc, which -// indicates the result of the comparison as follows: -// fcc decscription -// 00 A = B -// 01 A < B -// 10 A > B -// 11 A and B are unordered (i.e., A or B is NaN) -// It also produces a invalid operation flag, which is one -// if either of the input operands is a signaling NaN. - -module exception_cmp_2 (invalid, fcc, LT_mag, EQ_mag, ANaN, BNaN, Azero, Bzero, Sel, A, B); - - input logic [63:0] A; - input logic [63:0] B; - input logic LT_mag; - input logic EQ_mag; - input logic [1:0] Sel; - - output logic invalid; - output logic [1:0] fcc; - - logic dp; - logic sp; - logic hp; - input logic Azero; - input logic Bzero; - input logic ANaN; - input logic BNaN; - logic ASNaN; - logic BSNaN; - logic UO; - logic GT; - logic LT; - logic EQ; - logic [62:0] sixtythreezeros = 63'h0; - - assign dp = !Sel[1]&!Sel[0]; - assign sp = !Sel[1]&Sel[0]; - assign hp = Sel[1]&!Sel[0]; - - // Values are unordered if ((A is NaN) OR (B is NaN)) AND (a floating - // point comparison is being performed. - assign UO = (ANaN | BNaN); - - // Test if A or B is a signaling NaN. - assign ASNaN = ANaN & (sp&~A[53] | dp&~A[50] | hp&~A[56]); - assign BSNaN = BNaN & (sp&~B[53] | dp&~B[50] | hp&~B[56]); - - // If either A or B is a signaling NaN the "Invalid Operation" - // exception flag is set to one; otherwise it is zero. - assign invalid = (ASNaN | BSNaN); - - // A and B are equal if (their magnitudes are equal) AND ((their signs are - // equal) or (their magnitudes are zero AND they are floating point - // numbers)). Also, A and B are not equal if they are unordered. - assign EQ = (EQ_mag | (Azero&Bzero)) & (~UO); - - // A is less than B if (A is negative and B is posiive) OR - // (A and B are positive and the magnitude of A is less than - // the magnitude of B) or (A and B are negative integers and - // the magnitude of A is less than the magnitude of B) or - // (A and B are negative floating point numbers and - // the magnitude of A is greater than the magnitude of B). - // Also, A is not less than B if A and B are equal or unordered. - assign LT = ((~LT_mag & A[63] & B[63]) | - (LT_mag & ~(A[63] & B[63])))&~EQ&~UO; - - // A is greater than B when LT, EQ, and UO are are false. - assign GT = ~(LT | EQ | UO); - - // Note: it may be possible to optimize the setting of fcc - // a little more, but it is probably not worth the effort. - - // Set the bits of fcc based on LT, GT, EQ, and UO - assign fcc[0] = LT | UO; - assign fcc[1] = GT | UO; - -endmodule // exception_cmp diff --git a/wally-pipelined/src/fpu/dev/freg.sv b/wally-pipelined/src/fpu/dev/freg.sv deleted file mode 100755 index 3ce18162a..000000000 --- a/wally-pipelined/src/fpu/dev/freg.sv +++ /dev/null @@ -1,513 +0,0 @@ -`include "../../../config/rv64icfd/wally-config.vh" - -module freg1adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //this could be done with: - // - //assign readData = regOutput[adr1]; - // - //but always_comb allows for finer control - - - //address decoder - //only 1 for this fp register set - //used with fpsign - //defaults to outputting zeroes - always_comb begin - case(adr1) - 5'b00000 : readData = regOutput[0]; - 5'b00001 : readData = regOutput[1]; - 5'b00010 : readData = regOutput[2]; - 5'b00011 : readData = regOutput[3]; - 5'b00100 : readData = regOutput[4]; - 5'b00101 : readData = regOutput[5]; - 5'b00110 : readData = regOutput[6]; - 5'b00111 : readData = regOutput[7]; - 5'b01000 : readData = regOutput[8]; - 5'b01001 : readData = regOutput[9]; - 5'b01010 : readData = regOutput[10]; - 5'b01011 : readData = regOutput[11]; - 5'b01100 : readData = regOutput[12]; - 5'b01101 : readData = regOutput[13]; - 5'b01110 : readData = regOutput[14]; - 5'b01111 : readData = regOutput[15]; - 5'b10000 : readData = regOutput[16]; - 5'b10001 : readData = regOutput[17]; - 5'b10010 : readData = regOutput[18]; - 5'b10011 : readData = regOutput[19]; - 5'b10100 : readData = regOutput[20]; - 5'b10101 : readData = regOutput[21]; - 5'b10110 : readData = regOutput[22]; - 5'b10111 : readData = regOutput[23]; - 5'b11000 : readData = regOutput[24]; - 5'b11001 : readData = regOutput[25]; - 5'b11010 : readData = regOutput[26]; - 5'b11011 : readData = regOutput[27]; - 5'b11100 : readData = regOutput[28]; - 5'b11101 : readData = regOutput[29]; - 5'b11110 : readData = regOutput[30]; - 5'b11111 : readData = regOutput[31]; - default : readData = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01000 : regInput[9] = writeData; - 5'b01001 : regInput[10] = writeData; - 5'b01010 : regInput[11] = writeData; - 5'b01111 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11000 : regInput[25] = writeData; - 5'b11001 : regInput[26] = writeData; - 5'b11010 : regInput[27] = writeData; - 5'b11111 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//******** -//formatting separation -//******** -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -module freg2adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [4:0] adr2, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData1, - output logic [`XLEN-1:0] readData2); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //address decoder - //2 are used for this fp register set - //used with fpadd/cvt, fpdiv/sqrt, and fpcmp - //defaults to outputting zeroes - always_comb begin - - //adderss 1 decoder - case(adr1) - 5'b00000 : readData1 = regOutput[0]; - 5'b00001 : readData1 = regOutput[1]; - 5'b00010 : readData1 = regOutput[2]; - 5'b00011 : readData1 = regOutput[3]; - 5'b00100 : readData1 = regOutput[4]; - 5'b00101 : readData1 = regOutput[5]; - 5'b00110 : readData1 = regOutput[6]; - 5'b00111 : readData1 = regOutput[7]; - 5'b01000 : readData1 = regOutput[8]; - 5'b01001 : readData1 = regOutput[9]; - 5'b01010 : readData1 = regOutput[10]; - 5'b01011 : readData1 = regOutput[11]; - 5'b01100 : readData1 = regOutput[12]; - 5'b01101 : readData1 = regOutput[13]; - 5'b01110 : readData1 = regOutput[14]; - 5'b01111 : readData1 = regOutput[15]; - 5'b10000 : readData1 = regOutput[16]; - 5'b10001 : readData1 = regOutput[17]; - 5'b10010 : readData1 = regOutput[18]; - 5'b10011 : readData1 = regOutput[19]; - 5'b10100 : readData1 = regOutput[20]; - 5'b10101 : readData1 = regOutput[21]; - 5'b10110 : readData1 = regOutput[22]; - 5'b10111 : readData1 = regOutput[23]; - 5'b11000 : readData1 = regOutput[24]; - 5'b11001 : readData1 = regOutput[25]; - 5'b11010 : readData1 = regOutput[26]; - 5'b11011 : readData1 = regOutput[27]; - 5'b11100 : readData1 = regOutput[28]; - 5'b11101 : readData1 = regOutput[29]; - 5'b11110 : readData1 = regOutput[30]; - 5'b11111 : readData1 = regOutput[31]; - default : readData1 = `XLEN'h0; - endcase - - //address 2 decoder - case(adr2) - 5'b00000 : readData2 = regOutput[0]; - 5'b00001 : readData2 = regOutput[1]; - 5'b00010 : readData2 = regOutput[2]; - 5'b00011 : readData2 = regOutput[3]; - 5'b00100 : readData2 = regOutput[4]; - 5'b00101 : readData2 = regOutput[5]; - 5'b00110 : readData2 = regOutput[6]; - 5'b00111 : readData2 = regOutput[7]; - 5'b01000 : readData2 = regOutput[8]; - 5'b01001 : readData2 = regOutput[9]; - 5'b01010 : readData2 = regOutput[10]; - 5'b01011 : readData2 = regOutput[11]; - 5'b01100 : readData2 = regOutput[12]; - 5'b01101 : readData2 = regOutput[13]; - 5'b01110 : readData2 = regOutput[14]; - 5'b01111 : readData2 = regOutput[15]; - 5'b10000 : readData2 = regOutput[16]; - 5'b10001 : readData2 = regOutput[17]; - 5'b10010 : readData2 = regOutput[18]; - 5'b10011 : readData2 = regOutput[19]; - 5'b10100 : readData2 = regOutput[20]; - 5'b10101 : readData2 = regOutput[21]; - 5'b10110 : readData2 = regOutput[22]; - 5'b10111 : readData2 = regOutput[23]; - 5'b11000 : readData2 = regOutput[24]; - 5'b11001 : readData2 = regOutput[25]; - 5'b11010 : readData2 = regOutput[26]; - 5'b11011 : readData2 = regOutput[27]; - 5'b11100 : readData2 = regOutput[28]; - 5'b11101 : readData2 = regOutput[29]; - 5'b11110 : readData2 = regOutput[30]; - 5'b11111 : readData2 = regOutput[31]; - default : readData2 = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01000 : regInput[9] = writeData; - 5'b01001 : regInput[10] = writeData; - 5'b01010 : regInput[11] = writeData; - 5'b01111 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11000 : regInput[25] = writeData; - 5'b11001 : regInput[26] = writeData; - 5'b11010 : regInput[27] = writeData; - 5'b11111 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule - -////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -//******** -//formatting separation -//******** -///////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -module freg3adr ( - input logic [2:0] frm, - input logic reset, - input logic clear, - input logic clk, - input logic [4:0] rd, - input logic write, - input logic [4:0] adr1, - input logic [4:0] adr2, - input logic [4:0] adr3, - input logic [`XLEN-1:0] writeData, - output logic [`XLEN-1:0] readData1, - output logic [`XLEN-1:0] readData2, - output logic [`XLEN-1:0] readData3); - - //note - not word aligning based on precision of - //operation (frm) - - //reg number should remain static, but it doesn't hurt - //to parameterize - parameter numRegs = 32; - - //intermediary signals - useful for debugging - //and easy instatiation of generated modules - logic [`XLEN-1:0] [numRegs-1:0] regInput; - logic [`XLEN-1:0] [numRegs-1:0] regOutput; - - //generate fp registers themselves - genvar i; - generate - for (i = 0; i < numRegs; i = i + 1) begin:register - - floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); - end - - endgenerate - - //address decoder - //3 are used for this fp register set - //used exclusively for fma - //defaults to outputting zeroes - always_comb begin - - //adderss 1 decoder - case(adr1) - 5'b00000 : readData1 = regOutput[0]; - 5'b00001 : readData1 = regOutput[1]; - 5'b00010 : readData1 = regOutput[2]; - 5'b00011 : readData1 = regOutput[3]; - 5'b00100 : readData1 = regOutput[4]; - 5'b00101 : readData1 = regOutput[5]; - 5'b00110 : readData1 = regOutput[6]; - 5'b00111 : readData1 = regOutput[7]; - 5'b01000 : readData1 = regOutput[8]; - 5'b01001 : readData1 = regOutput[9]; - 5'b01010 : readData1 = regOutput[10]; - 5'b01011 : readData1 = regOutput[11]; - 5'b01100 : readData1 = regOutput[12]; - 5'b01101 : readData1 = regOutput[13]; - 5'b01110 : readData1 = regOutput[14]; - 5'b01111 : readData1 = regOutput[15]; - 5'b10000 : readData1 = regOutput[16]; - 5'b10001 : readData1 = regOutput[17]; - 5'b10010 : readData1 = regOutput[18]; - 5'b10011 : readData1 = regOutput[19]; - 5'b10100 : readData1 = regOutput[20]; - 5'b10101 : readData1 = regOutput[21]; - 5'b10110 : readData1 = regOutput[22]; - 5'b10111 : readData1 = regOutput[23]; - 5'b11000 : readData1 = regOutput[24]; - 5'b11001 : readData1 = regOutput[25]; - 5'b11010 : readData1 = regOutput[26]; - 5'b11011 : readData1 = regOutput[27]; - 5'b11100 : readData1 = regOutput[28]; - 5'b11101 : readData1 = regOutput[29]; - 5'b11110 : readData1 = regOutput[30]; - 5'b11111 : readData1 = regOutput[31]; - default : readData1 = `XLEN'h0; - endcase - - //address 2 decoder - case(adr2) - 5'b00000 : readData2 = regOutput[0]; - 5'b00001 : readData2 = regOutput[1]; - 5'b00010 : readData2 = regOutput[2]; - 5'b00011 : readData2 = regOutput[3]; - 5'b00100 : readData2 = regOutput[4]; - 5'b00101 : readData2 = regOutput[5]; - 5'b00110 : readData2 = regOutput[6]; - 5'b00111 : readData2 = regOutput[7]; - 5'b01000 : readData2 = regOutput[8]; - 5'b01001 : readData2 = regOutput[9]; - 5'b01010 : readData2 = regOutput[10]; - 5'b01011 : readData2 = regOutput[11]; - 5'b01100 : readData2 = regOutput[12]; - 5'b01101 : readData2 = regOutput[13]; - 5'b01110 : readData2 = regOutput[14]; - 5'b01111 : readData2 = regOutput[15]; - 5'b10000 : readData2 = regOutput[16]; - 5'b10001 : readData2 = regOutput[17]; - 5'b10010 : readData2 = regOutput[18]; - 5'b10011 : readData2 = regOutput[19]; - 5'b10100 : readData2 = regOutput[20]; - 5'b10101 : readData2 = regOutput[21]; - 5'b10110 : readData2 = regOutput[22]; - 5'b10111 : readData2 = regOutput[23]; - 5'b11000 : readData2 = regOutput[24]; - 5'b11001 : readData2 = regOutput[25]; - 5'b11010 : readData2 = regOutput[26]; - 5'b11011 : readData2 = regOutput[27]; - 5'b11100 : readData2 = regOutput[28]; - 5'b11101 : readData2 = regOutput[29]; - 5'b11110 : readData2 = regOutput[30]; - 5'b11111 : readData2 = regOutput[31]; - default : readData2 = `XLEN'h0; - endcase - - //address 3 decoder - case(adr3) - 5'b00000 : readData3 = regOutput[0]; - 5'b00001 : readData3 = regOutput[1]; - 5'b00010 : readData3 = regOutput[2]; - 5'b00011 : readData3 = regOutput[3]; - 5'b00100 : readData3 = regOutput[4]; - 5'b00101 : readData3 = regOutput[5]; - 5'b00110 : readData3 = regOutput[6]; - 5'b00111 : readData3 = regOutput[7]; - 5'b01000 : readData3 = regOutput[8]; - 5'b01001 : readData3 = regOutput[9]; - 5'b01010 : readData3 = regOutput[10]; - 5'b01011 : readData3 = regOutput[11]; - 5'b01100 : readData3 = regOutput[12]; - 5'b01101 : readData3 = regOutput[13]; - 5'b01110 : readData3 = regOutput[14]; - 5'b01111 : readData3 = regOutput[15]; - 5'b10000 : readData3 = regOutput[16]; - 5'b10001 : readData3 = regOutput[17]; - 5'b10010 : readData3 = regOutput[18]; - 5'b10011 : readData3 = regOutput[19]; - 5'b10100 : readData3 = regOutput[20]; - 5'b10101 : readData3 = regOutput[21]; - 5'b10110 : readData3 = regOutput[22]; - 5'b10111 : readData3 = regOutput[23]; - 5'b11000 : readData3 = regOutput[24]; - 5'b11001 : readData3 = regOutput[25]; - 5'b11010 : readData3 = regOutput[26]; - 5'b11011 : readData3 = regOutput[27]; - 5'b11100 : readData3 = regOutput[28]; - 5'b11101 : readData3 = regOutput[29]; - 5'b11110 : readData3 = regOutput[30]; - 5'b11111 : readData3 = regOutput[31]; - default : readData3 = `XLEN'h0; - endcase - end - - //destination register decoder - //only change input values on write - //defaults to undefined with invalid address - // - //note - this is an intermediary signal, so - //this is not asynch assignment. FF in flopr - //will not update data until clk pulse - always_comb begin - if(write) begin - case(rd) - 5'b00000 : regInput[0] = writeData; - 5'b00001 : regInput[1] = writeData; - 5'b00010 : regInput[2] = writeData; - 5'b00011 : regInput[3] = writeData; - 5'b00100 : regInput[4] = writeData; - 5'b00101 : regInput[5] = writeData; - 5'b00110 : regInput[6] = writeData; - 5'b00111 : regInput[7] = writeData; - 5'b01000 : regInput[8] = writeData; - 5'b01001 : regInput[9] = writeData; - 5'b01010 : regInput[10] = writeData; - 5'b01011 : regInput[11] = writeData; - 5'b01100 : regInput[12] = writeData; - 5'b01101 : regInput[13] = writeData; - 5'b01110 : regInput[14] = writeData; - 5'b01111 : regInput[15] = writeData; - 5'b10000 : regInput[16] = writeData; - 5'b10001 : regInput[17] = writeData; - 5'b10010 : regInput[18] = writeData; - 5'b10011 : regInput[19] = writeData; - 5'b10100 : regInput[20] = writeData; - 5'b10101 : regInput[21] = writeData; - 5'b10110 : regInput[22] = writeData; - 5'b10111 : regInput[23] = writeData; - 5'b11000 : regInput[24] = writeData; - 5'b11001 : regInput[25] = writeData; - 5'b11010 : regInput[26] = writeData; - 5'b11011 : regInput[27] = writeData; - 5'b11100 : regInput[28] = writeData; - 5'b11101 : regInput[29] = writeData; - 5'b11110 : regInput[30] = writeData; - 5'b11111 : regInput[31] = writeData; - default : regInput[0] = `XLEN'hx; - endcase - end - end - -endmodule diff --git a/wally-pipelined/src/fpu/dev/fsgn.sv b/wally-pipelined/src/fpu/dev/fsgn.sv deleted file mode 100755 index 2d51af883..000000000 --- a/wally-pipelined/src/fpu/dev/fsgn.sv +++ /dev/null @@ -1,31 +0,0 @@ -//performs the fsgnj/fsgnjn/fsgnjx RISCV instructions - -module fpusgn (op_code, Y, Flags, A, B); - - input [63:0] A, B; - input [1:0] op_code; - output [63:0] Y; - output [4:0] Flags; - - wire AonesExp; - - //op code designation: - // - //00 - fsgnj - directly copy over sign value of B - //01 - fsgnjn - negate sign value of B - //10 - fsgnjx - XOR sign values of A & B - // - - assign Y[63] = op_code[1] ? (A[63] ^ B[63]) : (B[63] ^ op_code[0]); - assign Y[62:0] = A[62:0]; - - //If the exponent is all ones, then the value is either Inf or NaN, - //both of which will produce a QNaN/SNaN value of some sort. This will - //set the invalid flag high. - assign AonesExp = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]; - - //the only flag that can occur during this operation is invalid - //due to changing sign on already existing NaN - assign Flags = {AonesExp & Y[63], 1'b0, 1'b0, 1'b0, 1'b0}; - -endmodule diff --git a/wally-pipelined/src/fpu/dev/fsm.v b/wally-pipelined/src/fpu/dev/fsm.v deleted file mode 100755 index 208b129c3..000000000 --- a/wally-pipelined/src/fpu/dev/fsm.v +++ /dev/null @@ -1,459 +0,0 @@ -module fsm (done, load_rega, load_regb, load_regc, - load_regd, load_regr, load_regs, - sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - input clk; - input reset; - input start; - input error; - input op_type; - - output done; - output load_rega; - output load_regb; - output load_regc; - output load_regd; - output load_regr; - output load_regs; - - output [2:0] sel_muxa; - output [2:0] sel_muxb; - output sel_muxr; - - reg done; // End of cycles - reg load_rega; // enable for regA - reg load_regb; // enable for regB - reg load_regc; // enable for regC - reg load_regd; // enable for regD - reg load_regr; // enable for rem - reg load_regs; // enable for q,qm,qp - reg [2:0] sel_muxa; // Select muxA - reg [2:0] sel_muxb; // Select muxB - reg sel_muxr; // Select rem mux - - reg [4:0] CURRENT_STATE; - reg [4:0] NEXT_STATE; - - parameter [4:0] - S0=5'd0, S1=5'd1, S2=5'd2, - S3=5'd3, S4=5'd4, S5=5'd5, - S6=5'd6, S7=5'd7, S8=5'd8, - S9=5'd9, S10=5'd10, - S13=5'd13, S14=5'd14, S15=5'd15, - S16=5'd16, S17=5'd17, S18=5'd18, - S19=5'd19, S20=5'd20, S21=5'd21, - S22=5'd22, S23=5'd23, S24=5'd24, - S25=5'd25, S26=5'd26, S27=5'd27, - S28=5'd28, S29=5'd29, S30=5'd30; - - always @(posedge clk) - begin - if(reset==1'b1) - CURRENT_STATE<=S0; - else - CURRENT_STATE<=NEXT_STATE; - end - - always @(*) - begin - case(CURRENT_STATE) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - else if (start==1'b1 && op_type==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S1; - end // if (start==1'b1 && op_type==1'b0) - else if (start==1'b1 && op_type==1'b1) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S13; - end - end // case: S0 - S1: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S2; - end - S2: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S3; - end - S3: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S4; - end - S4: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S5; - end - S5: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; // add - NEXT_STATE <= S6; - end - S6: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end - S7: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end // case: S7 - S8: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S9; - end - S9: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - NEXT_STATE <= S10; - end - S10: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - S13: // start of sqrt path - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S14; - end - S14: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - NEXT_STATE <= S15; - end - S15: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S16; - end - S16: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S17; - end - S17: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S18; - end - S18: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S19; - end - S19: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S20; - end - S20: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S21; - end - S21: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S22; - end - S22: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S23; - end - S23: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S24; - end - S24: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S25; - end - S25: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - NEXT_STATE <= S26; - end - S26: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - default: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - endcase // case(CURRENT_STATE) - end // always @ (CURRENT_STATE or X) - -endmodule // fsm diff --git a/wally-pipelined/src/fpu/dev/ldf128.v b/wally-pipelined/src/fpu/dev/ldf128.v deleted file mode 100755 index 6c8387781..000000000 --- a/wally-pipelined/src/fpu/dev/ldf128.v +++ /dev/null @@ -1,543 +0,0 @@ -// Ladner-Fischer Prefix Adder - -module ldf128 (cout, sum, a, b, cin); - - input [127:0] a, b; - input cin; - - output [127:0] sum; - output cout; - - wire [128:0] p,g; - wire [127:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - - // prefix tree - ladner_fischer128 prefix_tree (c, p[127:0], g[127:0]); - - // post-computation - assign sum=p[128:1]^c; - assign cout=g[128]|(p[128]&c[127]); - -endmodule - -module ladner_fischer128 (c, p, g); - - input [127:0] p; - input [127:0] g; - - output [128:1] c; - - // parallel-prefix, Ladner-Fischer - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]}); - - black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]}); - black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]}); - black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]}); - black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]}); - black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]}); - black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]}); - black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]}); - black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]}); - - black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]}); - black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]}); - black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]}); - black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]}); - black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]}); - black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]}); - black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]}); - black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]}); - - black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]}); - black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]}); - black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]}); - black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]}); - black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]}); - black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]}); - black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]}); - black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]}); - - black b_65_64 (G_65_64, P_65_64, {g[65],g[64]}, {p[65],p[64]}); - black b_67_66 (G_67_66, P_67_66, {g[67],g[66]}, {p[67],p[66]}); - black b_69_68 (G_69_68, P_69_68, {g[69],g[68]}, {p[69],p[68]}); - black b_71_70 (G_71_70, P_71_70, {g[71],g[70]}, {p[71],p[70]}); - black b_73_72 (G_73_72, P_73_72, {g[73],g[72]}, {p[73],p[72]}); - black b_75_74 (G_75_74, P_75_74, {g[75],g[74]}, {p[75],p[74]}); - black b_77_76 (G_77_76, P_77_76, {g[77],g[76]}, {p[77],p[76]}); - black b_79_78 (G_79_78, P_79_78, {g[79],g[78]}, {p[79],p[78]}); - - black b_81_80 (G_81_80, P_81_80, {g[81],g[80]}, {p[81],p[80]}); - black b_83_82 (G_83_82, P_83_82, {g[83],g[82]}, {p[83],p[82]}); - black b_85_84 (G_85_84, P_85_84, {g[85],g[84]}, {p[85],p[84]}); - black b_87_86 (G_87_86, P_87_86, {g[87],g[86]}, {p[87],p[86]}); - black b_89_88 (G_89_88, P_89_88, {g[89],g[88]}, {p[89],p[88]}); - black b_91_90 (G_91_90, P_91_90, {g[91],g[90]}, {p[91],p[90]}); - black b_93_92 (G_93_92, P_93_92, {g[93],g[92]}, {p[93],p[92]}); - black b_95_94 (G_95_94, P_95_94, {g[95],g[94]}, {p[95],p[94]}); - - black b_97_96 (G_97_96, P_97_96, {g[97],g[96]}, {p[97],p[96]}); - black b_99_98 (G_99_98, P_99_98, {g[99],g[98]}, {p[99],p[98]}); - black b_101_100 (G_101_100, P_101_100, {g[101],g[100]}, {p[101],p[100]}); - black b_103_102 (G_103_102, P_103_102, {g[103],g[102]}, {p[103],p[102]}); - black b_105_104 (G_105_104, P_105_104, {g[105],g[104]}, {p[105],p[104]}); - black b_107_106 (G_107_106, P_107_106, {g[107],g[106]}, {p[107],p[106]}); - black b_109_108 (G_109_108, P_109_108, {g[109],g[108]}, {p[109],p[108]}); - black b_111_110 (G_111_110, P_111_110, {g[111],g[110]}, {p[111],p[110]}); - - black b_113_112 (G_113_112, P_113_112, {g[113],g[112]}, {p[113],p[112]}); - black b_115_114 (G_115_114, P_115_114, {g[115],g[114]}, {p[115],p[114]}); - black b_117_116 (G_117_116, P_117_116, {g[117],g[116]}, {p[117],p[116]}); - black b_119_118 (G_119_118, P_119_118, {g[119],g[118]}, {p[119],p[118]}); - black b_121_120 (G_121_120, P_121_120, {g[121],g[120]}, {p[121],p[120]}); - black b_123_122 (G_123_122, P_123_122, {g[123],g[122]}, {p[123],p[122]}); - black b_125_124 (G_125_124, P_125_124, {g[125],g[124]}, {p[125],p[124]}); - black b_127_126 (G_127_126, P_127_126, {g[127],g[126]}, {p[127],p[126]}); - - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12}); - black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16}); - black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20}); - black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24}); - black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28}); - - black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32}); - black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36}); - black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40}); - black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44}); - black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48}); - black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52}); - black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56}); - black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60}); - - black b_67_64 (G_67_64, P_67_64, {G_67_66,G_65_64}, {P_67_66,P_65_64}); - black b_71_68 (G_71_68, P_71_68, {G_71_70,G_69_68}, {P_71_70,P_69_68}); - black b_75_72 (G_75_72, P_75_72, {G_75_74,G_73_72}, {P_75_74,P_73_72}); - black b_79_76 (G_79_76, P_79_76, {G_79_78,G_77_76}, {P_79_78,P_77_76}); - black b_83_80 (G_83_80, P_83_80, {G_83_82,G_81_80}, {P_83_82,P_81_80}); - black b_87_84 (G_87_84, P_87_84, {G_87_86,G_85_84}, {P_87_86,P_85_84}); - black b_91_88 (G_91_88, P_91_88, {G_91_90,G_89_88}, {P_91_90,P_89_88}); - black b_95_92 (G_95_92, P_95_92, {G_95_94,G_93_92}, {P_95_94,P_93_92}); - - black b_99_96 (G_99_96, P_99_96, {G_99_98,G_97_96}, {P_99_98,P_97_96}); - black b_103_100 (G_103_100, P_103_100, {G_103_102,G_101_100}, {P_103_102,P_101_100}); - black b_107_104 (G_107_104, P_107_104, {G_107_106,G_105_104}, {P_107_106,P_105_104}); - black b_111_108 (G_111_108, P_111_108, {G_111_110,G_109_108}, {P_111_110,P_109_108}); - black b_115_112 (G_115_112, P_115_112, {G_115_114,G_113_112}, {P_115_114,P_113_112}); - black b_119_116 (G_119_116, P_119_116, {G_119_118,G_117_116}, {P_119_118,P_117_116}); - black b_123_120 (G_123_120, P_123_120, {G_123_122,G_121_120}, {P_123_122,P_121_120}); - black b_127_124 (G_127_124, P_127_124, {G_127_126,G_125_124}, {P_127_126,P_125_124}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8}); - black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8}); - black b_21_16 (G_21_16, P_21_16, {G_21_20,G_19_16}, {P_21_20,P_19_16}); - black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16}); - black b_29_24 (G_29_24, P_29_24, {G_29_28,G_27_24}, {P_29_28,P_27_24}); - black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24}); - - black b_37_32 (G_37_32, P_37_32, {G_37_36,G_35_32}, {P_37_36,P_35_32}); - black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32}); - black b_45_40 (G_45_40, P_45_40, {G_45_44,G_43_40}, {P_45_44,P_43_40}); - black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40}); - black b_53_48 (G_53_48, P_53_48, {G_53_52,G_51_48}, {P_53_52,P_51_48}); - black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48}); - black b_61_56 (G_61_56, P_61_56, {G_61_60,G_59_56}, {P_61_60,P_59_56}); - black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56}); - - black b_69_64 (G_69_64, P_69_64, {G_69_68,G_67_64}, {P_69_68,P_67_64}); - black b_71_64 (G_71_64, P_71_64, {G_71_68,G_67_64}, {P_71_68,P_67_64}); - black b_77_72 (G_77_72, P_77_72, {G_77_76,G_75_72}, {P_77_76,P_75_72}); - black b_79_72 (G_79_72, P_79_72, {G_79_76,G_75_72}, {P_79_76,P_75_72}); - black b_85_80 (G_85_80, P_85_80, {G_85_84,G_83_80}, {P_85_84,P_83_80}); - black b_87_80 (G_87_80, P_87_80, {G_87_84,G_83_80}, {P_87_84,P_83_80}); - black b_93_88 (G_93_88, P_93_88, {G_93_92,G_91_88}, {P_93_92,P_91_88}); - black b_95_88 (G_95_88, P_95_88, {G_95_92,G_91_88}, {P_95_92,P_91_88}); - - black b_101_96 (G_101_96, P_101_96, {G_101_100,G_99_96}, {P_101_100,P_99_96}); - black b_103_96 (G_103_96, P_103_96, {G_103_100,G_99_96}, {P_103_100,P_99_96}); - black b_109_104 (G_109_104, P_109_104, {G_109_108,G_107_104}, {P_109_108,P_107_104}); - black b_111_104 (G_111_104, P_111_104, {G_111_108,G_107_104}, {P_111_108,P_107_104}); - black b_117_112 (G_117_112, P_117_112, {G_117_116,G_115_112}, {P_117_116,P_115_112}); - black b_119_112 (G_119_112, P_119_112, {G_119_116,G_115_112}, {P_119_116,P_115_112}); - black b_125_120 (G_125_120, P_125_120, {G_125_124,G_123_120}, {P_125_124,P_123_120}); - black b_127_120 (G_127_120, P_127_120, {G_127_124,G_123_120}, {P_127_124,P_123_120}); - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8); - grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8); - black b_25_16 (G_25_16, P_25_16, {G_25_24,G_23_16}, {P_25_24,P_23_16}); - black b_27_16 (G_27_16, P_27_16, {G_27_24,G_23_16}, {P_27_24,P_23_16}); - black b_29_16 (G_29_16, P_29_16, {G_29_24,G_23_16}, {P_29_24,P_23_16}); - black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16}); - - black b_41_32 (G_41_32, P_41_32, {G_41_40,G_39_32}, {P_41_40,P_39_32}); - black b_43_32 (G_43_32, P_43_32, {G_43_40,G_39_32}, {P_43_40,P_39_32}); - black b_45_32 (G_45_32, P_45_32, {G_45_40,G_39_32}, {P_45_40,P_39_32}); - black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32}); - black b_57_48 (G_57_48, P_57_48, {G_57_56,G_55_48}, {P_57_56,P_55_48}); - black b_59_48 (G_59_48, P_59_48, {G_59_56,G_55_48}, {P_59_56,P_55_48}); - black b_61_48 (G_61_48, P_61_48, {G_61_56,G_55_48}, {P_61_56,P_55_48}); - black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48}); - - black b_73_64 (G_73_64, P_73_64, {G_73_72,G_71_64}, {P_73_72,P_71_64}); - black b_75_64 (G_75_64, P_75_64, {G_75_72,G_71_64}, {P_75_72,P_71_64}); - black b_77_64 (G_77_64, P_77_64, {G_77_72,G_71_64}, {P_77_72,P_71_64}); - black b_79_64 (G_79_64, P_79_64, {G_79_72,G_71_64}, {P_79_72,P_71_64}); - black b_89_80 (G_89_80, P_89_80, {G_89_88,G_87_80}, {P_89_88,P_87_80}); - black b_91_80 (G_91_80, P_91_80, {G_91_88,G_87_80}, {P_91_88,P_87_80}); - black b_93_80 (G_93_80, P_93_80, {G_93_88,G_87_80}, {P_93_88,P_87_80}); - black b_95_80 (G_95_80, P_95_80, {G_95_88,G_87_80}, {P_95_88,P_87_80}); - - black b_105_96 (G_105_96, P_105_96, {G_105_104,G_103_96}, {P_105_104,P_103_96}); - black b_107_96 (G_107_96, P_107_96, {G_107_104,G_103_96}, {P_107_104,P_103_96}); - black b_109_96 (G_109_96, P_109_96, {G_109_104,G_103_96}, {P_109_104,P_103_96}); - black b_111_96 (G_111_96, P_111_96, {G_111_104,G_103_96}, {P_111_104,P_103_96}); - black b_121_112 (G_121_112, P_121_112, {G_121_120,G_119_112}, {P_121_120,P_119_112}); - black b_123_112 (G_123_112, P_123_112, {G_123_120,G_119_112}, {P_123_120,P_119_112}); - black b_125_112 (G_125_112, P_125_112, {G_125_120,G_119_112}, {P_125_120,P_119_112}); - black b_127_112 (G_127_112, P_127_112, {G_127_120,G_119_112}, {P_127_120,P_119_112}); - - // Stage 5: Generates G/P pairs that span 16 bits - grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16); - grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16); - grey g_21_0 (G_21_0, {G_21_16,G_15_0}, P_21_16); - grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16); - grey g_25_0 (G_25_0, {G_25_16,G_15_0}, P_25_16); - grey g_27_0 (G_27_0, {G_27_16,G_15_0}, P_27_16); - grey g_29_0 (G_29_0, {G_29_16,G_15_0}, P_29_16); - grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16); - - black b_49_32 (G_49_32, P_49_32, {G_49_48,G_47_32}, {P_49_48,P_47_32}); - black b_51_32 (G_51_32, P_51_32, {G_51_48,G_47_32}, {P_51_48,P_47_32}); - black b_53_32 (G_53_32, P_53_32, {G_53_48,G_47_32}, {P_53_48,P_47_32}); - black b_55_32 (G_55_32, P_55_32, {G_55_48,G_47_32}, {P_55_48,P_47_32}); - black b_57_32 (G_57_32, P_57_32, {G_57_48,G_47_32}, {P_57_48,P_47_32}); - black b_59_32 (G_59_32, P_59_32, {G_59_48,G_47_32}, {P_59_48,P_47_32}); - black b_61_32 (G_61_32, P_61_32, {G_61_48,G_47_32}, {P_61_48,P_47_32}); - black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32}); - - black b_81_64 (G_81_64, P_81_64, {G_81_80,G_79_64}, {P_81_80,P_79_64}); - black b_83_64 (G_83_64, P_83_64, {G_83_80,G_79_64}, {P_83_80,P_79_64}); - black b_85_64 (G_85_64, P_85_64, {G_85_80,G_79_64}, {P_85_80,P_79_64}); - black b_87_64 (G_87_64, P_87_64, {G_87_80,G_79_64}, {P_87_80,P_79_64}); - black b_89_64 (G_89_64, P_89_64, {G_89_80,G_79_64}, {P_89_80,P_79_64}); - black b_91_64 (G_91_64, P_91_64, {G_91_80,G_79_64}, {P_91_80,P_79_64}); - black b_93_64 (G_93_64, P_93_64, {G_93_80,G_79_64}, {P_93_80,P_79_64}); - black b_95_64 (G_95_64, P_95_64, {G_95_80,G_79_64}, {P_95_80,P_79_64}); - - black b_113_96 (G_113_96, P_113_96, {G_113_112,G_111_96}, {P_113_112,P_111_96}); - black b_115_96 (G_115_96, P_115_96, {G_115_112,G_111_96}, {P_115_112,P_111_96}); - black b_117_96 (G_117_96, P_117_96, {G_117_112,G_111_96}, {P_117_112,P_111_96}); - black b_119_96 (G_119_96, P_119_96, {G_119_112,G_111_96}, {P_119_112,P_111_96}); - black b_121_96 (G_121_96, P_121_96, {G_121_112,G_111_96}, {P_121_112,P_111_96}); - black b_123_96 (G_123_96, P_123_96, {G_123_112,G_111_96}, {P_123_112,P_111_96}); - black b_125_96 (G_125_96, P_125_96, {G_125_112,G_111_96}, {P_125_112,P_111_96}); - black b_127_96 (G_127_96, P_127_96, {G_127_112,G_111_96}, {P_127_112,P_111_96}); - - // Stage 6: Generates G/P pairs that span 32 bits - grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32); - grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32); - grey g_37_0 (G_37_0, {G_37_32,G_31_0}, P_37_32); - grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32); - grey g_41_0 (G_41_0, {G_41_32,G_31_0}, P_41_32); - grey g_43_0 (G_43_0, {G_43_32,G_31_0}, P_43_32); - grey g_45_0 (G_45_0, {G_45_32,G_31_0}, P_45_32); - grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32); - - grey g_49_0 (G_49_0, {G_49_32,G_31_0}, P_49_32); - grey g_51_0 (G_51_0, {G_51_32,G_31_0}, P_51_32); - grey g_53_0 (G_53_0, {G_53_32,G_31_0}, P_53_32); - grey g_55_0 (G_55_0, {G_55_32,G_31_0}, P_55_32); - grey g_57_0 (G_57_0, {G_57_32,G_31_0}, P_57_32); - grey g_59_0 (G_59_0, {G_59_32,G_31_0}, P_59_32); - grey g_61_0 (G_61_0, {G_61_32,G_31_0}, P_61_32); - grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32); - - black b_97_64 (G_97_64, P_97_64, {G_97_96,G_95_64}, {P_97_96,P_95_64}); - black b_99_64 (G_99_64, P_99_64, {G_99_96,G_95_64}, {P_99_96,P_95_64}); - black b_101_64 (G_101_64, P_101_64, {G_101_96,G_95_64}, {P_101_96,P_95_64}); - black b_103_64 (G_103_64, P_103_64, {G_103_96,G_95_64}, {P_103_96,P_95_64}); - black b_105_64 (G_105_64, P_105_64, {G_105_96,G_95_64}, {P_105_96,P_95_64}); - black b_107_64 (G_107_64, P_107_64, {G_107_96,G_95_64}, {P_107_96,P_95_64}); - black b_109_64 (G_109_64, P_109_64, {G_109_96,G_95_64}, {P_109_96,P_95_64}); - black b_111_64 (G_111_64, P_111_64, {G_111_96,G_95_64}, {P_111_96,P_95_64}); - - black b_113_64 (G_113_64, P_113_64, {G_113_96,G_95_64}, {P_113_96,P_95_64}); - black b_115_64 (G_115_64, P_115_64, {G_115_96,G_95_64}, {P_115_96,P_95_64}); - black b_117_64 (G_117_64, P_117_64, {G_117_96,G_95_64}, {P_117_96,P_95_64}); - black b_119_64 (G_119_64, P_119_64, {G_119_96,G_95_64}, {P_119_96,P_95_64}); - black b_121_64 (G_121_64, P_121_64, {G_121_96,G_95_64}, {P_121_96,P_95_64}); - black b_123_64 (G_123_64, P_123_64, {G_123_96,G_95_64}, {P_123_96,P_95_64}); - black b_125_64 (G_125_64, P_125_64, {G_125_96,G_95_64}, {P_125_96,P_95_64}); - black b_127_64 (G_127_64, P_127_64, {G_127_96,G_95_64}, {P_127_96,P_95_64}); - - // Stage 7: Generates G/P pairs that span 64 bits - grey g_65_0 (G_65_0, {G_65_64,G_63_0}, P_65_64); - grey g_67_0 (G_67_0, {G_67_64,G_63_0}, P_67_64); - grey g_69_0 (G_69_0, {G_69_64,G_63_0}, P_69_64); - grey g_71_0 (G_71_0, {G_71_64,G_63_0}, P_71_64); - grey g_73_0 (G_73_0, {G_73_64,G_63_0}, P_73_64); - grey g_75_0 (G_75_0, {G_75_64,G_63_0}, P_75_64); - grey g_77_0 (G_77_0, {G_77_64,G_63_0}, P_77_64); - grey g_79_0 (G_79_0, {G_79_64,G_63_0}, P_79_64); - - grey g_81_0 (G_81_0, {G_81_64,G_63_0}, P_81_64); - grey g_83_0 (G_83_0, {G_83_64,G_63_0}, P_83_64); - grey g_85_0 (G_85_0, {G_85_64,G_63_0}, P_85_64); - grey g_87_0 (G_87_0, {G_87_64,G_63_0}, P_87_64); - grey g_89_0 (G_89_0, {G_89_64,G_63_0}, P_89_64); - grey g_91_0 (G_91_0, {G_91_64,G_63_0}, P_91_64); - grey g_93_0 (G_93_0, {G_93_64,G_63_0}, P_93_64); - grey g_95_0 (G_95_0, {G_95_64,G_63_0}, P_95_64); - - grey g_97_0 (G_97_0, {G_97_64,G_63_0}, P_97_64); - grey g_99_0 (G_99_0, {G_99_64,G_63_0}, P_99_64); - grey g_101_0 (G_101_0, {G_101_64,G_63_0}, P_101_64); - grey g_103_0 (G_103_0, {G_103_64,G_63_0}, P_103_64); - grey g_105_0 (G_105_0, {G_105_64,G_63_0}, P_105_64); - grey g_107_0 (G_107_0, {G_107_64,G_63_0}, P_107_64); - grey g_109_0 (G_109_0, {G_109_64,G_63_0}, P_109_64); - grey g_111_0 (G_111_0, {G_111_64,G_63_0}, P_111_64); - - grey g_113_0 (G_113_0, {G_113_64,G_63_0}, P_113_64); - grey g_115_0 (G_115_0, {G_115_64,G_63_0}, P_115_64); - grey g_117_0 (G_117_0, {G_117_64,G_63_0}, P_117_64); - grey g_119_0 (G_119_0, {G_119_64,G_63_0}, P_119_64); - grey g_121_0 (G_121_0, {G_121_64,G_63_0}, P_121_64); - grey g_123_0 (G_123_0, {G_123_64,G_63_0}, P_123_64); - grey g_125_0 (G_125_0, {G_125_64,G_63_0}, P_125_64); - grey g_127_0 (G_127_0, {G_127_64,G_63_0}, P_127_64); - - // Extra grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]); - grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]); - grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]); - grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]); - grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]); - grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]); - grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]); - grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]); - grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]); - grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]); - grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]); - grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]); - grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]); - grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]); - grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]); - grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]); - grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]); - grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]); - grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]); - grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]); - grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]); - grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]); - grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]); - grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]); - grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]); - grey g_64_0 (G_64_0, {g[64],G_63_0}, p[64]); - grey g_66_0 (G_66_0, {g[66],G_65_0}, p[66]); - grey g_68_0 (G_68_0, {g[68],G_67_0}, p[68]); - grey g_70_0 (G_70_0, {g[70],G_69_0}, p[70]); - grey g_72_0 (G_72_0, {g[72],G_71_0}, p[72]); - grey g_74_0 (G_74_0, {g[74],G_73_0}, p[74]); - grey g_76_0 (G_76_0, {g[76],G_75_0}, p[76]); - grey g_78_0 (G_78_0, {g[78],G_77_0}, p[78]); - grey g_80_0 (G_80_0, {g[80],G_79_0}, p[80]); - grey g_82_0 (G_82_0, {g[82],G_81_0}, p[82]); - grey g_84_0 (G_84_0, {g[84],G_83_0}, p[84]); - grey g_86_0 (G_86_0, {g[86],G_85_0}, p[86]); - grey g_88_0 (G_88_0, {g[88],G_87_0}, p[88]); - grey g_90_0 (G_90_0, {g[90],G_89_0}, p[90]); - grey g_92_0 (G_92_0, {g[92],G_91_0}, p[92]); - grey g_94_0 (G_94_0, {g[94],G_93_0}, p[94]); - grey g_96_0 (G_96_0, {g[96],G_95_0}, p[96]); - grey g_98_0 (G_98_0, {g[98],G_97_0}, p[98]); - grey g_100_0 (G_100_0, {g[100],G_99_0}, p[100]); - grey g_102_0 (G_102_0, {g[102],G_101_0}, p[102]); - grey g_104_0 (G_104_0, {g[104],G_103_0}, p[104]); - grey g_106_0 (G_106_0, {g[106],G_105_0}, p[106]); - grey g_108_0 (G_108_0, {g[108],G_107_0}, p[108]); - grey g_110_0 (G_110_0, {g[110],G_109_0}, p[110]); - grey g_112_0 (G_112_0, {g[112],G_111_0}, p[112]); - grey g_114_0 (G_114_0, {g[114],G_113_0}, p[114]); - grey g_116_0 (G_116_0, {g[116],G_115_0}, p[116]); - grey g_118_0 (G_118_0, {g[118],G_117_0}, p[118]); - grey g_120_0 (G_120_0, {g[120],G_119_0}, p[120]); - grey g_122_0 (G_122_0, {g[122],G_121_0}, p[122]); - grey g_124_0 (G_124_0, {g[124],G_123_0}, p[124]); - grey g_126_0 (G_126_0, {g[126],G_125_0}, p[126]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - assign c[15]=G_14_0; - assign c[16]=G_15_0; - assign c[17]=G_16_0; - - assign c[18]=G_17_0; - assign c[19]=G_18_0; - assign c[20]=G_19_0; - assign c[21]=G_20_0; - assign c[22]=G_21_0; - assign c[23]=G_22_0; - assign c[24]=G_23_0; - assign c[25]=G_24_0; - - assign c[26]=G_25_0; - assign c[27]=G_26_0; - assign c[28]=G_27_0; - assign c[29]=G_28_0; - assign c[30]=G_29_0; - assign c[31]=G_30_0; - assign c[32]=G_31_0; - assign c[33]=G_32_0; - - assign c[34]=G_33_0; - assign c[35]=G_34_0; - assign c[36]=G_35_0; - assign c[37]=G_36_0; - assign c[38]=G_37_0; - assign c[39]=G_38_0; - assign c[40]=G_39_0; - assign c[41]=G_40_0; - - assign c[42]=G_41_0; - assign c[43]=G_42_0; - assign c[44]=G_43_0; - assign c[45]=G_44_0; - assign c[46]=G_45_0; - assign c[47]=G_46_0; - assign c[48]=G_47_0; - assign c[49]=G_48_0; - - assign c[50]=G_49_0; - assign c[51]=G_50_0; - assign c[52]=G_51_0; - assign c[53]=G_52_0; - assign c[54]=G_53_0; - assign c[55]=G_54_0; - assign c[56]=G_55_0; - assign c[57]=G_56_0; - - assign c[58]=G_57_0; - assign c[59]=G_58_0; - assign c[60]=G_59_0; - assign c[61]=G_60_0; - assign c[62]=G_61_0; - assign c[63]=G_62_0; - assign c[64]=G_63_0; - assign c[65]=G_64_0; - - assign c[66]=G_65_0; - assign c[67]=G_66_0; - assign c[68]=G_67_0; - assign c[69]=G_68_0; - assign c[70]=G_69_0; - assign c[71]=G_70_0; - assign c[72]=G_71_0; - assign c[73]=G_72_0; - - assign c[74]=G_73_0; - assign c[75]=G_74_0; - assign c[76]=G_75_0; - assign c[77]=G_76_0; - assign c[78]=G_77_0; - assign c[79]=G_78_0; - assign c[80]=G_79_0; - assign c[81]=G_80_0; - - assign c[82]=G_81_0; - assign c[83]=G_82_0; - assign c[84]=G_83_0; - assign c[85]=G_84_0; - assign c[86]=G_85_0; - assign c[87]=G_86_0; - assign c[88]=G_87_0; - assign c[89]=G_88_0; - - assign c[90]=G_89_0; - assign c[91]=G_90_0; - assign c[92]=G_91_0; - assign c[93]=G_92_0; - assign c[94]=G_93_0; - assign c[95]=G_94_0; - assign c[96]=G_95_0; - assign c[97]=G_96_0; - - assign c[98]=G_97_0; - assign c[99]=G_98_0; - assign c[100]=G_99_0; - assign c[101]=G_100_0; - assign c[102]=G_101_0; - assign c[103]=G_102_0; - assign c[104]=G_103_0; - assign c[105]=G_104_0; - - assign c[106]=G_105_0; - assign c[107]=G_106_0; - assign c[108]=G_107_0; - assign c[109]=G_108_0; - assign c[110]=G_109_0; - assign c[111]=G_110_0; - assign c[112]=G_111_0; - assign c[113]=G_112_0; - - assign c[114]=G_113_0; - assign c[115]=G_114_0; - assign c[116]=G_115_0; - assign c[117]=G_116_0; - assign c[118]=G_117_0; - assign c[119]=G_118_0; - assign c[120]=G_119_0; - assign c[121]=G_120_0; - - assign c[122]=G_121_0; - assign c[123]=G_122_0; - assign c[124]=G_123_0; - assign c[125]=G_124_0; - assign c[126]=G_125_0; - assign c[127]=G_126_0; - assign c[128]=G_127_0; - -endmodule // ladner_fischer - diff --git a/wally-pipelined/src/fpu/dev/ldf64.v b/wally-pipelined/src/fpu/dev/ldf64.v deleted file mode 100755 index 70f8af3a1..000000000 --- a/wally-pipelined/src/fpu/dev/ldf64.v +++ /dev/null @@ -1,273 +0,0 @@ -// Ladner-Fischer Prefix Adder - -module ldf64 (cout, sum, a, b, cin); - input [63:0] a, b; - input cin; - output [63:0] sum; - output cout; - - wire [64:0] p,g; - wire [63:0] c; - - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - - // prefix tree - ladner_fischer64 prefix_tree(c, p[63:0], g[63:0]); - - // post-computation - assign sum=p[64:1]^c; - assign cout=g[64]|(p[64]&c[63]); - -endmodule - -module ladner_fischer64 (c, p, g); - - input [63:0] p; - input [63:0] g; - - output [64:1] c; - - // parallel-prefix, Ladner-Fischer - - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - black b_15_14 (G_15_14, P_15_14, {g[15],g[14]}, {p[15],p[14]}); - - black b_17_16 (G_17_16, P_17_16, {g[17],g[16]}, {p[17],p[16]}); - black b_19_18 (G_19_18, P_19_18, {g[19],g[18]}, {p[19],p[18]}); - black b_21_20 (G_21_20, P_21_20, {g[21],g[20]}, {p[21],p[20]}); - black b_23_22 (G_23_22, P_23_22, {g[23],g[22]}, {p[23],p[22]}); - black b_25_24 (G_25_24, P_25_24, {g[25],g[24]}, {p[25],p[24]}); - black b_27_26 (G_27_26, P_27_26, {g[27],g[26]}, {p[27],p[26]}); - black b_29_28 (G_29_28, P_29_28, {g[29],g[28]}, {p[29],p[28]}); - black b_31_30 (G_31_30, P_31_30, {g[31],g[30]}, {p[31],p[30]}); - - black b_33_32 (G_33_32, P_33_32, {g[33],g[32]}, {p[33],p[32]}); - black b_35_34 (G_35_34, P_35_34, {g[35],g[34]}, {p[35],p[34]}); - black b_37_36 (G_37_36, P_37_36, {g[37],g[36]}, {p[37],p[36]}); - black b_39_38 (G_39_38, P_39_38, {g[39],g[38]}, {p[39],p[38]}); - black b_41_40 (G_41_40, P_41_40, {g[41],g[40]}, {p[41],p[40]}); - black b_43_42 (G_43_42, P_43_42, {g[43],g[42]}, {p[43],p[42]}); - black b_45_44 (G_45_44, P_45_44, {g[45],g[44]}, {p[45],p[44]}); - black b_47_46 (G_47_46, P_47_46, {g[47],g[46]}, {p[47],p[46]}); - - black b_49_48 (G_49_48, P_49_48, {g[49],g[48]}, {p[49],p[48]}); - black b_51_50 (G_51_50, P_51_50, {g[51],g[50]}, {p[51],p[50]}); - black b_53_52 (G_53_52, P_53_52, {g[53],g[52]}, {p[53],p[52]}); - black b_55_54 (G_55_54, P_55_54, {g[55],g[54]}, {p[55],p[54]}); - black b_57_56 (G_57_56, P_57_56, {g[57],g[56]}, {p[57],p[56]}); - black b_59_58 (G_59_58, P_59_58, {g[59],g[58]}, {p[59],p[58]}); - black b_61_60 (G_61_60, P_61_60, {g[61],g[60]}, {p[61],p[60]}); - black b_63_62 (G_63_62, P_63_62, {g[63],g[62]}, {p[63],p[62]}); - - // Stage 2: Generates G/P pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12}); - black b_19_16 (G_19_16, P_19_16, {G_19_18,G_17_16}, {P_19_18,P_17_16}); - black b_23_20 (G_23_20, P_23_20, {G_23_22,G_21_20}, {P_23_22,P_21_20}); - black b_27_24 (G_27_24, P_27_24, {G_27_26,G_25_24}, {P_27_26,P_25_24}); - black b_31_28 (G_31_28, P_31_28, {G_31_30,G_29_28}, {P_31_30,P_29_28}); - - black b_35_32 (G_35_32, P_35_32, {G_35_34,G_33_32}, {P_35_34,P_33_32}); - black b_39_36 (G_39_36, P_39_36, {G_39_38,G_37_36}, {P_39_38,P_37_36}); - black b_43_40 (G_43_40, P_43_40, {G_43_42,G_41_40}, {P_43_42,P_41_40}); - black b_47_44 (G_47_44, P_47_44, {G_47_46,G_45_44}, {P_47_46,P_45_44}); - black b_51_48 (G_51_48, P_51_48, {G_51_50,G_49_48}, {P_51_50,P_49_48}); - black b_55_52 (G_55_52, P_55_52, {G_55_54,G_53_52}, {P_55_54,P_53_52}); - black b_59_56 (G_59_56, P_59_56, {G_59_58,G_57_56}, {P_59_58,P_57_56}); - black b_63_60 (G_63_60, P_63_60, {G_63_62,G_61_60}, {P_63_62,P_61_60}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8}); - black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8}); - black b_21_16 (G_21_16, P_21_16, {G_21_20,G_19_16}, {P_21_20,P_19_16}); - black b_23_16 (G_23_16, P_23_16, {G_23_20,G_19_16}, {P_23_20,P_19_16}); - black b_29_24 (G_29_24, P_29_24, {G_29_28,G_27_24}, {P_29_28,P_27_24}); - black b_31_24 (G_31_24, P_31_24, {G_31_28,G_27_24}, {P_31_28,P_27_24}); - - black b_37_32 (G_37_32, P_37_32, {G_37_36,G_35_32}, {P_37_36,P_35_32}); - black b_39_32 (G_39_32, P_39_32, {G_39_36,G_35_32}, {P_39_36,P_35_32}); - black b_45_40 (G_45_40, P_45_40, {G_45_44,G_43_40}, {P_45_44,P_43_40}); - black b_47_40 (G_47_40, P_47_40, {G_47_44,G_43_40}, {P_47_44,P_43_40}); - black b_53_48 (G_53_48, P_53_48, {G_53_52,G_51_48}, {P_53_52,P_51_48}); - black b_55_48 (G_55_48, P_55_48, {G_55_52,G_51_48}, {P_55_52,P_51_48}); - black b_61_56 (G_61_56, P_61_56, {G_61_60,G_59_56}, {P_61_60,P_59_56}); - black b_63_56 (G_63_56, P_63_56, {G_63_60,G_59_56}, {P_63_60,P_59_56}); - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8); - grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8); - black b_25_16 (G_25_16, P_25_16, {G_25_24,G_23_16}, {P_25_24,P_23_16}); - black b_27_16 (G_27_16, P_27_16, {G_27_24,G_23_16}, {P_27_24,P_23_16}); - black b_29_16 (G_29_16, P_29_16, {G_29_24,G_23_16}, {P_29_24,P_23_16}); - black b_31_16 (G_31_16, P_31_16, {G_31_24,G_23_16}, {P_31_24,P_23_16}); - - black b_41_32 (G_41_32, P_41_32, {G_41_40,G_39_32}, {P_41_40,P_39_32}); - black b_43_32 (G_43_32, P_43_32, {G_43_40,G_39_32}, {P_43_40,P_39_32}); - black b_45_32 (G_45_32, P_45_32, {G_45_40,G_39_32}, {P_45_40,P_39_32}); - black b_47_32 (G_47_32, P_47_32, {G_47_40,G_39_32}, {P_47_40,P_39_32}); - black b_57_48 (G_57_48, P_57_48, {G_57_56,G_55_48}, {P_57_56,P_55_48}); - black b_59_48 (G_59_48, P_59_48, {G_59_56,G_55_48}, {P_59_56,P_55_48}); - black b_61_48 (G_61_48, P_61_48, {G_61_56,G_55_48}, {P_61_56,P_55_48}); - black b_63_48 (G_63_48, P_63_48, {G_63_56,G_55_48}, {P_63_56,P_55_48}); - - // Stage 5: Generates G/P pairs that span 16 bits - grey g_17_0 (G_17_0, {G_17_16,G_15_0}, P_17_16); - grey g_19_0 (G_19_0, {G_19_16,G_15_0}, P_19_16); - grey g_21_0 (G_21_0, {G_21_16,G_15_0}, P_21_16); - grey g_23_0 (G_23_0, {G_23_16,G_15_0}, P_23_16); - grey g_25_0 (G_25_0, {G_25_16,G_15_0}, P_25_16); - grey g_27_0 (G_27_0, {G_27_16,G_15_0}, P_27_16); - grey g_29_0 (G_29_0, {G_29_16,G_15_0}, P_29_16); - grey g_31_0 (G_31_0, {G_31_16,G_15_0}, P_31_16); - - black b_49_32 (G_49_32, P_49_32, {G_49_48,G_47_32}, {P_49_48,P_47_32}); - black b_51_32 (G_51_32, P_51_32, {G_51_48,G_47_32}, {P_51_48,P_47_32}); - black b_53_32 (G_53_32, P_53_32, {G_53_48,G_47_32}, {P_53_48,P_47_32}); - black b_55_32 (G_55_32, P_55_32, {G_55_48,G_47_32}, {P_55_48,P_47_32}); - black b_57_32 (G_57_32, P_57_32, {G_57_48,G_47_32}, {P_57_48,P_47_32}); - black b_59_32 (G_59_32, P_59_32, {G_59_48,G_47_32}, {P_59_48,P_47_32}); - black b_61_32 (G_61_32, P_61_32, {G_61_48,G_47_32}, {P_61_48,P_47_32}); - black b_63_32 (G_63_32, P_63_32, {G_63_48,G_47_32}, {P_63_48,P_47_32}); - - // Stage 6: Generates G/P pairs that span 32 bits - grey g_33_0 (G_33_0, {G_33_32,G_31_0}, P_33_32); - grey g_35_0 (G_35_0, {G_35_32,G_31_0}, P_35_32); - grey g_37_0 (G_37_0, {G_37_32,G_31_0}, P_37_32); - grey g_39_0 (G_39_0, {G_39_32,G_31_0}, P_39_32); - grey g_41_0 (G_41_0, {G_41_32,G_31_0}, P_41_32); - grey g_43_0 (G_43_0, {G_43_32,G_31_0}, P_43_32); - grey g_45_0 (G_45_0, {G_45_32,G_31_0}, P_45_32); - grey g_47_0 (G_47_0, {G_47_32,G_31_0}, P_47_32); - - grey g_49_0 (G_49_0, {G_49_32,G_31_0}, P_49_32); - grey g_51_0 (G_51_0, {G_51_32,G_31_0}, P_51_32); - grey g_53_0 (G_53_0, {G_53_32,G_31_0}, P_53_32); - grey g_55_0 (G_55_0, {G_55_32,G_31_0}, P_55_32); - grey g_57_0 (G_57_0, {G_57_32,G_31_0}, P_57_32); - grey g_59_0 (G_59_0, {G_59_32,G_31_0}, P_59_32); - grey g_61_0 (G_61_0, {G_61_32,G_31_0}, P_61_32); - grey g_63_0 (G_63_0, {G_63_32,G_31_0}, P_63_32); - - // Extra grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - grey g_14_0 (G_14_0, {g[14],G_13_0}, p[14]); - grey g_16_0 (G_16_0, {g[16],G_15_0}, p[16]); - grey g_18_0 (G_18_0, {g[18],G_17_0}, p[18]); - grey g_20_0 (G_20_0, {g[20],G_19_0}, p[20]); - grey g_22_0 (G_22_0, {g[22],G_21_0}, p[22]); - grey g_24_0 (G_24_0, {g[24],G_23_0}, p[24]); - grey g_26_0 (G_26_0, {g[26],G_25_0}, p[26]); - grey g_28_0 (G_28_0, {g[28],G_27_0}, p[28]); - grey g_30_0 (G_30_0, {g[30],G_29_0}, p[30]); - grey g_32_0 (G_32_0, {g[32],G_31_0}, p[32]); - grey g_34_0 (G_34_0, {g[34],G_33_0}, p[34]); - grey g_36_0 (G_36_0, {g[36],G_35_0}, p[36]); - grey g_38_0 (G_38_0, {g[38],G_37_0}, p[38]); - grey g_40_0 (G_40_0, {g[40],G_39_0}, p[40]); - grey g_42_0 (G_42_0, {g[42],G_41_0}, p[42]); - grey g_44_0 (G_44_0, {g[44],G_43_0}, p[44]); - grey g_46_0 (G_46_0, {g[46],G_45_0}, p[46]); - grey g_48_0 (G_48_0, {g[48],G_47_0}, p[48]); - grey g_50_0 (G_50_0, {g[50],G_49_0}, p[50]); - grey g_52_0 (G_52_0, {g[52],G_51_0}, p[52]); - grey g_54_0 (G_54_0, {g[54],G_53_0}, p[54]); - grey g_56_0 (G_56_0, {g[56],G_55_0}, p[56]); - grey g_58_0 (G_58_0, {g[58],G_57_0}, p[58]); - grey g_60_0 (G_60_0, {g[60],G_59_0}, p[60]); - grey g_62_0 (G_62_0, {g[62],G_61_0}, p[62]); - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - assign c[15]=G_14_0; - assign c[16]=G_15_0; - assign c[17]=G_16_0; - - assign c[18]=G_17_0; - assign c[19]=G_18_0; - assign c[20]=G_19_0; - assign c[21]=G_20_0; - assign c[22]=G_21_0; - assign c[23]=G_22_0; - assign c[24]=G_23_0; - assign c[25]=G_24_0; - - assign c[26]=G_25_0; - assign c[27]=G_26_0; - assign c[28]=G_27_0; - assign c[29]=G_28_0; - assign c[30]=G_29_0; - assign c[31]=G_30_0; - assign c[32]=G_31_0; - assign c[33]=G_32_0; - - assign c[34]=G_33_0; - assign c[35]=G_34_0; - assign c[36]=G_35_0; - assign c[37]=G_36_0; - assign c[38]=G_37_0; - assign c[39]=G_38_0; - assign c[40]=G_39_0; - assign c[41]=G_40_0; - - assign c[42]=G_41_0; - assign c[43]=G_42_0; - assign c[44]=G_43_0; - assign c[45]=G_44_0; - assign c[46]=G_45_0; - assign c[47]=G_46_0; - assign c[48]=G_47_0; - assign c[49]=G_48_0; - - assign c[50]=G_49_0; - assign c[51]=G_50_0; - assign c[52]=G_51_0; - assign c[53]=G_52_0; - assign c[54]=G_53_0; - assign c[55]=G_54_0; - assign c[56]=G_55_0; - assign c[57]=G_56_0; - - assign c[58]=G_57_0; - assign c[59]=G_58_0; - assign c[60]=G_59_0; - assign c[61]=G_60_0; - assign c[62]=G_61_0; - assign c[63]=G_62_0; - assign c[64]=G_63_0; - -endmodule // ladner_fischer - diff --git a/wally-pipelined/src/fpu/dev/ling_bk13.v b/wally-pipelined/src/fpu/dev/ling_bk13.v deleted file mode 100755 index 55456970a..000000000 --- a/wally-pipelined/src/fpu/dev/ling_bk13.v +++ /dev/null @@ -1,132 +0,0 @@ -// Brent-Kung Prefix Adder - -module exp_add (cout, sum, a, b, cin); - input [12:0] a, b; - input cin; - output [12:0] sum; - output cout; - - wire [13:0] p,g; - wire [13:1] h,c; - -// pre-computation - assign p={a|b,1'b1}; - assign g={a&b, cin}; - -// prefix tree - brent_kung prefix_tree(h, c, p[12:0], g[12:0]); - -// post-computation - assign h[13]=g[13]|c[13]; - assign sum=p[13:1]^h|g[13:1]&c; - assign cout=p[13]&h[13]; - -endmodule - -module brent_kung (h, c, p, g); - - input [12:0] p; - input [13:0] g; - output [13:1] h; - output [13:1] c; - - - // parallel-prefix, Brent-Kung - - // Stage 1: Generates H/I pairs that span 1 bits - rgry g_1_0 (H_1_0, {g[1],g[0]}); - rblk b_3_2 (H_3_2, I_3_2, {g[3],g[2]}, {p[2],p[1]}); - rblk b_5_4 (H_5_4, I_5_4, {g[5],g[4]}, {p[4],p[3]}); - rblk b_7_6 (H_7_6, I_7_6, {g[7],g[6]}, {p[6],p[5]}); - rblk b_9_8 (H_9_8, I_9_8, {g[9],g[8]}, {p[8],p[7]}); - rblk b_11_10 (H_11_10, I_11_10, {g[11],g[10]}, {p[10],p[9]}); - rblk b_13_12 (H_13_12, I_13_12, {g[13],g[12]}, {p[12],p[11]}); - - // Stage 2: Generates H/I pairs that span 2 bits - grey g_3_0 (H_3_0, {H_3_2,H_1_0}, I_3_2); - black b_7_4 (H_7_4, I_7_4, {H_7_6,H_5_4}, {I_7_6,I_5_4}); - black b_11_8 (H_11_8, I_11_8, {H_11_10,H_9_8}, {I_11_10,I_9_8}); - - // Stage 3: Generates H/I pairs that span 4 bits - grey g_7_0 (H_7_0, {H_7_4,H_3_0}, I_7_4); - - // Stage 4: Generates H/I pairs that span 8 bits - - // Stage 5: Generates H/I pairs that span 4 bits - grey g_11_0 (H_11_0, {H_11_8,H_7_0}, I_11_8); - - // Stage 6: Generates H/I pairs that span 2 bits - grey g_5_0 (H_5_0, {H_5_4,H_3_0}, I_5_4); - grey g_9_0 (H_9_0, {H_9_8,H_7_0}, I_9_8); - - // Last grey cell stage - grey g_2_0 (H_2_0, {g[2],H_1_0}, p[1]); - grey g_4_0 (H_4_0, {g[4],H_3_0}, p[3]); - grey g_6_0 (H_6_0, {g[6],H_5_0}, p[5]); - grey g_8_0 (H_8_0, {g[8],H_7_0}, p[7]); - grey g_10_0 (H_10_0, {g[10],H_9_0}, p[9]); - grey g_12_0 (H_12_0, {g[12],H_11_0}, p[11]); - - // Final Stage: Apply c_k+1=p_k&H_k_0 - assign c[1]=g[0]; - - assign h[1]=H_1_0; assign c[2]=p[1]&H_1_0; - assign h[2]=H_2_0; assign c[3]=p[2]&H_2_0; - assign h[3]=H_3_0; assign c[4]=p[3]&H_3_0; - assign h[4]=H_4_0; assign c[5]=p[4]&H_4_0; - assign h[5]=H_5_0; assign c[6]=p[5]&H_5_0; - assign h[6]=H_6_0; assign c[7]=p[6]&H_6_0; - assign h[7]=H_7_0; assign c[8]=p[7]&H_7_0; - assign h[8]=H_8_0; assign c[9]=p[8]&H_8_0; - - assign h[9]=H_9_0; assign c[10]=p[9]&H_9_0; - assign h[10]=H_10_0; assign c[11]=p[10]&H_10_0; - assign h[11]=H_11_0; assign c[12]=p[11]&H_11_0; - assign h[12]=H_12_0; assign c[13]=p[12]&H_12_0; - -endmodule - - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule - - -// reduced Black cell -module rblk(hout, iout, gin, pin); - - input [1:0] gin, pin; - output hout, iout; - - assign iout=pin[1]&pin[0]; - assign hout=gin[1]|gin[0]; - -endmodule - -// reduced Grey cell -module rgry(hout, gin); - - input[1:0] gin; - output hout; - - assign hout=gin[1]|gin[0]; - -endmodule diff --git a/wally-pipelined/src/fpu/dev/lzd_denorm.v b/wally-pipelined/src/fpu/dev/lzd_denorm.v deleted file mode 100755 index 6755b567a..000000000 --- a/wally-pipelined/src/fpu/dev/lzd_denorm.v +++ /dev/null @@ -1,170 +0,0 @@ -module lz2 (P, V, B0, B1); - - input B0; - input B1; - - output P; - output V; - - assign V = B0 | B1; - assign P = B0 & ~B1; - -endmodule // lz2 - -// Note: This module is not made out of two lz2's - why not? (MJS) - -module lz4 (ZP, ZV, B0, B1, V0, V1); - - input B0; - input B1; - input V0; - input V1; - - output [1:0] ZP; - output ZV; - - assign ZP[0] = V0 ? B0 : B1; - assign ZP[1] = ~V0; - assign ZV = V0 | V1; - -endmodule // lz4 - -// Note: This module is not made out of two lz4's - why not? (MJS) - -module lz8 (ZP, ZV, B); - - input [7:0] B; - - wire s1p0; - wire s1v0; - wire s1p1; - wire s1v1; - wire s2p0; - wire s2v0; - wire s2p1; - wire s2v1; - wire [1:0] ZPa; - wire [1:0] ZPb; - wire ZVa; - wire ZVb; - - output [2:0] ZP; - output ZV; - - lz2 l1(s1p0, s1v0, B[2], B[3]); - lz2 l2(s1p1, s1v1, B[0], B[1]); - lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1); - - lz2 l4(s2p0, s2v0, B[6], B[7]); - lz2 l5(s2p1, s2v1, B[4], B[5]); - lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1); - - assign ZP[1:0] = ZVb ? ZPb : ZPa; - assign ZP[2] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz8 - -module lz16 (ZP, ZV, B); - - input [15:0] B; - - wire [2:0] ZPa; - wire [2:0] ZPb; - wire ZVa; - wire ZVb; - - output [3:0] ZP; - output ZV; - - lz8 l1(ZPa, ZVa, B[7:0]); - lz8 l2(ZPb, ZVb, B[15:8]); - - assign ZP[2:0] = ZVb ? ZPb : ZPa; - assign ZP[3] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz16 - -module lz32 (ZP, ZV, B); - - input [31:0] B; - - wire [3:0] ZPa; - wire [3:0] ZPb; - wire ZVa; - wire ZVb; - - output [4:0] ZP; - output ZV; - - lz16 l1(ZPa, ZVa, B[15:0]); - lz16 l2(ZPb, ZVb, B[31:16]); - - assign ZP[3:0] = ZVb ? ZPb : ZPa; - assign ZP[4] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz32 - -// This module returns the number of leading zeros ZP in the 64-bit -// number B. If there are no ones in B, then ZP and ZV are both 0. - -module lz64 (ZP, ZV, B); - - input [63:0] B; - - wire [4:0] ZPa; - wire [4:0] ZPb; - wire ZVa; - wire ZVb; - - output [5:0] ZP; - output ZV; - - lz32 l1(ZPa, ZVa, B[31:0]); - lz32 l2(ZPb, ZVb, B[63:32]); - - assign ZV = ZVa | ZVb; - assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}}; - assign ZP[5] = ~ZVb & ZV; - -endmodule // lz64 - -// This module returns the number of leading zeros ZP in the 52-bit -// number B. If there are no ones in B, then ZP and ZV are both 0. - -module lz52 (ZP, ZV, B); - - input [51:0] B; - - wire [4:0] ZP_32; - wire [3:0] ZP_16; - wire [1:0] ZP_4; - wire ZV_32; - wire ZV_16; - wire ZV_4; - - wire ZP_2_1; - wire ZP_2_2; - wire ZV_2_1; - wire ZV_2_2; - - output [5:0] ZP; - output ZV; - - lz32 l1 (ZP_32, ZV_32, B[51:20]); - lz16 l2 (ZP_16, ZV_16, B[19:4]); - - lz2 l3_1 (ZP_2_1, ZV_2_1, B[3], B[2]); - lz2 l3_2 (ZP_2_2, ZV_2_2, B[1], B[0]); - lz4 l3_final (ZP_4, ZV_4, ZP_2_1, ZP_2_2, ZV_2_1, ZV_2_2); - - assign ZV = ZV_32 | ZV_16 | ZV_4; - assign ZP[5] = ~ZV_32; - assign ZP[4] = ZV_32 ? ZP_32[4] : ~ZV_16; - assign ZP[3:2] = ZV_32 ? ZP_32[3:2] : (ZV_16 ? ZP_16[3:2] : 2'b0); - assign ZP[1:0] = ZV_32 ? ZP_32[1:0] : (ZV_16 ? ZP_16[1:0] : ZP_4); - -endmodule // lz52 - diff --git a/wally-pipelined/src/fpu/dev/mult_R4_64_64_cs.v b/wally-pipelined/src/fpu/dev/mult_R4_64_64_cs.v deleted file mode 100755 index 7ad230df8..000000000 --- a/wally-pipelined/src/fpu/dev/mult_R4_64_64_cs.v +++ /dev/null @@ -1,11995 +0,0 @@ -// This module is a 64 by 64 TDM multiplier. -// It is unsigned and uses Radix-4 Booth encoding. -// This file was automatically generated by tdm.pl. - -module mult64 (x, y, P); - - input [63:0] x; - input [63:0] y; - - output [127:0] P; - - wire [127:0] Sum; - wire [127:0] Carry; - wire [128:0] Pt; - - multiplier p1 (y, x, Sum, Carry); - //assign Pt = Sum + Carry; - //assign P = Pt[127:0]; - ldf128 cpa (cout, P, Sum, Carry, 1'b0); - -endmodule // mult64 - -module multiplier( y, x, Sum, Carry ); - - input [63:0] x; - input [63:0] y; - - output [127:0] Sum; - output [127:0] Carry; - - supply0 gnd; - - //Buffers and their nets. - - wire [63:0] xx; - wire [63:0] yy; - - buffer buffer_0_0( xx[0], x[0]); - buffer buffer_0_32( yy[0], y[0]); - buffer buffer_80_0( xx[1], x[1]); - buffer buffer_80_32( yy[1], y[1]); - buffer buffer_160_0( xx[2], x[2]); - buffer buffer_160_32( yy[2], y[2]); - buffer buffer_240_0( xx[3], x[3]); - buffer buffer_240_32( yy[3], y[3]); - buffer buffer_320_0( xx[4], x[4]); - buffer buffer_320_32( yy[4], y[4]); - buffer buffer_400_0( xx[5], x[5]); - buffer buffer_400_32( yy[5], y[5]); - buffer buffer_480_0( xx[6], x[6]); - buffer buffer_480_32( yy[6], y[6]); - buffer buffer_560_0( xx[7], x[7]); - buffer buffer_560_32( yy[7], y[7]); - buffer buffer_640_0( xx[8], x[8]); - buffer buffer_640_32( yy[8], y[8]); - buffer buffer_720_0( xx[9], x[9]); - buffer buffer_720_32( yy[9], y[9]); - buffer buffer_800_0( xx[10], x[10]); - buffer buffer_800_32( yy[10], y[10]); - buffer buffer_880_0( xx[11], x[11]); - buffer buffer_880_32( yy[11], y[11]); - buffer buffer_960_0( xx[12], x[12]); - buffer buffer_960_32( yy[12], y[12]); - buffer buffer_1040_0( xx[13], x[13]); - buffer buffer_1040_32( yy[13], y[13]); - buffer buffer_1120_0( xx[14], x[14]); - buffer buffer_1120_32( yy[14], y[14]); - buffer buffer_1200_0( xx[15], x[15]); - buffer buffer_1200_32( yy[15], y[15]); - buffer buffer_1280_0( xx[16], x[16]); - buffer buffer_1280_32( yy[16], y[16]); - buffer buffer_1360_0( xx[17], x[17]); - buffer buffer_1360_32( yy[17], y[17]); - buffer buffer_1440_0( xx[18], x[18]); - buffer buffer_1440_32( yy[18], y[18]); - buffer buffer_1520_0( xx[19], x[19]); - buffer buffer_1520_32( yy[19], y[19]); - buffer buffer_1600_0( xx[20], x[20]); - buffer buffer_1600_32( yy[20], y[20]); - buffer buffer_1680_0( xx[21], x[21]); - buffer buffer_1680_32( yy[21], y[21]); - buffer buffer_1760_0( xx[22], x[22]); - buffer buffer_1760_32( yy[22], y[22]); - buffer buffer_1840_0( xx[23], x[23]); - buffer buffer_1840_32( yy[23], y[23]); - buffer buffer_1920_0( xx[24], x[24]); - buffer buffer_1920_32( yy[24], y[24]); - buffer buffer_2000_0( xx[25], x[25]); - buffer buffer_2000_32( yy[25], y[25]); - buffer buffer_2080_0( xx[26], x[26]); - buffer buffer_2080_32( yy[26], y[26]); - buffer buffer_2160_0( xx[27], x[27]); - buffer buffer_2160_32( yy[27], y[27]); - buffer buffer_2240_0( xx[28], x[28]); - buffer buffer_2240_32( yy[28], y[28]); - buffer buffer_2320_0( xx[29], x[29]); - buffer buffer_2320_32( yy[29], y[29]); - buffer buffer_2400_0( xx[30], x[30]); - buffer buffer_2400_32( yy[30], y[30]); - buffer buffer_2480_0( xx[31], x[31]); - buffer buffer_2480_32( yy[31], y[31]); - buffer buffer_2560_0( xx[32], x[32]); - buffer buffer_2560_32( yy[32], y[32]); - buffer buffer_2640_0( xx[33], x[33]); - buffer buffer_2640_32( yy[33], y[33]); - buffer buffer_2720_0( xx[34], x[34]); - buffer buffer_2720_32( yy[34], y[34]); - buffer buffer_2800_0( xx[35], x[35]); - buffer buffer_2800_32( yy[35], y[35]); - buffer buffer_2880_0( xx[36], x[36]); - buffer buffer_2880_32( yy[36], y[36]); - buffer buffer_2960_0( xx[37], x[37]); - buffer buffer_2960_32( yy[37], y[37]); - buffer buffer_3040_0( xx[38], x[38]); - buffer buffer_3040_32( yy[38], y[38]); - buffer buffer_3120_0( xx[39], x[39]); - buffer buffer_3120_32( yy[39], y[39]); - buffer buffer_3200_0( xx[40], x[40]); - buffer buffer_3200_32( yy[40], y[40]); - buffer buffer_3280_0( xx[41], x[41]); - buffer buffer_3280_32( yy[41], y[41]); - buffer buffer_3360_0( xx[42], x[42]); - buffer buffer_3360_32( yy[42], y[42]); - buffer buffer_3440_0( xx[43], x[43]); - buffer buffer_3440_32( yy[43], y[43]); - buffer buffer_3520_0( xx[44], x[44]); - buffer buffer_3520_32( yy[44], y[44]); - buffer buffer_3600_0( xx[45], x[45]); - buffer buffer_3600_32( yy[45], y[45]); - buffer buffer_3680_0( xx[46], x[46]); - buffer buffer_3680_32( yy[46], y[46]); - buffer buffer_3760_0( xx[47], x[47]); - buffer buffer_3760_32( yy[47], y[47]); - buffer buffer_3840_0( xx[48], x[48]); - buffer buffer_3840_32( yy[48], y[48]); - buffer buffer_3920_0( xx[49], x[49]); - buffer buffer_3920_32( yy[49], y[49]); - buffer buffer_4000_0( xx[50], x[50]); - buffer buffer_4000_32( yy[50], y[50]); - buffer buffer_4080_0( xx[51], x[51]); - buffer buffer_4080_32( yy[51], y[51]); - buffer buffer_4160_0( xx[52], x[52]); - buffer buffer_4160_32( yy[52], y[52]); - buffer buffer_4240_0( xx[53], x[53]); - buffer buffer_4240_32( yy[53], y[53]); - buffer buffer_4320_0( xx[54], x[54]); - buffer buffer_4320_32( yy[54], y[54]); - buffer buffer_4400_0( xx[55], x[55]); - buffer buffer_4400_32( yy[55], y[55]); - buffer buffer_4480_0( xx[56], x[56]); - buffer buffer_4480_32( yy[56], y[56]); - buffer buffer_4560_0( xx[57], x[57]); - buffer buffer_4560_32( yy[57], y[57]); - buffer buffer_4640_0( xx[58], x[58]); - buffer buffer_4640_32( yy[58], y[58]); - buffer buffer_4720_0( xx[59], x[59]); - buffer buffer_4720_32( yy[59], y[59]); - buffer buffer_4800_0( xx[60], x[60]); - buffer buffer_4800_32( yy[60], y[60]); - buffer buffer_4880_0( xx[61], x[61]); - buffer buffer_4880_32( yy[61], y[61]); - buffer buffer_4960_0( xx[62], x[62]); - buffer buffer_4960_32( yy[62], y[62]); - buffer buffer_5040_0( xx[63], x[63]); - buffer buffer_5040_32( yy[63], y[63]); - - - //Booth encoders and related wiring - - wire [32:0] single; - wire [32:0] double; - wire [32:0] neg; - wire [31:0] negbar; - - r4be r4be_10240_0(gnd, xx[0], xx[1], single[0], double[0], neg[0]); - inverter inverter_10240_168(negbar[0], neg[0]); - r4be r4be_10240_184(xx[1], xx[2], xx[3], single[1], double[1], neg[1]); - inverter inverter_10240_352(negbar[1], neg[1]); - r4be r4be_10240_368(xx[3], xx[4], xx[5], single[2], double[2], neg[2]); - inverter inverter_10240_536(negbar[2], neg[2]); - r4be r4be_10240_552(xx[5], xx[6], xx[7], single[3], double[3], neg[3]); - inverter inverter_10240_720(negbar[3], neg[3]); - r4be r4be_10240_736(xx[7], xx[8], xx[9], single[4], double[4], neg[4]); - inverter inverter_10240_904(negbar[4], neg[4]); - r4be r4be_10240_920(xx[9], xx[10], xx[11], single[5], double[5], neg[5]); - inverter inverter_10240_1088(negbar[5], neg[5]); - r4be r4be_10240_1104(xx[11], xx[12], xx[13], single[6], double[6], neg[6]); - inverter inverter_10240_1272(negbar[6], neg[6]); - r4be r4be_10240_1288(xx[13], xx[14], xx[15], single[7], double[7], neg[7]); - inverter inverter_10240_1456(negbar[7], neg[7]); - r4be r4be_10240_1472(xx[15], xx[16], xx[17], single[8], double[8], neg[8]); - inverter inverter_10240_1640(negbar[8], neg[8]); - r4be r4be_10240_1656(xx[17], xx[18], xx[19], single[9], double[9], neg[9]); - inverter inverter_10240_1824(negbar[9], neg[9]); - r4be r4be_10240_1840(xx[19], xx[20], xx[21], single[10], double[10], neg[10]); - inverter inverter_10240_2008(negbar[10], neg[10]); - r4be r4be_10240_2024(xx[21], xx[22], xx[23], single[11], double[11], neg[11]); - inverter inverter_10240_2192(negbar[11], neg[11]); - r4be r4be_10240_2208(xx[23], xx[24], xx[25], single[12], double[12], neg[12]); - inverter inverter_10240_2376(negbar[12], neg[12]); - r4be r4be_10240_2392(xx[25], xx[26], xx[27], single[13], double[13], neg[13]); - inverter inverter_10240_2560(negbar[13], neg[13]); - r4be r4be_10240_2576(xx[27], xx[28], xx[29], single[14], double[14], neg[14]); - inverter inverter_10240_2744(negbar[14], neg[14]); - r4be r4be_10240_2760(xx[29], xx[30], xx[31], single[15], double[15], neg[15]); - inverter inverter_10240_2928(negbar[15], neg[15]); - r4be r4be_10240_2944(xx[31], xx[32], xx[33], single[16], double[16], neg[16]); - inverter inverter_10240_3112(negbar[16], neg[16]); - r4be r4be_10240_3128(xx[33], xx[34], xx[35], single[17], double[17], neg[17]); - inverter inverter_10240_3296(negbar[17], neg[17]); - r4be r4be_10240_3312(xx[35], xx[36], xx[37], single[18], double[18], neg[18]); - inverter inverter_10240_3480(negbar[18], neg[18]); - r4be r4be_10240_3496(xx[37], xx[38], xx[39], single[19], double[19], neg[19]); - inverter inverter_10240_3664(negbar[19], neg[19]); - r4be r4be_10240_3680(xx[39], xx[40], xx[41], single[20], double[20], neg[20]); - inverter inverter_10240_3848(negbar[20], neg[20]); - r4be r4be_10240_3864(xx[41], xx[42], xx[43], single[21], double[21], neg[21]); - inverter inverter_10240_4032(negbar[21], neg[21]); - r4be r4be_10240_4048(xx[43], xx[44], xx[45], single[22], double[22], neg[22]); - inverter inverter_10240_4216(negbar[22], neg[22]); - r4be r4be_10240_4232(xx[45], xx[46], xx[47], single[23], double[23], neg[23]); - inverter inverter_10240_4400(negbar[23], neg[23]); - r4be r4be_10240_4416(xx[47], xx[48], xx[49], single[24], double[24], neg[24]); - inverter inverter_10240_4584(negbar[24], neg[24]); - r4be r4be_10240_4600(xx[49], xx[50], xx[51], single[25], double[25], neg[25]); - inverter inverter_10240_4768(negbar[25], neg[25]); - r4be r4be_10240_4784(xx[51], xx[52], xx[53], single[26], double[26], neg[26]); - inverter inverter_10240_4952(negbar[26], neg[26]); - r4be r4be_10240_4968(xx[53], xx[54], xx[55], single[27], double[27], neg[27]); - inverter inverter_10240_5136(negbar[27], neg[27]); - r4be r4be_10240_5152(xx[55], xx[56], xx[57], single[28], double[28], neg[28]); - inverter inverter_10240_5320(negbar[28], neg[28]); - r4be r4be_10240_5336(xx[57], xx[58], xx[59], single[29], double[29], neg[29]); - inverter inverter_10240_5504(negbar[29], neg[29]); - r4be r4be_10240_5520(xx[59], xx[60], xx[61], single[30], double[30], neg[30]); - inverter inverter_10240_5688(negbar[30], neg[30]); - r4be r4be_10240_5704(xx[61], xx[62], xx[63], single[31], double[31], neg[31]); - inverter inverter_10240_5872(negbar[31], neg[31]); - r4be r4be_10240_5888(xx[63], gnd, gnd, single[32], double[32], neg[32]); - - // Below are the nets for the partial products (booth) - wire pp_0_0; - wire pp_0_2; - wire pp_1_2; - wire pp_0_3; - wire pp_1_3; - wire pp_0_4; - wire pp_1_4; - wire pp_2_4; - wire pp_0_5; - wire pp_1_5; - wire pp_2_5; - wire pp_0_6; - wire pp_1_6; - wire pp_2_6; - wire pp_3_6; - wire pp_0_7; - wire pp_1_7; - wire pp_2_7; - wire pp_3_7; - wire pp_0_8; - wire pp_1_8; - wire pp_2_8; - wire pp_3_8; - wire pp_4_8; - wire pp_0_9; - wire pp_1_9; - wire pp_2_9; - wire pp_3_9; - wire pp_4_9; - wire pp_0_10; - wire pp_1_10; - wire pp_2_10; - wire pp_3_10; - wire pp_4_10; - wire pp_5_10; - wire pp_0_11; - wire pp_1_11; - wire pp_2_11; - wire pp_3_11; - wire pp_4_11; - wire pp_5_11; - wire pp_0_12; - wire pp_1_12; - wire pp_2_12; - wire pp_3_12; - wire pp_4_12; - wire pp_5_12; - wire pp_6_12; - wire pp_0_13; - wire pp_1_13; - wire pp_2_13; - wire pp_3_13; - wire pp_4_13; - wire pp_5_13; - wire pp_6_13; - wire pp_0_14; - wire pp_1_14; - wire pp_2_14; - wire pp_3_14; - wire pp_4_14; - wire pp_5_14; - wire pp_6_14; - wire pp_7_14; - wire pp_0_15; - wire pp_1_15; - wire pp_2_15; - wire pp_3_15; - wire pp_4_15; - wire pp_5_15; - wire pp_6_15; - wire pp_7_15; - wire pp_0_16; - wire pp_1_16; - wire pp_2_16; - wire pp_3_16; - wire pp_4_16; - wire pp_5_16; - wire pp_6_16; - wire pp_7_16; - wire pp_8_16; - wire pp_0_17; - wire pp_1_17; - wire pp_2_17; - wire pp_3_17; - wire pp_4_17; - wire pp_5_17; - wire pp_6_17; - wire pp_7_17; - wire pp_8_17; - wire pp_0_18; - wire pp_1_18; - wire pp_2_18; - wire pp_3_18; - wire pp_4_18; - wire pp_5_18; - wire pp_6_18; - wire pp_7_18; - wire pp_8_18; - wire pp_9_18; - wire pp_0_19; - wire pp_1_19; - wire pp_2_19; - wire pp_3_19; - wire pp_4_19; - wire pp_5_19; - wire pp_6_19; - wire pp_7_19; - wire pp_8_19; - wire pp_9_19; - wire pp_0_20; - wire pp_1_20; - wire pp_2_20; - wire pp_3_20; - wire pp_4_20; - wire pp_5_20; - wire pp_6_20; - wire pp_7_20; - wire pp_8_20; - wire pp_9_20; - wire pp_10_20; - wire pp_0_21; - wire pp_1_21; - wire pp_2_21; - wire pp_3_21; - wire pp_4_21; - wire pp_5_21; - wire pp_6_21; - wire pp_7_21; - wire pp_8_21; - wire pp_9_21; - wire pp_10_21; - wire pp_0_22; - wire pp_1_22; - wire pp_2_22; - wire pp_3_22; - wire pp_4_22; - wire pp_5_22; - wire pp_6_22; - wire pp_7_22; - wire pp_8_22; - wire pp_9_22; - wire pp_10_22; - wire pp_11_22; - wire pp_0_23; - wire pp_1_23; - wire pp_2_23; - wire pp_3_23; - wire pp_4_23; - wire pp_5_23; - wire pp_6_23; - wire pp_7_23; - wire pp_8_23; - wire pp_9_23; - wire pp_10_23; - wire pp_11_23; - wire pp_0_24; - wire pp_1_24; - wire pp_2_24; - wire pp_3_24; - wire pp_4_24; - wire pp_5_24; - wire pp_6_24; - wire pp_7_24; - wire pp_8_24; - wire pp_9_24; - wire pp_10_24; - wire pp_11_24; - wire pp_12_24; - wire pp_0_25; - wire pp_1_25; - wire pp_2_25; - wire pp_3_25; - wire pp_4_25; - wire pp_5_25; - wire pp_6_25; - wire pp_7_25; - wire pp_8_25; - wire pp_9_25; - wire pp_10_25; - wire pp_11_25; - wire pp_12_25; - wire pp_0_26; - wire pp_1_26; - wire pp_2_26; - wire pp_3_26; - wire pp_4_26; - wire pp_5_26; - wire pp_6_26; - wire pp_7_26; - wire pp_8_26; - wire pp_9_26; - wire pp_10_26; - wire pp_11_26; - wire pp_12_26; - wire pp_13_26; - wire pp_0_27; - wire pp_1_27; - wire pp_2_27; - wire pp_3_27; - wire pp_4_27; - wire pp_5_27; - wire pp_6_27; - wire pp_7_27; - wire pp_8_27; - wire pp_9_27; - wire pp_10_27; - wire pp_11_27; - wire pp_12_27; - wire pp_13_27; - wire pp_0_28; - wire pp_1_28; - wire pp_2_28; - wire pp_3_28; - wire pp_4_28; - wire pp_5_28; - wire pp_6_28; - wire pp_7_28; - wire pp_8_28; - wire pp_9_28; - wire pp_10_28; - wire pp_11_28; - wire pp_12_28; - wire pp_13_28; - wire pp_14_28; - wire pp_0_29; - wire pp_1_29; - wire pp_2_29; - wire pp_3_29; - wire pp_4_29; - wire pp_5_29; - wire pp_6_29; - wire pp_7_29; - wire pp_8_29; - wire pp_9_29; - wire pp_10_29; - wire pp_11_29; - wire pp_12_29; - wire pp_13_29; - wire pp_14_29; - wire pp_0_30; - wire pp_1_30; - wire pp_2_30; - wire pp_3_30; - wire pp_4_30; - wire pp_5_30; - wire pp_6_30; - wire pp_7_30; - wire pp_8_30; - wire pp_9_30; - wire pp_10_30; - wire pp_11_30; - wire pp_12_30; - wire pp_13_30; - wire pp_14_30; - wire pp_15_30; - wire pp_0_31; - wire pp_1_31; - wire pp_2_31; - wire pp_3_31; - wire pp_4_31; - wire pp_5_31; - wire pp_6_31; - wire pp_7_31; - wire pp_8_31; - wire pp_9_31; - wire pp_10_31; - wire pp_11_31; - wire pp_12_31; - wire pp_13_31; - wire pp_14_31; - wire pp_15_31; - wire pp_0_32; - wire pp_1_32; - wire pp_2_32; - wire pp_3_32; - wire pp_4_32; - wire pp_5_32; - wire pp_6_32; - wire pp_7_32; - wire pp_8_32; - wire pp_9_32; - wire pp_10_32; - wire pp_11_32; - wire pp_12_32; - wire pp_13_32; - wire pp_14_32; - wire pp_15_32; - wire pp_16_32; - wire pp_0_33; - wire pp_1_33; - wire pp_2_33; - wire pp_3_33; - wire pp_4_33; - wire pp_5_33; - wire pp_6_33; - wire pp_7_33; - wire pp_8_33; - wire pp_9_33; - wire pp_10_33; - wire pp_11_33; - wire pp_12_33; - wire pp_13_33; - wire pp_14_33; - wire pp_15_33; - wire pp_16_33; - wire pp_0_34; - wire pp_1_34; - wire pp_2_34; - wire pp_3_34; - wire pp_4_34; - wire pp_5_34; - wire pp_6_34; - wire pp_7_34; - wire pp_8_34; - wire pp_9_34; - wire pp_10_34; - wire pp_11_34; - wire pp_12_34; - wire pp_13_34; - wire pp_14_34; - wire pp_15_34; - wire pp_16_34; - wire pp_17_34; - wire pp_0_35; - wire pp_1_35; - wire pp_2_35; - wire pp_3_35; - wire pp_4_35; - wire pp_5_35; - wire pp_6_35; - wire pp_7_35; - wire pp_8_35; - wire pp_9_35; - wire pp_10_35; - wire pp_11_35; - wire pp_12_35; - wire pp_13_35; - wire pp_14_35; - wire pp_15_35; - wire pp_16_35; - wire pp_17_35; - wire pp_0_36; - wire pp_1_36; - wire pp_2_36; - wire pp_3_36; - wire pp_4_36; - wire pp_5_36; - wire pp_6_36; - wire pp_7_36; - wire pp_8_36; - wire pp_9_36; - wire pp_10_36; - wire pp_11_36; - wire pp_12_36; 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- wire pp_26_103; - wire pp_27_103; - wire pp_28_103; - wire pp_29_103; - wire pp_30_103; - wire pp_31_103; - wire pp_32_103; - wire pp_20_104; - wire pp_21_104; - wire pp_22_104; - wire pp_23_104; - wire pp_24_104; - wire pp_25_104; - wire pp_26_104; - wire pp_27_104; - wire pp_28_104; - wire pp_29_104; - wire pp_30_104; - wire pp_31_104; - wire pp_32_104; - wire pp_21_105; - wire pp_22_105; - wire pp_23_105; - wire pp_24_105; - wire pp_25_105; - wire pp_26_105; - wire pp_27_105; - wire pp_28_105; - wire pp_29_105; - wire pp_30_105; - wire pp_31_105; - wire pp_32_105; - wire pp_21_106; - wire pp_22_106; - wire pp_23_106; - wire pp_24_106; - wire pp_25_106; - wire pp_26_106; - wire pp_27_106; - wire pp_28_106; - wire pp_29_106; - wire pp_30_106; - wire pp_31_106; - wire pp_32_106; - wire pp_22_107; - wire pp_23_107; - wire pp_24_107; - wire pp_25_107; - wire pp_26_107; - wire pp_27_107; - wire pp_28_107; - wire pp_29_107; - wire pp_30_107; - wire pp_31_107; - wire pp_32_107; - wire pp_22_108; - wire pp_23_108; - wire pp_24_108; - wire pp_25_108; - wire pp_26_108; - wire pp_27_108; - wire pp_28_108; - wire pp_29_108; - wire pp_30_108; - wire pp_31_108; - wire pp_32_108; - wire pp_23_109; - wire pp_24_109; - wire pp_25_109; - wire pp_26_109; - wire pp_27_109; - wire pp_28_109; - wire pp_29_109; - wire pp_30_109; - wire pp_31_109; - wire pp_32_109; - wire pp_23_110; - wire pp_24_110; - wire pp_25_110; - wire pp_26_110; - wire pp_27_110; - wire pp_28_110; - wire pp_29_110; - wire pp_30_110; - wire pp_31_110; - wire pp_32_110; - wire pp_24_111; - wire pp_25_111; - wire pp_26_111; - wire pp_27_111; - wire pp_28_111; - wire pp_29_111; - wire pp_30_111; - wire pp_31_111; - wire pp_32_111; - wire pp_24_112; - wire pp_25_112; - wire pp_26_112; - wire pp_27_112; - wire pp_28_112; - wire pp_29_112; - wire pp_30_112; - wire pp_31_112; - wire pp_32_112; - wire pp_25_113; - wire pp_26_113; - wire pp_27_113; - wire pp_28_113; - wire pp_29_113; - wire pp_30_113; - wire pp_31_113; - wire pp_32_113; - wire pp_25_114; - wire pp_26_114; - wire pp_27_114; - wire pp_28_114; - wire pp_29_114; - wire pp_30_114; - wire pp_31_114; - wire pp_32_114; - wire pp_26_115; - wire pp_27_115; - wire pp_28_115; - wire pp_29_115; - wire pp_30_115; - wire pp_31_115; - wire pp_32_115; - wire pp_26_116; - wire pp_27_116; - wire pp_28_116; - wire pp_29_116; - wire pp_30_116; - wire pp_31_116; - wire pp_32_116; - wire pp_27_117; - wire pp_28_117; - wire pp_29_117; - wire pp_30_117; - wire pp_31_117; - wire pp_32_117; - wire pp_27_118; - wire pp_28_118; - wire pp_29_118; - wire pp_30_118; - wire pp_31_118; - wire pp_32_118; - wire pp_28_119; - wire pp_29_119; - wire pp_30_119; - wire pp_31_119; - wire pp_32_119; - wire pp_28_120; - wire pp_29_120; - wire pp_30_120; - wire pp_31_120; - wire pp_32_120; - wire pp_29_121; - wire pp_30_121; - wire pp_31_121; - wire pp_32_121; - wire pp_29_122; - wire pp_30_122; - wire pp_31_122; - wire pp_32_122; - wire pp_30_123; - wire pp_31_123; - wire pp_32_123; - wire pp_30_124; - wire pp_31_124; - wire pp_32_124; - wire pp_31_125; - wire pp_32_125; - wire pp_31_126; - wire pp_32_126; - wire pp_32_127; - - // Below are the intermediate nets generated by the tree adders - wire int_0_2; - wire int_1_2; - wire int_0_3; - wire int_1_3; - wire int_0_4; - wire int_1_4; - wire int_2_4; - wire int_3_4; - wire int_0_5; - wire int_1_5; - wire int_2_5; - wire int_3_5; - wire int_0_6; - wire int_1_6; - wire int_2_6; - wire int_3_6; - wire int_4_6; - wire int_5_6; - wire int_0_7; - wire int_1_7; - wire int_2_7; - wire int_3_7; - wire int_4_7; - wire int_5_7; - wire int_0_8; - wire int_1_8; - wire int_2_8; - wire int_3_8; - wire int_4_8; - wire int_5_8; - wire int_6_8; - wire int_7_8; - wire int_0_9; - wire int_1_9; - wire int_2_9; - wire int_3_9; - wire int_4_9; - wire int_5_9; - wire int_6_9; - wire int_7_9; - wire int_0_10; - wire int_1_10; - wire int_2_10; - wire int_3_10; - wire int_4_10; - wire int_5_10; - wire int_6_10; - wire int_7_10; - wire int_8_10; - wire int_9_10; - wire int_0_11; - wire int_1_11; - wire int_2_11; - wire int_3_11; - wire int_4_11; - wire int_5_11; - wire int_6_11; - wire int_7_11; - wire int_8_11; - wire int_9_11; - wire int_0_12; - wire int_1_12; - wire int_2_12; - wire int_3_12; - wire int_4_12; - wire int_5_12; - wire int_6_12; - wire int_7_12; - wire int_8_12; - wire int_9_12; - wire int_10_12; - wire int_11_12; - wire int_0_13; - wire int_1_13; - wire int_2_13; - wire int_3_13; - wire int_4_13; - wire int_5_13; - wire int_6_13; - wire int_7_13; - wire int_8_13; - wire int_9_13; - wire int_10_13; - wire int_11_13; - wire int_0_14; - wire int_1_14; - wire int_2_14; - wire int_3_14; - wire int_4_14; - wire int_5_14; - wire int_6_14; - wire int_7_14; - wire int_8_14; - wire int_9_14; - wire int_10_14; - wire int_11_14; - wire int_12_14; - wire int_13_14; - wire int_0_15; - wire int_1_15; - wire int_2_15; - wire int_3_15; - wire int_4_15; - wire int_5_15; - wire int_6_15; - wire int_7_15; - wire int_8_15; - wire int_9_15; - wire int_10_15; - wire int_11_15; - wire int_12_15; - wire int_13_15; - wire int_0_16; - wire int_1_16; - wire int_2_16; - wire int_3_16; - wire int_4_16; - wire int_5_16; - wire int_6_16; - wire int_7_16; - wire int_8_16; - wire int_9_16; - wire int_10_16; - wire int_11_16; - wire int_12_16; - wire int_13_16; - wire int_14_16; - wire int_15_16; - wire int_0_17; - wire int_1_17; - wire int_2_17; - wire int_3_17; - wire int_4_17; - wire int_5_17; - wire int_6_17; - wire int_7_17; - wire int_8_17; - wire int_9_17; - wire int_10_17; - wire int_11_17; - wire int_12_17; - wire int_13_17; - wire int_14_17; - wire int_15_17; - wire int_0_18; - wire int_1_18; - wire int_2_18; - wire int_3_18; - wire int_4_18; - wire int_5_18; - wire int_6_18; - wire int_7_18; - wire int_8_18; - wire int_9_18; - wire int_10_18; - wire int_11_18; - wire int_12_18; - wire int_13_18; - wire int_14_18; - wire int_15_18; - wire int_16_18; - wire int_17_18; - wire int_0_19; - wire int_1_19; - wire int_2_19; - wire int_3_19; - wire int_4_19; - wire int_5_19; - wire int_6_19; - wire int_7_19; - wire int_8_19; - wire int_9_19; - wire int_10_19; - wire int_11_19; - wire int_12_19; - wire int_13_19; - wire int_14_19; - wire int_15_19; - wire int_16_19; - wire int_17_19; - wire int_0_20; - wire int_1_20; - wire int_2_20; - wire int_3_20; - wire int_4_20; - wire int_5_20; - wire int_6_20; - wire int_7_20; - wire int_8_20; - wire int_9_20; - wire int_10_20; - wire int_11_20; - wire int_12_20; - wire int_13_20; - wire int_14_20; - wire int_15_20; - wire int_16_20; - wire int_17_20; - wire int_18_20; - wire int_19_20; - wire int_0_21; - wire int_1_21; - wire int_2_21; - wire int_3_21; - wire int_4_21; - wire int_5_21; - wire int_6_21; - wire int_7_21; - wire int_8_21; - wire int_9_21; - wire int_10_21; - wire int_11_21; - wire int_12_21; - wire int_13_21; - wire int_14_21; - wire int_15_21; - wire int_16_21; - wire int_17_21; - wire int_18_21; - wire int_19_21; - wire int_0_22; - wire int_1_22; - wire int_2_22; - wire int_3_22; - wire int_4_22; - wire int_5_22; - wire int_6_22; - wire int_7_22; - wire int_8_22; - wire int_9_22; - wire int_10_22; - wire int_11_22; - wire int_12_22; - wire int_13_22; - wire int_14_22; - wire int_15_22; - wire int_16_22; - wire int_17_22; - wire int_18_22; - wire int_19_22; - wire int_20_22; - wire int_21_22; - wire int_0_23; - wire int_1_23; - wire int_2_23; - wire int_3_23; - wire int_4_23; - wire int_5_23; - wire int_6_23; - wire int_7_23; - wire int_8_23; - wire int_9_23; - wire int_10_23; - wire int_11_23; - wire int_12_23; - wire int_13_23; - wire int_14_23; - wire int_15_23; - wire int_16_23; - wire int_17_23; - wire int_18_23; - wire int_19_23; - wire int_20_23; - wire int_21_23; - wire int_0_24; - wire int_1_24; - wire int_2_24; - wire int_3_24; - wire int_4_24; - wire int_5_24; - wire int_6_24; - wire int_7_24; - wire int_8_24; - wire int_9_24; - wire int_10_24; - wire int_11_24; - wire int_12_24; - wire int_13_24; - wire int_14_24; - wire int_15_24; - wire int_16_24; - wire int_17_24; - wire int_18_24; - wire int_19_24; - wire int_20_24; - wire int_21_24; - wire int_22_24; - wire int_23_24; - wire int_0_25; - wire int_1_25; - wire int_2_25; - wire int_3_25; - wire int_4_25; - wire int_5_25; - wire int_6_25; - wire int_7_25; - wire int_8_25; - wire int_9_25; - wire int_10_25; - wire int_11_25; - wire int_12_25; - wire int_13_25; - wire int_14_25; - wire int_15_25; - wire int_16_25; - wire int_17_25; - wire int_18_25; - wire int_19_25; - wire int_20_25; - wire int_21_25; - wire int_22_25; - wire int_23_25; - wire int_0_26; - wire int_1_26; - wire int_2_26; - wire int_3_26; - wire int_4_26; - wire int_5_26; - wire int_6_26; - wire int_7_26; - wire int_8_26; - wire int_9_26; - wire int_10_26; - wire int_11_26; - wire int_12_26; - wire int_13_26; - wire int_14_26; - wire int_15_26; - wire int_16_26; - wire int_17_26; - wire int_18_26; - wire int_19_26; - wire int_20_26; - wire int_21_26; - wire int_22_26; - wire int_23_26; - wire int_24_26; - wire int_25_26; - wire int_0_27; - wire int_1_27; - wire int_2_27; - wire int_3_27; - wire int_4_27; - wire int_5_27; - wire int_6_27; - wire int_7_27; - wire int_8_27; - wire int_9_27; - wire int_10_27; - wire int_11_27; - wire int_12_27; - wire int_13_27; - wire int_14_27; - wire int_15_27; - wire int_16_27; - wire int_17_27; - wire int_18_27; - wire int_19_27; - wire int_20_27; - wire int_21_27; - wire int_22_27; - wire int_23_27; - wire int_24_27; - wire int_25_27; - wire int_0_28; - wire int_1_28; - wire int_2_28; - wire int_3_28; - wire int_4_28; - wire int_5_28; - wire int_6_28; - wire int_7_28; - wire int_8_28; - wire int_9_28; - wire int_10_28; - wire int_11_28; - wire int_12_28; - wire int_13_28; - wire int_14_28; - wire int_15_28; - wire int_16_28; - wire int_17_28; - wire int_18_28; - wire int_19_28; - wire int_20_28; - wire int_21_28; - wire int_22_28; - wire int_23_28; - wire int_24_28; - wire int_25_28; - wire int_26_28; - wire int_27_28; - wire int_0_29; - wire int_1_29; - wire int_2_29; - wire int_3_29; - wire int_4_29; - wire int_5_29; - wire int_6_29; - wire int_7_29; - wire int_8_29; - wire int_9_29; - wire int_10_29; - wire int_11_29; - wire int_12_29; - wire int_13_29; - wire int_14_29; - wire int_15_29; - wire int_16_29; - wire int_17_29; - wire int_18_29; - wire int_19_29; - wire int_20_29; - wire int_21_29; - wire int_22_29; - wire int_23_29; - wire int_24_29; - wire int_25_29; - wire int_26_29; - wire int_27_29; - wire int_0_30; - wire int_1_30; - wire int_2_30; - wire int_3_30; - wire int_4_30; - wire int_5_30; - wire int_6_30; - wire int_7_30; - wire int_8_30; - wire int_9_30; - wire int_10_30; - wire int_11_30; - wire int_12_30; - wire int_13_30; - wire int_14_30; - wire int_15_30; - wire int_16_30; - wire int_17_30; - wire int_18_30; - wire int_19_30; - wire int_20_30; - wire int_21_30; - wire int_22_30; - wire int_23_30; - wire int_24_30; - wire int_25_30; - wire int_26_30; - wire int_27_30; - wire int_28_30; - wire int_29_30; - wire int_0_31; - wire int_1_31; - wire int_2_31; - wire int_3_31; - wire int_4_31; - wire int_5_31; - wire int_6_31; - wire int_7_31; - wire int_8_31; - wire int_9_31; - wire int_10_31; - wire int_11_31; - wire int_12_31; - wire int_13_31; - wire int_14_31; - wire int_15_31; - wire int_16_31; - wire int_17_31; - wire int_18_31; - wire int_19_31; - wire int_20_31; - wire int_21_31; - wire int_22_31; - wire int_23_31; - wire int_24_31; - wire int_25_31; - wire int_26_31; - wire int_27_31; - wire int_28_31; - wire int_29_31; - wire int_0_32; - wire int_1_32; - wire int_2_32; - wire int_3_32; - wire int_4_32; - wire int_5_32; - wire int_6_32; - wire int_7_32; - wire int_8_32; - wire int_9_32; - wire int_10_32; - wire int_11_32; - wire int_12_32; - wire int_13_32; - wire int_14_32; - wire int_15_32; - wire int_16_32; - wire int_17_32; - wire int_18_32; - wire int_19_32; - wire int_20_32; - wire int_21_32; - wire int_22_32; - wire int_23_32; - wire int_24_32; - wire int_25_32; - wire int_26_32; - wire int_27_32; - wire int_28_32; - wire int_29_32; - wire int_30_32; - wire int_31_32; - wire int_0_33; - wire int_1_33; - wire int_2_33; - wire int_3_33; - wire int_4_33; - wire int_5_33; - wire int_6_33; - wire int_7_33; - wire int_8_33; - wire int_9_33; - wire int_10_33; - wire int_11_33; - wire int_12_33; - wire int_13_33; - wire int_14_33; - wire int_15_33; - wire int_16_33; - wire int_17_33; - wire int_18_33; - wire int_19_33; - wire int_20_33; - wire int_21_33; - wire int_22_33; - wire int_23_33; - wire int_24_33; - wire int_25_33; - wire int_26_33; - wire int_27_33; - wire int_28_33; - wire int_29_33; - wire int_30_33; - wire int_31_33; - wire int_0_34; - wire int_1_34; - wire int_2_34; - wire int_3_34; - wire int_4_34; - wire int_5_34; - wire int_6_34; - wire int_7_34; - wire int_8_34; - wire int_9_34; - wire int_10_34; - wire int_11_34; - wire int_12_34; - wire int_13_34; - wire int_14_34; - wire int_15_34; - wire int_16_34; - wire int_17_34; - wire int_18_34; - wire int_19_34; - wire int_20_34; - wire int_21_34; - wire int_22_34; - wire int_23_34; - wire int_24_34; - wire int_25_34; - wire int_26_34; - wire int_27_34; - wire int_28_34; - wire int_29_34; - wire int_30_34; - wire int_31_34; - wire int_32_34; - wire int_33_34; - wire int_0_35; - wire int_1_35; - wire int_2_35; - wire int_3_35; - wire int_4_35; - wire int_5_35; - wire int_6_35; - wire int_7_35; - wire int_8_35; - wire int_9_35; - wire int_10_35; - wire int_11_35; - wire int_12_35; - wire int_13_35; - wire int_14_35; - wire int_15_35; - wire int_16_35; - wire int_17_35; - wire int_18_35; - wire int_19_35; - wire int_20_35; - wire int_21_35; - wire int_22_35; - wire int_23_35; - wire int_24_35; - wire int_25_35; - wire int_26_35; - wire int_27_35; - wire int_28_35; - wire int_29_35; - wire int_30_35; - wire int_31_35; - wire int_32_35; - wire int_33_35; - wire int_0_36; - wire int_1_36; - wire int_2_36; - wire int_3_36; - wire int_4_36; - wire int_5_36; - wire int_6_36; - wire int_7_36; - wire int_8_36; - wire int_9_36; - wire int_10_36; - wire int_11_36; - wire int_12_36; - wire int_13_36; - wire int_14_36; - wire int_15_36; - wire int_16_36; - wire int_17_36; - wire int_18_36; - wire int_19_36; - wire int_20_36; - wire int_21_36; - wire int_22_36; - wire int_23_36; - wire int_24_36; - wire int_25_36; - wire int_26_36; - wire int_27_36; - wire int_28_36; - wire int_29_36; - wire int_30_36; - wire int_31_36; - wire int_32_36; - wire int_33_36; - wire int_34_36; - wire int_35_36; - wire int_0_37; - wire int_1_37; - wire int_2_37; - wire int_3_37; - wire int_4_37; - wire int_5_37; - wire int_6_37; - wire int_7_37; - wire int_8_37; - wire int_9_37; - wire int_10_37; - wire int_11_37; - wire int_12_37; - wire int_13_37; - wire int_14_37; - wire int_15_37; - wire int_16_37; - wire int_17_37; - wire int_18_37; - wire int_19_37; - wire int_20_37; - wire int_21_37; - wire int_22_37; - wire int_23_37; - wire int_24_37; - wire int_25_37; - wire int_26_37; - wire int_27_37; - wire int_28_37; - wire int_29_37; - wire int_30_37; - wire int_31_37; - wire int_32_37; - wire int_33_37; - wire int_34_37; - wire int_35_37; - wire int_0_38; - wire int_1_38; - wire int_2_38; - wire int_3_38; - wire int_4_38; - wire int_5_38; - wire int_6_38; - wire int_7_38; - wire int_8_38; - wire int_9_38; - wire int_10_38; - wire int_11_38; - wire int_12_38; - wire int_13_38; - wire int_14_38; - wire int_15_38; - wire int_16_38; - wire int_17_38; - wire int_18_38; - wire int_19_38; - wire int_20_38; - wire int_21_38; - wire int_22_38; - wire int_23_38; - wire int_24_38; - wire int_25_38; - wire int_26_38; - wire int_27_38; - wire int_28_38; - wire int_29_38; - wire int_30_38; - wire int_31_38; - wire int_32_38; - wire int_33_38; - wire int_34_38; - wire int_35_38; - wire int_36_38; - wire int_37_38; - wire int_0_39; - wire int_1_39; - wire int_2_39; - wire int_3_39; - wire int_4_39; - wire int_5_39; - wire int_6_39; - wire int_7_39; - wire int_8_39; - wire int_9_39; - wire int_10_39; - wire int_11_39; - wire int_12_39; - wire int_13_39; - wire int_14_39; - wire int_15_39; - wire int_16_39; - wire int_17_39; - wire int_18_39; - wire int_19_39; - wire int_20_39; - wire int_21_39; - wire int_22_39; - wire int_23_39; - wire int_24_39; - wire int_25_39; - wire int_26_39; - wire int_27_39; - wire int_28_39; - wire int_29_39; - wire int_30_39; - wire int_31_39; - wire int_32_39; - wire int_33_39; - wire int_34_39; - wire int_35_39; - wire int_36_39; - wire int_37_39; - wire int_0_40; - wire int_1_40; - wire int_2_40; - wire int_3_40; - wire int_4_40; - wire int_5_40; - wire int_6_40; - wire int_7_40; - wire int_8_40; - wire int_9_40; - wire int_10_40; - wire int_11_40; - wire int_12_40; - wire int_13_40; - wire int_14_40; - wire int_15_40; - wire int_16_40; - wire int_17_40; - wire int_18_40; - wire int_19_40; - wire int_20_40; - wire int_21_40; - wire int_22_40; - wire int_23_40; - wire int_24_40; - wire int_25_40; - wire int_26_40; - wire int_27_40; - wire int_28_40; - wire int_29_40; - wire int_30_40; - wire int_31_40; - wire int_32_40; - wire int_33_40; - wire int_34_40; - wire int_35_40; - wire int_36_40; - wire int_37_40; - wire int_38_40; - wire int_39_40; - wire int_0_41; - wire int_1_41; - wire int_2_41; - wire int_3_41; - wire int_4_41; - wire int_5_41; - wire int_6_41; - wire int_7_41; - wire int_8_41; - wire int_9_41; - wire int_10_41; - wire int_11_41; - wire int_12_41; - wire int_13_41; - wire int_14_41; - wire int_15_41; - wire int_16_41; - wire int_17_41; - wire int_18_41; - wire int_19_41; - wire int_20_41; - wire int_21_41; - wire int_22_41; - wire int_23_41; - wire int_24_41; - wire int_25_41; - wire int_26_41; - wire int_27_41; - wire int_28_41; - wire int_29_41; - wire int_30_41; - wire int_31_41; - wire int_32_41; - wire int_33_41; - wire int_34_41; - wire int_35_41; - wire int_36_41; - wire int_37_41; - wire int_38_41; - wire int_39_41; - wire int_0_42; - wire int_1_42; - wire int_2_42; - wire int_3_42; - wire int_4_42; - wire int_5_42; - wire int_6_42; - wire int_7_42; - wire int_8_42; - wire int_9_42; - wire int_10_42; - wire int_11_42; - wire int_12_42; - wire int_13_42; - wire int_14_42; - wire int_15_42; - wire int_16_42; - wire int_17_42; - wire int_18_42; - wire int_19_42; - wire int_20_42; - wire int_21_42; - wire int_22_42; - wire int_23_42; - wire int_24_42; - wire int_25_42; - wire int_26_42; - wire int_27_42; - wire int_28_42; - wire int_29_42; - wire int_30_42; - wire int_31_42; - wire int_32_42; - wire int_33_42; - wire int_34_42; - wire int_35_42; - wire int_36_42; - wire int_37_42; - wire int_38_42; - wire int_39_42; - wire int_40_42; - wire int_41_42; - wire int_0_43; - wire int_1_43; - wire int_2_43; - wire int_3_43; - wire int_4_43; - wire int_5_43; - wire int_6_43; - wire int_7_43; - wire int_8_43; - wire int_9_43; - wire int_10_43; - wire int_11_43; - wire int_12_43; - wire int_13_43; - wire int_14_43; - wire int_15_43; - wire int_16_43; - wire int_17_43; - wire int_18_43; - wire int_19_43; - wire int_20_43; - wire int_21_43; - wire int_22_43; - wire int_23_43; - wire int_24_43; - wire int_25_43; - wire int_26_43; - wire int_27_43; - wire int_28_43; - wire int_29_43; - wire int_30_43; - wire int_31_43; - wire int_32_43; - wire int_33_43; - wire int_34_43; - wire int_35_43; - wire int_36_43; - wire int_37_43; - wire int_38_43; - wire int_39_43; - wire int_40_43; - wire int_41_43; - wire int_0_44; - wire int_1_44; - wire int_2_44; - wire int_3_44; - wire int_4_44; - wire int_5_44; - wire int_6_44; - wire int_7_44; - wire int_8_44; - wire int_9_44; - wire int_10_44; - wire int_11_44; - wire int_12_44; - wire int_13_44; - wire int_14_44; - wire int_15_44; - wire int_16_44; - wire int_17_44; - wire int_18_44; - wire int_19_44; - wire int_20_44; - wire int_21_44; - wire int_22_44; - wire int_23_44; - wire int_24_44; - wire int_25_44; - wire int_26_44; - wire int_27_44; - wire int_28_44; - wire int_29_44; - wire int_30_44; - wire int_31_44; - wire int_32_44; - wire int_33_44; - wire int_34_44; - wire int_35_44; - wire int_36_44; - wire int_37_44; - wire int_38_44; - wire int_39_44; - wire int_40_44; - wire int_41_44; - wire int_42_44; - wire int_43_44; - wire int_0_45; - wire int_1_45; - wire int_2_45; - wire int_3_45; - wire int_4_45; - wire int_5_45; - wire int_6_45; - wire int_7_45; - wire int_8_45; - wire int_9_45; - wire int_10_45; - wire int_11_45; - wire int_12_45; - wire int_13_45; - wire int_14_45; - wire int_15_45; - wire int_16_45; - wire int_17_45; - wire int_18_45; - wire int_19_45; - wire int_20_45; - wire int_21_45; - wire int_22_45; - wire int_23_45; - wire int_24_45; - wire int_25_45; - wire int_26_45; - wire int_27_45; - wire int_28_45; - wire int_29_45; - wire int_30_45; - wire int_31_45; - wire int_32_45; - wire int_33_45; - wire int_34_45; - wire int_35_45; - wire int_36_45; - wire int_37_45; - wire int_38_45; - wire int_39_45; - wire int_40_45; - wire int_41_45; - wire int_42_45; - wire int_43_45; - wire int_0_46; - wire int_1_46; - wire int_2_46; - wire int_3_46; - wire int_4_46; - wire int_5_46; - wire int_6_46; - wire int_7_46; - wire int_8_46; - wire int_9_46; - wire int_10_46; - wire int_11_46; - wire int_12_46; - wire int_13_46; - wire int_14_46; - wire int_15_46; - wire int_16_46; - wire int_17_46; - wire int_18_46; - wire int_19_46; - wire int_20_46; - wire int_21_46; - wire int_22_46; - wire int_23_46; - wire int_24_46; - wire int_25_46; - wire int_26_46; - wire int_27_46; - wire int_28_46; - wire int_29_46; - wire int_30_46; - wire int_31_46; - wire int_32_46; - wire int_33_46; - wire int_34_46; - wire int_35_46; - wire int_36_46; - wire int_37_46; - wire int_38_46; - wire int_39_46; - wire int_40_46; - wire int_41_46; - wire int_42_46; - wire int_43_46; - wire int_44_46; - wire int_45_46; - wire int_0_47; - wire int_1_47; - wire int_2_47; - wire int_3_47; - wire int_4_47; - wire int_5_47; - wire int_6_47; - wire int_7_47; - wire int_8_47; - wire int_9_47; - wire int_10_47; - wire int_11_47; - wire int_12_47; - wire int_13_47; - wire int_14_47; - wire int_15_47; - wire int_16_47; - wire int_17_47; - wire int_18_47; - wire int_19_47; - wire int_20_47; - wire int_21_47; - wire int_22_47; - wire int_23_47; - wire int_24_47; - wire int_25_47; - wire int_26_47; - wire int_27_47; - wire int_28_47; - wire int_29_47; - wire int_30_47; - wire int_31_47; - wire int_32_47; - wire int_33_47; - wire int_34_47; - wire int_35_47; - wire int_36_47; - wire int_37_47; - wire int_38_47; - wire int_39_47; - wire int_40_47; - wire int_41_47; - wire int_42_47; - wire int_43_47; - wire int_44_47; - wire int_45_47; - wire int_0_48; - wire int_1_48; - wire int_2_48; - wire int_3_48; - wire int_4_48; - wire int_5_48; - wire int_6_48; - wire int_7_48; - wire int_8_48; - wire int_9_48; - wire int_10_48; - wire int_11_48; - wire int_12_48; - wire int_13_48; - wire int_14_48; - wire int_15_48; - wire int_16_48; - wire int_17_48; - wire int_18_48; - wire int_19_48; - wire int_20_48; - wire int_21_48; - wire int_22_48; - wire int_23_48; - wire int_24_48; - wire int_25_48; - wire int_26_48; - wire int_27_48; - wire int_28_48; - wire int_29_48; - wire int_30_48; - wire int_31_48; - wire int_32_48; - wire int_33_48; - wire int_34_48; - wire int_35_48; - wire int_36_48; - wire int_37_48; - wire int_38_48; - wire int_39_48; - wire int_40_48; - wire int_41_48; - wire int_42_48; - wire int_43_48; - wire int_44_48; - wire int_45_48; - wire int_46_48; - wire int_47_48; - wire int_0_49; - wire int_1_49; - wire int_2_49; - wire int_3_49; - wire int_4_49; - wire int_5_49; - wire int_6_49; - wire int_7_49; - wire int_8_49; - wire int_9_49; - wire int_10_49; - wire int_11_49; - wire int_12_49; - wire int_13_49; - wire int_14_49; - wire int_15_49; - wire int_16_49; - wire int_17_49; - wire int_18_49; - wire int_19_49; - wire int_20_49; - wire int_21_49; - wire int_22_49; - wire int_23_49; - wire int_24_49; - wire int_25_49; - wire int_26_49; - wire int_27_49; - wire int_28_49; - wire int_29_49; - wire int_30_49; - wire int_31_49; - wire int_32_49; - wire int_33_49; - wire int_34_49; - wire int_35_49; - wire int_36_49; - wire int_37_49; - wire int_38_49; - wire int_39_49; - wire int_40_49; - wire int_41_49; - wire int_42_49; - wire int_43_49; - wire int_44_49; - wire int_45_49; - wire int_46_49; - wire int_47_49; - wire int_0_50; - wire int_1_50; - wire int_2_50; - wire int_3_50; - wire int_4_50; - wire int_5_50; - wire int_6_50; - wire int_7_50; - wire int_8_50; - wire int_9_50; - wire int_10_50; - wire int_11_50; - wire int_12_50; - wire int_13_50; - wire int_14_50; - wire int_15_50; - wire int_16_50; - wire int_17_50; - wire int_18_50; - wire int_19_50; - wire int_20_50; - wire int_21_50; - wire int_22_50; - wire int_23_50; - wire int_24_50; - wire int_25_50; - wire int_26_50; - wire int_27_50; - wire int_28_50; - wire int_29_50; - wire int_30_50; - wire int_31_50; - wire int_32_50; - wire int_33_50; - wire int_34_50; - wire int_35_50; - wire int_36_50; - wire int_37_50; - wire int_38_50; - wire int_39_50; - wire int_40_50; - wire int_41_50; - wire int_42_50; - wire int_43_50; - wire int_44_50; - wire int_45_50; - wire int_46_50; - wire int_47_50; - wire int_48_50; - wire int_49_50; - wire int_0_51; - wire int_1_51; - wire int_2_51; - wire int_3_51; - wire int_4_51; - wire int_5_51; - wire int_6_51; - wire int_7_51; - wire int_8_51; - wire int_9_51; - wire int_10_51; - wire int_11_51; - wire int_12_51; - wire int_13_51; - wire int_14_51; - wire int_15_51; - wire int_16_51; - wire int_17_51; - wire int_18_51; - wire int_19_51; - wire int_20_51; - wire int_21_51; - wire int_22_51; - wire int_23_51; - wire int_24_51; - wire int_25_51; - wire int_26_51; - wire int_27_51; - wire int_28_51; - wire int_29_51; - wire int_30_51; - wire int_31_51; - wire int_32_51; - wire int_33_51; - wire int_34_51; - wire int_35_51; - wire int_36_51; - wire int_37_51; - wire int_38_51; - wire int_39_51; - wire int_40_51; - wire int_41_51; - wire int_42_51; - wire int_43_51; - wire int_44_51; - wire int_45_51; - wire int_46_51; - wire int_47_51; - wire int_48_51; - wire int_49_51; - wire int_0_52; - wire int_1_52; - wire int_2_52; - wire int_3_52; - wire int_4_52; - wire int_5_52; - wire int_6_52; - wire int_7_52; - wire int_8_52; - wire int_9_52; - wire int_10_52; - wire int_11_52; - wire int_12_52; - wire int_13_52; - wire int_14_52; - wire int_15_52; - wire int_16_52; - wire int_17_52; - wire int_18_52; - wire int_19_52; - wire int_20_52; - wire int_21_52; - wire int_22_52; - wire int_23_52; - wire int_24_52; - wire int_25_52; - wire int_26_52; - wire int_27_52; - wire int_28_52; - wire int_29_52; - wire int_30_52; - wire int_31_52; - wire int_32_52; - wire int_33_52; - wire int_34_52; - wire int_35_52; - wire int_36_52; - wire int_37_52; - wire int_38_52; - wire int_39_52; - wire int_40_52; - wire int_41_52; - wire int_42_52; - wire int_43_52; - wire int_44_52; - wire int_45_52; - wire int_46_52; - wire int_47_52; - wire int_48_52; - wire int_49_52; - wire int_50_52; - wire int_51_52; - wire int_0_53; - wire int_1_53; - wire int_2_53; - wire int_3_53; - wire int_4_53; - wire int_5_53; - wire int_6_53; - wire int_7_53; - wire int_8_53; - wire int_9_53; - wire int_10_53; - wire int_11_53; - wire int_12_53; - wire int_13_53; - wire int_14_53; - wire int_15_53; - wire int_16_53; - wire int_17_53; - wire int_18_53; - wire int_19_53; - wire int_20_53; - wire int_21_53; - wire int_22_53; - wire int_23_53; - wire int_24_53; - wire int_25_53; - wire int_26_53; - wire int_27_53; - wire int_28_53; - wire int_29_53; - wire int_30_53; - wire int_31_53; - wire int_32_53; - wire int_33_53; - wire int_34_53; - wire int_35_53; - wire int_36_53; - wire int_37_53; - wire int_38_53; - wire int_39_53; - wire int_40_53; - wire int_41_53; - wire int_42_53; - wire int_43_53; - wire int_44_53; - wire int_45_53; - wire int_46_53; - wire int_47_53; - wire int_48_53; - wire int_49_53; - wire int_50_53; - wire int_51_53; - wire int_0_54; - wire int_1_54; - wire int_2_54; - wire int_3_54; - wire int_4_54; - wire int_5_54; - wire int_6_54; - wire int_7_54; - wire int_8_54; - wire int_9_54; - wire int_10_54; - wire int_11_54; - wire int_12_54; - wire int_13_54; - wire int_14_54; - wire int_15_54; - wire int_16_54; - wire int_17_54; - wire int_18_54; - wire int_19_54; - wire int_20_54; - wire int_21_54; - wire int_22_54; - wire int_23_54; - wire int_24_54; - wire int_25_54; - wire int_26_54; - wire int_27_54; - wire int_28_54; - wire int_29_54; - wire int_30_54; - wire int_31_54; - wire int_32_54; - wire int_33_54; - wire int_34_54; - wire int_35_54; - wire int_36_54; - wire int_37_54; - wire int_38_54; - wire int_39_54; - wire int_40_54; - wire int_41_54; - wire int_42_54; - wire int_43_54; - wire int_44_54; - wire int_45_54; - wire int_46_54; - wire int_47_54; - wire int_48_54; - wire int_49_54; - wire int_50_54; - wire int_51_54; - wire int_52_54; - wire int_53_54; - wire int_0_55; - wire int_1_55; - wire int_2_55; - wire int_3_55; - wire int_4_55; - wire int_5_55; - wire int_6_55; - wire int_7_55; - wire int_8_55; - wire int_9_55; - wire int_10_55; - wire int_11_55; - wire int_12_55; - wire int_13_55; - wire int_14_55; - wire int_15_55; - wire int_16_55; - wire int_17_55; - wire int_18_55; - wire int_19_55; - wire int_20_55; - wire int_21_55; - wire int_22_55; - wire int_23_55; - wire int_24_55; - wire int_25_55; - wire int_26_55; - wire int_27_55; - wire int_28_55; - wire int_29_55; - wire int_30_55; - wire int_31_55; - wire int_32_55; - wire int_33_55; - wire int_34_55; - wire int_35_55; - wire int_36_55; - wire int_37_55; - wire int_38_55; - wire int_39_55; - wire int_40_55; - wire int_41_55; - wire int_42_55; - wire int_43_55; - wire int_44_55; - wire int_45_55; - wire int_46_55; - wire int_47_55; - wire int_48_55; - wire int_49_55; - wire int_50_55; - wire int_51_55; - wire int_52_55; - wire int_53_55; - wire int_0_56; - wire int_1_56; - wire int_2_56; - wire int_3_56; - wire int_4_56; - wire int_5_56; - wire int_6_56; - wire int_7_56; - wire int_8_56; - wire int_9_56; - wire int_10_56; - wire int_11_56; - wire int_12_56; - wire int_13_56; - wire int_14_56; - wire int_15_56; - wire int_16_56; - wire int_17_56; - wire int_18_56; - wire int_19_56; - wire int_20_56; - wire int_21_56; - wire int_22_56; - wire int_23_56; - wire int_24_56; - wire int_25_56; - wire int_26_56; - wire int_27_56; - wire int_28_56; - wire int_29_56; - wire int_30_56; - wire int_31_56; - wire int_32_56; - wire int_33_56; - wire int_34_56; - wire int_35_56; - wire int_36_56; - wire int_37_56; - wire int_38_56; - wire int_39_56; - wire int_40_56; - wire int_41_56; - wire int_42_56; - wire int_43_56; - wire int_44_56; - wire int_45_56; - wire int_46_56; - wire int_47_56; - wire int_48_56; - wire int_49_56; - wire int_50_56; - wire int_51_56; - wire int_52_56; - wire int_53_56; - wire int_54_56; - wire int_55_56; - wire int_0_57; - wire int_1_57; - wire int_2_57; - wire int_3_57; - wire int_4_57; - wire int_5_57; - wire int_6_57; - wire int_7_57; - wire int_8_57; - wire int_9_57; - wire int_10_57; - wire int_11_57; - wire int_12_57; - wire int_13_57; - wire int_14_57; - wire int_15_57; - wire int_16_57; - wire int_17_57; - wire int_18_57; - wire int_19_57; - wire int_20_57; - wire int_21_57; - wire int_22_57; - wire int_23_57; - wire int_24_57; - wire int_25_57; - wire int_26_57; - wire int_27_57; - wire int_28_57; - wire int_29_57; - wire int_30_57; - wire int_31_57; - wire int_32_57; - wire int_33_57; - wire int_34_57; - wire int_35_57; - wire int_36_57; - wire int_37_57; - wire int_38_57; - wire int_39_57; - wire int_40_57; - wire int_41_57; - wire int_42_57; - wire int_43_57; - wire int_44_57; - wire int_45_57; - wire int_46_57; - wire int_47_57; - wire int_48_57; - wire int_49_57; - wire int_50_57; - wire int_51_57; - wire int_52_57; - wire int_53_57; - wire int_54_57; - wire int_55_57; - wire int_0_58; - wire int_1_58; - wire int_2_58; - wire int_3_58; - wire int_4_58; - wire int_5_58; - wire int_6_58; - wire int_7_58; - wire int_8_58; - wire int_9_58; - wire int_10_58; - wire int_11_58; - wire int_12_58; - wire int_13_58; - wire int_14_58; - wire int_15_58; - wire int_16_58; - wire int_17_58; - wire int_18_58; - wire int_19_58; - wire int_20_58; - wire int_21_58; - wire int_22_58; - wire int_23_58; - wire int_24_58; - wire int_25_58; - wire int_26_58; - wire int_27_58; - wire int_28_58; - wire int_29_58; - wire int_30_58; - wire int_31_58; - wire int_32_58; - wire int_33_58; - wire int_34_58; - wire int_35_58; - wire int_36_58; - wire int_37_58; - wire int_38_58; - wire int_39_58; - wire int_40_58; - wire int_41_58; - wire int_42_58; - wire int_43_58; - wire int_44_58; - wire int_45_58; - wire int_46_58; - wire int_47_58; - wire int_48_58; - wire int_49_58; - wire int_50_58; - wire int_51_58; - wire int_52_58; - wire int_53_58; - wire int_54_58; - wire int_55_58; - wire int_56_58; - wire int_57_58; - wire int_0_59; - wire int_1_59; - wire int_2_59; - wire int_3_59; - wire int_4_59; - wire int_5_59; - wire int_6_59; - wire int_7_59; - wire int_8_59; - wire int_9_59; - wire int_10_59; - wire int_11_59; - wire int_12_59; - wire int_13_59; - wire int_14_59; - wire int_15_59; - wire int_16_59; - wire int_17_59; - wire int_18_59; - wire int_19_59; - wire int_20_59; - wire int_21_59; - wire int_22_59; - wire int_23_59; - wire int_24_59; - wire int_25_59; - wire int_26_59; - wire int_27_59; - wire int_28_59; - wire int_29_59; - wire int_30_59; - wire int_31_59; - wire int_32_59; - wire int_33_59; - wire int_34_59; - wire int_35_59; - wire int_36_59; - wire int_37_59; - wire int_38_59; - wire int_39_59; - wire int_40_59; - wire int_41_59; - wire int_42_59; - wire int_43_59; - wire int_44_59; - wire int_45_59; - wire int_46_59; - wire int_47_59; - wire int_48_59; - wire int_49_59; - wire int_50_59; - wire int_51_59; - wire int_52_59; - wire int_53_59; - wire int_54_59; - wire int_55_59; - wire int_56_59; - wire int_57_59; - wire int_0_60; - wire int_1_60; - wire int_2_60; - wire int_3_60; - wire int_4_60; - wire int_5_60; - wire int_6_60; - wire int_7_60; - wire int_8_60; - wire int_9_60; - wire int_10_60; - wire int_11_60; - wire int_12_60; - wire int_13_60; - wire int_14_60; - wire int_15_60; - wire int_16_60; - wire int_17_60; - wire int_18_60; - wire int_19_60; - wire int_20_60; - wire int_21_60; - wire int_22_60; - wire int_23_60; - wire int_24_60; - wire int_25_60; - wire int_26_60; - wire int_27_60; - wire int_28_60; - wire int_29_60; - wire int_30_60; - wire int_31_60; - wire int_32_60; - wire int_33_60; - wire int_34_60; - wire int_35_60; - wire int_36_60; - wire int_37_60; - wire int_38_60; - wire int_39_60; - wire int_40_60; - wire int_41_60; - wire int_42_60; - wire int_43_60; - wire int_44_60; - wire int_45_60; - wire int_46_60; - wire int_47_60; - wire int_48_60; - wire int_49_60; - wire int_50_60; - wire int_51_60; - wire int_52_60; - wire int_53_60; - wire int_54_60; - wire int_55_60; - wire int_56_60; - wire int_57_60; - wire int_58_60; - wire int_59_60; - wire int_0_61; - wire int_1_61; - wire int_2_61; - wire int_3_61; - wire int_4_61; - wire int_5_61; - wire int_6_61; - wire int_7_61; - wire int_8_61; - wire int_9_61; - wire int_10_61; - wire int_11_61; - wire int_12_61; - wire int_13_61; - wire int_14_61; - wire int_15_61; - wire int_16_61; - wire int_17_61; - wire int_18_61; - wire int_19_61; - wire int_20_61; - wire int_21_61; - wire int_22_61; - wire int_23_61; - wire int_24_61; - wire int_25_61; - wire int_26_61; - wire int_27_61; - wire int_28_61; - wire int_29_61; - wire int_30_61; - wire int_31_61; - wire int_32_61; - wire int_33_61; - wire int_34_61; - wire int_35_61; - wire int_36_61; - wire int_37_61; - wire int_38_61; - wire int_39_61; - wire int_40_61; - wire int_41_61; - wire int_42_61; - wire int_43_61; - wire int_44_61; - wire int_45_61; - wire int_46_61; - wire int_47_61; - wire int_48_61; - wire int_49_61; - wire int_50_61; - wire int_51_61; - wire int_52_61; - wire int_53_61; - wire int_54_61; - wire int_55_61; - wire int_56_61; - wire int_57_61; - wire int_58_61; - wire int_59_61; - wire int_0_62; - wire int_1_62; - wire int_2_62; - wire int_3_62; - wire int_4_62; - wire int_5_62; - wire int_6_62; - wire int_7_62; - wire int_8_62; - wire int_9_62; - wire int_10_62; - wire int_11_62; - wire int_12_62; - wire int_13_62; - wire int_14_62; - wire int_15_62; - wire int_16_62; - wire int_17_62; - wire int_18_62; - wire int_19_62; - wire int_20_62; - wire int_21_62; - wire int_22_62; - wire int_23_62; - wire int_24_62; - wire int_25_62; - wire int_26_62; - wire int_27_62; - wire int_28_62; - wire int_29_62; - wire int_30_62; - wire int_31_62; - wire int_32_62; - wire int_33_62; - wire int_34_62; - wire int_35_62; - wire int_36_62; - wire int_37_62; - wire int_38_62; - wire int_39_62; - wire int_40_62; - wire int_41_62; - wire int_42_62; - wire int_43_62; - wire int_44_62; - wire int_45_62; - wire int_46_62; - wire int_47_62; - wire int_48_62; - wire int_49_62; - wire int_50_62; - wire int_51_62; - wire int_52_62; - wire int_53_62; - wire int_54_62; - wire int_55_62; - wire int_56_62; - wire int_57_62; - wire int_58_62; - wire int_59_62; - wire int_60_62; - wire int_61_62; - wire int_0_63; - wire int_1_63; - wire int_2_63; - wire int_3_63; - wire int_4_63; - wire int_5_63; - wire int_6_63; - wire int_7_63; - wire int_8_63; - wire int_9_63; - wire int_10_63; - wire int_11_63; - wire int_12_63; - wire int_13_63; - wire int_14_63; - wire int_15_63; - wire int_16_63; - wire int_17_63; - wire int_18_63; - wire int_19_63; - wire int_20_63; - wire int_21_63; - wire int_22_63; - wire int_23_63; - wire int_24_63; - wire int_25_63; - wire int_26_63; - wire int_27_63; - wire int_28_63; - wire int_29_63; - wire int_30_63; - wire int_31_63; - wire int_32_63; - wire int_33_63; - wire int_34_63; - wire int_35_63; - wire int_36_63; - wire int_37_63; - wire int_38_63; - wire int_39_63; - wire int_40_63; - wire int_41_63; - wire int_42_63; - wire int_43_63; - wire int_44_63; - wire int_45_63; - wire int_46_63; - wire int_47_63; - wire int_48_63; - wire int_49_63; - wire int_50_63; - wire int_51_63; - wire int_52_63; - wire int_53_63; - wire int_54_63; - wire int_55_63; - wire int_56_63; - wire int_57_63; - wire int_58_63; - wire int_59_63; - wire int_60_63; - wire int_61_63; - wire int_0_64; - wire int_1_64; - wire int_2_64; - wire int_3_64; - wire int_4_64; - wire int_5_64; - wire int_6_64; - wire int_7_64; - wire int_8_64; - wire int_9_64; - wire int_10_64; - wire int_11_64; - wire int_12_64; - wire int_13_64; - wire int_14_64; - wire int_15_64; - wire int_16_64; - wire int_17_64; - wire int_18_64; - wire int_19_64; - wire int_20_64; - wire int_21_64; - wire int_22_64; - wire int_23_64; - wire int_24_64; - wire int_25_64; - wire int_26_64; - wire int_27_64; - wire int_28_64; - wire int_29_64; - wire int_30_64; - wire int_31_64; - wire int_32_64; - wire int_33_64; - wire int_34_64; - wire int_35_64; - wire int_36_64; - wire int_37_64; - wire int_38_64; - wire int_39_64; - wire int_40_64; - wire int_41_64; - wire int_42_64; - wire int_43_64; - wire int_44_64; - wire int_45_64; - wire int_46_64; - wire int_47_64; - wire int_48_64; - wire int_49_64; - wire int_50_64; - wire int_51_64; - wire int_52_64; - wire int_53_64; - wire int_54_64; - wire int_55_64; - wire int_56_64; - wire int_57_64; - wire int_58_64; - wire int_59_64; - wire int_60_64; - wire int_61_64; - wire int_0_65; - wire int_1_65; - wire int_2_65; - wire int_3_65; - wire int_4_65; - wire int_5_65; - wire int_6_65; - wire int_7_65; - wire int_8_65; - wire int_9_65; - wire int_10_65; - wire int_11_65; - wire int_12_65; - wire int_13_65; - wire int_14_65; - wire int_15_65; - wire int_16_65; - wire int_17_65; - wire int_18_65; - wire int_19_65; - wire int_20_65; - wire int_21_65; - wire int_22_65; - wire int_23_65; - wire int_24_65; - wire int_25_65; - wire int_26_65; - wire int_27_65; - wire int_28_65; - wire int_29_65; - wire int_30_65; - wire int_31_65; - wire int_32_65; - wire int_33_65; - wire int_34_65; - wire int_35_65; - wire int_36_65; - wire int_37_65; - wire int_38_65; - wire int_39_65; - wire int_40_65; - wire int_41_65; - wire int_42_65; - wire int_43_65; - wire int_44_65; - wire int_45_65; - wire int_46_65; - wire int_47_65; - wire int_48_65; - wire int_49_65; - wire int_50_65; - wire int_51_65; - wire int_52_65; - wire int_53_65; - wire int_54_65; - wire int_55_65; - wire int_56_65; - wire int_57_65; - wire int_58_65; - wire int_59_65; - wire int_60_65; - wire int_61_65; - wire int_0_66; - wire int_1_66; - wire int_2_66; - wire int_3_66; - wire int_4_66; - wire int_5_66; - wire int_6_66; - wire int_7_66; - wire int_8_66; - wire int_9_66; - wire int_10_66; - wire int_11_66; - wire int_12_66; - wire int_13_66; - wire int_14_66; - wire int_15_66; - wire int_16_66; - wire int_17_66; - wire int_18_66; - wire int_19_66; - wire int_20_66; - wire int_21_66; - wire int_22_66; - wire int_23_66; - wire int_24_66; - wire int_25_66; - wire int_26_66; - wire int_27_66; - wire int_28_66; - wire int_29_66; - wire int_30_66; - wire int_31_66; - wire int_32_66; - wire int_33_66; - wire int_34_66; - wire int_35_66; - wire int_36_66; - wire int_37_66; - wire int_38_66; - wire int_39_66; - wire int_40_66; - wire int_41_66; - wire int_42_66; - wire int_43_66; - wire int_44_66; - wire int_45_66; - wire int_46_66; - wire int_47_66; - wire int_48_66; - wire int_49_66; - wire int_50_66; - wire int_51_66; - wire int_52_66; - wire int_53_66; - wire int_54_66; - wire int_55_66; - wire int_56_66; - wire int_57_66; - wire int_58_66; - wire int_59_66; - wire int_60_66; - wire int_61_66; - wire int_0_67; - wire int_1_67; - wire int_2_67; - wire int_3_67; - wire int_4_67; - wire int_5_67; - wire int_6_67; - wire int_7_67; - wire int_8_67; - wire int_9_67; - wire int_10_67; - wire int_11_67; - wire int_12_67; - wire int_13_67; - wire int_14_67; - wire int_15_67; - wire int_16_67; - wire int_17_67; - wire int_18_67; - wire int_19_67; - wire int_20_67; - wire int_21_67; - wire int_22_67; - wire int_23_67; - wire int_24_67; - wire int_25_67; - wire int_26_67; - wire int_27_67; - wire int_28_67; - wire int_29_67; - wire int_30_67; - wire int_31_67; - wire int_32_67; - wire int_33_67; - wire int_34_67; - wire int_35_67; - wire int_36_67; - wire int_37_67; - wire int_38_67; - wire int_39_67; - wire int_40_67; - wire int_41_67; - wire int_42_67; - wire int_43_67; - wire int_44_67; - wire int_45_67; - wire int_46_67; - wire int_47_67; - wire int_48_67; - wire int_49_67; - wire int_50_67; - wire int_51_67; - wire int_52_67; - wire int_53_67; - wire int_54_67; - wire int_55_67; - wire int_56_67; - wire int_57_67; - wire int_58_67; - wire int_59_67; - wire int_60_67; - wire int_61_67; - wire int_0_68; - wire int_1_68; - wire int_2_68; - wire int_3_68; - wire int_4_68; - wire int_5_68; - wire int_6_68; - wire int_7_68; - wire int_8_68; - wire int_9_68; - wire int_10_68; - wire int_11_68; - wire int_12_68; - wire int_13_68; - wire int_14_68; - wire int_15_68; - wire int_16_68; - wire int_17_68; - wire int_18_68; - wire int_19_68; - wire int_20_68; - wire int_21_68; - wire int_22_68; - wire int_23_68; - wire int_24_68; - wire int_25_68; - wire int_26_68; - wire int_27_68; - wire int_28_68; - wire int_29_68; - wire int_30_68; - wire int_31_68; - wire int_32_68; - wire int_33_68; - wire int_34_68; - wire int_35_68; - wire int_36_68; - wire int_37_68; - wire int_38_68; - wire int_39_68; - wire int_40_68; - wire int_41_68; - wire int_42_68; - wire int_43_68; - wire int_44_68; - wire int_45_68; - wire int_46_68; - wire int_47_68; - wire int_48_68; - wire int_49_68; - wire int_50_68; - wire int_51_68; - wire int_52_68; - wire int_53_68; - wire int_54_68; - wire int_55_68; - wire int_56_68; - wire int_57_68; - wire int_58_68; - wire int_59_68; - wire int_60_68; - wire int_61_68; - wire int_0_69; - wire int_1_69; - wire int_2_69; - wire int_3_69; - wire int_4_69; - wire int_5_69; - wire int_6_69; - wire int_7_69; - wire int_8_69; - wire int_9_69; - wire int_10_69; - wire int_11_69; - wire int_12_69; - wire int_13_69; - wire int_14_69; - wire int_15_69; - wire int_16_69; - wire int_17_69; - wire int_18_69; - wire int_19_69; - wire int_20_69; - wire int_21_69; - wire int_22_69; - wire int_23_69; - wire int_24_69; - wire int_25_69; - wire int_26_69; - wire int_27_69; - wire int_28_69; - wire int_29_69; - wire int_30_69; - wire int_31_69; - wire int_32_69; - wire int_33_69; - wire int_34_69; - wire int_35_69; - wire int_36_69; - wire int_37_69; - wire int_38_69; - wire int_39_69; - wire int_40_69; - wire int_41_69; - wire int_42_69; - wire int_43_69; - wire int_44_69; - wire int_45_69; - wire int_46_69; - wire int_47_69; - wire int_48_69; - wire int_49_69; - wire int_50_69; - wire int_51_69; - wire int_52_69; - wire int_53_69; - wire int_54_69; - wire int_55_69; - wire int_56_69; - wire int_57_69; - wire int_58_69; - wire int_59_69; - wire int_0_70; - wire int_1_70; - wire int_2_70; - wire int_3_70; - wire int_4_70; - wire int_5_70; - wire int_6_70; - wire int_7_70; - wire int_8_70; - wire int_9_70; - wire int_10_70; - wire int_11_70; - wire int_12_70; - wire int_13_70; - wire int_14_70; - wire int_15_70; - wire int_16_70; - wire int_17_70; - wire int_18_70; - wire int_19_70; - wire int_20_70; - wire int_21_70; - wire int_22_70; - wire int_23_70; - wire int_24_70; - wire int_25_70; - wire int_26_70; - wire int_27_70; - wire int_28_70; - wire int_29_70; - wire int_30_70; - wire int_31_70; - wire int_32_70; - wire int_33_70; - wire int_34_70; - wire int_35_70; - wire int_36_70; - wire int_37_70; - wire int_38_70; - wire int_39_70; - wire int_40_70; - wire int_41_70; - wire int_42_70; - wire int_43_70; - wire int_44_70; - wire int_45_70; - wire int_46_70; - wire int_47_70; - wire int_48_70; - wire int_49_70; - wire int_50_70; - wire int_51_70; - wire int_52_70; - wire int_53_70; - wire int_54_70; - wire int_55_70; - wire int_56_70; - wire int_57_70; - wire int_58_70; - wire int_59_70; - wire int_0_71; - wire int_1_71; - wire int_2_71; - wire int_3_71; - wire int_4_71; - wire int_5_71; - wire int_6_71; - wire int_7_71; - wire int_8_71; - wire int_9_71; - wire int_10_71; - wire int_11_71; - wire int_12_71; - wire int_13_71; - wire int_14_71; - wire int_15_71; - wire int_16_71; - wire int_17_71; - wire int_18_71; - wire int_19_71; - wire int_20_71; - wire int_21_71; - wire int_22_71; - wire int_23_71; - wire int_24_71; - wire int_25_71; - wire int_26_71; - wire int_27_71; - wire int_28_71; - wire int_29_71; - wire int_30_71; - wire int_31_71; - wire int_32_71; - wire int_33_71; - wire int_34_71; - wire int_35_71; - wire int_36_71; - wire int_37_71; - wire int_38_71; - wire int_39_71; - wire int_40_71; - wire int_41_71; - wire int_42_71; - wire int_43_71; - wire int_44_71; - wire int_45_71; - wire int_46_71; - wire int_47_71; - wire int_48_71; - wire int_49_71; - wire int_50_71; - wire int_51_71; - wire int_52_71; - wire int_53_71; - wire int_54_71; - wire int_55_71; - wire int_56_71; - wire int_57_71; - wire int_0_72; - wire int_1_72; - wire int_2_72; - wire int_3_72; - wire int_4_72; - wire int_5_72; - wire int_6_72; - wire int_7_72; - wire int_8_72; - wire int_9_72; - wire int_10_72; - wire int_11_72; - wire int_12_72; - wire int_13_72; - wire int_14_72; - wire int_15_72; - wire int_16_72; - wire int_17_72; - wire int_18_72; - wire int_19_72; - wire int_20_72; - wire int_21_72; - wire int_22_72; - wire int_23_72; - wire int_24_72; - wire int_25_72; - wire int_26_72; - wire int_27_72; - wire int_28_72; - wire int_29_72; - wire int_30_72; - wire int_31_72; - wire int_32_72; - wire int_33_72; - wire int_34_72; - wire int_35_72; - wire int_36_72; - wire int_37_72; - wire int_38_72; - wire int_39_72; - wire int_40_72; - wire int_41_72; - wire int_42_72; - wire int_43_72; - wire int_44_72; - wire int_45_72; - wire int_46_72; - wire int_47_72; - wire int_48_72; - wire int_49_72; - wire int_50_72; - wire int_51_72; - wire int_52_72; - wire int_53_72; - wire int_54_72; - wire int_55_72; - wire int_56_72; - wire int_57_72; - wire int_0_73; - wire int_1_73; - wire int_2_73; - wire int_3_73; - wire int_4_73; - wire int_5_73; - wire int_6_73; - wire int_7_73; - wire int_8_73; - wire int_9_73; - wire int_10_73; - wire int_11_73; - wire int_12_73; - wire int_13_73; - wire int_14_73; - wire int_15_73; - wire int_16_73; - wire int_17_73; - wire int_18_73; - wire int_19_73; - wire int_20_73; - wire int_21_73; - wire int_22_73; - wire int_23_73; - wire int_24_73; - wire int_25_73; - wire int_26_73; - wire int_27_73; - wire int_28_73; - wire int_29_73; - wire int_30_73; - wire int_31_73; - wire int_32_73; - wire int_33_73; - wire int_34_73; - wire int_35_73; - wire int_36_73; - wire int_37_73; - wire int_38_73; - wire int_39_73; - wire int_40_73; - wire int_41_73; - wire int_42_73; - wire int_43_73; - wire int_44_73; - wire int_45_73; - wire int_46_73; - wire int_47_73; - wire int_48_73; - wire int_49_73; - wire int_50_73; - wire int_51_73; - wire int_52_73; - wire int_53_73; - wire int_54_73; - wire int_55_73; - wire int_0_74; - wire int_1_74; - wire int_2_74; - wire int_3_74; - wire int_4_74; - wire int_5_74; - wire int_6_74; - wire int_7_74; - wire int_8_74; - wire int_9_74; - wire int_10_74; - wire int_11_74; - wire int_12_74; - wire int_13_74; - wire int_14_74; - wire int_15_74; - wire int_16_74; - wire int_17_74; - wire int_18_74; - wire int_19_74; - wire int_20_74; - wire int_21_74; - wire int_22_74; - wire int_23_74; - wire int_24_74; - wire int_25_74; - wire int_26_74; - wire int_27_74; - wire int_28_74; - wire int_29_74; - wire int_30_74; - wire int_31_74; - wire int_32_74; - wire int_33_74; - wire int_34_74; - wire int_35_74; - wire int_36_74; - wire int_37_74; - wire int_38_74; - wire int_39_74; - wire int_40_74; - wire int_41_74; - wire int_42_74; - wire int_43_74; - wire int_44_74; - wire int_45_74; - wire int_46_74; - wire int_47_74; - wire int_48_74; - wire int_49_74; - wire int_50_74; - wire int_51_74; - wire int_52_74; - wire int_53_74; - wire int_54_74; - wire int_55_74; - wire int_0_75; - wire int_1_75; - wire int_2_75; - wire int_3_75; - wire int_4_75; - wire int_5_75; - wire int_6_75; - wire int_7_75; - wire int_8_75; - wire int_9_75; - wire int_10_75; - wire int_11_75; - wire int_12_75; - wire int_13_75; - wire int_14_75; - wire int_15_75; - wire int_16_75; - wire int_17_75; - wire int_18_75; - wire int_19_75; - wire int_20_75; - wire int_21_75; - wire int_22_75; - wire int_23_75; - wire int_24_75; - wire int_25_75; - wire int_26_75; - wire int_27_75; - wire int_28_75; - wire int_29_75; - wire int_30_75; - wire int_31_75; - wire int_32_75; - wire int_33_75; - wire int_34_75; - wire int_35_75; - wire int_36_75; - wire int_37_75; - wire int_38_75; - wire int_39_75; - wire int_40_75; - wire int_41_75; - wire int_42_75; - wire int_43_75; - wire int_44_75; - wire int_45_75; - wire int_46_75; - wire int_47_75; - wire int_48_75; - wire int_49_75; - wire int_50_75; - wire int_51_75; - wire int_52_75; - wire int_53_75; - wire int_0_76; - wire int_1_76; - wire int_2_76; - wire int_3_76; - wire int_4_76; - wire int_5_76; - wire int_6_76; - wire int_7_76; - wire int_8_76; - wire int_9_76; - wire int_10_76; - wire int_11_76; - wire int_12_76; - wire int_13_76; - wire int_14_76; - wire int_15_76; - wire int_16_76; - wire int_17_76; - wire int_18_76; - wire int_19_76; - wire int_20_76; - wire int_21_76; - wire int_22_76; - wire int_23_76; - wire int_24_76; - wire int_25_76; - wire int_26_76; - wire int_27_76; - wire int_28_76; - wire int_29_76; - wire int_30_76; - wire int_31_76; - wire int_32_76; - wire int_33_76; - wire int_34_76; - wire int_35_76; - wire int_36_76; - wire int_37_76; - wire int_38_76; - wire int_39_76; - wire int_40_76; - wire int_41_76; - wire int_42_76; - wire int_43_76; - wire int_44_76; - wire int_45_76; - wire int_46_76; - wire int_47_76; - wire int_48_76; - wire int_49_76; - wire int_50_76; - wire int_51_76; - wire int_52_76; - wire int_53_76; - wire int_0_77; - wire int_1_77; - wire int_2_77; - wire int_3_77; - wire int_4_77; - wire int_5_77; - wire int_6_77; - wire int_7_77; - wire int_8_77; - wire int_9_77; - wire int_10_77; - wire int_11_77; - wire int_12_77; - wire int_13_77; - wire int_14_77; - wire int_15_77; - wire int_16_77; - wire int_17_77; - wire int_18_77; - wire int_19_77; - wire int_20_77; - wire int_21_77; - wire int_22_77; - wire int_23_77; - wire int_24_77; - wire int_25_77; - wire int_26_77; - wire int_27_77; - wire int_28_77; - wire int_29_77; - wire int_30_77; - wire int_31_77; - wire int_32_77; - wire int_33_77; - wire int_34_77; - wire int_35_77; - wire int_36_77; - wire int_37_77; - wire int_38_77; - wire int_39_77; - wire int_40_77; - wire int_41_77; - wire int_42_77; - wire int_43_77; - wire int_44_77; - wire int_45_77; - wire int_46_77; - wire int_47_77; - wire int_48_77; - wire int_49_77; - wire int_50_77; - wire int_51_77; - wire int_0_78; - wire int_1_78; - wire int_2_78; - wire int_3_78; - wire int_4_78; - wire int_5_78; - wire int_6_78; - wire int_7_78; - wire int_8_78; - wire int_9_78; - wire int_10_78; - wire int_11_78; - wire int_12_78; - wire int_13_78; - wire int_14_78; - wire int_15_78; - wire int_16_78; - wire int_17_78; - wire int_18_78; - wire int_19_78; - wire int_20_78; - wire int_21_78; - wire int_22_78; - wire int_23_78; - wire int_24_78; - wire int_25_78; - wire int_26_78; - wire int_27_78; - wire int_28_78; - wire int_29_78; - wire int_30_78; - wire int_31_78; - wire int_32_78; - wire int_33_78; - wire int_34_78; - wire int_35_78; - wire int_36_78; - wire int_37_78; - wire int_38_78; - wire int_39_78; - wire int_40_78; - wire int_41_78; - wire int_42_78; - wire int_43_78; - wire int_44_78; - wire int_45_78; - wire int_46_78; - wire int_47_78; - wire int_48_78; - wire int_49_78; - wire int_50_78; - wire int_51_78; - wire int_0_79; - wire int_1_79; - wire int_2_79; - wire int_3_79; - wire int_4_79; - wire int_5_79; - wire int_6_79; - wire int_7_79; - wire int_8_79; - wire int_9_79; - wire int_10_79; - wire int_11_79; - wire int_12_79; - wire int_13_79; - wire int_14_79; - wire int_15_79; - wire int_16_79; - wire int_17_79; - wire int_18_79; - wire int_19_79; - wire int_20_79; - wire int_21_79; - wire int_22_79; - wire int_23_79; - wire int_24_79; - wire int_25_79; - wire int_26_79; - wire int_27_79; - wire int_28_79; - wire int_29_79; - wire int_30_79; - wire int_31_79; - wire int_32_79; - wire int_33_79; - wire int_34_79; - wire int_35_79; - wire int_36_79; - wire int_37_79; - wire int_38_79; - wire int_39_79; - wire int_40_79; - wire int_41_79; - wire int_42_79; - wire int_43_79; - wire int_44_79; - wire int_45_79; - wire int_46_79; - wire int_47_79; - wire int_48_79; - wire int_49_79; - wire int_0_80; - wire int_1_80; - wire int_2_80; - wire int_3_80; - wire int_4_80; - wire int_5_80; - wire int_6_80; - wire int_7_80; - wire int_8_80; - wire int_9_80; - wire int_10_80; - wire int_11_80; - wire int_12_80; - wire int_13_80; - wire int_14_80; - wire int_15_80; - wire int_16_80; - wire int_17_80; - wire int_18_80; - wire int_19_80; - wire int_20_80; - wire int_21_80; - wire int_22_80; - wire int_23_80; - wire int_24_80; - wire int_25_80; - wire int_26_80; - wire int_27_80; - wire int_28_80; - wire int_29_80; - wire int_30_80; - wire int_31_80; - wire int_32_80; - wire int_33_80; - wire int_34_80; - wire int_35_80; - wire int_36_80; - wire int_37_80; - wire int_38_80; - wire int_39_80; - wire int_40_80; - wire int_41_80; - wire int_42_80; - wire int_43_80; - wire int_44_80; - wire int_45_80; - wire int_46_80; - wire int_47_80; - wire int_48_80; - wire int_49_80; - wire int_0_81; - wire int_1_81; - wire int_2_81; - wire int_3_81; - wire int_4_81; - wire int_5_81; - wire int_6_81; - wire int_7_81; - wire int_8_81; - wire int_9_81; - wire int_10_81; - wire int_11_81; - wire int_12_81; - wire int_13_81; - wire int_14_81; - wire int_15_81; - wire int_16_81; - wire int_17_81; - wire int_18_81; - wire int_19_81; - wire int_20_81; - wire int_21_81; - wire int_22_81; - wire int_23_81; - wire int_24_81; - wire int_25_81; - wire int_26_81; - wire int_27_81; - wire int_28_81; - wire int_29_81; - wire int_30_81; - wire int_31_81; - wire int_32_81; - wire int_33_81; - wire int_34_81; - wire int_35_81; - wire int_36_81; - wire int_37_81; - wire int_38_81; - wire int_39_81; - wire int_40_81; - wire int_41_81; - wire int_42_81; - wire int_43_81; - wire int_44_81; - wire int_45_81; - wire int_46_81; - wire int_47_81; - wire int_0_82; - wire int_1_82; - wire int_2_82; - wire int_3_82; - wire int_4_82; - wire int_5_82; - wire int_6_82; - wire int_7_82; - wire int_8_82; - wire int_9_82; - wire int_10_82; - wire int_11_82; - wire int_12_82; - wire int_13_82; - wire int_14_82; - wire int_15_82; - wire int_16_82; - wire int_17_82; - wire int_18_82; - wire int_19_82; - wire int_20_82; - wire int_21_82; - wire int_22_82; - wire int_23_82; - wire int_24_82; - wire int_25_82; - wire int_26_82; - wire int_27_82; - wire int_28_82; - wire int_29_82; - wire int_30_82; - wire int_31_82; - wire int_32_82; - wire int_33_82; - wire int_34_82; - wire int_35_82; - wire int_36_82; - wire int_37_82; - wire int_38_82; - wire int_39_82; - wire int_40_82; - wire int_41_82; - wire int_42_82; - wire int_43_82; - wire int_44_82; - wire int_45_82; - wire int_46_82; - wire int_47_82; - wire int_0_83; - wire int_1_83; - wire int_2_83; - wire int_3_83; - wire int_4_83; - wire int_5_83; - wire int_6_83; - wire int_7_83; - wire int_8_83; - wire int_9_83; - wire int_10_83; - wire int_11_83; - wire int_12_83; - wire int_13_83; - wire int_14_83; - wire int_15_83; - wire int_16_83; - wire int_17_83; - wire int_18_83; - wire int_19_83; - wire int_20_83; - wire int_21_83; - wire int_22_83; - wire int_23_83; - wire int_24_83; - wire int_25_83; - wire int_26_83; - wire int_27_83; - wire int_28_83; - wire int_29_83; - wire int_30_83; - wire int_31_83; - wire int_32_83; - wire int_33_83; - wire int_34_83; - wire int_35_83; - wire int_36_83; - wire int_37_83; - wire int_38_83; - wire int_39_83; - wire int_40_83; - wire int_41_83; - wire int_42_83; - wire int_43_83; - wire int_44_83; - wire int_45_83; - wire int_0_84; - wire int_1_84; - wire int_2_84; - wire int_3_84; - wire int_4_84; - wire int_5_84; - wire int_6_84; - wire int_7_84; - wire int_8_84; - wire int_9_84; - wire int_10_84; - wire int_11_84; - wire int_12_84; - wire int_13_84; - wire int_14_84; - wire int_15_84; - wire int_16_84; - wire int_17_84; - wire int_18_84; - wire int_19_84; - wire int_20_84; - wire int_21_84; - wire int_22_84; - wire int_23_84; - wire int_24_84; - wire int_25_84; - wire int_26_84; - wire int_27_84; - wire int_28_84; - wire int_29_84; - wire int_30_84; - wire int_31_84; - wire int_32_84; - wire int_33_84; - wire int_34_84; - wire int_35_84; - wire int_36_84; - wire int_37_84; - wire int_38_84; - wire int_39_84; - wire int_40_84; - wire int_41_84; - wire int_42_84; - wire int_43_84; - wire int_44_84; - wire int_45_84; - wire int_0_85; - wire int_1_85; - wire int_2_85; - wire int_3_85; - wire int_4_85; - wire int_5_85; - wire int_6_85; - wire int_7_85; - wire int_8_85; - wire int_9_85; - wire int_10_85; - wire int_11_85; - wire int_12_85; - wire int_13_85; - wire int_14_85; - wire int_15_85; - wire int_16_85; - wire int_17_85; - wire int_18_85; - wire int_19_85; - wire int_20_85; - wire int_21_85; - wire int_22_85; - wire int_23_85; - wire int_24_85; - wire int_25_85; - wire int_26_85; - wire int_27_85; - wire int_28_85; - wire int_29_85; - wire int_30_85; - wire int_31_85; - wire int_32_85; - wire int_33_85; - wire int_34_85; - wire int_35_85; - wire int_36_85; - wire int_37_85; - wire int_38_85; - wire int_39_85; - wire int_40_85; - wire int_41_85; - wire int_42_85; - wire int_43_85; - wire int_0_86; - wire int_1_86; - wire int_2_86; - wire int_3_86; - wire int_4_86; - wire int_5_86; - wire int_6_86; - wire int_7_86; - wire int_8_86; - wire int_9_86; - wire int_10_86; - wire int_11_86; - wire int_12_86; - wire int_13_86; - wire int_14_86; - wire int_15_86; - wire int_16_86; - wire int_17_86; - wire int_18_86; - wire int_19_86; - wire int_20_86; - wire int_21_86; - wire int_22_86; - wire int_23_86; - wire int_24_86; - wire int_25_86; - wire int_26_86; - wire int_27_86; - wire int_28_86; - wire int_29_86; - wire int_30_86; - wire int_31_86; - wire int_32_86; - wire int_33_86; - wire int_34_86; - wire int_35_86; - wire int_36_86; - wire int_37_86; - wire int_38_86; - wire int_39_86; - wire int_40_86; - wire int_41_86; - wire int_42_86; - wire int_43_86; - wire int_0_87; - wire int_1_87; - wire int_2_87; - wire int_3_87; - wire int_4_87; - wire int_5_87; - wire int_6_87; - wire int_7_87; - wire int_8_87; - wire int_9_87; - wire int_10_87; - wire int_11_87; - wire int_12_87; - wire int_13_87; - wire int_14_87; - wire int_15_87; - wire int_16_87; - wire int_17_87; - wire int_18_87; - wire int_19_87; - wire int_20_87; - wire int_21_87; - wire int_22_87; - wire int_23_87; - wire int_24_87; - wire int_25_87; - wire int_26_87; - wire int_27_87; - wire int_28_87; - wire int_29_87; - wire int_30_87; - wire int_31_87; - wire int_32_87; - wire int_33_87; - wire int_34_87; - wire int_35_87; - wire int_36_87; - wire int_37_87; - wire int_38_87; - wire int_39_87; - wire int_40_87; - wire int_41_87; - wire int_0_88; - wire int_1_88; - wire int_2_88; - wire int_3_88; - wire int_4_88; - wire int_5_88; - wire int_6_88; - wire int_7_88; - wire int_8_88; - wire int_9_88; - wire int_10_88; - wire int_11_88; - wire int_12_88; - wire int_13_88; - wire int_14_88; - wire int_15_88; - wire int_16_88; - wire int_17_88; - wire int_18_88; - wire int_19_88; - wire int_20_88; - wire int_21_88; - wire int_22_88; - wire int_23_88; - wire int_24_88; - wire int_25_88; - wire int_26_88; - wire int_27_88; - wire int_28_88; - wire int_29_88; - wire int_30_88; - wire int_31_88; - wire int_32_88; - wire int_33_88; - wire int_34_88; - wire int_35_88; - wire int_36_88; - wire int_37_88; - wire int_38_88; - wire int_39_88; - wire int_40_88; - wire int_41_88; - wire int_0_89; - wire int_1_89; - wire int_2_89; - wire int_3_89; - wire int_4_89; - wire int_5_89; - wire int_6_89; - wire int_7_89; - wire int_8_89; - wire int_9_89; - wire int_10_89; - wire int_11_89; - wire int_12_89; - wire int_13_89; - wire int_14_89; - wire int_15_89; - wire int_16_89; - wire int_17_89; - wire int_18_89; - wire int_19_89; - wire int_20_89; - wire int_21_89; - wire int_22_89; - wire int_23_89; - wire int_24_89; - wire int_25_89; - wire int_26_89; - wire int_27_89; - wire int_28_89; - wire int_29_89; - wire int_30_89; - wire int_31_89; - wire int_32_89; - wire int_33_89; - wire int_34_89; - wire int_35_89; - wire int_36_89; - wire int_37_89; - wire int_38_89; - wire int_39_89; - wire int_0_90; - wire int_1_90; - wire int_2_90; - wire int_3_90; - wire int_4_90; - wire int_5_90; - wire int_6_90; - wire int_7_90; - wire int_8_90; - wire int_9_90; - wire int_10_90; - wire int_11_90; - wire int_12_90; - wire int_13_90; - wire int_14_90; - wire int_15_90; - wire int_16_90; - wire int_17_90; - wire int_18_90; - wire int_19_90; - wire int_20_90; - wire int_21_90; - wire int_22_90; - wire int_23_90; - wire int_24_90; - wire int_25_90; - wire int_26_90; - wire int_27_90; - wire int_28_90; - wire int_29_90; - wire int_30_90; - wire int_31_90; - wire int_32_90; - wire int_33_90; - wire int_34_90; - wire int_35_90; - wire int_36_90; - wire int_37_90; - wire int_38_90; - wire int_39_90; - wire int_0_91; - wire int_1_91; - wire int_2_91; - wire int_3_91; - wire int_4_91; - wire int_5_91; - wire int_6_91; - wire int_7_91; - wire int_8_91; - wire int_9_91; - wire int_10_91; - wire int_11_91; - wire int_12_91; - wire int_13_91; - wire int_14_91; - wire int_15_91; - wire int_16_91; - wire int_17_91; - wire int_18_91; - wire int_19_91; - wire int_20_91; - wire int_21_91; - wire int_22_91; - wire int_23_91; - wire int_24_91; - wire int_25_91; - wire int_26_91; - wire int_27_91; - wire int_28_91; - wire int_29_91; - wire int_30_91; - wire int_31_91; - wire int_32_91; - wire int_33_91; - wire int_34_91; - wire int_35_91; - wire int_36_91; - wire int_37_91; - wire int_0_92; - wire int_1_92; - wire int_2_92; - wire int_3_92; - wire int_4_92; - wire int_5_92; - wire int_6_92; - wire int_7_92; - wire int_8_92; - wire int_9_92; - wire int_10_92; - wire int_11_92; - wire int_12_92; - wire int_13_92; - wire int_14_92; - wire int_15_92; - wire int_16_92; - wire int_17_92; - wire int_18_92; - wire int_19_92; - wire int_20_92; - wire int_21_92; - wire int_22_92; - wire int_23_92; - wire int_24_92; - wire int_25_92; - wire int_26_92; - wire int_27_92; - wire int_28_92; - wire int_29_92; - wire int_30_92; - wire int_31_92; - wire int_32_92; - wire int_33_92; - wire int_34_92; - wire int_35_92; - wire int_36_92; - wire int_37_92; - wire int_0_93; - wire int_1_93; - wire int_2_93; - wire int_3_93; - wire int_4_93; - wire int_5_93; - wire int_6_93; - wire int_7_93; - wire int_8_93; - wire int_9_93; - wire int_10_93; - wire int_11_93; - wire int_12_93; - wire int_13_93; - wire int_14_93; - wire int_15_93; - wire int_16_93; - wire int_17_93; - wire int_18_93; - wire int_19_93; - wire int_20_93; - wire int_21_93; - wire int_22_93; - wire int_23_93; - wire int_24_93; - wire int_25_93; - wire int_26_93; - wire int_27_93; - wire int_28_93; - wire int_29_93; - wire int_30_93; - wire int_31_93; - wire int_32_93; - wire int_33_93; - wire int_34_93; - wire int_35_93; - wire int_0_94; - wire int_1_94; - wire int_2_94; - wire int_3_94; - wire int_4_94; - wire int_5_94; - wire int_6_94; - wire int_7_94; - wire int_8_94; - wire int_9_94; - wire int_10_94; - wire int_11_94; - wire int_12_94; - wire int_13_94; - wire int_14_94; - wire int_15_94; - wire int_16_94; - wire int_17_94; - wire int_18_94; - wire int_19_94; - wire int_20_94; - wire int_21_94; - wire int_22_94; - wire int_23_94; - wire int_24_94; - wire int_25_94; - wire int_26_94; - wire int_27_94; - wire int_28_94; - wire int_29_94; - wire int_30_94; - wire int_31_94; - wire int_32_94; - wire int_33_94; - wire int_34_94; - wire int_35_94; - wire int_0_95; - wire int_1_95; - wire int_2_95; - wire int_3_95; - wire int_4_95; - wire int_5_95; - wire int_6_95; - wire int_7_95; - wire int_8_95; - wire int_9_95; - wire int_10_95; - wire int_11_95; - wire int_12_95; - wire int_13_95; - wire int_14_95; - wire int_15_95; - wire int_16_95; - wire int_17_95; - wire int_18_95; - wire int_19_95; - wire int_20_95; - wire int_21_95; - wire int_22_95; - wire int_23_95; - wire int_24_95; - wire int_25_95; - wire int_26_95; - wire int_27_95; - wire int_28_95; - wire int_29_95; - wire int_30_95; - wire int_31_95; - wire int_32_95; - wire int_33_95; - wire int_0_96; - wire int_1_96; - wire int_2_96; - wire int_3_96; - wire int_4_96; - wire int_5_96; - wire int_6_96; - wire int_7_96; - wire int_8_96; - wire int_9_96; - wire int_10_96; - wire int_11_96; - wire int_12_96; - wire int_13_96; - wire int_14_96; - wire int_15_96; - wire int_16_96; - wire int_17_96; - wire int_18_96; - wire int_19_96; - wire int_20_96; - wire int_21_96; - wire int_22_96; - wire int_23_96; - wire int_24_96; - wire int_25_96; - wire int_26_96; - wire int_27_96; - wire int_28_96; - wire int_29_96; - wire int_30_96; - wire int_31_96; - wire int_32_96; - wire int_33_96; - wire int_0_97; - wire int_1_97; - wire int_2_97; - wire int_3_97; - wire int_4_97; - wire int_5_97; - wire int_6_97; - wire int_7_97; - wire int_8_97; - wire int_9_97; - wire int_10_97; - wire int_11_97; - wire int_12_97; - wire int_13_97; - wire int_14_97; - wire int_15_97; - wire int_16_97; - wire int_17_97; - wire int_18_97; - wire int_19_97; - wire int_20_97; - wire int_21_97; - wire int_22_97; - wire int_23_97; - wire int_24_97; - wire int_25_97; - wire int_26_97; - wire int_27_97; - wire int_28_97; - wire int_29_97; - wire int_30_97; - wire int_31_97; - wire int_0_98; - wire int_1_98; - wire int_2_98; - wire int_3_98; - wire int_4_98; - wire int_5_98; - wire int_6_98; - wire int_7_98; - wire int_8_98; - wire int_9_98; - wire int_10_98; - wire int_11_98; - wire int_12_98; - wire int_13_98; - wire int_14_98; - wire int_15_98; - wire int_16_98; - wire int_17_98; - wire int_18_98; - wire int_19_98; - wire int_20_98; - wire int_21_98; - wire int_22_98; - wire int_23_98; - wire int_24_98; - wire int_25_98; - wire int_26_98; - wire int_27_98; - wire int_28_98; - wire int_29_98; - wire int_30_98; - wire int_31_98; - wire int_0_99; - wire int_1_99; - wire int_2_99; - wire int_3_99; - wire int_4_99; - wire int_5_99; - wire int_6_99; - wire int_7_99; - wire int_8_99; - wire int_9_99; - wire int_10_99; - wire int_11_99; - wire int_12_99; - wire int_13_99; - wire int_14_99; - wire int_15_99; - wire int_16_99; - wire int_17_99; - wire int_18_99; - wire int_19_99; - wire int_20_99; - wire int_21_99; - wire int_22_99; - wire int_23_99; - wire int_24_99; - wire int_25_99; - wire int_26_99; - wire int_27_99; - wire int_28_99; - wire int_29_99; - wire int_0_100; - wire int_1_100; - wire int_2_100; - wire int_3_100; - wire int_4_100; - wire int_5_100; - wire int_6_100; - wire int_7_100; - wire int_8_100; - wire int_9_100; - wire int_10_100; - wire int_11_100; - wire int_12_100; - wire int_13_100; - wire int_14_100; - wire int_15_100; - wire int_16_100; - wire int_17_100; - wire int_18_100; - wire int_19_100; - wire int_20_100; - wire int_21_100; - wire int_22_100; - wire int_23_100; - wire int_24_100; - wire int_25_100; - wire int_26_100; - wire int_27_100; - wire int_28_100; - wire int_29_100; - wire int_0_101; - wire int_1_101; - wire int_2_101; - wire int_3_101; - wire int_4_101; - wire int_5_101; - wire int_6_101; - wire int_7_101; - wire int_8_101; - wire int_9_101; - wire int_10_101; - wire int_11_101; - wire int_12_101; - wire int_13_101; - wire int_14_101; - wire int_15_101; - wire int_16_101; - wire int_17_101; - wire int_18_101; - wire int_19_101; - wire int_20_101; - wire int_21_101; - wire int_22_101; - wire int_23_101; - wire int_24_101; - wire int_25_101; - wire int_26_101; - wire int_27_101; - wire int_0_102; - wire int_1_102; - wire int_2_102; - wire int_3_102; - wire int_4_102; - wire int_5_102; - wire int_6_102; - wire int_7_102; - wire int_8_102; - wire int_9_102; - wire int_10_102; - wire int_11_102; - wire int_12_102; - wire int_13_102; - wire int_14_102; - wire int_15_102; - wire int_16_102; - wire int_17_102; - wire int_18_102; - wire int_19_102; - wire int_20_102; - wire int_21_102; - wire int_22_102; - wire int_23_102; - wire int_24_102; - wire int_25_102; - wire int_26_102; - wire int_27_102; - wire int_0_103; - wire int_1_103; - wire int_2_103; - wire int_3_103; - wire int_4_103; - wire int_5_103; - wire int_6_103; - wire int_7_103; - wire int_8_103; - wire int_9_103; - wire int_10_103; - wire int_11_103; - wire int_12_103; - wire int_13_103; - wire int_14_103; - wire int_15_103; - wire int_16_103; - wire int_17_103; - wire int_18_103; - wire int_19_103; - wire int_20_103; - wire int_21_103; - wire int_22_103; - wire int_23_103; - wire int_24_103; - wire int_25_103; - wire int_0_104; - wire int_1_104; - wire int_2_104; - wire int_3_104; - wire int_4_104; - wire int_5_104; - wire int_6_104; - wire int_7_104; - wire int_8_104; - wire int_9_104; - wire int_10_104; - wire int_11_104; - wire int_12_104; - wire int_13_104; - wire int_14_104; - wire int_15_104; - wire int_16_104; - wire int_17_104; - wire int_18_104; - wire int_19_104; - wire int_20_104; - wire int_21_104; - wire int_22_104; - wire int_23_104; - wire int_24_104; - wire int_25_104; - wire int_0_105; - wire int_1_105; - wire int_2_105; - wire int_3_105; - wire int_4_105; - wire int_5_105; - wire int_6_105; - wire int_7_105; - wire int_8_105; - wire int_9_105; - wire int_10_105; - wire int_11_105; - wire int_12_105; - wire int_13_105; - wire int_14_105; - wire int_15_105; - wire int_16_105; - wire int_17_105; - wire int_18_105; - wire int_19_105; - wire int_20_105; - wire int_21_105; - wire int_22_105; - wire int_23_105; - wire int_0_106; - wire int_1_106; - wire int_2_106; - wire int_3_106; - wire int_4_106; - wire int_5_106; - wire int_6_106; - wire int_7_106; - wire int_8_106; - wire int_9_106; - wire int_10_106; - wire int_11_106; - wire int_12_106; - wire int_13_106; - wire int_14_106; - wire int_15_106; - wire int_16_106; - wire int_17_106; - wire int_18_106; - wire int_19_106; - wire int_20_106; - wire int_21_106; - wire int_22_106; - wire int_23_106; - wire int_0_107; - wire int_1_107; - wire int_2_107; - wire int_3_107; - wire int_4_107; - wire int_5_107; - wire int_6_107; - wire int_7_107; - wire int_8_107; - wire int_9_107; - wire int_10_107; - wire int_11_107; - wire int_12_107; - wire int_13_107; - wire int_14_107; - wire int_15_107; - wire int_16_107; - wire int_17_107; - wire int_18_107; - wire int_19_107; - wire int_20_107; - wire int_21_107; - wire int_0_108; - wire int_1_108; - wire int_2_108; - wire int_3_108; - wire int_4_108; - wire int_5_108; - wire int_6_108; - wire int_7_108; - wire int_8_108; - wire int_9_108; - wire int_10_108; - wire int_11_108; - wire int_12_108; - wire int_13_108; - wire int_14_108; - wire int_15_108; - wire int_16_108; - wire int_17_108; - wire int_18_108; - wire int_19_108; - wire int_20_108; - wire int_21_108; - wire int_0_109; - wire int_1_109; - wire int_2_109; - wire int_3_109; - wire int_4_109; - wire int_5_109; - wire int_6_109; - wire int_7_109; - wire int_8_109; - wire int_9_109; - wire int_10_109; - wire int_11_109; - wire int_12_109; - wire int_13_109; - wire int_14_109; - wire int_15_109; - wire int_16_109; - wire int_17_109; - wire int_18_109; - wire int_19_109; - wire int_0_110; - wire int_1_110; - wire int_2_110; - wire int_3_110; - wire int_4_110; - wire int_5_110; - wire int_6_110; - wire int_7_110; - wire int_8_110; - wire int_9_110; - wire int_10_110; - wire int_11_110; - wire int_12_110; - wire int_13_110; - wire int_14_110; - wire int_15_110; - wire int_16_110; - wire int_17_110; - wire int_18_110; - wire int_19_110; - wire int_0_111; - wire int_1_111; - wire int_2_111; - wire int_3_111; - wire int_4_111; - wire int_5_111; - wire int_6_111; - wire int_7_111; - wire int_8_111; - wire int_9_111; - wire int_10_111; - wire int_11_111; - wire int_12_111; - wire int_13_111; - wire int_14_111; - wire int_15_111; - wire int_16_111; - wire int_17_111; - wire int_0_112; - wire int_1_112; - wire int_2_112; - wire int_3_112; - wire int_4_112; - wire int_5_112; - wire int_6_112; - wire int_7_112; - wire int_8_112; - wire int_9_112; - wire int_10_112; - wire int_11_112; - wire int_12_112; - wire int_13_112; - wire int_14_112; - wire int_15_112; - wire int_16_112; - wire int_17_112; - wire int_0_113; - wire int_1_113; - wire int_2_113; - wire int_3_113; - wire int_4_113; - wire int_5_113; - wire int_6_113; - wire int_7_113; - wire int_8_113; - wire int_9_113; - wire int_10_113; - wire int_11_113; - wire int_12_113; - wire int_13_113; - wire int_14_113; - wire int_15_113; - wire int_0_114; - wire int_1_114; - wire int_2_114; - wire int_3_114; - wire int_4_114; - wire int_5_114; - wire int_6_114; - wire int_7_114; - wire int_8_114; - wire int_9_114; - wire int_10_114; - wire int_11_114; - wire int_12_114; - wire int_13_114; - wire int_14_114; - wire int_15_114; - wire int_0_115; - wire int_1_115; - wire int_2_115; - wire int_3_115; - wire int_4_115; - wire int_5_115; - wire int_6_115; - wire int_7_115; - wire int_8_115; - wire int_9_115; - wire int_10_115; - wire int_11_115; - wire int_12_115; - wire int_13_115; - wire int_0_116; - wire int_1_116; - wire int_2_116; - wire int_3_116; - wire int_4_116; - wire int_5_116; - wire int_6_116; - wire int_7_116; - wire int_8_116; - wire int_9_116; - wire int_10_116; - wire int_11_116; - wire int_12_116; - wire int_13_116; - wire int_0_117; - wire int_1_117; - wire int_2_117; - wire int_3_117; - wire int_4_117; - wire int_5_117; - wire int_6_117; - wire int_7_117; - wire int_8_117; - wire int_9_117; - wire int_10_117; - wire int_11_117; - wire int_0_118; - wire int_1_118; - wire int_2_118; - wire int_3_118; - wire int_4_118; - wire int_5_118; - wire int_6_118; - wire int_7_118; - wire int_8_118; - wire int_9_118; - wire int_10_118; - wire int_11_118; - wire int_0_119; - wire int_1_119; - wire int_2_119; - wire int_3_119; - wire int_4_119; - wire int_5_119; - wire int_6_119; - wire int_7_119; - wire int_8_119; - wire int_9_119; - wire int_0_120; - wire int_1_120; - wire int_2_120; - wire int_3_120; - wire int_4_120; - wire int_5_120; - wire int_6_120; - wire int_7_120; - wire int_8_120; - wire int_9_120; - wire int_0_121; - wire int_1_121; - wire int_2_121; - wire int_3_121; - wire int_4_121; - wire int_5_121; - wire int_6_121; - wire int_7_121; - wire int_0_122; - wire int_1_122; - wire int_2_122; - wire int_3_122; - wire int_4_122; - wire int_5_122; - wire int_6_122; - wire int_7_122; - wire int_0_123; - wire int_1_123; - wire int_2_123; - wire int_3_123; - wire int_4_123; - wire int_5_123; - wire int_0_124; - wire int_1_124; - wire int_2_124; - wire int_3_124; - wire int_4_124; - wire int_5_124; - wire int_0_125; - wire int_1_125; - wire int_2_125; - wire int_3_125; - wire int_0_126; - wire int_1_126; - wire int_2_126; - wire int_3_126; - wire int_0_127; - wire int_1_127; - - // Below are the intermediate nets for the final adders - wire final_0; - wire final_1; - wire final_2; - wire final_3; - wire final_4; - wire final_5; - wire final_6; - wire final_7; - wire final_8; - wire final_9; - wire final_10; - wire final_11; - wire final_12; - wire final_13; - wire final_14; - wire final_15; - wire final_16; - wire final_17; - wire final_18; - wire final_19; - wire final_20; - wire final_21; - wire final_22; - wire final_23; - wire final_24; - wire final_25; - wire final_26; - wire final_27; - wire final_28; - wire final_29; - wire final_30; - wire final_31; - wire final_32; - wire final_33; - wire final_34; - wire final_35; - wire final_36; - wire final_37; - wire final_38; - wire final_39; - wire final_40; - wire final_41; - wire final_42; - wire final_43; - wire final_44; - wire final_45; - wire final_46; - wire final_47; - wire final_48; - wire final_49; - wire final_50; - wire final_51; - wire final_52; - wire final_53; - wire final_54; - wire final_55; - wire final_56; - wire final_57; - wire final_58; - wire final_59; - wire final_60; - wire final_61; - wire final_62; - wire final_63; - wire final_64; - wire final_65; - wire final_66; - wire final_67; - wire final_68; - wire final_69; - wire final_70; - wire final_71; - wire final_72; - wire final_73; - wire final_74; - wire final_75; - wire final_76; - wire final_77; - wire final_78; - wire final_79; - wire final_80; - wire final_81; - wire final_82; - wire final_83; - wire final_84; - wire final_85; - wire final_86; - wire final_87; - wire final_88; - wire final_89; - wire final_90; - wire final_91; - wire final_92; - wire final_93; - wire final_94; - wire final_95; - wire final_96; - wire final_97; - wire final_98; - wire final_99; - wire final_100; - wire final_101; - wire final_102; - wire final_103; - wire final_104; - wire final_105; - wire final_106; - wire final_107; - wire final_108; - wire final_109; - wire final_110; - wire final_111; - wire final_112; - wire final_113; - wire final_114; - wire final_115; - wire final_116; - wire final_117; - wire final_118; - wire final_119; - wire final_120; - wire final_121; - wire final_122; - wire final_123; - wire final_124; - wire final_125; - wire final_126; - - // Below are the gates for the TDM trees. - - // Hardware for column 0 - - r4bs r4bs_0_64(gnd, yy[0], single[0], double[0], neg[0], pp_0_0); - assign Sum[0] = neg[0]; - assign Carry[0] = pp_0_0; - - // Hardware for column 1 - - r4bs r4bs_80_64(yy[0], yy[1], single[0], double[0], neg[0], pp_0_1); - assign Sum[1] = pp_0_1; - assign Carry[1] = gnd; - - // Hardware for column 2 - - r4bs r4bs_160_64(yy[1], yy[2], single[0], double[0], neg[0], pp_0_2); - halfAdd HA_160_192(int_1_2, int_0_2, neg[1], pp_0_2); - r4bs r4bs_160_272(gnd, yy[0], single[1], double[1], neg[1], pp_1_2); - assign Sum[2] = pp_1_2; - assign Carry[2] = int_0_2; - - // Hardware for column 3 - - r4bs r4bs_240_64(yy[2], yy[3], single[0], double[0], neg[0], pp_0_3); - r4bs r4bs_240_192(yy[0], yy[1], single[1], double[1], neg[1], pp_1_3); - halfAdd HA_240_320(int_1_3, int_0_3, pp_0_3, pp_1_3); - assign Sum[3] = int_1_2; - assign Carry[3] = int_0_3; - - // Hardware for column 4 - - r4bs r4bs_320_64(yy[3], yy[4], single[0], double[0], neg[0], pp_0_4); - halfAdd HA_320_192(int_1_4, int_0_4, neg[2], pp_0_4); - r4bs r4bs_320_272(yy[1], yy[2], single[1], double[1], neg[1], pp_1_4); - r4bs r4bs_320_400(gnd, yy[0], single[2], double[2], neg[2], pp_2_4); - fullAdd_x FA_320_528(int_3_4, int_2_4, pp_1_4, pp_2_4, int_1_3); - assign Sum[4] = int_0_4; - assign Carry[4] = int_2_4; - - // Hardware for column 5 - - r4bs r4bs_400_64(yy[4], yy[5], single[0], double[0], neg[0], pp_0_5); - r4bs r4bs_400_192(yy[2], yy[3], single[1], double[1], neg[1], pp_1_5); - halfAdd HA_400_320(int_1_5, int_0_5, pp_0_5, pp_1_5); - r4bs r4bs_400_400(yy[0], yy[1], single[2], double[2], neg[2], pp_2_5); - fullAdd_x FA_400_528(int_3_5, int_2_5, pp_2_5, int_1_4, int_0_5); - assign Sum[5] = int_3_4; - assign Carry[5] = int_2_5; - - // Hardware for column 6 - - r4bs r4bs_480_64(yy[5], yy[6], single[0], double[0], neg[0], pp_0_6); - halfAdd HA_480_192(int_1_6, int_0_6, neg[3], pp_0_6); - r4bs r4bs_480_272(yy[3], yy[4], single[1], double[1], neg[1], pp_1_6); - r4bs r4bs_480_400(yy[1], yy[2], single[2], double[2], neg[2], pp_2_6); - r4bs r4bs_480_528(gnd, yy[0], single[3], double[3], neg[3], pp_3_6); - fullAdd_x FA_480_656(int_3_6, int_2_6, pp_1_6, pp_2_6, pp_3_6); - fullAdd_x FA_480_872(int_5_6, int_4_6, int_1_5, int_0_6, int_3_5); - assign Sum[6] = int_2_6; - assign Carry[6] = int_4_6; - - // Hardware for column 7 - - r4bs r4bs_560_64(yy[6], yy[7], single[0], double[0], neg[0], pp_0_7); - r4bs r4bs_560_192(yy[4], yy[5], single[1], double[1], neg[1], pp_1_7); - halfAdd HA_560_320(int_1_7, int_0_7, pp_0_7, pp_1_7); - r4bs r4bs_560_400(yy[2], yy[3], single[2], double[2], neg[2], pp_2_7); - r4bs r4bs_560_528(yy[0], yy[1], single[3], double[3], neg[3], pp_3_7); - fullAdd_x FA_560_656(int_3_7, int_2_7, pp_2_7, pp_3_7, int_1_6); - fullAdd_x FA_560_872(int_5_7, int_4_7, int_3_6, int_0_7, int_2_7); - assign Sum[7] = int_5_6; - assign Carry[7] = int_4_7; - - // Hardware for column 8 - - r4bs r4bs_640_64(yy[7], yy[8], single[0], double[0], neg[0], pp_0_8); - halfAdd HA_640_192(int_1_8, int_0_8, neg[4], pp_0_8); - r4bs r4bs_640_272(yy[5], yy[6], single[1], double[1], neg[1], pp_1_8); - r4bs r4bs_640_400(yy[3], yy[4], single[2], double[2], neg[2], pp_2_8); - r4bs r4bs_640_528(yy[1], yy[2], single[3], double[3], neg[3], pp_3_8); - fullAdd_x FA_640_656(int_3_8, int_2_8, pp_1_8, pp_2_8, pp_3_8); - r4bs r4bs_640_872(gnd, yy[0], single[4], double[4], neg[4], pp_4_8); - fullAdd_x FA_640_1000(int_5_8, int_4_8, pp_4_8, int_1_7, int_0_8); - fullAdd_x FA_640_1216(int_7_8, int_6_8, int_3_7, int_2_8, int_4_8); - assign Sum[8] = int_5_7; - assign Carry[8] = int_6_8; - - // Hardware for column 9 - - r4bs r4bs_720_64(yy[8], yy[9], single[0], double[0], neg[0], pp_0_9); - r4bs r4bs_720_192(yy[6], yy[7], single[1], double[1], neg[1], pp_1_9); - halfAdd HA_720_320(int_1_9, int_0_9, pp_0_9, pp_1_9); - r4bs r4bs_720_400(yy[4], yy[5], single[2], double[2], neg[2], pp_2_9); - r4bs r4bs_720_528(yy[2], yy[3], single[3], double[3], neg[3], pp_3_9); - r4bs r4bs_720_656(yy[0], yy[1], single[4], double[4], neg[4], pp_4_9); - fullAdd_x FA_720_784(int_3_9, int_2_9, pp_2_9, pp_3_9, pp_4_9); - fullAdd_x FA_720_1000(int_5_9, int_4_9, int_1_8, int_3_8, int_0_9); - fullAdd_x FA_720_1216(int_7_9, int_6_9, int_5_8, int_2_9, int_4_9); - assign Sum[9] = int_7_8; - assign Carry[9] = int_6_9; - - // Hardware for column 10 - - r4bs r4bs_800_64(yy[9], yy[10], single[0], double[0], neg[0], pp_0_10); - halfAdd HA_800_192(int_1_10, int_0_10, neg[5], pp_0_10); - r4bs r4bs_800_272(yy[7], yy[8], single[1], double[1], neg[1], pp_1_10); - r4bs r4bs_800_400(yy[5], yy[6], single[2], double[2], neg[2], pp_2_10); - r4bs r4bs_800_528(yy[3], yy[4], single[3], double[3], neg[3], pp_3_10); - fullAdd_x FA_800_656(int_3_10, int_2_10, pp_1_10, pp_2_10, pp_3_10); - r4bs r4bs_800_872(yy[1], yy[2], single[4], double[4], neg[4], pp_4_10); - r4bs r4bs_800_1000(gnd, yy[0], single[5], double[5], neg[5], pp_5_10); - fullAdd_x FA_800_1128(int_5_10, int_4_10, pp_4_10, pp_5_10, int_1_9); - fullAdd_x FA_800_1344(int_7_10, int_6_10, int_3_9, int_0_10, int_5_9); - fullAdd_x FA_800_1560(int_9_10, int_8_10, int_2_10, int_4_10, int_6_10); - assign Sum[10] = int_7_9; - assign Carry[10] = int_8_10; - - // Hardware for column 11 - - r4bs r4bs_880_64(yy[10], yy[11], single[0], double[0], neg[0], pp_0_11); - r4bs r4bs_880_192(yy[8], yy[9], single[1], double[1], neg[1], pp_1_11); - halfAdd HA_880_320(int_1_11, int_0_11, pp_0_11, pp_1_11); - r4bs r4bs_880_400(yy[6], yy[7], single[2], double[2], neg[2], pp_2_11); - r4bs r4bs_880_528(yy[4], yy[5], single[3], double[3], neg[3], pp_3_11); - r4bs r4bs_880_656(yy[2], yy[3], single[4], double[4], neg[4], pp_4_11); - fullAdd_x FA_880_784(int_3_11, int_2_11, pp_2_11, pp_3_11, pp_4_11); - r4bs r4bs_880_1000(yy[0], yy[1], single[5], double[5], neg[5], pp_5_11); - fullAdd_x FA_880_1128(int_5_11, int_4_11, pp_5_11, int_1_10, int_3_10); - fullAdd_x FA_880_1344(int_7_11, int_6_11, int_0_11, int_5_10, int_2_11); - fullAdd_x FA_880_1560(int_9_11, int_8_11, int_4_11, int_7_10, int_6_11); - assign Sum[11] = int_9_10; - assign Carry[11] = int_8_11; - - // Hardware for column 12 - - r4bs r4bs_960_64(yy[11], yy[12], single[0], double[0], neg[0], pp_0_12); - halfAdd HA_960_192(int_1_12, int_0_12, neg[6], pp_0_12); - r4bs r4bs_960_272(yy[9], yy[10], single[1], double[1], neg[1], pp_1_12); - r4bs r4bs_960_400(yy[7], yy[8], single[2], double[2], neg[2], pp_2_12); - r4bs r4bs_960_528(yy[5], yy[6], single[3], double[3], neg[3], pp_3_12); - fullAdd_x FA_960_656(int_3_12, int_2_12, pp_1_12, pp_2_12, pp_3_12); - r4bs r4bs_960_872(yy[3], yy[4], single[4], double[4], neg[4], pp_4_12); - r4bs r4bs_960_1000(yy[1], yy[2], single[5], double[5], neg[5], pp_5_12); - r4bs r4bs_960_1128(gnd, yy[0], single[6], double[6], neg[6], pp_6_12); - fullAdd_x FA_960_1256(int_5_12, int_4_12, pp_4_12, pp_5_12, pp_6_12); - fullAdd_x FA_960_1472(int_7_12, int_6_12, int_1_11, int_3_11, int_0_12); - fullAdd_x FA_960_1688(int_9_12, int_8_12, int_5_11, int_2_12, int_4_12); - fullAdd_x FA_960_1904(int_11_12, int_10_12, int_7_11, int_6_12, int_8_12); - assign Sum[12] = int_9_11; - assign Carry[12] = int_10_12; - - // Hardware for column 13 - - r4bs r4bs_1040_64(yy[12], yy[13], single[0], double[0], neg[0], pp_0_13); - r4bs r4bs_1040_192(yy[10], yy[11], single[1], double[1], neg[1], pp_1_13); - halfAdd HA_1040_320(int_1_13, int_0_13, pp_0_13, pp_1_13); - r4bs r4bs_1040_400(yy[8], yy[9], single[2], double[2], neg[2], pp_2_13); - r4bs r4bs_1040_528(yy[6], yy[7], single[3], double[3], neg[3], pp_3_13); - r4bs r4bs_1040_656(yy[4], yy[5], single[4], double[4], neg[4], pp_4_13); - fullAdd_x FA_1040_784(int_3_13, int_2_13, pp_2_13, pp_3_13, pp_4_13); - r4bs r4bs_1040_1000(yy[2], yy[3], single[5], double[5], neg[5], pp_5_13); - r4bs r4bs_1040_1128(yy[0], yy[1], single[6], double[6], neg[6], pp_6_13); - fullAdd_x FA_1040_1256(int_5_13, int_4_13, pp_5_13, pp_6_13, int_1_12); - fullAdd_x FA_1040_1472(int_7_13, int_6_13, int_3_12, int_5_12, int_0_13); - fullAdd_x FA_1040_1688(int_9_13, int_8_13, int_7_12, int_2_13, int_4_13); - fullAdd_x FA_1040_1904(int_11_13, int_10_13, int_9_12, int_6_13, int_8_13); - assign Sum[13] = int_11_12; - assign Carry[13] = int_10_13; - - // Hardware for column 14 - - r4bs r4bs_1120_64(yy[13], yy[14], single[0], double[0], neg[0], pp_0_14); - halfAdd HA_1120_192(int_1_14, int_0_14, neg[7], pp_0_14); - r4bs r4bs_1120_272(yy[11], yy[12], single[1], double[1], neg[1], pp_1_14); - r4bs r4bs_1120_400(yy[9], yy[10], single[2], double[2], neg[2], pp_2_14); - r4bs r4bs_1120_528(yy[7], yy[8], single[3], double[3], neg[3], pp_3_14); - fullAdd_x FA_1120_656(int_3_14, int_2_14, pp_1_14, pp_2_14, pp_3_14); - r4bs r4bs_1120_872(yy[5], yy[6], single[4], double[4], neg[4], pp_4_14); - r4bs r4bs_1120_1000(yy[3], yy[4], single[5], double[5], neg[5], pp_5_14); - r4bs r4bs_1120_1128(yy[1], yy[2], single[6], double[6], neg[6], pp_6_14); - fullAdd_x FA_1120_1256(int_5_14, int_4_14, pp_4_14, pp_5_14, pp_6_14); - r4bs r4bs_1120_1472(gnd, yy[0], single[7], double[7], neg[7], pp_7_14); - fullAdd_x FA_1120_1600(int_7_14, int_6_14, pp_7_14, int_1_13, int_3_13); - fullAdd_x FA_1120_1816(int_9_14, int_8_14, int_0_14, int_5_13, int_7_13); - fullAdd_x FA_1120_2032(int_11_14, int_10_14, int_2_14, int_4_14, int_6_14); - fullAdd_x FA_1120_2248(int_13_14, int_12_14, int_9_13, int_8_14, int_10_14); - assign Sum[14] = int_11_13; - assign Carry[14] = int_12_14; - - // Hardware for column 15 - - r4bs r4bs_1200_64(yy[14], yy[15], single[0], double[0], neg[0], pp_0_15); - r4bs r4bs_1200_192(yy[12], yy[13], single[1], double[1], neg[1], pp_1_15); - halfAdd HA_1200_320(int_1_15, int_0_15, pp_0_15, pp_1_15); - r4bs r4bs_1200_400(yy[10], yy[11], single[2], double[2], neg[2], pp_2_15); - r4bs r4bs_1200_528(yy[8], yy[9], single[3], double[3], neg[3], pp_3_15); - r4bs r4bs_1200_656(yy[6], yy[7], single[4], double[4], neg[4], pp_4_15); - fullAdd_x FA_1200_784(int_3_15, int_2_15, pp_2_15, pp_3_15, pp_4_15); - r4bs r4bs_1200_1000(yy[4], yy[5], single[5], double[5], neg[5], pp_5_15); - r4bs r4bs_1200_1128(yy[2], yy[3], single[6], double[6], neg[6], pp_6_15); - r4bs r4bs_1200_1256(yy[0], yy[1], single[7], double[7], neg[7], pp_7_15); - fullAdd_x FA_1200_1384(int_5_15, int_4_15, pp_5_15, pp_6_15, pp_7_15); - fullAdd_x FA_1200_1600(int_7_15, int_6_15, int_1_14, int_3_14, int_5_14); - fullAdd_x FA_1200_1816(int_9_15, int_8_15, int_0_15, int_7_14, int_2_15); - fullAdd_x FA_1200_2032(int_11_15, int_10_15, int_4_15, int_9_14, int_6_15); - fullAdd_x FA_1200_2248(int_13_15, int_12_15, int_11_14, int_8_15, int_13_14); - assign Sum[15] = int_10_15; - assign Carry[15] = int_12_15; - - // Hardware for column 16 - - r4bs r4bs_1280_64(yy[15], yy[16], single[0], double[0], neg[0], pp_0_16); - halfAdd HA_1280_192(int_1_16, int_0_16, neg[8], pp_0_16); - r4bs r4bs_1280_272(yy[13], yy[14], single[1], double[1], neg[1], pp_1_16); - r4bs r4bs_1280_400(yy[11], yy[12], single[2], double[2], neg[2], pp_2_16); - r4bs r4bs_1280_528(yy[9], yy[10], single[3], double[3], neg[3], pp_3_16); - fullAdd_x FA_1280_656(int_3_16, int_2_16, pp_1_16, pp_2_16, pp_3_16); - r4bs r4bs_1280_872(yy[7], yy[8], single[4], double[4], neg[4], pp_4_16); - r4bs r4bs_1280_1000(yy[5], yy[6], single[5], double[5], neg[5], pp_5_16); - r4bs r4bs_1280_1128(yy[3], yy[4], single[6], double[6], neg[6], pp_6_16); - fullAdd_x FA_1280_1256(int_5_16, int_4_16, pp_4_16, pp_5_16, pp_6_16); - r4bs r4bs_1280_1472(yy[1], yy[2], single[7], double[7], neg[7], pp_7_16); - r4bs r4bs_1280_1600(gnd, yy[0], single[8], double[8], neg[8], pp_8_16); - fullAdd_x FA_1280_1728(int_7_16, int_6_16, pp_7_16, pp_8_16, int_1_15); - fullAdd_x FA_1280_1944(int_9_16, int_8_16, int_3_15, int_5_15, int_0_16); - fullAdd_x FA_1280_2160(int_11_16, int_10_16, int_7_15, int_2_16, int_4_16); - fullAdd_x FA_1280_2376(int_13_16, int_12_16, int_6_16, int_9_15, int_8_16); - fullAdd_x FA_1280_2592(int_15_16, int_14_16, int_11_15, int_10_16, int_12_16); - assign Sum[16] = int_13_15; - assign Carry[16] = int_14_16; - - // Hardware for column 17 - - r4bs r4bs_1360_64(yy[16], yy[17], single[0], double[0], neg[0], pp_0_17); - r4bs r4bs_1360_192(yy[14], yy[15], single[1], double[1], neg[1], pp_1_17); - halfAdd HA_1360_320(int_1_17, int_0_17, pp_0_17, pp_1_17); - r4bs r4bs_1360_400(yy[12], yy[13], single[2], double[2], neg[2], pp_2_17); - r4bs r4bs_1360_528(yy[10], yy[11], single[3], double[3], neg[3], pp_3_17); - r4bs r4bs_1360_656(yy[8], yy[9], single[4], double[4], neg[4], pp_4_17); - fullAdd_x FA_1360_784(int_3_17, int_2_17, pp_2_17, pp_3_17, pp_4_17); - r4bs r4bs_1360_1000(yy[6], yy[7], single[5], double[5], neg[5], pp_5_17); - r4bs r4bs_1360_1128(yy[4], yy[5], single[6], double[6], neg[6], pp_6_17); - r4bs r4bs_1360_1256(yy[2], yy[3], single[7], double[7], neg[7], pp_7_17); - fullAdd_x FA_1360_1384(int_5_17, int_4_17, pp_5_17, pp_6_17, pp_7_17); - r4bs r4bs_1360_1600(yy[0], yy[1], single[8], double[8], neg[8], pp_8_17); - fullAdd_x FA_1360_1728(int_7_17, int_6_17, pp_8_17, int_1_16, int_3_16); - fullAdd_x FA_1360_1944(int_9_17, int_8_17, int_5_16, int_0_17, int_7_16); - fullAdd_x FA_1360_2160(int_11_17, int_10_17, int_9_16, int_2_17, int_4_17); - fullAdd_x FA_1360_2376(int_13_17, int_12_17, int_6_17, int_11_16, int_8_17); - fullAdd_x FA_1360_2592(int_15_17, int_14_17, int_13_16, int_10_17, int_12_17); - assign Sum[17] = int_15_16; - assign Carry[17] = int_14_17; - - // Hardware for column 18 - - r4bs r4bs_1440_64(yy[17], yy[18], single[0], double[0], neg[0], pp_0_18); - halfAdd HA_1440_192(int_1_18, int_0_18, neg[9], pp_0_18); - r4bs r4bs_1440_272(yy[15], yy[16], single[1], double[1], neg[1], pp_1_18); - r4bs r4bs_1440_400(yy[13], yy[14], single[2], double[2], neg[2], pp_2_18); - r4bs r4bs_1440_528(yy[11], yy[12], single[3], double[3], neg[3], pp_3_18); - fullAdd_x FA_1440_656(int_3_18, int_2_18, pp_1_18, pp_2_18, pp_3_18); - r4bs r4bs_1440_872(yy[9], yy[10], single[4], double[4], neg[4], pp_4_18); - r4bs r4bs_1440_1000(yy[7], yy[8], single[5], double[5], neg[5], pp_5_18); - r4bs r4bs_1440_1128(yy[5], yy[6], single[6], double[6], neg[6], pp_6_18); - fullAdd_x FA_1440_1256(int_5_18, int_4_18, pp_4_18, pp_5_18, pp_6_18); - r4bs r4bs_1440_1472(yy[3], yy[4], single[7], double[7], neg[7], pp_7_18); - r4bs r4bs_1440_1600(yy[1], yy[2], single[8], double[8], neg[8], pp_8_18); - r4bs r4bs_1440_1728(gnd, yy[0], single[9], double[9], neg[9], pp_9_18); - fullAdd_x FA_1440_1856(int_7_18, int_6_18, pp_7_18, pp_8_18, pp_9_18); - fullAdd_x FA_1440_2072(int_9_18, int_8_18, int_1_17, int_3_17, int_5_17); - fullAdd_x FA_1440_2288(int_11_18, int_10_18, int_0_18, int_7_17, int_2_18); - fullAdd_x FA_1440_2504(int_13_18, int_12_18, int_4_18, int_6_18, int_9_17); - fullAdd_x FA_1440_2720(int_15_18, int_14_18, int_11_17, int_8_18, int_13_17); - fullAdd_x FA_1440_2936(int_17_18, int_16_18, int_10_18, int_12_18, int_14_18); - assign Sum[18] = int_15_17; - assign Carry[18] = int_16_18; - - // Hardware for column 19 - - r4bs r4bs_1520_64(yy[18], yy[19], single[0], double[0], neg[0], pp_0_19); - r4bs r4bs_1520_192(yy[16], yy[17], single[1], double[1], neg[1], pp_1_19); - halfAdd HA_1520_320(int_1_19, int_0_19, pp_0_19, pp_1_19); - r4bs r4bs_1520_400(yy[14], yy[15], single[2], double[2], neg[2], pp_2_19); - r4bs r4bs_1520_528(yy[12], yy[13], single[3], double[3], neg[3], pp_3_19); - r4bs r4bs_1520_656(yy[10], yy[11], single[4], double[4], neg[4], pp_4_19); - fullAdd_x FA_1520_784(int_3_19, int_2_19, pp_2_19, pp_3_19, pp_4_19); - r4bs r4bs_1520_1000(yy[8], yy[9], single[5], double[5], neg[5], pp_5_19); - r4bs r4bs_1520_1128(yy[6], yy[7], single[6], double[6], neg[6], pp_6_19); - r4bs r4bs_1520_1256(yy[4], yy[5], single[7], double[7], neg[7], pp_7_19); - fullAdd_x FA_1520_1384(int_5_19, int_4_19, pp_5_19, pp_6_19, pp_7_19); - r4bs r4bs_1520_1600(yy[2], yy[3], single[8], double[8], neg[8], pp_8_19); - r4bs r4bs_1520_1728(yy[0], yy[1], single[9], double[9], neg[9], pp_9_19); - fullAdd_x FA_1520_1856(int_7_19, int_6_19, pp_8_19, pp_9_19, int_1_18); - fullAdd_x FA_1520_2072(int_9_19, int_8_19, int_3_18, int_5_18, int_7_18); - fullAdd_x FA_1520_2288(int_11_19, int_10_19, int_0_19, int_9_18, int_2_19); - fullAdd_x FA_1520_2504(int_13_19, int_12_19, int_4_19, int_6_19, int_11_18); - fullAdd_x FA_1520_2720(int_15_19, int_14_19, int_8_19, int_13_18, int_10_19); - fullAdd_x FA_1520_2936(int_17_19, int_16_19, int_12_19, int_15_18, int_14_19); - assign Sum[19] = int_17_18; - assign Carry[19] = int_16_19; - - // Hardware for column 20 - - r4bs r4bs_1600_64(yy[19], yy[20], single[0], double[0], neg[0], pp_0_20); - halfAdd HA_1600_192(int_1_20, int_0_20, neg[10], pp_0_20); - r4bs r4bs_1600_272(yy[17], yy[18], single[1], double[1], neg[1], pp_1_20); - r4bs r4bs_1600_400(yy[15], yy[16], single[2], double[2], neg[2], pp_2_20); - r4bs r4bs_1600_528(yy[13], yy[14], single[3], double[3], neg[3], pp_3_20); - fullAdd_x FA_1600_656(int_3_20, int_2_20, pp_1_20, pp_2_20, pp_3_20); - r4bs r4bs_1600_872(yy[11], yy[12], single[4], double[4], neg[4], pp_4_20); - r4bs r4bs_1600_1000(yy[9], yy[10], single[5], double[5], neg[5], pp_5_20); - r4bs r4bs_1600_1128(yy[7], yy[8], single[6], double[6], neg[6], pp_6_20); - fullAdd_x FA_1600_1256(int_5_20, int_4_20, pp_4_20, pp_5_20, pp_6_20); - r4bs r4bs_1600_1472(yy[5], yy[6], single[7], double[7], neg[7], pp_7_20); - r4bs r4bs_1600_1600(yy[3], yy[4], single[8], double[8], neg[8], pp_8_20); - r4bs r4bs_1600_1728(yy[1], yy[2], single[9], double[9], neg[9], pp_9_20); - fullAdd_x FA_1600_1856(int_7_20, int_6_20, pp_7_20, pp_8_20, pp_9_20); - r4bs r4bs_1600_2072(gnd, yy[0], single[10], double[10], neg[10], pp_10_20); - fullAdd_x FA_1600_2200(int_9_20, int_8_20, pp_10_20, int_1_19, int_3_19); - fullAdd_x FA_1600_2416(int_11_20, int_10_20, int_5_19, int_0_20, int_7_19); - fullAdd_x FA_1600_2632(int_13_20, int_12_20, int_9_19, int_2_20, int_4_20); - fullAdd_x FA_1600_2848(int_15_20, int_14_20, int_6_20, int_8_20, int_11_19); - fullAdd_x FA_1600_3064(int_17_20, int_16_20, int_10_20, int_13_19, int_12_20); - fullAdd_x FA_1600_3280(int_19_20, int_18_20, int_14_20, int_15_19, int_16_20); - assign Sum[20] = int_17_19; - assign Carry[20] = int_18_20; - - // Hardware for column 21 - - r4bs r4bs_1680_64(yy[20], yy[21], single[0], double[0], neg[0], pp_0_21); - r4bs r4bs_1680_192(yy[18], yy[19], single[1], double[1], neg[1], pp_1_21); - halfAdd HA_1680_320(int_1_21, int_0_21, pp_0_21, pp_1_21); - r4bs r4bs_1680_400(yy[16], yy[17], single[2], double[2], neg[2], pp_2_21); - r4bs r4bs_1680_528(yy[14], yy[15], single[3], double[3], neg[3], pp_3_21); - r4bs r4bs_1680_656(yy[12], yy[13], single[4], double[4], neg[4], pp_4_21); - fullAdd_x FA_1680_784(int_3_21, int_2_21, pp_2_21, pp_3_21, pp_4_21); - r4bs r4bs_1680_1000(yy[10], yy[11], single[5], double[5], neg[5], pp_5_21); - r4bs r4bs_1680_1128(yy[8], yy[9], single[6], double[6], neg[6], pp_6_21); - r4bs r4bs_1680_1256(yy[6], yy[7], single[7], double[7], neg[7], pp_7_21); - fullAdd_x FA_1680_1384(int_5_21, int_4_21, pp_5_21, pp_6_21, pp_7_21); - r4bs r4bs_1680_1600(yy[4], yy[5], single[8], double[8], neg[8], pp_8_21); - r4bs r4bs_1680_1728(yy[2], yy[3], single[9], double[9], neg[9], pp_9_21); - r4bs r4bs_1680_1856(yy[0], yy[1], single[10], double[10], neg[10], pp_10_21); - fullAdd_x FA_1680_1984(int_7_21, int_6_21, pp_8_21, pp_9_21, pp_10_21); - fullAdd_x FA_1680_2200(int_9_21, int_8_21, int_1_20, int_3_20, int_5_20); - fullAdd_x FA_1680_2416(int_11_21, int_10_21, int_7_20, int_0_21, int_9_20); - fullAdd_x FA_1680_2632(int_13_21, int_12_21, int_2_21, int_4_21, int_6_21); - fullAdd_x FA_1680_2848(int_15_21, int_14_21, int_11_20, int_13_20, int_8_21); - fullAdd_x FA_1680_3064(int_17_21, int_16_21, int_10_21, int_15_20, int_12_21); - fullAdd_x FA_1680_3280(int_19_21, int_18_21, int_17_20, int_14_21, int_16_21); - assign Sum[21] = int_19_20; - assign Carry[21] = int_18_21; - - // Hardware for column 22 - - r4bs r4bs_1760_64(yy[21], yy[22], single[0], double[0], neg[0], pp_0_22); - halfAdd HA_1760_192(int_1_22, int_0_22, neg[11], pp_0_22); - r4bs r4bs_1760_272(yy[19], yy[20], single[1], double[1], neg[1], pp_1_22); - r4bs r4bs_1760_400(yy[17], yy[18], single[2], double[2], neg[2], pp_2_22); - r4bs r4bs_1760_528(yy[15], yy[16], single[3], double[3], neg[3], pp_3_22); - fullAdd_x FA_1760_656(int_3_22, int_2_22, pp_1_22, pp_2_22, pp_3_22); - r4bs r4bs_1760_872(yy[13], yy[14], single[4], double[4], neg[4], pp_4_22); - r4bs r4bs_1760_1000(yy[11], yy[12], single[5], double[5], neg[5], pp_5_22); - r4bs r4bs_1760_1128(yy[9], yy[10], single[6], double[6], neg[6], pp_6_22); - fullAdd_x FA_1760_1256(int_5_22, int_4_22, pp_4_22, pp_5_22, pp_6_22); - r4bs r4bs_1760_1472(yy[7], yy[8], single[7], double[7], neg[7], pp_7_22); - r4bs r4bs_1760_1600(yy[5], yy[6], single[8], double[8], neg[8], pp_8_22); - r4bs r4bs_1760_1728(yy[3], yy[4], single[9], double[9], neg[9], pp_9_22); - fullAdd_x FA_1760_1856(int_7_22, int_6_22, pp_7_22, pp_8_22, pp_9_22); - r4bs r4bs_1760_2072(yy[1], yy[2], single[10], double[10], neg[10], pp_10_22); - r4bs r4bs_1760_2200(gnd, yy[0], single[11], double[11], neg[11], pp_11_22); - fullAdd_x FA_1760_2328(int_9_22, int_8_22, pp_10_22, pp_11_22, int_1_21); - fullAdd_x FA_1760_2544(int_11_22, int_10_22, int_3_21, int_5_21, int_7_21); - fullAdd_x FA_1760_2760(int_13_22, int_12_22, int_0_22, int_9_21, int_2_22); - fullAdd_x FA_1760_2976(int_15_22, int_14_22, int_4_22, int_6_22, int_8_22); - fullAdd_x FA_1760_3192(int_17_22, int_16_22, int_11_21, int_13_21, int_10_22); - fullAdd_x FA_1760_3408(int_19_22, int_18_22, int_15_21, int_12_22, int_14_22); - fullAdd_x FA_1760_3624(int_21_22, int_20_22, int_17_21, int_16_22, int_18_22); - assign Sum[22] = int_19_21; - assign Carry[22] = int_20_22; - - // Hardware for column 23 - - r4bs r4bs_1840_64(yy[22], yy[23], single[0], double[0], neg[0], pp_0_23); - r4bs r4bs_1840_192(yy[20], yy[21], single[1], double[1], neg[1], pp_1_23); - halfAdd HA_1840_320(int_1_23, int_0_23, pp_0_23, pp_1_23); - r4bs r4bs_1840_400(yy[18], yy[19], single[2], double[2], neg[2], pp_2_23); - r4bs r4bs_1840_528(yy[16], yy[17], single[3], double[3], neg[3], pp_3_23); - r4bs r4bs_1840_656(yy[14], yy[15], single[4], double[4], neg[4], pp_4_23); - fullAdd_x FA_1840_784(int_3_23, int_2_23, pp_2_23, pp_3_23, pp_4_23); - r4bs r4bs_1840_1000(yy[12], yy[13], single[5], double[5], neg[5], pp_5_23); - r4bs r4bs_1840_1128(yy[10], yy[11], single[6], double[6], neg[6], pp_6_23); - r4bs r4bs_1840_1256(yy[8], yy[9], single[7], double[7], neg[7], pp_7_23); - fullAdd_x FA_1840_1384(int_5_23, int_4_23, pp_5_23, pp_6_23, pp_7_23); - r4bs r4bs_1840_1600(yy[6], yy[7], single[8], double[8], neg[8], pp_8_23); - r4bs r4bs_1840_1728(yy[4], yy[5], single[9], double[9], neg[9], pp_9_23); - r4bs r4bs_1840_1856(yy[2], yy[3], single[10], double[10], neg[10], pp_10_23); - fullAdd_x FA_1840_1984(int_7_23, int_6_23, pp_8_23, pp_9_23, pp_10_23); - r4bs r4bs_1840_2200(yy[0], yy[1], single[11], double[11], neg[11], pp_11_23); - fullAdd_x FA_1840_2328(int_9_23, int_8_23, pp_11_23, int_1_22, int_3_22); - fullAdd_x FA_1840_2544(int_11_23, int_10_23, int_5_22, int_7_22, int_0_23); - fullAdd_x FA_1840_2760(int_13_23, int_12_23, int_9_22, int_11_22, int_2_23); - fullAdd_x FA_1840_2976(int_15_23, int_14_23, int_4_23, int_6_23, int_8_23); - fullAdd_x FA_1840_3192(int_17_23, int_16_23, int_13_22, int_15_22, int_10_23); - fullAdd_x FA_1840_3408(int_19_23, int_18_23, int_17_22, int_12_23, int_14_23); - fullAdd_x FA_1840_3624(int_21_23, int_20_23, int_19_22, int_16_23, int_18_23); - assign Sum[23] = int_21_22; - assign Carry[23] = int_20_23; - - // Hardware for column 24 - - r4bs r4bs_1920_64(yy[23], yy[24], single[0], double[0], neg[0], pp_0_24); - halfAdd HA_1920_192(int_1_24, int_0_24, neg[12], pp_0_24); - r4bs r4bs_1920_272(yy[21], yy[22], single[1], double[1], neg[1], pp_1_24); - r4bs r4bs_1920_400(yy[19], yy[20], single[2], double[2], neg[2], pp_2_24); - r4bs r4bs_1920_528(yy[17], yy[18], single[3], double[3], neg[3], pp_3_24); - fullAdd_x FA_1920_656(int_3_24, int_2_24, pp_1_24, pp_2_24, pp_3_24); - r4bs r4bs_1920_872(yy[15], yy[16], single[4], double[4], neg[4], pp_4_24); - r4bs r4bs_1920_1000(yy[13], yy[14], single[5], double[5], neg[5], pp_5_24); - r4bs r4bs_1920_1128(yy[11], yy[12], single[6], double[6], neg[6], pp_6_24); - fullAdd_x FA_1920_1256(int_5_24, int_4_24, pp_4_24, pp_5_24, pp_6_24); - r4bs r4bs_1920_1472(yy[9], yy[10], single[7], double[7], neg[7], pp_7_24); - r4bs r4bs_1920_1600(yy[7], yy[8], single[8], double[8], neg[8], pp_8_24); - r4bs r4bs_1920_1728(yy[5], yy[6], single[9], double[9], neg[9], pp_9_24); - fullAdd_x FA_1920_1856(int_7_24, int_6_24, pp_7_24, pp_8_24, pp_9_24); - r4bs r4bs_1920_2072(yy[3], yy[4], single[10], double[10], neg[10], pp_10_24); - r4bs r4bs_1920_2200(yy[1], yy[2], single[11], double[11], neg[11], pp_11_24); - r4bs r4bs_1920_2328(gnd, yy[0], single[12], double[12], neg[12], pp_12_24); - fullAdd_x FA_1920_2456(int_9_24, int_8_24, pp_10_24, pp_11_24, pp_12_24); - fullAdd_x FA_1920_2672(int_11_24, int_10_24, int_1_23, int_3_23, int_5_23); - fullAdd_x FA_1920_2888(int_13_24, int_12_24, int_7_23, int_0_24, int_9_23); - fullAdd_x FA_1920_3104(int_15_24, int_14_24, int_11_23, int_2_24, int_4_24); - fullAdd_x FA_1920_3320(int_17_24, int_16_24, int_6_24, int_8_24, int_13_23); - fullAdd_x FA_1920_3536(int_19_24, int_18_24, int_10_24, int_12_24, int_15_23); - fullAdd_x FA_1920_3752(int_21_24, int_20_24, int_17_23, int_14_24, int_16_24); - fullAdd_x FA_1920_3968(int_23_24, int_22_24, int_19_23, int_18_24, int_20_24); - assign Sum[24] = int_21_23; - assign Carry[24] = int_22_24; - - // Hardware for column 25 - - r4bs r4bs_2000_64(yy[24], yy[25], single[0], double[0], neg[0], pp_0_25); - r4bs r4bs_2000_192(yy[22], yy[23], single[1], double[1], neg[1], pp_1_25); - halfAdd HA_2000_320(int_1_25, int_0_25, pp_0_25, pp_1_25); - r4bs r4bs_2000_400(yy[20], yy[21], single[2], double[2], neg[2], pp_2_25); - r4bs r4bs_2000_528(yy[18], yy[19], single[3], double[3], neg[3], pp_3_25); - r4bs r4bs_2000_656(yy[16], yy[17], single[4], double[4], neg[4], pp_4_25); - fullAdd_x FA_2000_784(int_3_25, int_2_25, pp_2_25, pp_3_25, pp_4_25); - r4bs r4bs_2000_1000(yy[14], yy[15], single[5], double[5], neg[5], pp_5_25); - r4bs r4bs_2000_1128(yy[12], yy[13], single[6], double[6], neg[6], pp_6_25); - r4bs r4bs_2000_1256(yy[10], yy[11], single[7], double[7], neg[7], pp_7_25); - fullAdd_x FA_2000_1384(int_5_25, int_4_25, pp_5_25, pp_6_25, pp_7_25); - r4bs r4bs_2000_1600(yy[8], yy[9], single[8], double[8], neg[8], pp_8_25); - r4bs r4bs_2000_1728(yy[6], yy[7], single[9], double[9], neg[9], pp_9_25); - r4bs r4bs_2000_1856(yy[4], yy[5], single[10], double[10], neg[10], pp_10_25); - fullAdd_x FA_2000_1984(int_7_25, int_6_25, pp_8_25, pp_9_25, pp_10_25); - r4bs r4bs_2000_2200(yy[2], yy[3], single[11], double[11], neg[11], pp_11_25); - r4bs r4bs_2000_2328(yy[0], yy[1], single[12], double[12], neg[12], pp_12_25); - fullAdd_x FA_2000_2456(int_9_25, int_8_25, pp_11_25, pp_12_25, int_1_24); - fullAdd_x FA_2000_2672(int_11_25, int_10_25, int_3_24, int_5_24, int_7_24); - fullAdd_x FA_2000_2888(int_13_25, int_12_25, int_9_24, int_0_25, int_11_24); - fullAdd_x FA_2000_3104(int_15_25, int_14_25, int_2_25, int_4_25, int_6_25); - fullAdd_x FA_2000_3320(int_17_25, int_16_25, int_8_25, int_13_24, int_15_24); - fullAdd_x FA_2000_3536(int_19_25, int_18_25, int_10_25, int_12_25, int_17_24); - fullAdd_x FA_2000_3752(int_21_25, int_20_25, int_14_25, int_19_24, int_21_24); - fullAdd_x FA_2000_3968(int_23_25, int_22_25, int_16_25, int_18_25, int_20_25); - assign Sum[25] = int_23_24; - assign Carry[25] = int_22_25; - - // Hardware for column 26 - - r4bs r4bs_2080_64(yy[25], yy[26], single[0], double[0], neg[0], pp_0_26); - halfAdd HA_2080_192(int_1_26, int_0_26, neg[13], pp_0_26); - r4bs r4bs_2080_272(yy[23], yy[24], single[1], double[1], neg[1], pp_1_26); - r4bs r4bs_2080_400(yy[21], yy[22], single[2], double[2], neg[2], pp_2_26); - r4bs r4bs_2080_528(yy[19], yy[20], single[3], double[3], neg[3], pp_3_26); - fullAdd_x FA_2080_656(int_3_26, int_2_26, pp_1_26, pp_2_26, pp_3_26); - r4bs r4bs_2080_872(yy[17], yy[18], single[4], double[4], neg[4], pp_4_26); - r4bs r4bs_2080_1000(yy[15], yy[16], single[5], double[5], neg[5], pp_5_26); - r4bs r4bs_2080_1128(yy[13], yy[14], single[6], double[6], neg[6], pp_6_26); - fullAdd_x FA_2080_1256(int_5_26, int_4_26, pp_4_26, pp_5_26, pp_6_26); - r4bs r4bs_2080_1472(yy[11], yy[12], single[7], double[7], neg[7], pp_7_26); - r4bs r4bs_2080_1600(yy[9], yy[10], single[8], double[8], neg[8], pp_8_26); - r4bs r4bs_2080_1728(yy[7], yy[8], single[9], double[9], neg[9], pp_9_26); - fullAdd_x FA_2080_1856(int_7_26, int_6_26, pp_7_26, pp_8_26, pp_9_26); - r4bs r4bs_2080_2072(yy[5], yy[6], single[10], double[10], neg[10], pp_10_26); - r4bs r4bs_2080_2200(yy[3], yy[4], single[11], double[11], neg[11], pp_11_26); - r4bs r4bs_2080_2328(yy[1], yy[2], single[12], double[12], neg[12], pp_12_26); - fullAdd_x FA_2080_2456(int_9_26, int_8_26, pp_10_26, pp_11_26, pp_12_26); - r4bs r4bs_2080_2672(gnd, yy[0], single[13], double[13], neg[13], pp_13_26); - fullAdd_x FA_2080_2800(int_11_26, int_10_26, pp_13_26, int_1_25, int_3_25); - fullAdd_x FA_2080_3016(int_13_26, int_12_26, int_5_25, int_7_25, int_0_26); - fullAdd_x FA_2080_3232(int_15_26, int_14_26, int_9_25, int_11_25, int_2_26); - fullAdd_x FA_2080_3448(int_17_26, int_16_26, int_4_26, int_6_26, int_8_26); - fullAdd_x FA_2080_3664(int_19_26, int_18_26, int_10_26, int_13_25, int_15_25); - fullAdd_x FA_2080_3880(int_21_26, int_20_26, int_12_26, int_17_25, int_14_26); - fullAdd_x FA_2080_4096(int_23_26, int_22_26, int_16_26, int_19_25, int_18_26); - fullAdd_x FA_2080_4312(int_25_26, int_24_26, int_21_25, int_20_26, int_22_26); - assign Sum[26] = int_23_25; - assign Carry[26] = int_24_26; - - // Hardware for column 27 - - r4bs r4bs_2160_64(yy[26], yy[27], single[0], double[0], neg[0], pp_0_27); - r4bs r4bs_2160_192(yy[24], yy[25], single[1], double[1], neg[1], pp_1_27); - halfAdd HA_2160_320(int_1_27, int_0_27, pp_0_27, pp_1_27); - r4bs r4bs_2160_400(yy[22], yy[23], single[2], double[2], neg[2], pp_2_27); - r4bs r4bs_2160_528(yy[20], yy[21], single[3], double[3], neg[3], pp_3_27); - r4bs r4bs_2160_656(yy[18], yy[19], single[4], double[4], neg[4], pp_4_27); - fullAdd_x FA_2160_784(int_3_27, int_2_27, pp_2_27, pp_3_27, pp_4_27); - r4bs r4bs_2160_1000(yy[16], yy[17], single[5], double[5], neg[5], pp_5_27); - r4bs r4bs_2160_1128(yy[14], yy[15], single[6], double[6], neg[6], pp_6_27); - r4bs r4bs_2160_1256(yy[12], yy[13], single[7], double[7], neg[7], pp_7_27); - fullAdd_x FA_2160_1384(int_5_27, int_4_27, pp_5_27, pp_6_27, pp_7_27); - r4bs r4bs_2160_1600(yy[10], yy[11], single[8], double[8], neg[8], pp_8_27); - r4bs r4bs_2160_1728(yy[8], yy[9], single[9], double[9], neg[9], pp_9_27); - r4bs r4bs_2160_1856(yy[6], yy[7], single[10], double[10], neg[10], pp_10_27); - fullAdd_x FA_2160_1984(int_7_27, int_6_27, pp_8_27, pp_9_27, pp_10_27); - r4bs r4bs_2160_2200(yy[4], yy[5], single[11], double[11], neg[11], pp_11_27); - r4bs r4bs_2160_2328(yy[2], yy[3], single[12], double[12], neg[12], pp_12_27); - r4bs r4bs_2160_2456(yy[0], yy[1], single[13], double[13], neg[13], pp_13_27); - fullAdd_x FA_2160_2584(int_9_27, int_8_27, pp_11_27, pp_12_27, pp_13_27); - fullAdd_x FA_2160_2800(int_11_27, int_10_27, int_1_26, int_3_26, int_5_26); - fullAdd_x FA_2160_3016(int_13_27, int_12_27, int_7_26, int_9_26, int_0_27); - fullAdd_x FA_2160_3232(int_15_27, int_14_27, int_11_26, int_13_26, int_2_27); - fullAdd_x FA_2160_3448(int_17_27, int_16_27, int_4_27, int_6_27, int_8_27); - fullAdd_x FA_2160_3664(int_19_27, int_18_27, int_15_26, int_17_26, int_10_27); - fullAdd_x FA_2160_3880(int_21_27, int_20_27, int_12_27, int_19_26, int_14_27); - fullAdd_x FA_2160_4096(int_23_27, int_22_27, int_16_27, int_21_26, int_18_27); - fullAdd_x FA_2160_4312(int_25_27, int_24_27, int_23_26, int_20_27, int_22_27); - assign Sum[27] = int_25_26; - assign Carry[27] = int_24_27; - - // Hardware for column 28 - - r4bs r4bs_2240_64(yy[27], yy[28], single[0], double[0], neg[0], pp_0_28); - halfAdd HA_2240_192(int_1_28, int_0_28, neg[14], pp_0_28); - r4bs r4bs_2240_272(yy[25], yy[26], single[1], double[1], neg[1], pp_1_28); - r4bs r4bs_2240_400(yy[23], yy[24], single[2], double[2], neg[2], pp_2_28); - r4bs r4bs_2240_528(yy[21], yy[22], single[3], double[3], neg[3], pp_3_28); - fullAdd_x FA_2240_656(int_3_28, int_2_28, pp_1_28, pp_2_28, pp_3_28); - r4bs r4bs_2240_872(yy[19], yy[20], single[4], double[4], neg[4], pp_4_28); - r4bs r4bs_2240_1000(yy[17], yy[18], single[5], double[5], neg[5], pp_5_28); - r4bs r4bs_2240_1128(yy[15], yy[16], single[6], double[6], neg[6], pp_6_28); - fullAdd_x FA_2240_1256(int_5_28, int_4_28, pp_4_28, pp_5_28, pp_6_28); - r4bs r4bs_2240_1472(yy[13], yy[14], single[7], double[7], neg[7], pp_7_28); - r4bs r4bs_2240_1600(yy[11], yy[12], single[8], double[8], neg[8], pp_8_28); - r4bs r4bs_2240_1728(yy[9], yy[10], single[9], double[9], neg[9], pp_9_28); - fullAdd_x FA_2240_1856(int_7_28, int_6_28, pp_7_28, pp_8_28, pp_9_28); - r4bs r4bs_2240_2072(yy[7], yy[8], single[10], double[10], neg[10], pp_10_28); - r4bs r4bs_2240_2200(yy[5], yy[6], single[11], double[11], neg[11], pp_11_28); - r4bs r4bs_2240_2328(yy[3], yy[4], single[12], double[12], neg[12], pp_12_28); - fullAdd_x FA_2240_2456(int_9_28, int_8_28, pp_10_28, pp_11_28, pp_12_28); - r4bs r4bs_2240_2672(yy[1], yy[2], single[13], double[13], neg[13], pp_13_28); - r4bs r4bs_2240_2800(gnd, yy[0], single[14], double[14], neg[14], pp_14_28); - fullAdd_x FA_2240_2928(int_11_28, int_10_28, pp_13_28, pp_14_28, int_1_27); - fullAdd_x FA_2240_3144(int_13_28, int_12_28, int_3_27, int_5_27, int_7_27); - fullAdd_x FA_2240_3360(int_15_28, int_14_28, int_9_27, int_0_28, int_11_27); - fullAdd_x FA_2240_3576(int_17_28, int_16_28, int_13_27, int_2_28, int_4_28); - fullAdd_x FA_2240_3792(int_19_28, int_18_28, int_6_28, int_8_28, int_10_28); - fullAdd_x FA_2240_4008(int_21_28, int_20_28, int_15_27, int_17_27, int_12_28); - fullAdd_x FA_2240_4224(int_23_28, int_22_28, int_14_28, int_19_27, int_16_28); - fullAdd_x FA_2240_4440(int_25_28, int_24_28, int_18_28, int_21_27, int_20_28); - fullAdd_x FA_2240_4656(int_27_28, int_26_28, int_23_27, int_22_28, int_24_28); - assign Sum[28] = int_25_27; - assign Carry[28] = int_26_28; - - // Hardware for column 29 - - r4bs r4bs_2320_64(yy[28], yy[29], single[0], double[0], neg[0], pp_0_29); - r4bs r4bs_2320_192(yy[26], yy[27], single[1], double[1], neg[1], pp_1_29); - halfAdd HA_2320_320(int_1_29, int_0_29, pp_0_29, pp_1_29); - r4bs r4bs_2320_400(yy[24], yy[25], single[2], double[2], neg[2], pp_2_29); - r4bs r4bs_2320_528(yy[22], yy[23], single[3], double[3], neg[3], pp_3_29); - r4bs r4bs_2320_656(yy[20], yy[21], single[4], double[4], neg[4], pp_4_29); - fullAdd_x FA_2320_784(int_3_29, int_2_29, pp_2_29, pp_3_29, pp_4_29); - r4bs r4bs_2320_1000(yy[18], yy[19], single[5], double[5], neg[5], pp_5_29); - r4bs r4bs_2320_1128(yy[16], yy[17], single[6], double[6], neg[6], pp_6_29); - r4bs r4bs_2320_1256(yy[14], yy[15], single[7], double[7], neg[7], pp_7_29); - fullAdd_x FA_2320_1384(int_5_29, int_4_29, pp_5_29, pp_6_29, pp_7_29); - r4bs r4bs_2320_1600(yy[12], yy[13], single[8], double[8], neg[8], pp_8_29); - r4bs r4bs_2320_1728(yy[10], yy[11], single[9], double[9], neg[9], pp_9_29); - r4bs r4bs_2320_1856(yy[8], yy[9], single[10], double[10], neg[10], pp_10_29); - fullAdd_x FA_2320_1984(int_7_29, int_6_29, pp_8_29, pp_9_29, pp_10_29); - r4bs r4bs_2320_2200(yy[6], yy[7], single[11], double[11], neg[11], pp_11_29); - r4bs r4bs_2320_2328(yy[4], yy[5], single[12], double[12], neg[12], pp_12_29); - r4bs r4bs_2320_2456(yy[2], yy[3], single[13], double[13], neg[13], pp_13_29); - fullAdd_x FA_2320_2584(int_9_29, int_8_29, pp_11_29, pp_12_29, pp_13_29); - r4bs r4bs_2320_2800(yy[0], yy[1], single[14], double[14], neg[14], pp_14_29); - fullAdd_x FA_2320_2928(int_11_29, int_10_29, pp_14_29, int_1_28, int_3_28); - fullAdd_x FA_2320_3144(int_13_29, int_12_29, int_5_28, int_7_28, int_9_28); - fullAdd_x FA_2320_3360(int_15_29, int_14_29, int_0_29, int_11_28, int_13_28); - fullAdd_x FA_2320_3576(int_17_29, int_16_29, int_2_29, int_4_29, int_6_29); - fullAdd_x FA_2320_3792(int_19_29, int_18_29, int_8_29, int_10_29, int_15_28); - fullAdd_x FA_2320_4008(int_21_29, int_20_29, int_17_28, int_19_28, int_12_29); - fullAdd_x FA_2320_4224(int_23_29, int_22_29, int_14_29, int_21_28, int_16_29); - fullAdd_x FA_2320_4440(int_25_29, int_24_29, int_18_29, int_23_28, int_20_29); - fullAdd_x FA_2320_4656(int_27_29, int_26_29, int_25_28, int_22_29, int_24_29); - assign Sum[29] = int_27_28; - assign Carry[29] = int_26_29; - - // Hardware for column 30 - - r4bs r4bs_2400_64(yy[29], yy[30], single[0], double[0], neg[0], pp_0_30); - halfAdd HA_2400_192(int_1_30, int_0_30, neg[15], pp_0_30); - r4bs r4bs_2400_272(yy[27], yy[28], single[1], double[1], neg[1], pp_1_30); - r4bs r4bs_2400_400(yy[25], yy[26], single[2], double[2], neg[2], pp_2_30); - r4bs r4bs_2400_528(yy[23], yy[24], single[3], double[3], neg[3], pp_3_30); - fullAdd_x FA_2400_656(int_3_30, int_2_30, pp_1_30, pp_2_30, pp_3_30); - r4bs r4bs_2400_872(yy[21], yy[22], single[4], double[4], neg[4], pp_4_30); - r4bs r4bs_2400_1000(yy[19], yy[20], single[5], double[5], neg[5], pp_5_30); - r4bs r4bs_2400_1128(yy[17], yy[18], single[6], double[6], neg[6], pp_6_30); - fullAdd_x FA_2400_1256(int_5_30, int_4_30, pp_4_30, pp_5_30, pp_6_30); - r4bs r4bs_2400_1472(yy[15], yy[16], single[7], double[7], neg[7], pp_7_30); - r4bs r4bs_2400_1600(yy[13], yy[14], single[8], double[8], neg[8], pp_8_30); - r4bs r4bs_2400_1728(yy[11], yy[12], single[9], double[9], neg[9], pp_9_30); - fullAdd_x FA_2400_1856(int_7_30, int_6_30, pp_7_30, pp_8_30, pp_9_30); - r4bs r4bs_2400_2072(yy[9], yy[10], single[10], double[10], neg[10], pp_10_30); - r4bs r4bs_2400_2200(yy[7], yy[8], single[11], double[11], neg[11], pp_11_30); - r4bs r4bs_2400_2328(yy[5], yy[6], single[12], double[12], neg[12], pp_12_30); - fullAdd_x FA_2400_2456(int_9_30, int_8_30, pp_10_30, pp_11_30, pp_12_30); - r4bs r4bs_2400_2672(yy[3], yy[4], single[13], double[13], neg[13], pp_13_30); - r4bs r4bs_2400_2800(yy[1], yy[2], single[14], double[14], neg[14], pp_14_30); - r4bs r4bs_2400_2928(gnd, yy[0], single[15], double[15], neg[15], pp_15_30); - fullAdd_x FA_2400_3056(int_11_30, int_10_30, pp_13_30, pp_14_30, pp_15_30); - fullAdd_x FA_2400_3272(int_13_30, int_12_30, int_1_29, int_3_29, int_5_29); - fullAdd_x FA_2400_3488(int_15_30, int_14_30, int_7_29, int_9_29, int_0_30); - fullAdd_x FA_2400_3704(int_17_30, int_16_30, int_11_29, int_13_29, int_2_30); - fullAdd_x FA_2400_3920(int_19_30, int_18_30, int_4_30, int_6_30, int_8_30); - fullAdd_x FA_2400_4136(int_21_30, int_20_30, int_10_30, int_15_29, int_17_29); - fullAdd_x FA_2400_4352(int_23_30, int_22_30, int_12_30, int_14_30, int_19_29); - fullAdd_x FA_2400_4568(int_25_30, int_24_30, int_21_29, int_16_30, int_18_30); - fullAdd_x FA_2400_4784(int_27_30, int_26_30, int_23_29, int_20_30, int_22_30); - fullAdd_x FA_2400_5000(int_29_30, int_28_30, int_25_29, int_24_30, int_26_30); - assign Sum[30] = int_27_29; - assign Carry[30] = int_28_30; - - // Hardware for column 31 - - r4bs r4bs_2480_64(yy[30], yy[31], single[0], double[0], neg[0], pp_0_31); - r4bs r4bs_2480_192(yy[28], yy[29], single[1], double[1], neg[1], pp_1_31); - halfAdd HA_2480_320(int_1_31, int_0_31, pp_0_31, pp_1_31); - r4bs r4bs_2480_400(yy[26], yy[27], single[2], double[2], neg[2], pp_2_31); - r4bs r4bs_2480_528(yy[24], yy[25], single[3], double[3], neg[3], pp_3_31); - r4bs r4bs_2480_656(yy[22], yy[23], single[4], double[4], neg[4], pp_4_31); - fullAdd_x FA_2480_784(int_3_31, int_2_31, pp_2_31, pp_3_31, pp_4_31); - r4bs r4bs_2480_1000(yy[20], yy[21], single[5], double[5], neg[5], pp_5_31); - r4bs r4bs_2480_1128(yy[18], yy[19], single[6], double[6], neg[6], pp_6_31); - r4bs r4bs_2480_1256(yy[16], yy[17], single[7], double[7], neg[7], pp_7_31); - fullAdd_x FA_2480_1384(int_5_31, int_4_31, pp_5_31, pp_6_31, pp_7_31); - r4bs r4bs_2480_1600(yy[14], yy[15], single[8], double[8], neg[8], pp_8_31); - r4bs r4bs_2480_1728(yy[12], yy[13], single[9], double[9], neg[9], pp_9_31); - r4bs r4bs_2480_1856(yy[10], yy[11], single[10], double[10], neg[10], pp_10_31); - fullAdd_x FA_2480_1984(int_7_31, int_6_31, pp_8_31, pp_9_31, pp_10_31); - r4bs r4bs_2480_2200(yy[8], yy[9], single[11], double[11], neg[11], pp_11_31); - r4bs r4bs_2480_2328(yy[6], yy[7], single[12], double[12], neg[12], pp_12_31); - r4bs r4bs_2480_2456(yy[4], yy[5], single[13], double[13], neg[13], pp_13_31); - fullAdd_x FA_2480_2584(int_9_31, int_8_31, pp_11_31, pp_12_31, pp_13_31); - r4bs r4bs_2480_2800(yy[2], yy[3], single[14], double[14], neg[14], pp_14_31); - r4bs r4bs_2480_2928(yy[0], yy[1], single[15], double[15], neg[15], pp_15_31); - fullAdd_x FA_2480_3056(int_11_31, int_10_31, pp_14_31, pp_15_31, int_1_30); - fullAdd_x FA_2480_3272(int_13_31, int_12_31, int_3_30, int_5_30, int_7_30); - fullAdd_x FA_2480_3488(int_15_31, int_14_31, int_9_30, int_11_30, int_0_31); - fullAdd_x FA_2480_3704(int_17_31, int_16_31, int_13_30, int_15_30, int_2_31); - fullAdd_x FA_2480_3920(int_19_31, int_18_31, int_4_31, int_6_31, int_8_31); - fullAdd_x FA_2480_4136(int_21_31, int_20_31, int_10_31, int_17_30, int_19_30); - fullAdd_x FA_2480_4352(int_23_31, int_22_31, int_12_31, int_14_31, int_21_30); - fullAdd_x FA_2480_4568(int_25_31, int_24_31, int_16_31, int_18_31, int_23_30); - fullAdd_x FA_2480_4784(int_27_31, int_26_31, int_25_30, int_20_31, int_22_31); - fullAdd_x FA_2480_5000(int_29_31, int_28_31, int_27_30, int_24_31, int_26_31); - assign Sum[31] = int_29_30; - assign Carry[31] = int_28_31; - - // Hardware for column 32 - - r4bs r4bs_2560_64(yy[31], yy[32], single[0], double[0], neg[0], pp_0_32); - halfAdd HA_2560_192(int_1_32, int_0_32, neg[16], pp_0_32); - r4bs r4bs_2560_272(yy[29], yy[30], single[1], double[1], neg[1], pp_1_32); - r4bs r4bs_2560_400(yy[27], yy[28], single[2], double[2], neg[2], pp_2_32); - r4bs r4bs_2560_528(yy[25], yy[26], single[3], double[3], neg[3], pp_3_32); - fullAdd_x FA_2560_656(int_3_32, int_2_32, pp_1_32, pp_2_32, pp_3_32); - r4bs r4bs_2560_872(yy[23], yy[24], single[4], double[4], neg[4], pp_4_32); - r4bs r4bs_2560_1000(yy[21], yy[22], single[5], double[5], neg[5], pp_5_32); - r4bs r4bs_2560_1128(yy[19], yy[20], single[6], double[6], neg[6], pp_6_32); - fullAdd_x FA_2560_1256(int_5_32, int_4_32, pp_4_32, pp_5_32, pp_6_32); - r4bs r4bs_2560_1472(yy[17], yy[18], single[7], double[7], neg[7], pp_7_32); - r4bs r4bs_2560_1600(yy[15], yy[16], single[8], double[8], neg[8], pp_8_32); - r4bs r4bs_2560_1728(yy[13], yy[14], single[9], double[9], neg[9], pp_9_32); - fullAdd_x FA_2560_1856(int_7_32, int_6_32, pp_7_32, pp_8_32, pp_9_32); - r4bs r4bs_2560_2072(yy[11], yy[12], single[10], double[10], neg[10], pp_10_32); - r4bs r4bs_2560_2200(yy[9], yy[10], single[11], double[11], neg[11], pp_11_32); - r4bs r4bs_2560_2328(yy[7], yy[8], single[12], double[12], neg[12], pp_12_32); - fullAdd_x FA_2560_2456(int_9_32, int_8_32, pp_10_32, pp_11_32, pp_12_32); - r4bs r4bs_2560_2672(yy[5], yy[6], single[13], double[13], neg[13], pp_13_32); - r4bs r4bs_2560_2800(yy[3], yy[4], single[14], double[14], neg[14], pp_14_32); - r4bs r4bs_2560_2928(yy[1], yy[2], single[15], double[15], neg[15], pp_15_32); - fullAdd_x FA_2560_3056(int_11_32, int_10_32, pp_13_32, pp_14_32, pp_15_32); - r4bs r4bs_2560_3272(gnd, yy[0], single[16], double[16], neg[16], pp_16_32); - fullAdd_x FA_2560_3400(int_13_32, int_12_32, pp_16_32, int_1_31, int_3_31); - fullAdd_x FA_2560_3616(int_15_32, int_14_32, int_5_31, int_7_31, int_9_31); - fullAdd_x FA_2560_3832(int_17_32, int_16_32, int_0_32, int_11_31, int_13_31); - fullAdd_x FA_2560_4048(int_19_32, int_18_32, int_15_31, int_2_32, int_4_32); - fullAdd_x FA_2560_4264(int_21_32, int_20_32, int_6_32, int_8_32, int_10_32); - fullAdd_x FA_2560_4480(int_23_32, int_22_32, int_12_32, int_17_31, int_19_31); - fullAdd_x FA_2560_4696(int_25_32, int_24_32, int_14_32, int_16_32, int_21_31); - fullAdd_x FA_2560_4912(int_27_32, int_26_32, int_18_32, int_20_32, int_23_31); - fullAdd_x FA_2560_5128(int_29_32, int_28_32, int_22_32, int_24_32, int_25_31); - fullAdd_x FA_2560_5344(int_31_32, int_30_32, int_27_31, int_26_32, int_28_32); - assign Sum[32] = int_29_31; - assign Carry[32] = int_30_32; - - // Hardware for column 33 - - r4bs r4bs_2640_64(yy[32], yy[33], single[0], double[0], neg[0], pp_0_33); - r4bs r4bs_2640_192(yy[30], yy[31], single[1], double[1], neg[1], pp_1_33); - halfAdd HA_2640_320(int_1_33, int_0_33, pp_0_33, pp_1_33); - r4bs r4bs_2640_400(yy[28], yy[29], single[2], double[2], neg[2], pp_2_33); - r4bs r4bs_2640_528(yy[26], yy[27], single[3], double[3], neg[3], pp_3_33); - r4bs r4bs_2640_656(yy[24], yy[25], single[4], double[4], neg[4], pp_4_33); - fullAdd_x FA_2640_784(int_3_33, int_2_33, pp_2_33, pp_3_33, pp_4_33); - r4bs r4bs_2640_1000(yy[22], yy[23], single[5], double[5], neg[5], pp_5_33); - r4bs r4bs_2640_1128(yy[20], yy[21], single[6], double[6], neg[6], pp_6_33); - r4bs r4bs_2640_1256(yy[18], yy[19], single[7], double[7], neg[7], pp_7_33); - fullAdd_x FA_2640_1384(int_5_33, int_4_33, pp_5_33, pp_6_33, pp_7_33); - r4bs r4bs_2640_1600(yy[16], yy[17], single[8], double[8], neg[8], pp_8_33); - r4bs r4bs_2640_1728(yy[14], yy[15], single[9], double[9], neg[9], pp_9_33); - r4bs r4bs_2640_1856(yy[12], yy[13], single[10], double[10], neg[10], pp_10_33); - fullAdd_x FA_2640_1984(int_7_33, int_6_33, pp_8_33, pp_9_33, pp_10_33); - r4bs r4bs_2640_2200(yy[10], yy[11], single[11], double[11], neg[11], pp_11_33); - r4bs r4bs_2640_2328(yy[8], yy[9], single[12], double[12], neg[12], pp_12_33); - r4bs r4bs_2640_2456(yy[6], yy[7], single[13], double[13], neg[13], pp_13_33); - fullAdd_x FA_2640_2584(int_9_33, int_8_33, pp_11_33, pp_12_33, pp_13_33); - r4bs r4bs_2640_2800(yy[4], yy[5], single[14], double[14], neg[14], pp_14_33); - r4bs r4bs_2640_2928(yy[2], yy[3], single[15], double[15], neg[15], pp_15_33); - r4bs r4bs_2640_3056(yy[0], yy[1], single[16], double[16], neg[16], pp_16_33); - fullAdd_x FA_2640_3184(int_11_33, int_10_33, pp_14_33, pp_15_33, pp_16_33); - fullAdd_x FA_2640_3400(int_13_33, int_12_33, int_1_32, int_3_32, int_5_32); - fullAdd_x FA_2640_3616(int_15_33, int_14_33, int_7_32, int_9_32, int_11_32); - fullAdd_x FA_2640_3832(int_17_33, int_16_33, int_0_33, int_13_32, int_15_32); - fullAdd_x FA_2640_4048(int_19_33, int_18_33, int_2_33, int_4_33, int_6_33); - fullAdd_x FA_2640_4264(int_21_33, int_20_33, int_8_33, int_10_33, int_17_32); - fullAdd_x FA_2640_4480(int_23_33, int_22_33, int_19_32, int_21_32, int_12_33); - fullAdd_x FA_2640_4696(int_25_33, int_24_33, int_14_33, int_23_32, int_16_33); - fullAdd_x FA_2640_4912(int_27_33, int_26_33, int_18_33, int_20_33, int_25_32); - fullAdd_x FA_2640_5128(int_29_33, int_28_33, int_22_33, int_27_32, int_24_33); - fullAdd_x FA_2640_5344(int_31_33, int_30_33, int_26_33, int_29_32, int_28_33); - assign Sum[33] = int_31_32; - assign Carry[33] = int_30_33; - - // Hardware for column 34 - - r4bs r4bs_2720_64(yy[33], yy[34], single[0], double[0], neg[0], pp_0_34); - halfAdd HA_2720_192(int_1_34, int_0_34, neg[17], pp_0_34); - r4bs r4bs_2720_272(yy[31], yy[32], single[1], double[1], neg[1], pp_1_34); - r4bs r4bs_2720_400(yy[29], yy[30], single[2], double[2], neg[2], pp_2_34); - r4bs r4bs_2720_528(yy[27], yy[28], single[3], double[3], neg[3], pp_3_34); - fullAdd_x FA_2720_656(int_3_34, int_2_34, pp_1_34, pp_2_34, pp_3_34); - r4bs r4bs_2720_872(yy[25], yy[26], single[4], double[4], neg[4], pp_4_34); - r4bs r4bs_2720_1000(yy[23], yy[24], single[5], double[5], neg[5], pp_5_34); - r4bs r4bs_2720_1128(yy[21], yy[22], single[6], double[6], neg[6], pp_6_34); - fullAdd_x FA_2720_1256(int_5_34, int_4_34, pp_4_34, pp_5_34, pp_6_34); - r4bs r4bs_2720_1472(yy[19], yy[20], single[7], double[7], neg[7], pp_7_34); - r4bs r4bs_2720_1600(yy[17], yy[18], single[8], double[8], neg[8], pp_8_34); - r4bs r4bs_2720_1728(yy[15], yy[16], single[9], double[9], neg[9], pp_9_34); - fullAdd_x FA_2720_1856(int_7_34, int_6_34, pp_7_34, pp_8_34, pp_9_34); - r4bs r4bs_2720_2072(yy[13], yy[14], single[10], double[10], neg[10], pp_10_34); - r4bs r4bs_2720_2200(yy[11], yy[12], single[11], double[11], neg[11], pp_11_34); - r4bs r4bs_2720_2328(yy[9], yy[10], single[12], double[12], neg[12], pp_12_34); - fullAdd_x FA_2720_2456(int_9_34, int_8_34, pp_10_34, pp_11_34, pp_12_34); - r4bs r4bs_2720_2672(yy[7], yy[8], single[13], double[13], neg[13], pp_13_34); - r4bs r4bs_2720_2800(yy[5], yy[6], single[14], double[14], neg[14], pp_14_34); - r4bs r4bs_2720_2928(yy[3], yy[4], single[15], double[15], neg[15], pp_15_34); - fullAdd_x FA_2720_3056(int_11_34, int_10_34, pp_13_34, pp_14_34, pp_15_34); - r4bs r4bs_2720_3272(yy[1], yy[2], single[16], double[16], neg[16], pp_16_34); - r4bs r4bs_2720_3400(gnd, yy[0], single[17], double[17], neg[17], pp_17_34); - fullAdd_x FA_2720_3528(int_13_34, int_12_34, pp_16_34, pp_17_34, int_1_33); - fullAdd_x FA_2720_3744(int_15_34, int_14_34, int_3_33, int_5_33, int_7_33); - fullAdd_x FA_2720_3960(int_17_34, int_16_34, int_9_33, int_11_33, int_0_34); - fullAdd_x FA_2720_4176(int_19_34, int_18_34, int_13_33, int_15_33, int_2_34); - fullAdd_x FA_2720_4392(int_21_34, int_20_34, int_4_34, int_6_34, int_8_34); - fullAdd_x FA_2720_4608(int_23_34, int_22_34, int_10_34, int_12_34, int_17_33); - fullAdd_x FA_2720_4824(int_25_34, int_24_34, int_19_33, int_14_34, int_16_34); - fullAdd_x FA_2720_5040(int_27_34, int_26_34, int_21_33, int_23_33, int_18_34); - fullAdd_x FA_2720_5256(int_29_34, int_28_34, int_20_34, int_22_34, int_25_33); - fullAdd_x FA_2720_5472(int_31_34, int_30_34, int_24_34, int_27_33, int_26_34); - fullAdd_x FA_2720_5688(int_33_34, int_32_34, int_28_34, int_29_33, int_30_34); - assign Sum[34] = int_31_33; - assign Carry[34] = int_32_34; - - // Hardware for column 35 - - r4bs r4bs_2800_64(yy[34], yy[35], single[0], double[0], neg[0], pp_0_35); - r4bs r4bs_2800_192(yy[32], yy[33], single[1], double[1], neg[1], pp_1_35); - halfAdd HA_2800_320(int_1_35, int_0_35, pp_0_35, pp_1_35); - r4bs r4bs_2800_400(yy[30], yy[31], single[2], double[2], neg[2], pp_2_35); - r4bs r4bs_2800_528(yy[28], yy[29], single[3], double[3], neg[3], pp_3_35); - r4bs r4bs_2800_656(yy[26], yy[27], single[4], double[4], neg[4], pp_4_35); - fullAdd_x FA_2800_784(int_3_35, int_2_35, pp_2_35, pp_3_35, pp_4_35); - r4bs r4bs_2800_1000(yy[24], yy[25], single[5], double[5], neg[5], pp_5_35); - r4bs r4bs_2800_1128(yy[22], yy[23], single[6], double[6], neg[6], pp_6_35); - r4bs r4bs_2800_1256(yy[20], yy[21], single[7], double[7], neg[7], pp_7_35); - fullAdd_x FA_2800_1384(int_5_35, int_4_35, pp_5_35, pp_6_35, pp_7_35); - r4bs r4bs_2800_1600(yy[18], yy[19], single[8], double[8], neg[8], pp_8_35); - r4bs r4bs_2800_1728(yy[16], yy[17], single[9], double[9], neg[9], pp_9_35); - r4bs r4bs_2800_1856(yy[14], yy[15], single[10], double[10], neg[10], pp_10_35); - fullAdd_x FA_2800_1984(int_7_35, int_6_35, pp_8_35, pp_9_35, pp_10_35); - r4bs r4bs_2800_2200(yy[12], yy[13], single[11], double[11], neg[11], pp_11_35); - r4bs r4bs_2800_2328(yy[10], yy[11], single[12], double[12], neg[12], pp_12_35); - r4bs r4bs_2800_2456(yy[8], yy[9], single[13], double[13], neg[13], pp_13_35); - fullAdd_x FA_2800_2584(int_9_35, int_8_35, pp_11_35, pp_12_35, pp_13_35); - r4bs r4bs_2800_2800(yy[6], yy[7], single[14], double[14], neg[14], pp_14_35); - r4bs r4bs_2800_2928(yy[4], yy[5], single[15], double[15], neg[15], pp_15_35); - r4bs r4bs_2800_3056(yy[2], yy[3], single[16], double[16], neg[16], pp_16_35); - fullAdd_x FA_2800_3184(int_11_35, int_10_35, pp_14_35, pp_15_35, pp_16_35); - r4bs r4bs_2800_3400(yy[0], yy[1], single[17], double[17], neg[17], pp_17_35); - fullAdd_x FA_2800_3528(int_13_35, int_12_35, pp_17_35, int_1_34, int_3_34); - fullAdd_x FA_2800_3744(int_15_35, int_14_35, int_5_34, int_7_34, int_9_34); - fullAdd_x FA_2800_3960(int_17_35, int_16_35, int_11_34, int_0_35, int_13_34); - fullAdd_x FA_2800_4176(int_19_35, int_18_35, int_15_34, int_17_34, int_2_35); - fullAdd_x FA_2800_4392(int_21_35, int_20_35, int_4_35, int_6_35, int_8_35); - fullAdd_x FA_2800_4608(int_23_35, int_22_35, int_10_35, int_12_35, int_19_34); - fullAdd_x FA_2800_4824(int_25_35, int_24_35, int_21_34, int_14_35, int_16_35); - fullAdd_x FA_2800_5040(int_27_35, int_26_35, int_23_34, int_25_34, int_18_35); - fullAdd_x FA_2800_5256(int_29_35, int_28_35, int_20_35, int_22_35, int_27_34); - fullAdd_x FA_2800_5472(int_31_35, int_30_35, int_24_35, int_29_34, int_26_35); - fullAdd_x FA_2800_5688(int_33_35, int_32_35, int_28_35, int_31_34, int_30_35); - assign Sum[35] = int_33_34; - assign Carry[35] = int_32_35; - - // Hardware for column 36 - - r4bs r4bs_2880_64(yy[35], yy[36], single[0], double[0], neg[0], pp_0_36); - halfAdd HA_2880_192(int_1_36, int_0_36, neg[18], pp_0_36); - r4bs r4bs_2880_272(yy[33], yy[34], single[1], double[1], neg[1], pp_1_36); - r4bs r4bs_2880_400(yy[31], yy[32], single[2], double[2], neg[2], pp_2_36); - r4bs r4bs_2880_528(yy[29], yy[30], single[3], double[3], neg[3], pp_3_36); - fullAdd_x FA_2880_656(int_3_36, int_2_36, pp_1_36, pp_2_36, pp_3_36); - r4bs r4bs_2880_872(yy[27], yy[28], single[4], double[4], neg[4], pp_4_36); - r4bs r4bs_2880_1000(yy[25], yy[26], single[5], double[5], neg[5], pp_5_36); - r4bs r4bs_2880_1128(yy[23], yy[24], single[6], double[6], neg[6], pp_6_36); - fullAdd_x FA_2880_1256(int_5_36, int_4_36, pp_4_36, pp_5_36, pp_6_36); - r4bs r4bs_2880_1472(yy[21], yy[22], single[7], double[7], neg[7], pp_7_36); - r4bs r4bs_2880_1600(yy[19], yy[20], single[8], double[8], neg[8], pp_8_36); - r4bs r4bs_2880_1728(yy[17], yy[18], single[9], double[9], neg[9], pp_9_36); - fullAdd_x FA_2880_1856(int_7_36, int_6_36, pp_7_36, pp_8_36, pp_9_36); - r4bs r4bs_2880_2072(yy[15], yy[16], single[10], double[10], neg[10], pp_10_36); - r4bs r4bs_2880_2200(yy[13], yy[14], single[11], double[11], neg[11], pp_11_36); - r4bs r4bs_2880_2328(yy[11], yy[12], single[12], double[12], neg[12], pp_12_36); - fullAdd_x FA_2880_2456(int_9_36, int_8_36, pp_10_36, pp_11_36, pp_12_36); - r4bs r4bs_2880_2672(yy[9], yy[10], single[13], double[13], neg[13], pp_13_36); - r4bs r4bs_2880_2800(yy[7], yy[8], single[14], double[14], neg[14], pp_14_36); - r4bs r4bs_2880_2928(yy[5], yy[6], single[15], double[15], neg[15], pp_15_36); - fullAdd_x FA_2880_3056(int_11_36, int_10_36, pp_13_36, pp_14_36, pp_15_36); - r4bs r4bs_2880_3272(yy[3], yy[4], single[16], double[16], neg[16], pp_16_36); - r4bs r4bs_2880_3400(yy[1], yy[2], single[17], double[17], neg[17], pp_17_36); - r4bs r4bs_2880_3528(gnd, yy[0], single[18], double[18], neg[18], pp_18_36); - fullAdd_x FA_2880_3656(int_13_36, int_12_36, pp_16_36, pp_17_36, pp_18_36); - fullAdd_x FA_2880_3872(int_15_36, int_14_36, int_1_35, int_3_35, int_5_35); - fullAdd_x FA_2880_4088(int_17_36, int_16_36, int_7_35, int_9_35, int_11_35); - fullAdd_x FA_2880_4304(int_19_36, int_18_36, int_0_36, int_13_35, int_15_35); - fullAdd_x FA_2880_4520(int_21_36, int_20_36, int_2_36, int_4_36, int_6_36); - fullAdd_x FA_2880_4736(int_23_36, int_22_36, int_8_36, int_10_36, int_12_36); - fullAdd_x FA_2880_4952(int_25_36, int_24_36, int_17_35, int_19_35, int_21_35); - fullAdd_x FA_2880_5168(int_27_36, int_26_36, int_14_36, int_16_36, int_23_35); - fullAdd_x FA_2880_5384(int_29_36, int_28_36, int_25_35, int_18_36, int_20_36); - fullAdd_x FA_2880_5600(int_31_36, int_30_36, int_22_36, int_27_35, int_24_36); - fullAdd_x FA_2880_5816(int_33_36, int_32_36, int_26_36, int_29_35, int_28_36); - fullAdd_x FA_2880_6032(int_35_36, int_34_36, int_31_35, int_30_36, int_32_36); - assign Sum[36] = int_33_35; - assign Carry[36] = int_34_36; - - // Hardware for column 37 - - r4bs r4bs_2960_64(yy[36], yy[37], single[0], double[0], neg[0], pp_0_37); - r4bs r4bs_2960_192(yy[34], yy[35], single[1], double[1], neg[1], pp_1_37); - halfAdd HA_2960_320(int_1_37, int_0_37, pp_0_37, pp_1_37); - r4bs r4bs_2960_400(yy[32], yy[33], single[2], double[2], neg[2], pp_2_37); - r4bs r4bs_2960_528(yy[30], yy[31], single[3], double[3], neg[3], pp_3_37); - r4bs r4bs_2960_656(yy[28], yy[29], single[4], double[4], neg[4], pp_4_37); - fullAdd_x FA_2960_784(int_3_37, int_2_37, pp_2_37, pp_3_37, pp_4_37); - r4bs r4bs_2960_1000(yy[26], yy[27], single[5], double[5], neg[5], pp_5_37); - r4bs r4bs_2960_1128(yy[24], yy[25], single[6], double[6], neg[6], pp_6_37); - r4bs r4bs_2960_1256(yy[22], yy[23], single[7], double[7], neg[7], pp_7_37); - fullAdd_x FA_2960_1384(int_5_37, int_4_37, pp_5_37, pp_6_37, pp_7_37); - r4bs r4bs_2960_1600(yy[20], yy[21], single[8], double[8], neg[8], pp_8_37); - r4bs r4bs_2960_1728(yy[18], yy[19], single[9], double[9], neg[9], pp_9_37); - r4bs r4bs_2960_1856(yy[16], yy[17], single[10], double[10], neg[10], pp_10_37); - fullAdd_x FA_2960_1984(int_7_37, int_6_37, pp_8_37, pp_9_37, pp_10_37); - r4bs r4bs_2960_2200(yy[14], yy[15], single[11], double[11], neg[11], pp_11_37); - r4bs r4bs_2960_2328(yy[12], yy[13], single[12], double[12], neg[12], pp_12_37); - r4bs r4bs_2960_2456(yy[10], yy[11], single[13], double[13], neg[13], pp_13_37); - fullAdd_x FA_2960_2584(int_9_37, int_8_37, pp_11_37, pp_12_37, pp_13_37); - r4bs r4bs_2960_2800(yy[8], yy[9], single[14], double[14], neg[14], pp_14_37); - r4bs r4bs_2960_2928(yy[6], yy[7], single[15], double[15], neg[15], pp_15_37); - r4bs r4bs_2960_3056(yy[4], yy[5], single[16], double[16], neg[16], pp_16_37); - fullAdd_x FA_2960_3184(int_11_37, int_10_37, pp_14_37, pp_15_37, pp_16_37); - r4bs r4bs_2960_3400(yy[2], yy[3], single[17], double[17], neg[17], pp_17_37); - r4bs r4bs_2960_3528(yy[0], yy[1], single[18], double[18], neg[18], pp_18_37); - fullAdd_x FA_2960_3656(int_13_37, int_12_37, pp_17_37, pp_18_37, int_1_36); - fullAdd_x FA_2960_3872(int_15_37, int_14_37, int_3_36, int_5_36, int_7_36); - fullAdd_x FA_2960_4088(int_17_37, int_16_37, int_9_36, int_11_36, int_13_36); - fullAdd_x FA_2960_4304(int_19_37, int_18_37, int_0_37, int_15_36, int_17_36); - fullAdd_x FA_2960_4520(int_21_37, int_20_37, int_2_37, int_4_37, int_6_37); - fullAdd_x FA_2960_4736(int_23_37, int_22_37, int_8_37, int_10_37, int_12_37); - fullAdd_x FA_2960_4952(int_25_37, int_24_37, int_19_36, int_21_36, int_23_36); - fullAdd_x FA_2960_5168(int_27_37, int_26_37, int_14_37, int_16_37, int_25_36); - fullAdd_x FA_2960_5384(int_29_37, int_28_37, int_18_37, int_20_37, int_22_37); - fullAdd_x FA_2960_5600(int_31_37, int_30_37, int_27_36, int_29_36, int_24_37); - fullAdd_x FA_2960_5816(int_33_37, int_32_37, int_26_37, int_31_36, int_28_37); - fullAdd_x FA_2960_6032(int_35_37, int_34_37, int_33_36, int_30_37, int_32_37); - assign Sum[37] = int_35_36; - assign Carry[37] = int_34_37; - - // Hardware for column 38 - - r4bs r4bs_3040_64(yy[37], yy[38], single[0], double[0], neg[0], pp_0_38); - halfAdd HA_3040_192(int_1_38, int_0_38, neg[19], pp_0_38); - r4bs r4bs_3040_272(yy[35], yy[36], single[1], double[1], neg[1], pp_1_38); - r4bs r4bs_3040_400(yy[33], yy[34], single[2], double[2], neg[2], pp_2_38); - r4bs r4bs_3040_528(yy[31], yy[32], single[3], double[3], neg[3], pp_3_38); - fullAdd_x FA_3040_656(int_3_38, int_2_38, pp_1_38, pp_2_38, pp_3_38); - r4bs r4bs_3040_872(yy[29], yy[30], single[4], double[4], neg[4], pp_4_38); - r4bs r4bs_3040_1000(yy[27], yy[28], single[5], double[5], neg[5], pp_5_38); - r4bs r4bs_3040_1128(yy[25], yy[26], single[6], double[6], neg[6], pp_6_38); - fullAdd_x FA_3040_1256(int_5_38, int_4_38, pp_4_38, pp_5_38, pp_6_38); - r4bs r4bs_3040_1472(yy[23], yy[24], single[7], double[7], neg[7], pp_7_38); - r4bs r4bs_3040_1600(yy[21], yy[22], single[8], double[8], neg[8], pp_8_38); - r4bs r4bs_3040_1728(yy[19], yy[20], single[9], double[9], neg[9], pp_9_38); - fullAdd_x FA_3040_1856(int_7_38, int_6_38, pp_7_38, pp_8_38, pp_9_38); - r4bs r4bs_3040_2072(yy[17], yy[18], single[10], double[10], neg[10], pp_10_38); - r4bs r4bs_3040_2200(yy[15], yy[16], single[11], double[11], neg[11], pp_11_38); - r4bs r4bs_3040_2328(yy[13], yy[14], single[12], double[12], neg[12], pp_12_38); - fullAdd_x FA_3040_2456(int_9_38, int_8_38, pp_10_38, pp_11_38, pp_12_38); - r4bs r4bs_3040_2672(yy[11], yy[12], single[13], double[13], neg[13], pp_13_38); - r4bs r4bs_3040_2800(yy[9], yy[10], single[14], double[14], neg[14], pp_14_38); - r4bs r4bs_3040_2928(yy[7], yy[8], single[15], double[15], neg[15], pp_15_38); - fullAdd_x FA_3040_3056(int_11_38, int_10_38, pp_13_38, pp_14_38, pp_15_38); - r4bs r4bs_3040_3272(yy[5], yy[6], single[16], double[16], neg[16], pp_16_38); - r4bs r4bs_3040_3400(yy[3], yy[4], single[17], double[17], neg[17], pp_17_38); - r4bs r4bs_3040_3528(yy[1], yy[2], single[18], double[18], neg[18], pp_18_38); - fullAdd_x FA_3040_3656(int_13_38, int_12_38, pp_16_38, pp_17_38, pp_18_38); - r4bs r4bs_3040_3872(gnd, yy[0], single[19], double[19], neg[19], pp_19_38); - fullAdd_x FA_3040_4000(int_15_38, int_14_38, pp_19_38, int_1_37, int_3_37); - fullAdd_x FA_3040_4216(int_17_38, int_16_38, int_5_37, int_7_37, int_9_37); - fullAdd_x FA_3040_4432(int_19_38, int_18_38, int_11_37, int_0_38, int_13_37); - fullAdd_x FA_3040_4648(int_21_38, int_20_38, int_15_37, int_17_37, int_2_38); - fullAdd_x FA_3040_4864(int_23_38, int_22_38, int_4_38, int_6_38, int_8_38); - fullAdd_x FA_3040_5080(int_25_38, int_24_38, int_10_38, int_12_38, int_14_38); - fullAdd_x FA_3040_5296(int_27_38, int_26_38, int_19_37, int_21_37, int_23_37); - fullAdd_x FA_3040_5512(int_29_38, int_28_38, int_16_38, int_18_38, int_25_37); - fullAdd_x FA_3040_5728(int_31_38, int_30_38, int_20_38, int_22_38, int_24_38); - fullAdd_x FA_3040_5944(int_33_38, int_32_38, int_27_37, int_29_37, int_26_38); - fullAdd_x FA_3040_6160(int_35_38, int_34_38, int_28_38, int_31_37, int_30_38); - fullAdd_x FA_3040_6376(int_37_38, int_36_38, int_33_37, int_32_38, int_34_38); - assign Sum[38] = int_35_37; - assign Carry[38] = int_36_38; - - // Hardware for column 39 - - r4bs r4bs_3120_64(yy[38], yy[39], single[0], double[0], neg[0], pp_0_39); - r4bs r4bs_3120_192(yy[36], yy[37], single[1], double[1], neg[1], pp_1_39); - halfAdd HA_3120_320(int_1_39, int_0_39, pp_0_39, pp_1_39); - r4bs r4bs_3120_400(yy[34], yy[35], single[2], double[2], neg[2], pp_2_39); - r4bs r4bs_3120_528(yy[32], yy[33], single[3], double[3], neg[3], pp_3_39); - r4bs r4bs_3120_656(yy[30], yy[31], single[4], double[4], neg[4], pp_4_39); - fullAdd_x FA_3120_784(int_3_39, int_2_39, pp_2_39, pp_3_39, pp_4_39); - r4bs r4bs_3120_1000(yy[28], yy[29], single[5], double[5], neg[5], pp_5_39); - r4bs r4bs_3120_1128(yy[26], yy[27], single[6], double[6], neg[6], pp_6_39); - r4bs r4bs_3120_1256(yy[24], yy[25], single[7], double[7], neg[7], pp_7_39); - fullAdd_x FA_3120_1384(int_5_39, int_4_39, pp_5_39, pp_6_39, pp_7_39); - r4bs r4bs_3120_1600(yy[22], yy[23], single[8], double[8], neg[8], pp_8_39); - r4bs r4bs_3120_1728(yy[20], yy[21], single[9], double[9], neg[9], pp_9_39); - r4bs r4bs_3120_1856(yy[18], yy[19], single[10], double[10], neg[10], pp_10_39); - fullAdd_x FA_3120_1984(int_7_39, int_6_39, pp_8_39, pp_9_39, pp_10_39); - r4bs r4bs_3120_2200(yy[16], yy[17], single[11], double[11], neg[11], pp_11_39); - r4bs r4bs_3120_2328(yy[14], yy[15], single[12], double[12], neg[12], pp_12_39); - r4bs r4bs_3120_2456(yy[12], yy[13], single[13], double[13], neg[13], pp_13_39); - fullAdd_x FA_3120_2584(int_9_39, int_8_39, pp_11_39, pp_12_39, pp_13_39); - r4bs r4bs_3120_2800(yy[10], yy[11], single[14], double[14], neg[14], pp_14_39); - r4bs r4bs_3120_2928(yy[8], yy[9], single[15], double[15], neg[15], pp_15_39); - r4bs r4bs_3120_3056(yy[6], yy[7], single[16], double[16], neg[16], pp_16_39); - fullAdd_x FA_3120_3184(int_11_39, int_10_39, pp_14_39, pp_15_39, pp_16_39); - r4bs r4bs_3120_3400(yy[4], yy[5], single[17], double[17], neg[17], pp_17_39); - r4bs r4bs_3120_3528(yy[2], yy[3], single[18], double[18], neg[18], pp_18_39); - r4bs r4bs_3120_3656(yy[0], yy[1], single[19], double[19], neg[19], pp_19_39); - fullAdd_x FA_3120_3784(int_13_39, int_12_39, pp_17_39, pp_18_39, pp_19_39); - fullAdd_x FA_3120_4000(int_15_39, int_14_39, int_1_38, int_3_38, int_5_38); - fullAdd_x FA_3120_4216(int_17_39, int_16_39, int_7_38, int_9_38, int_11_38); - fullAdd_x FA_3120_4432(int_19_39, int_18_39, int_13_38, int_0_39, int_15_38); - fullAdd_x FA_3120_4648(int_21_39, int_20_39, int_17_38, int_2_39, int_4_39); - fullAdd_x FA_3120_4864(int_23_39, int_22_39, int_6_39, int_8_39, int_10_39); - fullAdd_x FA_3120_5080(int_25_39, int_24_39, int_12_39, int_19_38, int_21_38); - fullAdd_x FA_3120_5296(int_27_39, int_26_39, int_23_38, int_14_39, int_16_39); - fullAdd_x FA_3120_5512(int_29_39, int_28_39, int_18_39, int_25_38, int_27_38); - fullAdd_x FA_3120_5728(int_31_39, int_30_39, int_20_39, int_22_39, int_24_39); - fullAdd_x FA_3120_5944(int_33_39, int_32_39, int_29_38, int_31_38, int_26_39); - fullAdd_x FA_3120_6160(int_35_39, int_34_39, int_28_39, int_33_38, int_30_39); - fullAdd_x FA_3120_6376(int_37_39, int_36_39, int_35_38, int_32_39, int_34_39); - assign Sum[39] = int_37_38; - assign Carry[39] = int_36_39; - - // Hardware for column 40 - - r4bs r4bs_3200_64(yy[39], yy[40], single[0], double[0], neg[0], pp_0_40); - halfAdd HA_3200_192(int_1_40, int_0_40, neg[20], pp_0_40); - r4bs r4bs_3200_272(yy[37], yy[38], single[1], double[1], neg[1], pp_1_40); - r4bs r4bs_3200_400(yy[35], yy[36], single[2], double[2], neg[2], pp_2_40); - r4bs r4bs_3200_528(yy[33], yy[34], single[3], double[3], neg[3], pp_3_40); - fullAdd_x FA_3200_656(int_3_40, int_2_40, pp_1_40, pp_2_40, pp_3_40); - r4bs r4bs_3200_872(yy[31], yy[32], single[4], double[4], neg[4], pp_4_40); - r4bs r4bs_3200_1000(yy[29], yy[30], single[5], double[5], neg[5], pp_5_40); - r4bs r4bs_3200_1128(yy[27], yy[28], single[6], double[6], neg[6], pp_6_40); - fullAdd_x FA_3200_1256(int_5_40, int_4_40, pp_4_40, pp_5_40, pp_6_40); - r4bs r4bs_3200_1472(yy[25], yy[26], single[7], double[7], neg[7], pp_7_40); - r4bs r4bs_3200_1600(yy[23], yy[24], single[8], double[8], neg[8], pp_8_40); - r4bs r4bs_3200_1728(yy[21], yy[22], single[9], double[9], neg[9], pp_9_40); - fullAdd_x FA_3200_1856(int_7_40, int_6_40, pp_7_40, pp_8_40, pp_9_40); - r4bs r4bs_3200_2072(yy[19], yy[20], single[10], double[10], neg[10], pp_10_40); - r4bs r4bs_3200_2200(yy[17], yy[18], single[11], double[11], neg[11], pp_11_40); - r4bs r4bs_3200_2328(yy[15], yy[16], single[12], double[12], neg[12], pp_12_40); - fullAdd_x FA_3200_2456(int_9_40, int_8_40, pp_10_40, pp_11_40, pp_12_40); - r4bs r4bs_3200_2672(yy[13], yy[14], single[13], double[13], neg[13], pp_13_40); - r4bs r4bs_3200_2800(yy[11], yy[12], single[14], double[14], neg[14], pp_14_40); - r4bs r4bs_3200_2928(yy[9], yy[10], single[15], double[15], neg[15], pp_15_40); - fullAdd_x FA_3200_3056(int_11_40, int_10_40, pp_13_40, pp_14_40, pp_15_40); - r4bs r4bs_3200_3272(yy[7], yy[8], single[16], double[16], neg[16], pp_16_40); - r4bs r4bs_3200_3400(yy[5], yy[6], single[17], double[17], neg[17], pp_17_40); - r4bs r4bs_3200_3528(yy[3], yy[4], single[18], double[18], neg[18], pp_18_40); - fullAdd_x FA_3200_3656(int_13_40, int_12_40, pp_16_40, pp_17_40, pp_18_40); - r4bs r4bs_3200_3872(yy[1], yy[2], single[19], double[19], neg[19], pp_19_40); - r4bs r4bs_3200_4000(gnd, yy[0], single[20], double[20], neg[20], pp_20_40); - fullAdd_x FA_3200_4128(int_15_40, int_14_40, pp_19_40, pp_20_40, int_1_39); - fullAdd_x FA_3200_4344(int_17_40, int_16_40, int_3_39, int_5_39, int_7_39); - fullAdd_x FA_3200_4560(int_19_40, int_18_40, int_9_39, int_11_39, int_13_39); - fullAdd_x FA_3200_4776(int_21_40, int_20_40, int_0_40, int_15_39, int_17_39); - fullAdd_x FA_3200_4992(int_23_40, int_22_40, int_2_40, int_4_40, int_6_40); - fullAdd_x FA_3200_5208(int_25_40, int_24_40, int_8_40, int_10_40, int_12_40); - fullAdd_x FA_3200_5424(int_27_40, int_26_40, int_14_40, int_19_39, int_21_39); - fullAdd_x FA_3200_5640(int_29_40, int_28_40, int_23_39, int_16_40, int_18_40); - fullAdd_x FA_3200_5856(int_31_40, int_30_40, int_25_39, int_27_39, int_20_40); - fullAdd_x FA_3200_6072(int_33_40, int_32_40, int_22_40, int_24_40, int_29_39); - fullAdd_x FA_3200_6288(int_35_40, int_34_40, int_26_40, int_28_40, int_31_39); - fullAdd_x FA_3200_6504(int_37_40, int_36_40, int_33_39, int_30_40, int_32_40); - fullAdd_x FA_3200_6720(int_39_40, int_38_40, int_35_39, int_34_40, int_36_40); - assign Sum[40] = int_37_39; - assign Carry[40] = int_38_40; - - // Hardware for column 41 - - r4bs r4bs_3280_64(yy[40], yy[41], single[0], double[0], neg[0], pp_0_41); - r4bs r4bs_3280_192(yy[38], yy[39], single[1], double[1], neg[1], pp_1_41); - halfAdd HA_3280_320(int_1_41, int_0_41, pp_0_41, pp_1_41); - r4bs r4bs_3280_400(yy[36], yy[37], single[2], double[2], neg[2], pp_2_41); - r4bs r4bs_3280_528(yy[34], yy[35], single[3], double[3], neg[3], pp_3_41); - r4bs r4bs_3280_656(yy[32], yy[33], single[4], double[4], neg[4], pp_4_41); - fullAdd_x FA_3280_784(int_3_41, int_2_41, pp_2_41, pp_3_41, pp_4_41); - r4bs r4bs_3280_1000(yy[30], yy[31], single[5], double[5], neg[5], pp_5_41); - r4bs r4bs_3280_1128(yy[28], yy[29], single[6], double[6], neg[6], pp_6_41); - r4bs r4bs_3280_1256(yy[26], yy[27], single[7], double[7], neg[7], pp_7_41); - fullAdd_x FA_3280_1384(int_5_41, int_4_41, pp_5_41, pp_6_41, pp_7_41); - r4bs r4bs_3280_1600(yy[24], yy[25], single[8], double[8], neg[8], pp_8_41); - r4bs r4bs_3280_1728(yy[22], yy[23], single[9], double[9], neg[9], pp_9_41); - r4bs r4bs_3280_1856(yy[20], yy[21], single[10], double[10], neg[10], pp_10_41); - fullAdd_x FA_3280_1984(int_7_41, int_6_41, pp_8_41, pp_9_41, pp_10_41); - r4bs r4bs_3280_2200(yy[18], yy[19], single[11], double[11], neg[11], pp_11_41); - r4bs r4bs_3280_2328(yy[16], yy[17], single[12], double[12], neg[12], pp_12_41); - r4bs r4bs_3280_2456(yy[14], yy[15], single[13], double[13], neg[13], pp_13_41); - fullAdd_x FA_3280_2584(int_9_41, int_8_41, pp_11_41, pp_12_41, pp_13_41); - r4bs r4bs_3280_2800(yy[12], yy[13], single[14], double[14], neg[14], pp_14_41); - r4bs r4bs_3280_2928(yy[10], yy[11], single[15], double[15], neg[15], pp_15_41); - r4bs r4bs_3280_3056(yy[8], yy[9], single[16], double[16], neg[16], pp_16_41); - fullAdd_x FA_3280_3184(int_11_41, int_10_41, pp_14_41, pp_15_41, pp_16_41); - r4bs r4bs_3280_3400(yy[6], yy[7], single[17], double[17], neg[17], pp_17_41); - r4bs r4bs_3280_3528(yy[4], yy[5], single[18], double[18], neg[18], pp_18_41); - r4bs r4bs_3280_3656(yy[2], yy[3], single[19], double[19], neg[19], pp_19_41); - fullAdd_x FA_3280_3784(int_13_41, int_12_41, pp_17_41, pp_18_41, pp_19_41); - r4bs r4bs_3280_4000(yy[0], yy[1], single[20], double[20], neg[20], pp_20_41); - fullAdd_x FA_3280_4128(int_15_41, int_14_41, pp_20_41, int_1_40, int_3_40); - fullAdd_x FA_3280_4344(int_17_41, int_16_41, int_5_40, int_7_40, int_9_40); - fullAdd_x FA_3280_4560(int_19_41, int_18_41, int_11_40, int_13_40, int_0_41); - fullAdd_x FA_3280_4776(int_21_41, int_20_41, int_15_40, int_17_40, int_19_40); - fullAdd_x FA_3280_4992(int_23_41, int_22_41, int_2_41, int_4_41, int_6_41); - fullAdd_x FA_3280_5208(int_25_41, int_24_41, int_8_41, int_10_41, int_12_41); - fullAdd_x FA_3280_5424(int_27_41, int_26_41, int_14_41, int_21_40, int_23_40); - fullAdd_x FA_3280_5640(int_29_41, int_28_41, int_25_40, int_16_41, int_18_41); - fullAdd_x FA_3280_5856(int_31_41, int_30_41, int_27_40, int_29_40, int_20_41); - fullAdd_x FA_3280_6072(int_33_41, int_32_41, int_22_41, int_24_41, int_31_40); - fullAdd_x FA_3280_6288(int_35_41, int_34_41, int_26_41, int_28_41, int_33_40); - fullAdd_x FA_3280_6504(int_37_41, int_36_41, int_30_41, int_32_41, int_35_40); - fullAdd_x FA_3280_6720(int_39_41, int_38_41, int_37_40, int_34_41, int_36_41); - assign Sum[41] = int_39_40; - assign Carry[41] = int_38_41; - - // Hardware for column 42 - - r4bs r4bs_3360_64(yy[41], yy[42], single[0], double[0], neg[0], pp_0_42); - halfAdd HA_3360_192(int_1_42, int_0_42, neg[21], pp_0_42); - r4bs r4bs_3360_272(yy[39], yy[40], single[1], double[1], neg[1], pp_1_42); - r4bs r4bs_3360_400(yy[37], yy[38], single[2], double[2], neg[2], pp_2_42); - r4bs r4bs_3360_528(yy[35], yy[36], single[3], double[3], neg[3], pp_3_42); - fullAdd_x FA_3360_656(int_3_42, int_2_42, pp_1_42, pp_2_42, pp_3_42); - r4bs r4bs_3360_872(yy[33], yy[34], single[4], double[4], neg[4], pp_4_42); - r4bs r4bs_3360_1000(yy[31], yy[32], single[5], double[5], neg[5], pp_5_42); - r4bs r4bs_3360_1128(yy[29], yy[30], single[6], double[6], neg[6], pp_6_42); - fullAdd_x FA_3360_1256(int_5_42, int_4_42, pp_4_42, pp_5_42, pp_6_42); - r4bs r4bs_3360_1472(yy[27], yy[28], single[7], double[7], neg[7], pp_7_42); - r4bs r4bs_3360_1600(yy[25], yy[26], single[8], double[8], neg[8], pp_8_42); - r4bs r4bs_3360_1728(yy[23], yy[24], single[9], double[9], neg[9], pp_9_42); - fullAdd_x FA_3360_1856(int_7_42, int_6_42, pp_7_42, pp_8_42, pp_9_42); - r4bs r4bs_3360_2072(yy[21], yy[22], single[10], double[10], neg[10], pp_10_42); - r4bs r4bs_3360_2200(yy[19], yy[20], single[11], double[11], neg[11], pp_11_42); - r4bs r4bs_3360_2328(yy[17], yy[18], single[12], double[12], neg[12], pp_12_42); - fullAdd_x FA_3360_2456(int_9_42, int_8_42, pp_10_42, pp_11_42, pp_12_42); - r4bs r4bs_3360_2672(yy[15], yy[16], single[13], double[13], neg[13], pp_13_42); - r4bs r4bs_3360_2800(yy[13], yy[14], single[14], double[14], neg[14], pp_14_42); - r4bs r4bs_3360_2928(yy[11], yy[12], single[15], double[15], neg[15], pp_15_42); - fullAdd_x FA_3360_3056(int_11_42, int_10_42, pp_13_42, pp_14_42, pp_15_42); - r4bs r4bs_3360_3272(yy[9], yy[10], single[16], double[16], neg[16], pp_16_42); - r4bs r4bs_3360_3400(yy[7], yy[8], single[17], double[17], neg[17], pp_17_42); - r4bs r4bs_3360_3528(yy[5], yy[6], single[18], double[18], neg[18], pp_18_42); - fullAdd_x FA_3360_3656(int_13_42, int_12_42, pp_16_42, pp_17_42, pp_18_42); - r4bs r4bs_3360_3872(yy[3], yy[4], single[19], double[19], neg[19], pp_19_42); - r4bs r4bs_3360_4000(yy[1], yy[2], single[20], double[20], neg[20], pp_20_42); - r4bs r4bs_3360_4128(gnd, yy[0], single[21], double[21], neg[21], pp_21_42); - fullAdd_x FA_3360_4256(int_15_42, int_14_42, pp_19_42, pp_20_42, pp_21_42); - fullAdd_x FA_3360_4472(int_17_42, int_16_42, int_1_41, int_3_41, int_5_41); - fullAdd_x FA_3360_4688(int_19_42, int_18_42, int_7_41, int_9_41, int_11_41); - fullAdd_x FA_3360_4904(int_21_42, int_20_42, int_13_41, int_0_42, int_15_41); - fullAdd_x FA_3360_5120(int_23_42, int_22_42, int_17_41, int_19_41, int_2_42); - fullAdd_x FA_3360_5336(int_25_42, int_24_42, int_4_42, int_6_42, int_8_42); - fullAdd_x FA_3360_5552(int_27_42, int_26_42, int_10_42, int_12_42, int_14_42); - fullAdd_x FA_3360_5768(int_29_42, int_28_42, int_21_41, int_23_41, int_25_41); - fullAdd_x FA_3360_5984(int_31_42, int_30_42, int_16_42, int_18_42, int_20_42); - fullAdd_x FA_3360_6200(int_33_42, int_32_42, int_27_41, int_29_41, int_22_42); - fullAdd_x FA_3360_6416(int_35_42, int_34_42, int_24_42, int_26_42, int_31_41); - fullAdd_x FA_3360_6632(int_37_42, int_36_42, int_28_42, int_30_42, int_33_41); - fullAdd_x FA_3360_6848(int_39_42, int_38_42, int_32_42, int_34_42, int_35_41); - fullAdd_x FA_3360_7064(int_41_42, int_40_42, int_36_42, int_37_41, int_38_42); - assign Sum[42] = int_39_41; - assign Carry[42] = int_40_42; - - // Hardware for column 43 - - r4bs r4bs_3440_64(yy[42], yy[43], single[0], double[0], neg[0], pp_0_43); - r4bs r4bs_3440_192(yy[40], yy[41], single[1], double[1], neg[1], pp_1_43); - halfAdd HA_3440_320(int_1_43, int_0_43, pp_0_43, pp_1_43); - r4bs r4bs_3440_400(yy[38], yy[39], single[2], double[2], neg[2], pp_2_43); - r4bs r4bs_3440_528(yy[36], yy[37], single[3], double[3], neg[3], pp_3_43); - r4bs r4bs_3440_656(yy[34], yy[35], single[4], double[4], neg[4], pp_4_43); - fullAdd_x FA_3440_784(int_3_43, int_2_43, pp_2_43, pp_3_43, pp_4_43); - r4bs r4bs_3440_1000(yy[32], yy[33], single[5], double[5], neg[5], pp_5_43); - r4bs r4bs_3440_1128(yy[30], yy[31], single[6], double[6], neg[6], pp_6_43); - r4bs r4bs_3440_1256(yy[28], yy[29], single[7], double[7], neg[7], pp_7_43); - fullAdd_x FA_3440_1384(int_5_43, int_4_43, pp_5_43, pp_6_43, pp_7_43); - r4bs r4bs_3440_1600(yy[26], yy[27], single[8], double[8], neg[8], pp_8_43); - r4bs r4bs_3440_1728(yy[24], yy[25], single[9], double[9], neg[9], pp_9_43); - r4bs r4bs_3440_1856(yy[22], yy[23], single[10], double[10], neg[10], pp_10_43); - fullAdd_x FA_3440_1984(int_7_43, int_6_43, pp_8_43, pp_9_43, pp_10_43); - r4bs r4bs_3440_2200(yy[20], yy[21], single[11], double[11], neg[11], pp_11_43); - r4bs r4bs_3440_2328(yy[18], yy[19], single[12], double[12], neg[12], pp_12_43); - r4bs r4bs_3440_2456(yy[16], yy[17], single[13], double[13], neg[13], pp_13_43); - fullAdd_x FA_3440_2584(int_9_43, int_8_43, pp_11_43, pp_12_43, pp_13_43); - r4bs r4bs_3440_2800(yy[14], yy[15], single[14], double[14], neg[14], pp_14_43); - r4bs r4bs_3440_2928(yy[12], yy[13], single[15], double[15], neg[15], pp_15_43); - r4bs r4bs_3440_3056(yy[10], yy[11], single[16], double[16], neg[16], pp_16_43); - fullAdd_x FA_3440_3184(int_11_43, int_10_43, pp_14_43, pp_15_43, pp_16_43); - r4bs r4bs_3440_3400(yy[8], yy[9], single[17], double[17], neg[17], pp_17_43); - r4bs r4bs_3440_3528(yy[6], yy[7], single[18], double[18], neg[18], pp_18_43); - r4bs r4bs_3440_3656(yy[4], yy[5], single[19], double[19], neg[19], pp_19_43); - fullAdd_x FA_3440_3784(int_13_43, int_12_43, pp_17_43, pp_18_43, pp_19_43); - r4bs r4bs_3440_4000(yy[2], yy[3], single[20], double[20], neg[20], pp_20_43); - r4bs r4bs_3440_4128(yy[0], yy[1], single[21], double[21], neg[21], pp_21_43); - fullAdd_x FA_3440_4256(int_15_43, int_14_43, pp_20_43, pp_21_43, int_1_42); - fullAdd_x FA_3440_4472(int_17_43, int_16_43, int_3_42, int_5_42, int_7_42); - fullAdd_x FA_3440_4688(int_19_43, int_18_43, int_9_42, int_11_42, int_13_42); - fullAdd_x FA_3440_4904(int_21_43, int_20_43, int_15_42, int_0_43, int_17_42); - fullAdd_x FA_3440_5120(int_23_43, int_22_43, int_19_42, int_2_43, int_4_43); - fullAdd_x FA_3440_5336(int_25_43, int_24_43, int_6_43, int_8_43, int_10_43); - fullAdd_x FA_3440_5552(int_27_43, int_26_43, int_12_43, int_14_43, int_21_42); - fullAdd_x FA_3440_5768(int_29_43, int_28_43, int_23_42, int_25_42, int_27_42); - fullAdd_x FA_3440_5984(int_31_43, int_30_43, int_16_43, int_18_43, int_20_43); - fullAdd_x FA_3440_6200(int_33_43, int_32_43, int_29_42, int_31_42, int_22_43); - fullAdd_x FA_3440_6416(int_35_43, int_34_43, int_24_43, int_26_43, int_33_42); - fullAdd_x FA_3440_6632(int_37_43, int_36_43, int_28_43, int_30_43, int_35_42); - fullAdd_x FA_3440_6848(int_39_43, int_38_43, int_32_43, int_34_43, int_37_42); - fullAdd_x FA_3440_7064(int_41_43, int_40_43, int_36_43, int_39_42, int_38_43); - assign Sum[43] = int_41_42; - assign Carry[43] = int_40_43; - - // Hardware for column 44 - - r4bs r4bs_3520_64(yy[43], yy[44], single[0], double[0], neg[0], pp_0_44); - halfAdd HA_3520_192(int_1_44, int_0_44, neg[22], pp_0_44); - r4bs r4bs_3520_272(yy[41], yy[42], single[1], double[1], neg[1], pp_1_44); - r4bs r4bs_3520_400(yy[39], yy[40], single[2], double[2], neg[2], pp_2_44); - r4bs r4bs_3520_528(yy[37], yy[38], single[3], double[3], neg[3], pp_3_44); - fullAdd_x FA_3520_656(int_3_44, int_2_44, pp_1_44, pp_2_44, pp_3_44); - r4bs r4bs_3520_872(yy[35], yy[36], single[4], double[4], neg[4], pp_4_44); - r4bs r4bs_3520_1000(yy[33], yy[34], single[5], double[5], neg[5], pp_5_44); - r4bs r4bs_3520_1128(yy[31], yy[32], single[6], double[6], neg[6], pp_6_44); - fullAdd_x FA_3520_1256(int_5_44, int_4_44, pp_4_44, pp_5_44, pp_6_44); - r4bs r4bs_3520_1472(yy[29], yy[30], single[7], double[7], neg[7], pp_7_44); - r4bs r4bs_3520_1600(yy[27], yy[28], single[8], double[8], neg[8], pp_8_44); - r4bs r4bs_3520_1728(yy[25], yy[26], single[9], double[9], neg[9], pp_9_44); - fullAdd_x FA_3520_1856(int_7_44, int_6_44, pp_7_44, pp_8_44, pp_9_44); - r4bs r4bs_3520_2072(yy[23], yy[24], single[10], double[10], neg[10], pp_10_44); - r4bs r4bs_3520_2200(yy[21], yy[22], single[11], double[11], neg[11], pp_11_44); - r4bs r4bs_3520_2328(yy[19], yy[20], single[12], double[12], neg[12], pp_12_44); - fullAdd_x FA_3520_2456(int_9_44, int_8_44, pp_10_44, pp_11_44, pp_12_44); - r4bs r4bs_3520_2672(yy[17], yy[18], single[13], double[13], neg[13], pp_13_44); - r4bs r4bs_3520_2800(yy[15], yy[16], single[14], double[14], neg[14], pp_14_44); - r4bs r4bs_3520_2928(yy[13], yy[14], single[15], double[15], neg[15], pp_15_44); - fullAdd_x FA_3520_3056(int_11_44, int_10_44, pp_13_44, pp_14_44, pp_15_44); - r4bs r4bs_3520_3272(yy[11], yy[12], single[16], double[16], neg[16], pp_16_44); - r4bs r4bs_3520_3400(yy[9], yy[10], single[17], double[17], neg[17], pp_17_44); - r4bs r4bs_3520_3528(yy[7], yy[8], single[18], double[18], neg[18], pp_18_44); - fullAdd_x FA_3520_3656(int_13_44, int_12_44, pp_16_44, pp_17_44, pp_18_44); - r4bs r4bs_3520_3872(yy[5], yy[6], single[19], double[19], neg[19], pp_19_44); - r4bs r4bs_3520_4000(yy[3], yy[4], single[20], double[20], neg[20], pp_20_44); - r4bs r4bs_3520_4128(yy[1], yy[2], single[21], double[21], neg[21], pp_21_44); - fullAdd_x FA_3520_4256(int_15_44, int_14_44, pp_19_44, pp_20_44, pp_21_44); - r4bs r4bs_3520_4472(gnd, yy[0], single[22], double[22], neg[22], pp_22_44); - fullAdd_x FA_3520_4600(int_17_44, int_16_44, pp_22_44, int_1_43, int_3_43); - fullAdd_x FA_3520_4816(int_19_44, int_18_44, int_5_43, int_7_43, int_9_43); - fullAdd_x FA_3520_5032(int_21_44, int_20_44, int_11_43, int_13_43, int_0_44); - fullAdd_x FA_3520_5248(int_23_44, int_22_44, int_15_43, int_17_43, int_19_43); - fullAdd_x FA_3520_5464(int_25_44, int_24_44, int_2_44, int_4_44, int_6_44); - fullAdd_x FA_3520_5680(int_27_44, int_26_44, int_8_44, int_10_44, int_12_44); - fullAdd_x FA_3520_5896(int_29_44, int_28_44, int_14_44, int_16_44, int_21_43); - fullAdd_x FA_3520_6112(int_31_44, int_30_44, int_23_43, int_25_43, int_18_44); - fullAdd_x FA_3520_6328(int_33_44, int_32_44, int_20_44, int_27_43, int_29_43); - fullAdd_x FA_3520_6544(int_35_44, int_34_44, int_31_43, int_22_44, int_24_44); - fullAdd_x FA_3520_6760(int_37_44, int_36_44, int_26_44, int_28_44, int_33_43); - fullAdd_x FA_3520_6976(int_39_44, int_38_44, int_30_44, int_35_43, int_32_44); - fullAdd_x FA_3520_7192(int_41_44, int_40_44, int_34_44, int_36_44, int_37_43); - fullAdd_x FA_3520_7408(int_43_44, int_42_44, int_39_43, int_38_44, int_40_44); - assign Sum[44] = int_41_43; - assign Carry[44] = int_42_44; - - // Hardware for column 45 - - r4bs r4bs_3600_64(yy[44], yy[45], single[0], double[0], neg[0], pp_0_45); - r4bs r4bs_3600_192(yy[42], yy[43], single[1], double[1], neg[1], pp_1_45); - halfAdd HA_3600_320(int_1_45, int_0_45, pp_0_45, pp_1_45); - r4bs r4bs_3600_400(yy[40], yy[41], single[2], double[2], neg[2], pp_2_45); - r4bs r4bs_3600_528(yy[38], yy[39], single[3], double[3], neg[3], pp_3_45); - r4bs r4bs_3600_656(yy[36], yy[37], single[4], double[4], neg[4], pp_4_45); - fullAdd_x FA_3600_784(int_3_45, int_2_45, pp_2_45, pp_3_45, pp_4_45); - r4bs r4bs_3600_1000(yy[34], yy[35], single[5], double[5], neg[5], pp_5_45); - r4bs r4bs_3600_1128(yy[32], yy[33], single[6], double[6], neg[6], pp_6_45); - r4bs r4bs_3600_1256(yy[30], yy[31], single[7], double[7], neg[7], pp_7_45); - fullAdd_x FA_3600_1384(int_5_45, int_4_45, pp_5_45, pp_6_45, pp_7_45); - r4bs r4bs_3600_1600(yy[28], yy[29], single[8], double[8], neg[8], pp_8_45); - r4bs r4bs_3600_1728(yy[26], yy[27], single[9], double[9], neg[9], pp_9_45); - r4bs r4bs_3600_1856(yy[24], yy[25], single[10], double[10], neg[10], pp_10_45); - fullAdd_x FA_3600_1984(int_7_45, int_6_45, pp_8_45, pp_9_45, pp_10_45); - r4bs r4bs_3600_2200(yy[22], yy[23], single[11], double[11], neg[11], pp_11_45); - r4bs r4bs_3600_2328(yy[20], yy[21], single[12], double[12], neg[12], pp_12_45); - r4bs r4bs_3600_2456(yy[18], yy[19], single[13], double[13], neg[13], pp_13_45); - fullAdd_x FA_3600_2584(int_9_45, int_8_45, pp_11_45, pp_12_45, pp_13_45); - r4bs r4bs_3600_2800(yy[16], yy[17], single[14], double[14], neg[14], pp_14_45); - r4bs r4bs_3600_2928(yy[14], yy[15], single[15], double[15], neg[15], pp_15_45); - r4bs r4bs_3600_3056(yy[12], yy[13], single[16], double[16], neg[16], pp_16_45); - fullAdd_x FA_3600_3184(int_11_45, int_10_45, pp_14_45, pp_15_45, pp_16_45); - r4bs r4bs_3600_3400(yy[10], yy[11], single[17], double[17], neg[17], pp_17_45); - r4bs r4bs_3600_3528(yy[8], yy[9], single[18], double[18], neg[18], pp_18_45); - r4bs r4bs_3600_3656(yy[6], yy[7], single[19], double[19], neg[19], pp_19_45); - fullAdd_x FA_3600_3784(int_13_45, int_12_45, pp_17_45, pp_18_45, pp_19_45); - r4bs r4bs_3600_4000(yy[4], yy[5], single[20], double[20], neg[20], pp_20_45); - r4bs r4bs_3600_4128(yy[2], yy[3], single[21], double[21], neg[21], pp_21_45); - r4bs r4bs_3600_4256(yy[0], yy[1], single[22], double[22], neg[22], pp_22_45); - fullAdd_x FA_3600_4384(int_15_45, int_14_45, pp_20_45, pp_21_45, pp_22_45); - fullAdd_x FA_3600_4600(int_17_45, int_16_45, int_1_44, int_3_44, int_5_44); - fullAdd_x FA_3600_4816(int_19_45, int_18_45, int_7_44, int_9_44, int_11_44); - fullAdd_x FA_3600_5032(int_21_45, int_20_45, int_13_44, int_15_44, int_0_45); - fullAdd_x FA_3600_5248(int_23_45, int_22_45, int_17_44, int_19_44, int_21_44); - fullAdd_x FA_3600_5464(int_25_45, int_24_45, int_2_45, int_4_45, int_6_45); - fullAdd_x FA_3600_5680(int_27_45, int_26_45, int_8_45, int_10_45, int_12_45); - fullAdd_x FA_3600_5896(int_29_45, int_28_45, int_14_45, int_23_44, int_25_44); - fullAdd_x FA_3600_6112(int_31_45, int_30_45, int_27_44, int_16_45, int_18_45); - fullAdd_x FA_3600_6328(int_33_45, int_32_45, int_20_45, int_29_44, int_31_44); - fullAdd_x FA_3600_6544(int_35_45, int_34_45, int_22_45, int_24_45, int_26_45); - fullAdd_x FA_3600_6760(int_37_45, int_36_45, int_33_44, int_35_44, int_28_45); - fullAdd_x FA_3600_6976(int_39_45, int_38_45, int_30_45, int_37_44, int_32_45); - fullAdd_x FA_3600_7192(int_41_45, int_40_45, int_34_45, int_39_44, int_36_45); - fullAdd_x FA_3600_7408(int_43_45, int_42_45, int_41_44, int_38_45, int_40_45); - assign Sum[45] = int_43_44; - assign Carry[45] = int_42_45; - - // Hardware for column 46 - - r4bs r4bs_3680_64(yy[45], yy[46], single[0], double[0], neg[0], pp_0_46); - halfAdd HA_3680_192(int_1_46, int_0_46, neg[23], pp_0_46); - r4bs r4bs_3680_272(yy[43], yy[44], single[1], double[1], neg[1], pp_1_46); - r4bs r4bs_3680_400(yy[41], yy[42], single[2], double[2], neg[2], pp_2_46); - r4bs r4bs_3680_528(yy[39], yy[40], single[3], double[3], neg[3], pp_3_46); - fullAdd_x FA_3680_656(int_3_46, int_2_46, pp_1_46, pp_2_46, pp_3_46); - r4bs r4bs_3680_872(yy[37], yy[38], single[4], double[4], neg[4], pp_4_46); - r4bs r4bs_3680_1000(yy[35], yy[36], single[5], double[5], neg[5], pp_5_46); - r4bs r4bs_3680_1128(yy[33], yy[34], single[6], double[6], neg[6], pp_6_46); - fullAdd_x FA_3680_1256(int_5_46, int_4_46, pp_4_46, pp_5_46, pp_6_46); - r4bs r4bs_3680_1472(yy[31], yy[32], single[7], double[7], neg[7], pp_7_46); - r4bs r4bs_3680_1600(yy[29], yy[30], single[8], double[8], neg[8], pp_8_46); - r4bs r4bs_3680_1728(yy[27], yy[28], single[9], double[9], neg[9], pp_9_46); - fullAdd_x FA_3680_1856(int_7_46, int_6_46, pp_7_46, pp_8_46, pp_9_46); - r4bs r4bs_3680_2072(yy[25], yy[26], single[10], double[10], neg[10], pp_10_46); - r4bs r4bs_3680_2200(yy[23], yy[24], single[11], double[11], neg[11], pp_11_46); - r4bs r4bs_3680_2328(yy[21], yy[22], single[12], double[12], neg[12], pp_12_46); - fullAdd_x FA_3680_2456(int_9_46, int_8_46, pp_10_46, pp_11_46, pp_12_46); - r4bs r4bs_3680_2672(yy[19], yy[20], single[13], double[13], neg[13], pp_13_46); - r4bs r4bs_3680_2800(yy[17], yy[18], single[14], double[14], neg[14], pp_14_46); - r4bs r4bs_3680_2928(yy[15], yy[16], single[15], double[15], neg[15], pp_15_46); - fullAdd_x FA_3680_3056(int_11_46, int_10_46, pp_13_46, pp_14_46, pp_15_46); - r4bs r4bs_3680_3272(yy[13], yy[14], single[16], double[16], neg[16], pp_16_46); - r4bs r4bs_3680_3400(yy[11], yy[12], single[17], double[17], neg[17], pp_17_46); - r4bs r4bs_3680_3528(yy[9], yy[10], single[18], double[18], neg[18], pp_18_46); - fullAdd_x FA_3680_3656(int_13_46, int_12_46, pp_16_46, pp_17_46, pp_18_46); - r4bs r4bs_3680_3872(yy[7], yy[8], single[19], double[19], neg[19], pp_19_46); - r4bs r4bs_3680_4000(yy[5], yy[6], single[20], double[20], neg[20], pp_20_46); - r4bs r4bs_3680_4128(yy[3], yy[4], single[21], double[21], neg[21], pp_21_46); - fullAdd_x FA_3680_4256(int_15_46, int_14_46, pp_19_46, pp_20_46, pp_21_46); - r4bs r4bs_3680_4472(yy[1], yy[2], single[22], double[22], neg[22], pp_22_46); - r4bs r4bs_3680_4600(gnd, yy[0], single[23], double[23], neg[23], pp_23_46); - fullAdd_x FA_3680_4728(int_17_46, int_16_46, pp_22_46, pp_23_46, int_1_45); - fullAdd_x FA_3680_4944(int_19_46, int_18_46, int_3_45, int_5_45, int_7_45); - fullAdd_x FA_3680_5160(int_21_46, int_20_46, int_9_45, int_11_45, int_13_45); - fullAdd_x FA_3680_5376(int_23_46, int_22_46, int_15_45, int_0_46, int_17_45); - fullAdd_x FA_3680_5592(int_25_46, int_24_46, int_19_45, int_21_45, int_2_46); - fullAdd_x FA_3680_5808(int_27_46, int_26_46, int_4_46, int_6_46, int_8_46); - fullAdd_x FA_3680_6024(int_29_46, int_28_46, int_10_46, int_12_46, int_14_46); - fullAdd_x FA_3680_6240(int_31_46, int_30_46, int_16_46, int_23_45, int_25_45); - fullAdd_x FA_3680_6456(int_33_46, int_32_46, int_27_45, int_18_46, int_20_46); - fullAdd_x FA_3680_6672(int_35_46, int_34_46, int_22_46, int_29_45, int_31_45); - fullAdd_x FA_3680_6888(int_37_46, int_36_46, int_24_46, int_26_46, int_28_46); - fullAdd_x FA_3680_7104(int_39_46, int_38_46, int_33_45, int_35_45, int_30_46); - fullAdd_x FA_3680_7320(int_41_46, int_40_46, int_32_46, int_37_45, int_34_46); - fullAdd_x FA_3680_7536(int_43_46, int_42_46, int_36_46, int_39_45, int_38_46); - fullAdd_x FA_3680_7752(int_45_46, int_44_46, int_41_45, int_40_46, int_42_46); - assign Sum[46] = int_43_45; - assign Carry[46] = int_44_46; - - // Hardware for column 47 - - r4bs r4bs_3760_64(yy[46], yy[47], single[0], double[0], neg[0], pp_0_47); - r4bs r4bs_3760_192(yy[44], yy[45], single[1], double[1], neg[1], pp_1_47); - halfAdd HA_3760_320(int_1_47, int_0_47, pp_0_47, pp_1_47); - r4bs r4bs_3760_400(yy[42], yy[43], single[2], double[2], neg[2], pp_2_47); - r4bs r4bs_3760_528(yy[40], yy[41], single[3], double[3], neg[3], pp_3_47); - r4bs r4bs_3760_656(yy[38], yy[39], single[4], double[4], neg[4], pp_4_47); - fullAdd_x FA_3760_784(int_3_47, int_2_47, pp_2_47, pp_3_47, pp_4_47); - r4bs r4bs_3760_1000(yy[36], yy[37], single[5], double[5], neg[5], pp_5_47); - r4bs r4bs_3760_1128(yy[34], yy[35], single[6], double[6], neg[6], pp_6_47); - r4bs r4bs_3760_1256(yy[32], yy[33], single[7], double[7], neg[7], pp_7_47); - fullAdd_x FA_3760_1384(int_5_47, int_4_47, pp_5_47, pp_6_47, pp_7_47); - r4bs r4bs_3760_1600(yy[30], yy[31], single[8], double[8], neg[8], pp_8_47); - r4bs r4bs_3760_1728(yy[28], yy[29], single[9], double[9], neg[9], pp_9_47); - r4bs r4bs_3760_1856(yy[26], yy[27], single[10], double[10], neg[10], pp_10_47); - fullAdd_x FA_3760_1984(int_7_47, int_6_47, pp_8_47, pp_9_47, pp_10_47); - r4bs r4bs_3760_2200(yy[24], yy[25], single[11], double[11], neg[11], pp_11_47); - r4bs r4bs_3760_2328(yy[22], yy[23], single[12], double[12], neg[12], pp_12_47); - r4bs r4bs_3760_2456(yy[20], yy[21], single[13], double[13], neg[13], pp_13_47); - fullAdd_x FA_3760_2584(int_9_47, int_8_47, pp_11_47, pp_12_47, pp_13_47); - r4bs r4bs_3760_2800(yy[18], yy[19], single[14], double[14], neg[14], pp_14_47); - r4bs r4bs_3760_2928(yy[16], yy[17], single[15], double[15], neg[15], pp_15_47); - r4bs r4bs_3760_3056(yy[14], yy[15], single[16], double[16], neg[16], pp_16_47); - fullAdd_x FA_3760_3184(int_11_47, int_10_47, pp_14_47, pp_15_47, pp_16_47); - r4bs r4bs_3760_3400(yy[12], yy[13], single[17], double[17], neg[17], pp_17_47); - r4bs r4bs_3760_3528(yy[10], yy[11], single[18], double[18], neg[18], pp_18_47); - r4bs r4bs_3760_3656(yy[8], yy[9], single[19], double[19], neg[19], pp_19_47); - fullAdd_x FA_3760_3784(int_13_47, int_12_47, pp_17_47, pp_18_47, pp_19_47); - r4bs r4bs_3760_4000(yy[6], yy[7], single[20], double[20], neg[20], pp_20_47); - r4bs r4bs_3760_4128(yy[4], yy[5], single[21], double[21], neg[21], pp_21_47); - r4bs r4bs_3760_4256(yy[2], yy[3], single[22], double[22], neg[22], pp_22_47); - fullAdd_x FA_3760_4384(int_15_47, int_14_47, pp_20_47, pp_21_47, pp_22_47); - r4bs r4bs_3760_4600(yy[0], yy[1], single[23], double[23], neg[23], pp_23_47); - fullAdd_x FA_3760_4728(int_17_47, int_16_47, pp_23_47, int_1_46, int_3_46); - fullAdd_x FA_3760_4944(int_19_47, int_18_47, int_5_46, int_7_46, int_9_46); - fullAdd_x FA_3760_5160(int_21_47, int_20_47, int_11_46, int_13_46, int_15_46); - fullAdd_x FA_3760_5376(int_23_47, int_22_47, int_0_47, int_17_46, int_19_46); - fullAdd_x FA_3760_5592(int_25_47, int_24_47, int_21_46, int_2_47, int_4_47); - fullAdd_x FA_3760_5808(int_27_47, int_26_47, int_6_47, int_8_47, int_10_47); - fullAdd_x FA_3760_6024(int_29_47, int_28_47, int_12_47, int_14_47, int_16_47); - fullAdd_x FA_3760_6240(int_31_47, int_30_47, int_23_46, int_25_46, int_27_46); - fullAdd_x FA_3760_6456(int_33_47, int_32_47, int_29_46, int_18_47, int_20_47); - fullAdd_x FA_3760_6672(int_35_47, int_34_47, int_22_47, int_31_46, int_33_46); - fullAdd_x FA_3760_6888(int_37_47, int_36_47, int_24_47, int_26_47, int_28_47); - fullAdd_x FA_3760_7104(int_39_47, int_38_47, int_35_46, int_37_46, int_30_47); - fullAdd_x FA_3760_7320(int_41_47, int_40_47, int_32_47, int_39_46, int_34_47); - fullAdd_x FA_3760_7536(int_43_47, int_42_47, int_36_47, int_41_46, int_38_47); - fullAdd_x FA_3760_7752(int_45_47, int_44_47, int_43_46, int_40_47, int_42_47); - assign Sum[47] = int_45_46; - assign Carry[47] = int_44_47; - - // Hardware for column 48 - - r4bs r4bs_3840_64(yy[47], yy[48], single[0], double[0], neg[0], pp_0_48); - halfAdd HA_3840_192(int_1_48, int_0_48, neg[24], pp_0_48); - r4bs r4bs_3840_272(yy[45], yy[46], single[1], double[1], neg[1], pp_1_48); - r4bs r4bs_3840_400(yy[43], yy[44], single[2], double[2], neg[2], pp_2_48); - r4bs r4bs_3840_528(yy[41], yy[42], single[3], double[3], neg[3], pp_3_48); - fullAdd_x FA_3840_656(int_3_48, int_2_48, pp_1_48, pp_2_48, pp_3_48); - r4bs r4bs_3840_872(yy[39], yy[40], single[4], double[4], neg[4], pp_4_48); - r4bs r4bs_3840_1000(yy[37], yy[38], single[5], double[5], neg[5], pp_5_48); - r4bs r4bs_3840_1128(yy[35], yy[36], single[6], double[6], neg[6], pp_6_48); - fullAdd_x FA_3840_1256(int_5_48, int_4_48, pp_4_48, pp_5_48, pp_6_48); - r4bs r4bs_3840_1472(yy[33], yy[34], single[7], double[7], neg[7], pp_7_48); - r4bs r4bs_3840_1600(yy[31], yy[32], single[8], double[8], neg[8], pp_8_48); - r4bs r4bs_3840_1728(yy[29], yy[30], single[9], double[9], neg[9], pp_9_48); - fullAdd_x FA_3840_1856(int_7_48, int_6_48, pp_7_48, pp_8_48, pp_9_48); - r4bs r4bs_3840_2072(yy[27], yy[28], single[10], double[10], neg[10], pp_10_48); - r4bs r4bs_3840_2200(yy[25], yy[26], single[11], double[11], neg[11], pp_11_48); - r4bs r4bs_3840_2328(yy[23], yy[24], single[12], double[12], neg[12], pp_12_48); - fullAdd_x FA_3840_2456(int_9_48, int_8_48, pp_10_48, pp_11_48, pp_12_48); - r4bs r4bs_3840_2672(yy[21], yy[22], single[13], double[13], neg[13], pp_13_48); - r4bs r4bs_3840_2800(yy[19], yy[20], single[14], double[14], neg[14], pp_14_48); - r4bs r4bs_3840_2928(yy[17], yy[18], single[15], double[15], neg[15], pp_15_48); - fullAdd_x FA_3840_3056(int_11_48, int_10_48, pp_13_48, pp_14_48, pp_15_48); - r4bs r4bs_3840_3272(yy[15], yy[16], single[16], double[16], neg[16], pp_16_48); - r4bs r4bs_3840_3400(yy[13], yy[14], single[17], double[17], neg[17], pp_17_48); - r4bs r4bs_3840_3528(yy[11], yy[12], single[18], double[18], neg[18], pp_18_48); - fullAdd_x FA_3840_3656(int_13_48, int_12_48, pp_16_48, pp_17_48, pp_18_48); - r4bs r4bs_3840_3872(yy[9], yy[10], single[19], double[19], neg[19], pp_19_48); - r4bs r4bs_3840_4000(yy[7], yy[8], single[20], double[20], neg[20], pp_20_48); - r4bs r4bs_3840_4128(yy[5], yy[6], single[21], double[21], neg[21], pp_21_48); - fullAdd_x FA_3840_4256(int_15_48, int_14_48, pp_19_48, pp_20_48, pp_21_48); - r4bs r4bs_3840_4472(yy[3], yy[4], single[22], double[22], neg[22], pp_22_48); - r4bs r4bs_3840_4600(yy[1], yy[2], single[23], double[23], neg[23], pp_23_48); - r4bs r4bs_3840_4728(gnd, yy[0], single[24], double[24], neg[24], pp_24_48); - fullAdd_x FA_3840_4856(int_17_48, int_16_48, pp_22_48, pp_23_48, pp_24_48); - fullAdd_x FA_3840_5072(int_19_48, int_18_48, int_1_47, int_3_47, int_5_47); - fullAdd_x FA_3840_5288(int_21_48, int_20_48, int_7_47, int_9_47, int_11_47); - fullAdd_x FA_3840_5504(int_23_48, int_22_48, int_13_47, int_15_47, int_0_48); - fullAdd_x FA_3840_5720(int_25_48, int_24_48, int_17_47, int_19_47, int_21_47); - fullAdd_x FA_3840_5936(int_27_48, int_26_48, int_2_48, int_4_48, int_6_48); - fullAdd_x FA_3840_6152(int_29_48, int_28_48, int_8_48, int_10_48, int_12_48); - fullAdd_x FA_3840_6368(int_31_48, int_30_48, int_14_48, int_16_48, int_23_47); - fullAdd_x FA_3840_6584(int_33_48, int_32_48, int_25_47, int_27_47, int_18_48); - fullAdd_x FA_3840_6800(int_35_48, int_34_48, int_20_48, int_22_48, int_29_47); - fullAdd_x FA_3840_7016(int_37_48, int_36_48, int_31_47, int_33_47, int_24_48); - fullAdd_x FA_3840_7232(int_39_48, int_38_48, int_26_48, int_28_48, int_30_48); - fullAdd_x FA_3840_7448(int_41_48, int_40_48, int_35_47, int_37_47, int_32_48); - fullAdd_x FA_3840_7664(int_43_48, int_42_48, int_34_48, int_39_47, int_36_48); - fullAdd_x FA_3840_7880(int_45_48, int_44_48, int_38_48, int_41_47, int_40_48); - fullAdd_x FA_3840_8096(int_47_48, int_46_48, int_43_47, int_42_48, int_44_48); - assign Sum[48] = int_45_47; - assign Carry[48] = int_46_48; - - // Hardware for column 49 - - r4bs r4bs_3920_64(yy[48], yy[49], single[0], double[0], neg[0], pp_0_49); - r4bs r4bs_3920_192(yy[46], yy[47], single[1], double[1], neg[1], pp_1_49); - halfAdd HA_3920_320(int_1_49, int_0_49, pp_0_49, pp_1_49); - r4bs r4bs_3920_400(yy[44], yy[45], single[2], double[2], neg[2], pp_2_49); - r4bs r4bs_3920_528(yy[42], yy[43], single[3], double[3], neg[3], pp_3_49); - r4bs r4bs_3920_656(yy[40], yy[41], single[4], double[4], neg[4], pp_4_49); - fullAdd_x FA_3920_784(int_3_49, int_2_49, pp_2_49, pp_3_49, pp_4_49); - r4bs r4bs_3920_1000(yy[38], yy[39], single[5], double[5], neg[5], pp_5_49); - r4bs r4bs_3920_1128(yy[36], yy[37], single[6], double[6], neg[6], pp_6_49); - r4bs r4bs_3920_1256(yy[34], yy[35], single[7], double[7], neg[7], pp_7_49); - fullAdd_x FA_3920_1384(int_5_49, int_4_49, pp_5_49, pp_6_49, pp_7_49); - r4bs r4bs_3920_1600(yy[32], yy[33], single[8], double[8], neg[8], pp_8_49); - r4bs r4bs_3920_1728(yy[30], yy[31], single[9], double[9], neg[9], pp_9_49); - r4bs r4bs_3920_1856(yy[28], yy[29], single[10], double[10], neg[10], pp_10_49); - fullAdd_x FA_3920_1984(int_7_49, int_6_49, pp_8_49, pp_9_49, pp_10_49); - r4bs r4bs_3920_2200(yy[26], yy[27], single[11], double[11], neg[11], pp_11_49); - r4bs r4bs_3920_2328(yy[24], yy[25], single[12], double[12], neg[12], pp_12_49); - r4bs r4bs_3920_2456(yy[22], yy[23], single[13], double[13], neg[13], pp_13_49); - fullAdd_x FA_3920_2584(int_9_49, int_8_49, pp_11_49, pp_12_49, pp_13_49); - r4bs r4bs_3920_2800(yy[20], yy[21], single[14], double[14], neg[14], pp_14_49); - r4bs r4bs_3920_2928(yy[18], yy[19], single[15], double[15], neg[15], pp_15_49); - r4bs r4bs_3920_3056(yy[16], yy[17], single[16], double[16], neg[16], pp_16_49); - fullAdd_x FA_3920_3184(int_11_49, int_10_49, pp_14_49, pp_15_49, pp_16_49); - r4bs r4bs_3920_3400(yy[14], yy[15], single[17], double[17], neg[17], pp_17_49); - r4bs r4bs_3920_3528(yy[12], yy[13], single[18], double[18], neg[18], pp_18_49); - r4bs r4bs_3920_3656(yy[10], yy[11], single[19], double[19], neg[19], pp_19_49); - fullAdd_x FA_3920_3784(int_13_49, int_12_49, pp_17_49, pp_18_49, pp_19_49); - r4bs r4bs_3920_4000(yy[8], yy[9], single[20], double[20], neg[20], pp_20_49); - r4bs r4bs_3920_4128(yy[6], yy[7], single[21], double[21], neg[21], pp_21_49); - r4bs r4bs_3920_4256(yy[4], yy[5], single[22], double[22], neg[22], pp_22_49); - fullAdd_x FA_3920_4384(int_15_49, int_14_49, pp_20_49, pp_21_49, pp_22_49); - r4bs r4bs_3920_4600(yy[2], yy[3], single[23], double[23], neg[23], pp_23_49); - r4bs r4bs_3920_4728(yy[0], yy[1], single[24], double[24], neg[24], pp_24_49); - fullAdd_x FA_3920_4856(int_17_49, int_16_49, pp_23_49, pp_24_49, int_1_48); - fullAdd_x FA_3920_5072(int_19_49, int_18_49, int_3_48, int_5_48, int_7_48); - fullAdd_x FA_3920_5288(int_21_49, int_20_49, int_9_48, int_11_48, int_13_48); - fullAdd_x FA_3920_5504(int_23_49, int_22_49, int_15_48, int_17_48, int_0_49); - fullAdd_x FA_3920_5720(int_25_49, int_24_49, int_19_48, int_21_48, int_23_48); - fullAdd_x FA_3920_5936(int_27_49, int_26_49, int_2_49, int_4_49, int_6_49); - fullAdd_x FA_3920_6152(int_29_49, int_28_49, int_8_49, int_10_49, int_12_49); - fullAdd_x FA_3920_6368(int_31_49, int_30_49, int_14_49, int_16_49, int_25_48); - fullAdd_x FA_3920_6584(int_33_49, int_32_49, int_27_48, int_29_48, int_18_49); - fullAdd_x FA_3920_6800(int_35_49, int_34_49, int_20_49, int_22_49, int_31_48); - fullAdd_x FA_3920_7016(int_37_49, int_36_49, int_33_48, int_24_49, int_26_49); - fullAdd_x FA_3920_7232(int_39_49, int_38_49, int_28_49, int_30_49, int_35_48); - fullAdd_x FA_3920_7448(int_41_49, int_40_49, int_37_48, int_39_48, int_32_49); - fullAdd_x FA_3920_7664(int_43_49, int_42_49, int_34_49, int_41_48, int_36_49); - fullAdd_x FA_3920_7880(int_45_49, int_44_49, int_38_49, int_43_48, int_40_49); - fullAdd_x FA_3920_8096(int_47_49, int_46_49, int_45_48, int_42_49, int_44_49); - assign Sum[49] = int_47_48; - assign Carry[49] = int_46_49; - - // Hardware for column 50 - - r4bs r4bs_4000_64(yy[49], yy[50], single[0], double[0], neg[0], pp_0_50); - halfAdd HA_4000_192(int_1_50, int_0_50, neg[25], pp_0_50); - r4bs r4bs_4000_272(yy[47], yy[48], single[1], double[1], neg[1], pp_1_50); - r4bs r4bs_4000_400(yy[45], yy[46], single[2], double[2], neg[2], pp_2_50); - r4bs r4bs_4000_528(yy[43], yy[44], single[3], double[3], neg[3], pp_3_50); - fullAdd_x FA_4000_656(int_3_50, int_2_50, pp_1_50, pp_2_50, pp_3_50); - r4bs r4bs_4000_872(yy[41], yy[42], single[4], double[4], neg[4], pp_4_50); - r4bs r4bs_4000_1000(yy[39], yy[40], single[5], double[5], neg[5], pp_5_50); - r4bs r4bs_4000_1128(yy[37], yy[38], single[6], double[6], neg[6], pp_6_50); - fullAdd_x FA_4000_1256(int_5_50, int_4_50, pp_4_50, pp_5_50, pp_6_50); - r4bs r4bs_4000_1472(yy[35], yy[36], single[7], double[7], neg[7], pp_7_50); - r4bs r4bs_4000_1600(yy[33], yy[34], single[8], double[8], neg[8], pp_8_50); - r4bs r4bs_4000_1728(yy[31], yy[32], single[9], double[9], neg[9], pp_9_50); - fullAdd_x FA_4000_1856(int_7_50, int_6_50, pp_7_50, pp_8_50, pp_9_50); - r4bs r4bs_4000_2072(yy[29], yy[30], single[10], double[10], neg[10], pp_10_50); - r4bs r4bs_4000_2200(yy[27], yy[28], single[11], double[11], neg[11], pp_11_50); - r4bs r4bs_4000_2328(yy[25], yy[26], single[12], double[12], neg[12], pp_12_50); - fullAdd_x FA_4000_2456(int_9_50, int_8_50, pp_10_50, pp_11_50, pp_12_50); - r4bs r4bs_4000_2672(yy[23], yy[24], single[13], double[13], neg[13], pp_13_50); - r4bs r4bs_4000_2800(yy[21], yy[22], single[14], double[14], neg[14], pp_14_50); - r4bs r4bs_4000_2928(yy[19], yy[20], single[15], double[15], neg[15], pp_15_50); - fullAdd_x FA_4000_3056(int_11_50, int_10_50, pp_13_50, pp_14_50, pp_15_50); - r4bs r4bs_4000_3272(yy[17], yy[18], single[16], double[16], neg[16], pp_16_50); - r4bs r4bs_4000_3400(yy[15], yy[16], single[17], double[17], neg[17], pp_17_50); - r4bs r4bs_4000_3528(yy[13], yy[14], single[18], double[18], neg[18], pp_18_50); - fullAdd_x FA_4000_3656(int_13_50, int_12_50, pp_16_50, pp_17_50, pp_18_50); - r4bs r4bs_4000_3872(yy[11], yy[12], single[19], double[19], neg[19], pp_19_50); - r4bs r4bs_4000_4000(yy[9], yy[10], single[20], double[20], neg[20], pp_20_50); - r4bs r4bs_4000_4128(yy[7], yy[8], single[21], double[21], neg[21], pp_21_50); - fullAdd_x FA_4000_4256(int_15_50, int_14_50, pp_19_50, pp_20_50, pp_21_50); - r4bs r4bs_4000_4472(yy[5], yy[6], single[22], double[22], neg[22], pp_22_50); - r4bs r4bs_4000_4600(yy[3], yy[4], single[23], double[23], neg[23], pp_23_50); - r4bs r4bs_4000_4728(yy[1], yy[2], single[24], double[24], neg[24], pp_24_50); - fullAdd_x FA_4000_4856(int_17_50, int_16_50, pp_22_50, pp_23_50, pp_24_50); - r4bs r4bs_4000_5072(gnd, yy[0], single[25], double[25], neg[25], pp_25_50); - fullAdd_x FA_4000_5200(int_19_50, int_18_50, pp_25_50, int_1_49, int_3_49); - fullAdd_x FA_4000_5416(int_21_50, int_20_50, int_5_49, int_7_49, int_9_49); - fullAdd_x FA_4000_5632(int_23_50, int_22_50, int_11_49, int_13_49, int_15_49); - fullAdd_x FA_4000_5848(int_25_50, int_24_50, int_0_50, int_17_49, int_19_49); - fullAdd_x FA_4000_6064(int_27_50, int_26_50, int_21_49, int_23_49, int_2_50); - fullAdd_x FA_4000_6280(int_29_50, int_28_50, int_4_50, int_6_50, int_8_50); - fullAdd_x FA_4000_6496(int_31_50, int_30_50, int_10_50, int_12_50, int_14_50); - fullAdd_x FA_4000_6712(int_33_50, int_32_50, int_16_50, int_18_50, int_25_49); - fullAdd_x FA_4000_6928(int_35_50, int_34_50, int_27_49, int_29_49, int_20_50); - fullAdd_x FA_4000_7144(int_37_50, int_36_50, int_22_50, int_24_50, int_31_49); - fullAdd_x FA_4000_7360(int_39_50, int_38_50, int_33_49, int_26_50, int_28_50); - fullAdd_x FA_4000_7576(int_41_50, int_40_50, int_30_50, int_32_50, int_35_49); - fullAdd_x FA_4000_7792(int_43_50, int_42_50, int_37_49, int_34_50, int_39_49); - fullAdd_x FA_4000_8008(int_45_50, int_44_50, int_36_50, int_41_49, int_38_50); - fullAdd_x FA_4000_8224(int_47_50, int_46_50, int_40_50, int_43_49, int_42_50); - fullAdd_x FA_4000_8440(int_49_50, int_48_50, int_45_49, int_44_50, int_46_50); - assign Sum[50] = int_47_49; - assign Carry[50] = int_48_50; - - // Hardware for column 51 - - r4bs r4bs_4080_64(yy[50], yy[51], single[0], double[0], neg[0], pp_0_51); - r4bs r4bs_4080_192(yy[48], yy[49], single[1], double[1], neg[1], pp_1_51); - halfAdd HA_4080_320(int_1_51, int_0_51, pp_0_51, pp_1_51); - r4bs r4bs_4080_400(yy[46], yy[47], single[2], double[2], neg[2], pp_2_51); - r4bs r4bs_4080_528(yy[44], yy[45], single[3], double[3], neg[3], pp_3_51); - r4bs r4bs_4080_656(yy[42], yy[43], single[4], double[4], neg[4], pp_4_51); - fullAdd_x FA_4080_784(int_3_51, int_2_51, pp_2_51, pp_3_51, pp_4_51); - r4bs r4bs_4080_1000(yy[40], yy[41], single[5], double[5], neg[5], pp_5_51); - r4bs r4bs_4080_1128(yy[38], yy[39], single[6], double[6], neg[6], pp_6_51); - r4bs r4bs_4080_1256(yy[36], yy[37], single[7], double[7], neg[7], pp_7_51); - fullAdd_x FA_4080_1384(int_5_51, int_4_51, pp_5_51, pp_6_51, pp_7_51); - r4bs r4bs_4080_1600(yy[34], yy[35], single[8], double[8], neg[8], pp_8_51); - r4bs r4bs_4080_1728(yy[32], yy[33], single[9], double[9], neg[9], pp_9_51); - r4bs r4bs_4080_1856(yy[30], yy[31], single[10], double[10], neg[10], pp_10_51); - fullAdd_x FA_4080_1984(int_7_51, int_6_51, pp_8_51, pp_9_51, pp_10_51); - r4bs r4bs_4080_2200(yy[28], yy[29], single[11], double[11], neg[11], pp_11_51); - r4bs r4bs_4080_2328(yy[26], yy[27], single[12], double[12], neg[12], pp_12_51); - r4bs r4bs_4080_2456(yy[24], yy[25], single[13], double[13], neg[13], pp_13_51); - fullAdd_x FA_4080_2584(int_9_51, int_8_51, pp_11_51, pp_12_51, pp_13_51); - r4bs r4bs_4080_2800(yy[22], yy[23], single[14], double[14], neg[14], pp_14_51); - r4bs r4bs_4080_2928(yy[20], yy[21], single[15], double[15], neg[15], pp_15_51); - r4bs r4bs_4080_3056(yy[18], yy[19], single[16], double[16], neg[16], pp_16_51); - fullAdd_x FA_4080_3184(int_11_51, int_10_51, pp_14_51, pp_15_51, pp_16_51); - r4bs r4bs_4080_3400(yy[16], yy[17], single[17], double[17], neg[17], pp_17_51); - r4bs r4bs_4080_3528(yy[14], yy[15], single[18], double[18], neg[18], pp_18_51); - r4bs r4bs_4080_3656(yy[12], yy[13], single[19], double[19], neg[19], pp_19_51); - fullAdd_x FA_4080_3784(int_13_51, int_12_51, pp_17_51, pp_18_51, pp_19_51); - r4bs r4bs_4080_4000(yy[10], yy[11], single[20], double[20], neg[20], pp_20_51); - r4bs r4bs_4080_4128(yy[8], yy[9], single[21], double[21], neg[21], pp_21_51); - r4bs r4bs_4080_4256(yy[6], yy[7], single[22], double[22], neg[22], pp_22_51); - fullAdd_x FA_4080_4384(int_15_51, int_14_51, pp_20_51, pp_21_51, pp_22_51); - r4bs r4bs_4080_4600(yy[4], yy[5], single[23], double[23], neg[23], pp_23_51); - r4bs r4bs_4080_4728(yy[2], yy[3], single[24], double[24], neg[24], pp_24_51); - r4bs r4bs_4080_4856(yy[0], yy[1], single[25], double[25], neg[25], pp_25_51); - fullAdd_x FA_4080_4984(int_17_51, int_16_51, pp_23_51, pp_24_51, pp_25_51); - fullAdd_x FA_4080_5200(int_19_51, int_18_51, int_1_50, int_3_50, int_5_50); - fullAdd_x FA_4080_5416(int_21_51, int_20_51, int_7_50, int_9_50, int_11_50); - fullAdd_x FA_4080_5632(int_23_51, int_22_51, int_13_50, int_15_50, int_17_50); - fullAdd_x FA_4080_5848(int_25_51, int_24_51, int_0_51, int_19_50, int_21_50); - fullAdd_x FA_4080_6064(int_27_51, int_26_51, int_23_50, int_2_51, int_4_51); - fullAdd_x FA_4080_6280(int_29_51, int_28_51, int_6_51, int_8_51, int_10_51); - fullAdd_x FA_4080_6496(int_31_51, int_30_51, int_12_51, int_14_51, int_16_51); - fullAdd_x FA_4080_6712(int_33_51, int_32_51, int_25_50, int_27_50, int_29_50); - fullAdd_x FA_4080_6928(int_35_51, int_34_51, int_31_50, int_18_51, int_20_51); - fullAdd_x FA_4080_7144(int_37_51, int_36_51, int_22_51, int_33_50, int_35_50); - fullAdd_x FA_4080_7360(int_39_51, int_38_51, int_24_51, int_26_51, int_28_51); - fullAdd_x FA_4080_7576(int_41_51, int_40_51, int_30_51, int_37_50, int_39_50); - fullAdd_x FA_4080_7792(int_43_51, int_42_51, int_32_51, int_34_51, int_41_50); - fullAdd_x FA_4080_8008(int_45_51, int_44_51, int_36_51, int_38_51, int_43_50); - fullAdd_x FA_4080_8224(int_47_51, int_46_51, int_45_50, int_40_51, int_42_51); - fullAdd_x FA_4080_8440(int_49_51, int_48_51, int_47_50, int_44_51, int_46_51); - assign Sum[51] = int_49_50; - assign Carry[51] = int_48_51; - - // Hardware for column 52 - - r4bs r4bs_4160_64(yy[51], yy[52], single[0], double[0], neg[0], pp_0_52); - halfAdd HA_4160_192(int_1_52, int_0_52, neg[26], pp_0_52); - r4bs r4bs_4160_272(yy[49], yy[50], single[1], double[1], neg[1], pp_1_52); - r4bs r4bs_4160_400(yy[47], yy[48], single[2], double[2], neg[2], pp_2_52); - r4bs r4bs_4160_528(yy[45], yy[46], single[3], double[3], neg[3], pp_3_52); - fullAdd_x FA_4160_656(int_3_52, int_2_52, pp_1_52, pp_2_52, pp_3_52); - r4bs r4bs_4160_872(yy[43], yy[44], single[4], double[4], neg[4], pp_4_52); - r4bs r4bs_4160_1000(yy[41], yy[42], single[5], double[5], neg[5], pp_5_52); - r4bs r4bs_4160_1128(yy[39], yy[40], single[6], double[6], neg[6], pp_6_52); - fullAdd_x FA_4160_1256(int_5_52, int_4_52, pp_4_52, pp_5_52, pp_6_52); - r4bs r4bs_4160_1472(yy[37], yy[38], single[7], double[7], neg[7], pp_7_52); - r4bs r4bs_4160_1600(yy[35], yy[36], single[8], double[8], neg[8], pp_8_52); - r4bs r4bs_4160_1728(yy[33], yy[34], single[9], double[9], neg[9], pp_9_52); - fullAdd_x FA_4160_1856(int_7_52, int_6_52, pp_7_52, pp_8_52, pp_9_52); - r4bs r4bs_4160_2072(yy[31], yy[32], single[10], double[10], neg[10], pp_10_52); - r4bs r4bs_4160_2200(yy[29], yy[30], single[11], double[11], neg[11], pp_11_52); - r4bs r4bs_4160_2328(yy[27], yy[28], single[12], double[12], neg[12], pp_12_52); - fullAdd_x FA_4160_2456(int_9_52, int_8_52, pp_10_52, pp_11_52, pp_12_52); - r4bs r4bs_4160_2672(yy[25], yy[26], single[13], double[13], neg[13], pp_13_52); - r4bs r4bs_4160_2800(yy[23], yy[24], single[14], double[14], neg[14], pp_14_52); - r4bs r4bs_4160_2928(yy[21], yy[22], single[15], double[15], neg[15], pp_15_52); - fullAdd_x FA_4160_3056(int_11_52, int_10_52, pp_13_52, pp_14_52, pp_15_52); - r4bs r4bs_4160_3272(yy[19], yy[20], single[16], double[16], neg[16], pp_16_52); - r4bs r4bs_4160_3400(yy[17], yy[18], single[17], double[17], neg[17], pp_17_52); - r4bs r4bs_4160_3528(yy[15], yy[16], single[18], double[18], neg[18], pp_18_52); - fullAdd_x FA_4160_3656(int_13_52, int_12_52, pp_16_52, pp_17_52, pp_18_52); - r4bs r4bs_4160_3872(yy[13], yy[14], single[19], double[19], neg[19], pp_19_52); - r4bs r4bs_4160_4000(yy[11], yy[12], single[20], double[20], neg[20], pp_20_52); - r4bs r4bs_4160_4128(yy[9], yy[10], single[21], double[21], neg[21], pp_21_52); - fullAdd_x FA_4160_4256(int_15_52, int_14_52, pp_19_52, pp_20_52, pp_21_52); - r4bs r4bs_4160_4472(yy[7], yy[8], single[22], double[22], neg[22], pp_22_52); - r4bs r4bs_4160_4600(yy[5], yy[6], single[23], double[23], neg[23], pp_23_52); - r4bs r4bs_4160_4728(yy[3], yy[4], single[24], double[24], neg[24], pp_24_52); - fullAdd_x FA_4160_4856(int_17_52, int_16_52, pp_22_52, pp_23_52, pp_24_52); - r4bs r4bs_4160_5072(yy[1], yy[2], single[25], double[25], neg[25], pp_25_52); - r4bs r4bs_4160_5200(gnd, yy[0], single[26], double[26], neg[26], pp_26_52); - fullAdd_x FA_4160_5328(int_19_52, int_18_52, pp_25_52, pp_26_52, int_1_51); - fullAdd_x FA_4160_5544(int_21_52, int_20_52, int_3_51, int_5_51, int_7_51); - fullAdd_x FA_4160_5760(int_23_52, int_22_52, int_9_51, int_11_51, int_13_51); - fullAdd_x FA_4160_5976(int_25_52, int_24_52, int_15_51, int_17_51, int_0_52); - fullAdd_x FA_4160_6192(int_27_52, int_26_52, int_19_51, int_21_51, int_23_51); - fullAdd_x FA_4160_6408(int_29_52, int_28_52, int_2_52, int_4_52, int_6_52); - fullAdd_x FA_4160_6624(int_31_52, int_30_52, int_8_52, int_10_52, int_12_52); - fullAdd_x FA_4160_6840(int_33_52, int_32_52, int_14_52, int_16_52, int_18_52); - fullAdd_x FA_4160_7056(int_35_52, int_34_52, int_25_51, int_27_51, int_29_51); - fullAdd_x FA_4160_7272(int_37_52, int_36_52, int_31_51, int_20_52, int_22_52); - fullAdd_x FA_4160_7488(int_39_52, int_38_52, int_24_52, int_33_51, int_35_51); - fullAdd_x FA_4160_7704(int_41_52, int_40_52, int_26_52, int_28_52, int_30_52); - fullAdd_x FA_4160_7920(int_43_52, int_42_52, int_32_52, int_37_51, int_39_51); - fullAdd_x FA_4160_8136(int_45_52, int_44_52, int_34_52, int_36_52, int_41_51); - fullAdd_x FA_4160_8352(int_47_52, int_46_52, int_38_52, int_40_52, int_43_51); - fullAdd_x FA_4160_8568(int_49_52, int_48_52, int_42_52, int_44_52, int_45_51); - fullAdd_x FA_4160_8784(int_51_52, int_50_52, int_47_51, int_46_52, int_48_52); - assign Sum[52] = int_49_51; - assign Carry[52] = int_50_52; - - // Hardware for column 53 - - r4bs r4bs_4240_64(yy[52], yy[53], single[0], double[0], neg[0], pp_0_53); - r4bs r4bs_4240_192(yy[50], yy[51], single[1], double[1], neg[1], pp_1_53); - halfAdd HA_4240_320(int_1_53, int_0_53, pp_0_53, pp_1_53); - r4bs r4bs_4240_400(yy[48], yy[49], single[2], double[2], neg[2], pp_2_53); - r4bs r4bs_4240_528(yy[46], yy[47], single[3], double[3], neg[3], pp_3_53); - r4bs r4bs_4240_656(yy[44], yy[45], single[4], double[4], neg[4], pp_4_53); - fullAdd_x FA_4240_784(int_3_53, int_2_53, pp_2_53, pp_3_53, pp_4_53); - r4bs r4bs_4240_1000(yy[42], yy[43], single[5], double[5], neg[5], pp_5_53); - r4bs r4bs_4240_1128(yy[40], yy[41], single[6], double[6], neg[6], pp_6_53); - r4bs r4bs_4240_1256(yy[38], yy[39], single[7], double[7], neg[7], pp_7_53); - fullAdd_x FA_4240_1384(int_5_53, int_4_53, pp_5_53, pp_6_53, pp_7_53); - r4bs r4bs_4240_1600(yy[36], yy[37], single[8], double[8], neg[8], pp_8_53); - r4bs r4bs_4240_1728(yy[34], yy[35], single[9], double[9], neg[9], pp_9_53); - r4bs r4bs_4240_1856(yy[32], yy[33], single[10], double[10], neg[10], pp_10_53); - fullAdd_x FA_4240_1984(int_7_53, int_6_53, pp_8_53, pp_9_53, pp_10_53); - r4bs r4bs_4240_2200(yy[30], yy[31], single[11], double[11], neg[11], pp_11_53); - r4bs r4bs_4240_2328(yy[28], yy[29], single[12], double[12], neg[12], pp_12_53); - r4bs r4bs_4240_2456(yy[26], yy[27], single[13], double[13], neg[13], pp_13_53); - fullAdd_x FA_4240_2584(int_9_53, int_8_53, pp_11_53, pp_12_53, pp_13_53); - r4bs r4bs_4240_2800(yy[24], yy[25], single[14], double[14], neg[14], pp_14_53); - r4bs r4bs_4240_2928(yy[22], yy[23], single[15], double[15], neg[15], pp_15_53); - r4bs r4bs_4240_3056(yy[20], yy[21], single[16], double[16], neg[16], pp_16_53); - fullAdd_x FA_4240_3184(int_11_53, int_10_53, pp_14_53, pp_15_53, pp_16_53); - r4bs r4bs_4240_3400(yy[18], yy[19], single[17], double[17], neg[17], pp_17_53); - r4bs r4bs_4240_3528(yy[16], yy[17], single[18], double[18], neg[18], pp_18_53); - r4bs r4bs_4240_3656(yy[14], yy[15], single[19], double[19], neg[19], pp_19_53); - fullAdd_x FA_4240_3784(int_13_53, int_12_53, pp_17_53, pp_18_53, pp_19_53); - r4bs r4bs_4240_4000(yy[12], yy[13], single[20], double[20], neg[20], pp_20_53); - r4bs r4bs_4240_4128(yy[10], yy[11], single[21], double[21], neg[21], pp_21_53); - r4bs r4bs_4240_4256(yy[8], yy[9], single[22], double[22], neg[22], pp_22_53); - fullAdd_x FA_4240_4384(int_15_53, int_14_53, pp_20_53, pp_21_53, pp_22_53); - r4bs r4bs_4240_4600(yy[6], yy[7], single[23], double[23], neg[23], pp_23_53); - r4bs r4bs_4240_4728(yy[4], yy[5], single[24], double[24], neg[24], pp_24_53); - r4bs r4bs_4240_4856(yy[2], yy[3], single[25], double[25], neg[25], pp_25_53); - fullAdd_x FA_4240_4984(int_17_53, int_16_53, pp_23_53, pp_24_53, pp_25_53); - r4bs r4bs_4240_5200(yy[0], yy[1], single[26], double[26], neg[26], pp_26_53); - fullAdd_x FA_4240_5328(int_19_53, int_18_53, pp_26_53, int_1_52, int_3_52); - fullAdd_x FA_4240_5544(int_21_53, int_20_53, int_5_52, int_7_52, int_9_52); - fullAdd_x FA_4240_5760(int_23_53, int_22_53, int_11_52, int_13_52, int_15_52); - fullAdd_x FA_4240_5976(int_25_53, int_24_53, int_17_52, int_0_53, int_19_52); - fullAdd_x FA_4240_6192(int_27_53, int_26_53, int_21_52, int_23_52, int_25_52); - fullAdd_x FA_4240_6408(int_29_53, int_28_53, int_2_53, int_4_53, int_6_53); - fullAdd_x FA_4240_6624(int_31_53, int_30_53, int_8_53, int_10_53, int_12_53); - fullAdd_x FA_4240_6840(int_33_53, int_32_53, int_14_53, int_16_53, int_18_53); - fullAdd_x FA_4240_7056(int_35_53, int_34_53, int_27_52, int_29_52, int_31_52); - fullAdd_x FA_4240_7272(int_37_53, int_36_53, int_33_52, int_20_53, int_22_53); - fullAdd_x FA_4240_7488(int_39_53, int_38_53, int_24_53, int_35_52, int_37_52); - fullAdd_x FA_4240_7704(int_41_53, int_40_53, int_26_53, int_28_53, int_30_53); - fullAdd_x FA_4240_7920(int_43_53, int_42_53, int_32_53, int_39_52, int_41_52); - fullAdd_x FA_4240_8136(int_45_53, int_44_53, int_34_53, int_36_53, int_43_52); - fullAdd_x FA_4240_8352(int_47_53, int_46_53, int_38_53, int_40_53, int_45_52); - fullAdd_x FA_4240_8568(int_49_53, int_48_53, int_42_53, int_44_53, int_47_52); - fullAdd_x FA_4240_8784(int_51_53, int_50_53, int_46_53, int_49_52, int_48_53); - assign Sum[53] = int_51_52; - assign Carry[53] = int_50_53; - - // Hardware for column 54 - - r4bs r4bs_4320_64(yy[53], yy[54], single[0], double[0], neg[0], pp_0_54); - halfAdd HA_4320_192(int_1_54, int_0_54, neg[27], pp_0_54); - r4bs r4bs_4320_272(yy[51], yy[52], single[1], double[1], neg[1], pp_1_54); - r4bs r4bs_4320_400(yy[49], yy[50], single[2], double[2], neg[2], pp_2_54); - r4bs r4bs_4320_528(yy[47], yy[48], single[3], double[3], neg[3], pp_3_54); - fullAdd_x FA_4320_656(int_3_54, int_2_54, pp_1_54, pp_2_54, pp_3_54); - r4bs r4bs_4320_872(yy[45], yy[46], single[4], double[4], neg[4], pp_4_54); - r4bs r4bs_4320_1000(yy[43], yy[44], single[5], double[5], neg[5], pp_5_54); - r4bs r4bs_4320_1128(yy[41], yy[42], single[6], double[6], neg[6], pp_6_54); - fullAdd_x FA_4320_1256(int_5_54, int_4_54, pp_4_54, pp_5_54, pp_6_54); - r4bs r4bs_4320_1472(yy[39], yy[40], single[7], double[7], neg[7], pp_7_54); - r4bs r4bs_4320_1600(yy[37], yy[38], single[8], double[8], neg[8], pp_8_54); - r4bs r4bs_4320_1728(yy[35], yy[36], single[9], double[9], neg[9], pp_9_54); - fullAdd_x FA_4320_1856(int_7_54, int_6_54, pp_7_54, pp_8_54, pp_9_54); - r4bs r4bs_4320_2072(yy[33], yy[34], single[10], double[10], neg[10], pp_10_54); - r4bs r4bs_4320_2200(yy[31], yy[32], single[11], double[11], neg[11], pp_11_54); - r4bs r4bs_4320_2328(yy[29], yy[30], single[12], double[12], neg[12], pp_12_54); - fullAdd_x FA_4320_2456(int_9_54, int_8_54, pp_10_54, pp_11_54, pp_12_54); - r4bs r4bs_4320_2672(yy[27], yy[28], single[13], double[13], neg[13], pp_13_54); - r4bs r4bs_4320_2800(yy[25], yy[26], single[14], double[14], neg[14], pp_14_54); - r4bs r4bs_4320_2928(yy[23], yy[24], single[15], double[15], neg[15], pp_15_54); - fullAdd_x FA_4320_3056(int_11_54, int_10_54, pp_13_54, pp_14_54, pp_15_54); - r4bs r4bs_4320_3272(yy[21], yy[22], single[16], double[16], neg[16], pp_16_54); - r4bs r4bs_4320_3400(yy[19], yy[20], single[17], double[17], neg[17], pp_17_54); - r4bs r4bs_4320_3528(yy[17], yy[18], single[18], double[18], neg[18], pp_18_54); - fullAdd_x FA_4320_3656(int_13_54, int_12_54, pp_16_54, pp_17_54, pp_18_54); - r4bs r4bs_4320_3872(yy[15], yy[16], single[19], double[19], neg[19], pp_19_54); - r4bs r4bs_4320_4000(yy[13], yy[14], single[20], double[20], neg[20], pp_20_54); - r4bs r4bs_4320_4128(yy[11], yy[12], single[21], double[21], neg[21], pp_21_54); - fullAdd_x FA_4320_4256(int_15_54, int_14_54, pp_19_54, pp_20_54, pp_21_54); - r4bs r4bs_4320_4472(yy[9], yy[10], single[22], double[22], neg[22], pp_22_54); - r4bs r4bs_4320_4600(yy[7], yy[8], single[23], double[23], neg[23], pp_23_54); - r4bs r4bs_4320_4728(yy[5], yy[6], single[24], double[24], neg[24], pp_24_54); - fullAdd_x FA_4320_4856(int_17_54, int_16_54, pp_22_54, pp_23_54, pp_24_54); - r4bs r4bs_4320_5072(yy[3], yy[4], single[25], double[25], neg[25], pp_25_54); - r4bs r4bs_4320_5200(yy[1], yy[2], single[26], double[26], neg[26], pp_26_54); - r4bs r4bs_4320_5328(gnd, yy[0], single[27], double[27], neg[27], pp_27_54); - fullAdd_x FA_4320_5456(int_19_54, int_18_54, pp_25_54, pp_26_54, pp_27_54); - fullAdd_x FA_4320_5672(int_21_54, int_20_54, int_1_53, int_3_53, int_5_53); - fullAdd_x FA_4320_5888(int_23_54, int_22_54, int_7_53, int_9_53, int_11_53); - fullAdd_x FA_4320_6104(int_25_54, int_24_54, int_13_53, int_15_53, int_17_53); - fullAdd_x FA_4320_6320(int_27_54, int_26_54, int_0_54, int_19_53, int_21_53); - fullAdd_x FA_4320_6536(int_29_54, int_28_54, int_23_53, int_2_54, int_4_54); - fullAdd_x FA_4320_6752(int_31_54, int_30_54, int_6_54, int_8_54, int_10_54); - fullAdd_x FA_4320_6968(int_33_54, int_32_54, int_12_54, int_14_54, int_16_54); - fullAdd_x FA_4320_7184(int_35_54, int_34_54, int_18_54, int_25_53, int_27_53); - fullAdd_x FA_4320_7400(int_37_54, int_36_54, int_29_53, int_31_53, int_20_54); - fullAdd_x FA_4320_7616(int_39_54, int_38_54, int_22_54, int_24_54, int_33_53); - fullAdd_x FA_4320_7832(int_41_54, int_40_54, int_35_53, int_37_53, int_26_54); - fullAdd_x FA_4320_8048(int_43_54, int_42_54, int_28_54, int_30_54, int_32_54); - fullAdd_x FA_4320_8264(int_45_54, int_44_54, int_34_54, int_39_53, int_41_53); - fullAdd_x FA_4320_8480(int_47_54, int_46_54, int_36_54, int_38_54, int_43_53); - fullAdd_x FA_4320_8696(int_49_54, int_48_54, int_40_54, int_42_54, int_45_53); - fullAdd_x FA_4320_8912(int_51_54, int_50_54, int_44_54, int_46_54, int_47_53); - fullAdd_x FA_4320_9128(int_53_54, int_52_54, int_48_54, int_49_53, int_50_54); - assign Sum[54] = int_51_53; - assign Carry[54] = int_52_54; - - // Hardware for column 55 - - r4bs r4bs_4400_64(yy[54], yy[55], single[0], double[0], neg[0], pp_0_55); - r4bs r4bs_4400_192(yy[52], yy[53], single[1], double[1], neg[1], pp_1_55); - halfAdd HA_4400_320(int_1_55, int_0_55, pp_0_55, pp_1_55); - r4bs r4bs_4400_400(yy[50], yy[51], single[2], double[2], neg[2], pp_2_55); - r4bs r4bs_4400_528(yy[48], yy[49], single[3], double[3], neg[3], pp_3_55); - r4bs r4bs_4400_656(yy[46], yy[47], single[4], double[4], neg[4], pp_4_55); - fullAdd_x FA_4400_784(int_3_55, int_2_55, pp_2_55, pp_3_55, pp_4_55); - r4bs r4bs_4400_1000(yy[44], yy[45], single[5], double[5], neg[5], pp_5_55); - r4bs r4bs_4400_1128(yy[42], yy[43], single[6], double[6], neg[6], pp_6_55); - r4bs r4bs_4400_1256(yy[40], yy[41], single[7], double[7], neg[7], pp_7_55); - fullAdd_x FA_4400_1384(int_5_55, int_4_55, pp_5_55, pp_6_55, pp_7_55); - r4bs r4bs_4400_1600(yy[38], yy[39], single[8], double[8], neg[8], pp_8_55); - r4bs r4bs_4400_1728(yy[36], yy[37], single[9], double[9], neg[9], pp_9_55); - r4bs r4bs_4400_1856(yy[34], yy[35], single[10], double[10], neg[10], pp_10_55); - fullAdd_x FA_4400_1984(int_7_55, int_6_55, pp_8_55, pp_9_55, pp_10_55); - r4bs r4bs_4400_2200(yy[32], yy[33], single[11], double[11], neg[11], pp_11_55); - r4bs r4bs_4400_2328(yy[30], yy[31], single[12], double[12], neg[12], pp_12_55); - r4bs r4bs_4400_2456(yy[28], yy[29], single[13], double[13], neg[13], pp_13_55); - fullAdd_x FA_4400_2584(int_9_55, int_8_55, pp_11_55, pp_12_55, pp_13_55); - r4bs r4bs_4400_2800(yy[26], yy[27], single[14], double[14], neg[14], pp_14_55); - r4bs r4bs_4400_2928(yy[24], yy[25], single[15], double[15], neg[15], pp_15_55); - r4bs r4bs_4400_3056(yy[22], yy[23], single[16], double[16], neg[16], pp_16_55); - fullAdd_x FA_4400_3184(int_11_55, int_10_55, pp_14_55, pp_15_55, pp_16_55); - r4bs r4bs_4400_3400(yy[20], yy[21], single[17], double[17], neg[17], pp_17_55); - r4bs r4bs_4400_3528(yy[18], yy[19], single[18], double[18], neg[18], pp_18_55); - r4bs r4bs_4400_3656(yy[16], yy[17], single[19], double[19], neg[19], pp_19_55); - fullAdd_x FA_4400_3784(int_13_55, int_12_55, pp_17_55, pp_18_55, pp_19_55); - r4bs r4bs_4400_4000(yy[14], yy[15], single[20], double[20], neg[20], pp_20_55); - r4bs r4bs_4400_4128(yy[12], yy[13], single[21], double[21], neg[21], pp_21_55); - r4bs r4bs_4400_4256(yy[10], yy[11], single[22], double[22], neg[22], pp_22_55); - fullAdd_x FA_4400_4384(int_15_55, int_14_55, pp_20_55, pp_21_55, pp_22_55); - r4bs r4bs_4400_4600(yy[8], yy[9], single[23], double[23], neg[23], pp_23_55); - r4bs r4bs_4400_4728(yy[6], yy[7], single[24], double[24], neg[24], pp_24_55); - r4bs r4bs_4400_4856(yy[4], yy[5], single[25], double[25], neg[25], pp_25_55); - fullAdd_x FA_4400_4984(int_17_55, int_16_55, pp_23_55, pp_24_55, pp_25_55); - r4bs r4bs_4400_5200(yy[2], yy[3], single[26], double[26], neg[26], pp_26_55); - r4bs r4bs_4400_5328(yy[0], yy[1], single[27], double[27], neg[27], pp_27_55); - fullAdd_x FA_4400_5456(int_19_55, int_18_55, pp_26_55, pp_27_55, int_1_54); - fullAdd_x FA_4400_5672(int_21_55, int_20_55, int_3_54, int_5_54, int_7_54); - fullAdd_x FA_4400_5888(int_23_55, int_22_55, int_9_54, int_11_54, int_13_54); - fullAdd_x FA_4400_6104(int_25_55, int_24_55, int_15_54, int_17_54, int_19_54); - fullAdd_x FA_4400_6320(int_27_55, int_26_55, int_0_55, int_21_54, int_23_54); - fullAdd_x FA_4400_6536(int_29_55, int_28_55, int_25_54, int_2_55, int_4_55); - fullAdd_x FA_4400_6752(int_31_55, int_30_55, int_6_55, int_8_55, int_10_55); - fullAdd_x FA_4400_6968(int_33_55, int_32_55, int_12_55, int_14_55, int_16_55); - fullAdd_x FA_4400_7184(int_35_55, int_34_55, int_18_55, int_27_54, int_29_54); - fullAdd_x FA_4400_7400(int_37_55, int_36_55, int_31_54, int_33_54, int_20_55); - fullAdd_x FA_4400_7616(int_39_55, int_38_55, int_22_55, int_24_55, int_35_54); - fullAdd_x FA_4400_7832(int_41_55, int_40_55, int_37_54, int_26_55, int_28_55); - fullAdd_x FA_4400_8048(int_43_55, int_42_55, int_30_55, int_32_55, int_39_54); - fullAdd_x FA_4400_8264(int_45_55, int_44_55, int_41_54, int_43_54, int_34_55); - fullAdd_x FA_4400_8480(int_47_55, int_46_55, int_36_55, int_38_55, int_45_54); - fullAdd_x FA_4400_8696(int_49_55, int_48_55, int_40_55, int_42_55, int_47_54); - fullAdd_x FA_4400_8912(int_51_55, int_50_55, int_44_55, int_46_55, int_49_54); - fullAdd_x FA_4400_9128(int_53_55, int_52_55, int_48_55, int_51_54, int_50_55); - assign Sum[55] = int_53_54; - assign Carry[55] = int_52_55; - - // Hardware for column 56 - - r4bs r4bs_4480_64(yy[55], yy[56], single[0], double[0], neg[0], pp_0_56); - halfAdd HA_4480_192(int_1_56, int_0_56, neg[28], pp_0_56); - r4bs r4bs_4480_272(yy[53], yy[54], single[1], double[1], neg[1], pp_1_56); - r4bs r4bs_4480_400(yy[51], yy[52], single[2], double[2], neg[2], pp_2_56); - r4bs r4bs_4480_528(yy[49], yy[50], single[3], double[3], neg[3], pp_3_56); - fullAdd_x FA_4480_656(int_3_56, int_2_56, pp_1_56, pp_2_56, pp_3_56); - r4bs r4bs_4480_872(yy[47], yy[48], single[4], double[4], neg[4], pp_4_56); - r4bs r4bs_4480_1000(yy[45], yy[46], single[5], double[5], neg[5], pp_5_56); - r4bs r4bs_4480_1128(yy[43], yy[44], single[6], double[6], neg[6], pp_6_56); - fullAdd_x FA_4480_1256(int_5_56, int_4_56, pp_4_56, pp_5_56, pp_6_56); - r4bs r4bs_4480_1472(yy[41], yy[42], single[7], double[7], neg[7], pp_7_56); - r4bs r4bs_4480_1600(yy[39], yy[40], single[8], double[8], neg[8], pp_8_56); - r4bs r4bs_4480_1728(yy[37], yy[38], single[9], double[9], neg[9], pp_9_56); - fullAdd_x FA_4480_1856(int_7_56, int_6_56, pp_7_56, pp_8_56, pp_9_56); - r4bs r4bs_4480_2072(yy[35], yy[36], single[10], double[10], neg[10], pp_10_56); - r4bs r4bs_4480_2200(yy[33], yy[34], single[11], double[11], neg[11], pp_11_56); - r4bs r4bs_4480_2328(yy[31], yy[32], single[12], double[12], neg[12], pp_12_56); - fullAdd_x FA_4480_2456(int_9_56, int_8_56, pp_10_56, pp_11_56, pp_12_56); - r4bs r4bs_4480_2672(yy[29], yy[30], single[13], double[13], neg[13], pp_13_56); - r4bs r4bs_4480_2800(yy[27], yy[28], single[14], double[14], neg[14], pp_14_56); - r4bs r4bs_4480_2928(yy[25], yy[26], single[15], double[15], neg[15], pp_15_56); - fullAdd_x FA_4480_3056(int_11_56, int_10_56, pp_13_56, pp_14_56, pp_15_56); - r4bs r4bs_4480_3272(yy[23], yy[24], single[16], double[16], neg[16], pp_16_56); - r4bs r4bs_4480_3400(yy[21], yy[22], single[17], double[17], neg[17], pp_17_56); - r4bs r4bs_4480_3528(yy[19], yy[20], single[18], double[18], neg[18], pp_18_56); - fullAdd_x FA_4480_3656(int_13_56, int_12_56, pp_16_56, pp_17_56, pp_18_56); - r4bs r4bs_4480_3872(yy[17], yy[18], single[19], double[19], neg[19], pp_19_56); - r4bs r4bs_4480_4000(yy[15], yy[16], single[20], double[20], neg[20], pp_20_56); - r4bs r4bs_4480_4128(yy[13], yy[14], single[21], double[21], neg[21], pp_21_56); - fullAdd_x FA_4480_4256(int_15_56, int_14_56, pp_19_56, pp_20_56, pp_21_56); - r4bs r4bs_4480_4472(yy[11], yy[12], single[22], double[22], neg[22], pp_22_56); - r4bs r4bs_4480_4600(yy[9], yy[10], single[23], double[23], neg[23], pp_23_56); - r4bs r4bs_4480_4728(yy[7], yy[8], single[24], double[24], neg[24], pp_24_56); - fullAdd_x FA_4480_4856(int_17_56, int_16_56, pp_22_56, pp_23_56, pp_24_56); - r4bs r4bs_4480_5072(yy[5], yy[6], single[25], double[25], neg[25], pp_25_56); - r4bs r4bs_4480_5200(yy[3], yy[4], single[26], double[26], neg[26], pp_26_56); - r4bs r4bs_4480_5328(yy[1], yy[2], single[27], double[27], neg[27], pp_27_56); - fullAdd_x FA_4480_5456(int_19_56, int_18_56, pp_25_56, pp_26_56, pp_27_56); - r4bs r4bs_4480_5672(gnd, yy[0], single[28], double[28], neg[28], pp_28_56); - fullAdd_x FA_4480_5800(int_21_56, int_20_56, pp_28_56, int_1_55, int_3_55); - fullAdd_x FA_4480_6016(int_23_56, int_22_56, int_5_55, int_7_55, int_9_55); - fullAdd_x FA_4480_6232(int_25_56, int_24_56, int_11_55, int_13_55, int_15_55); - fullAdd_x FA_4480_6448(int_27_56, int_26_56, int_17_55, int_0_56, int_19_55); - fullAdd_x FA_4480_6664(int_29_56, int_28_56, int_21_55, int_23_55, int_25_55); - fullAdd_x FA_4480_6880(int_31_56, int_30_56, int_2_56, int_4_56, int_6_56); - fullAdd_x FA_4480_7096(int_33_56, int_32_56, int_8_56, int_10_56, int_12_56); - fullAdd_x FA_4480_7312(int_35_56, int_34_56, int_14_56, int_16_56, int_18_56); - fullAdd_x FA_4480_7528(int_37_56, int_36_56, int_20_56, int_27_55, int_29_55); - fullAdd_x FA_4480_7744(int_39_56, int_38_56, int_31_55, int_33_55, int_22_56); - fullAdd_x FA_4480_7960(int_41_56, int_40_56, int_24_56, int_26_56, int_35_55); - fullAdd_x FA_4480_8176(int_43_56, int_42_56, int_37_55, int_28_56, int_30_56); - fullAdd_x FA_4480_8392(int_45_56, int_44_56, int_32_56, int_34_56, int_39_55); - fullAdd_x FA_4480_8608(int_47_56, int_46_56, int_41_55, int_36_56, int_38_56); - fullAdd_x FA_4480_8824(int_49_56, int_48_56, int_40_56, int_43_55, int_45_55); - fullAdd_x FA_4480_9040(int_51_56, int_50_56, int_42_56, int_44_56, int_47_55); - fullAdd_x FA_4480_9256(int_53_56, int_52_56, int_46_56, int_48_56, int_49_55); - fullAdd_x FA_4480_9472(int_55_56, int_54_56, int_50_56, int_51_55, int_52_56); - assign Sum[56] = int_53_55; - assign Carry[56] = int_54_56; - - // Hardware for column 57 - - r4bs r4bs_4560_64(yy[56], yy[57], single[0], double[0], neg[0], pp_0_57); - r4bs r4bs_4560_192(yy[54], yy[55], single[1], double[1], neg[1], pp_1_57); - halfAdd HA_4560_320(int_1_57, int_0_57, pp_0_57, pp_1_57); - r4bs r4bs_4560_400(yy[52], yy[53], single[2], double[2], neg[2], pp_2_57); - r4bs r4bs_4560_528(yy[50], yy[51], single[3], double[3], neg[3], pp_3_57); - r4bs r4bs_4560_656(yy[48], yy[49], single[4], double[4], neg[4], pp_4_57); - fullAdd_x FA_4560_784(int_3_57, int_2_57, pp_2_57, pp_3_57, pp_4_57); - r4bs r4bs_4560_1000(yy[46], yy[47], single[5], double[5], neg[5], pp_5_57); - r4bs r4bs_4560_1128(yy[44], yy[45], single[6], double[6], neg[6], pp_6_57); - r4bs r4bs_4560_1256(yy[42], yy[43], single[7], double[7], neg[7], pp_7_57); - fullAdd_x FA_4560_1384(int_5_57, int_4_57, pp_5_57, pp_6_57, pp_7_57); - r4bs r4bs_4560_1600(yy[40], yy[41], single[8], double[8], neg[8], pp_8_57); - r4bs r4bs_4560_1728(yy[38], yy[39], single[9], double[9], neg[9], pp_9_57); - r4bs r4bs_4560_1856(yy[36], yy[37], single[10], double[10], neg[10], pp_10_57); - fullAdd_x FA_4560_1984(int_7_57, int_6_57, pp_8_57, pp_9_57, pp_10_57); - r4bs r4bs_4560_2200(yy[34], yy[35], single[11], double[11], neg[11], pp_11_57); - r4bs r4bs_4560_2328(yy[32], yy[33], single[12], double[12], neg[12], pp_12_57); - r4bs r4bs_4560_2456(yy[30], yy[31], single[13], double[13], neg[13], pp_13_57); - fullAdd_x FA_4560_2584(int_9_57, int_8_57, pp_11_57, pp_12_57, pp_13_57); - r4bs r4bs_4560_2800(yy[28], yy[29], single[14], double[14], neg[14], pp_14_57); - r4bs r4bs_4560_2928(yy[26], yy[27], single[15], double[15], neg[15], pp_15_57); - r4bs r4bs_4560_3056(yy[24], yy[25], single[16], double[16], neg[16], pp_16_57); - fullAdd_x FA_4560_3184(int_11_57, int_10_57, pp_14_57, pp_15_57, pp_16_57); - r4bs r4bs_4560_3400(yy[22], yy[23], single[17], double[17], neg[17], pp_17_57); - r4bs r4bs_4560_3528(yy[20], yy[21], single[18], double[18], neg[18], pp_18_57); - r4bs r4bs_4560_3656(yy[18], yy[19], single[19], double[19], neg[19], pp_19_57); - fullAdd_x FA_4560_3784(int_13_57, int_12_57, pp_17_57, pp_18_57, pp_19_57); - r4bs r4bs_4560_4000(yy[16], yy[17], single[20], double[20], neg[20], pp_20_57); - r4bs r4bs_4560_4128(yy[14], yy[15], single[21], double[21], neg[21], pp_21_57); - r4bs r4bs_4560_4256(yy[12], yy[13], single[22], double[22], neg[22], pp_22_57); - fullAdd_x FA_4560_4384(int_15_57, int_14_57, pp_20_57, pp_21_57, pp_22_57); - r4bs r4bs_4560_4600(yy[10], yy[11], single[23], double[23], neg[23], pp_23_57); - r4bs r4bs_4560_4728(yy[8], yy[9], single[24], double[24], neg[24], pp_24_57); - r4bs r4bs_4560_4856(yy[6], yy[7], single[25], double[25], neg[25], pp_25_57); - fullAdd_x FA_4560_4984(int_17_57, int_16_57, pp_23_57, pp_24_57, pp_25_57); - r4bs r4bs_4560_5200(yy[4], yy[5], single[26], double[26], neg[26], pp_26_57); - r4bs r4bs_4560_5328(yy[2], yy[3], single[27], double[27], neg[27], pp_27_57); - r4bs r4bs_4560_5456(yy[0], yy[1], single[28], double[28], neg[28], pp_28_57); - fullAdd_x FA_4560_5584(int_19_57, int_18_57, pp_26_57, pp_27_57, pp_28_57); - fullAdd_x FA_4560_5800(int_21_57, int_20_57, int_1_56, int_3_56, int_5_56); - fullAdd_x FA_4560_6016(int_23_57, int_22_57, int_7_56, int_9_56, int_11_56); - fullAdd_x FA_4560_6232(int_25_57, int_24_57, int_13_56, int_15_56, int_17_56); - fullAdd_x FA_4560_6448(int_27_57, int_26_57, int_19_56, int_0_57, int_21_56); - fullAdd_x FA_4560_6664(int_29_57, int_28_57, int_23_56, int_25_56, int_2_57); - fullAdd_x FA_4560_6880(int_31_57, int_30_57, int_4_57, int_6_57, int_8_57); - fullAdd_x FA_4560_7096(int_33_57, int_32_57, int_10_57, int_12_57, int_14_57); - fullAdd_x FA_4560_7312(int_35_57, int_34_57, int_16_57, int_18_57, int_27_56); - fullAdd_x FA_4560_7528(int_37_57, int_36_57, int_29_56, int_31_56, int_33_56); - fullAdd_x FA_4560_7744(int_39_57, int_38_57, int_35_56, int_20_57, int_22_57); - fullAdd_x FA_4560_7960(int_41_57, int_40_57, int_24_57, int_26_57, int_37_56); - fullAdd_x FA_4560_8176(int_43_57, int_42_57, int_39_56, int_28_57, int_30_57); - fullAdd_x FA_4560_8392(int_45_57, int_44_57, int_32_57, int_34_57, int_41_56); - fullAdd_x FA_4560_8608(int_47_57, int_46_57, int_43_56, int_36_57, int_38_57); - fullAdd_x FA_4560_8824(int_49_57, int_48_57, int_40_57, int_45_56, int_47_56); - fullAdd_x FA_4560_9040(int_51_57, int_50_57, int_42_57, int_44_57, int_49_56); - fullAdd_x FA_4560_9256(int_53_57, int_52_57, int_46_57, int_51_56, int_48_57); - fullAdd_x FA_4560_9472(int_55_57, int_54_57, int_50_57, int_53_56, int_52_57); - assign Sum[57] = int_55_56; - assign Carry[57] = int_54_57; - - // Hardware for column 58 - - r4bs r4bs_4640_64(yy[57], yy[58], single[0], double[0], neg[0], pp_0_58); - halfAdd HA_4640_192(int_1_58, int_0_58, neg[29], pp_0_58); - r4bs r4bs_4640_272(yy[55], yy[56], single[1], double[1], neg[1], pp_1_58); - r4bs r4bs_4640_400(yy[53], yy[54], single[2], double[2], neg[2], pp_2_58); - r4bs r4bs_4640_528(yy[51], yy[52], single[3], double[3], neg[3], pp_3_58); - fullAdd_x FA_4640_656(int_3_58, int_2_58, pp_1_58, pp_2_58, pp_3_58); - r4bs r4bs_4640_872(yy[49], yy[50], single[4], double[4], neg[4], pp_4_58); - r4bs r4bs_4640_1000(yy[47], yy[48], single[5], double[5], neg[5], pp_5_58); - r4bs r4bs_4640_1128(yy[45], yy[46], single[6], double[6], neg[6], pp_6_58); - fullAdd_x FA_4640_1256(int_5_58, int_4_58, pp_4_58, pp_5_58, pp_6_58); - r4bs r4bs_4640_1472(yy[43], yy[44], single[7], double[7], neg[7], pp_7_58); - r4bs r4bs_4640_1600(yy[41], yy[42], single[8], double[8], neg[8], pp_8_58); - r4bs r4bs_4640_1728(yy[39], yy[40], single[9], double[9], neg[9], pp_9_58); - fullAdd_x FA_4640_1856(int_7_58, int_6_58, pp_7_58, pp_8_58, pp_9_58); - r4bs r4bs_4640_2072(yy[37], yy[38], single[10], double[10], neg[10], pp_10_58); - r4bs r4bs_4640_2200(yy[35], yy[36], single[11], double[11], neg[11], pp_11_58); - r4bs r4bs_4640_2328(yy[33], yy[34], single[12], double[12], neg[12], pp_12_58); - fullAdd_x FA_4640_2456(int_9_58, int_8_58, pp_10_58, pp_11_58, pp_12_58); - r4bs r4bs_4640_2672(yy[31], yy[32], single[13], double[13], neg[13], pp_13_58); - r4bs r4bs_4640_2800(yy[29], yy[30], single[14], double[14], neg[14], pp_14_58); - r4bs r4bs_4640_2928(yy[27], yy[28], single[15], double[15], neg[15], pp_15_58); - fullAdd_x FA_4640_3056(int_11_58, int_10_58, pp_13_58, pp_14_58, pp_15_58); - r4bs r4bs_4640_3272(yy[25], yy[26], single[16], double[16], neg[16], pp_16_58); - r4bs r4bs_4640_3400(yy[23], yy[24], single[17], double[17], neg[17], pp_17_58); - r4bs r4bs_4640_3528(yy[21], yy[22], single[18], double[18], neg[18], pp_18_58); - fullAdd_x FA_4640_3656(int_13_58, int_12_58, pp_16_58, pp_17_58, pp_18_58); - r4bs r4bs_4640_3872(yy[19], yy[20], single[19], double[19], neg[19], pp_19_58); - r4bs r4bs_4640_4000(yy[17], yy[18], single[20], double[20], neg[20], pp_20_58); - r4bs r4bs_4640_4128(yy[15], yy[16], single[21], double[21], neg[21], pp_21_58); - fullAdd_x FA_4640_4256(int_15_58, int_14_58, pp_19_58, pp_20_58, pp_21_58); - r4bs r4bs_4640_4472(yy[13], yy[14], single[22], double[22], neg[22], pp_22_58); - r4bs r4bs_4640_4600(yy[11], yy[12], single[23], double[23], neg[23], pp_23_58); - r4bs r4bs_4640_4728(yy[9], yy[10], single[24], double[24], neg[24], pp_24_58); - fullAdd_x FA_4640_4856(int_17_58, int_16_58, pp_22_58, pp_23_58, pp_24_58); - r4bs r4bs_4640_5072(yy[7], yy[8], single[25], double[25], neg[25], pp_25_58); - r4bs r4bs_4640_5200(yy[5], yy[6], single[26], double[26], neg[26], pp_26_58); - r4bs r4bs_4640_5328(yy[3], yy[4], single[27], double[27], neg[27], pp_27_58); - fullAdd_x FA_4640_5456(int_19_58, int_18_58, pp_25_58, pp_26_58, pp_27_58); - r4bs r4bs_4640_5672(yy[1], yy[2], single[28], double[28], neg[28], pp_28_58); - r4bs r4bs_4640_5800(gnd, yy[0], single[29], double[29], neg[29], pp_29_58); - fullAdd_x FA_4640_5928(int_21_58, int_20_58, pp_28_58, pp_29_58, int_1_57); - fullAdd_x FA_4640_6144(int_23_58, int_22_58, int_3_57, int_5_57, int_7_57); - fullAdd_x FA_4640_6360(int_25_58, int_24_58, int_9_57, int_11_57, int_13_57); - fullAdd_x FA_4640_6576(int_27_58, int_26_58, int_15_57, int_17_57, int_19_57); - fullAdd_x FA_4640_6792(int_29_58, int_28_58, int_0_58, int_21_57, int_23_57); - fullAdd_x FA_4640_7008(int_31_58, int_30_58, int_25_57, int_2_58, int_4_58); - fullAdd_x FA_4640_7224(int_33_58, int_32_58, int_6_58, int_8_58, int_10_58); - fullAdd_x FA_4640_7440(int_35_58, int_34_58, int_12_58, int_14_58, int_16_58); - fullAdd_x FA_4640_7656(int_37_58, int_36_58, int_18_58, int_20_58, int_27_57); - fullAdd_x FA_4640_7872(int_39_58, int_38_58, int_29_57, int_31_57, int_33_57); - fullAdd_x FA_4640_8088(int_41_58, int_40_58, int_22_58, int_24_58, int_26_58); - fullAdd_x FA_4640_8304(int_43_58, int_42_58, int_35_57, int_37_57, int_39_57); - fullAdd_x FA_4640_8520(int_45_58, int_44_58, int_28_58, int_30_58, int_32_58); - fullAdd_x FA_4640_8736(int_47_58, int_46_58, int_34_58, int_36_58, int_41_57); - fullAdd_x FA_4640_8952(int_49_58, int_48_58, int_43_57, int_38_58, int_40_58); - fullAdd_x FA_4640_9168(int_51_58, int_50_58, int_45_57, int_47_57, int_42_58); - fullAdd_x FA_4640_9384(int_53_58, int_52_58, int_44_58, int_46_58, int_49_57); - fullAdd_x FA_4640_9600(int_55_58, int_54_58, int_48_58, int_51_57, int_50_58); - fullAdd_x FA_4640_9816(int_57_58, int_56_58, int_52_58, int_53_57, int_54_58); - assign Sum[58] = int_55_57; - assign Carry[58] = int_56_58; - - // Hardware for column 59 - - r4bs r4bs_4720_64(yy[58], yy[59], single[0], double[0], neg[0], pp_0_59); - r4bs r4bs_4720_192(yy[56], yy[57], single[1], double[1], neg[1], pp_1_59); - halfAdd HA_4720_320(int_1_59, int_0_59, pp_0_59, pp_1_59); - r4bs r4bs_4720_400(yy[54], yy[55], single[2], double[2], neg[2], pp_2_59); - r4bs r4bs_4720_528(yy[52], yy[53], single[3], double[3], neg[3], pp_3_59); - r4bs r4bs_4720_656(yy[50], yy[51], single[4], double[4], neg[4], pp_4_59); - fullAdd_x FA_4720_784(int_3_59, int_2_59, pp_2_59, pp_3_59, pp_4_59); - r4bs r4bs_4720_1000(yy[48], yy[49], single[5], double[5], neg[5], pp_5_59); - r4bs r4bs_4720_1128(yy[46], yy[47], single[6], double[6], neg[6], pp_6_59); - r4bs r4bs_4720_1256(yy[44], yy[45], single[7], double[7], neg[7], pp_7_59); - fullAdd_x FA_4720_1384(int_5_59, int_4_59, pp_5_59, pp_6_59, pp_7_59); - r4bs r4bs_4720_1600(yy[42], yy[43], single[8], double[8], neg[8], pp_8_59); - r4bs r4bs_4720_1728(yy[40], yy[41], single[9], double[9], neg[9], pp_9_59); - r4bs r4bs_4720_1856(yy[38], yy[39], single[10], double[10], neg[10], pp_10_59); - fullAdd_x FA_4720_1984(int_7_59, int_6_59, pp_8_59, pp_9_59, pp_10_59); - r4bs r4bs_4720_2200(yy[36], yy[37], single[11], double[11], neg[11], pp_11_59); - r4bs r4bs_4720_2328(yy[34], yy[35], single[12], double[12], neg[12], pp_12_59); - r4bs r4bs_4720_2456(yy[32], yy[33], single[13], double[13], neg[13], pp_13_59); - fullAdd_x FA_4720_2584(int_9_59, int_8_59, pp_11_59, pp_12_59, pp_13_59); - r4bs r4bs_4720_2800(yy[30], yy[31], single[14], double[14], neg[14], pp_14_59); - r4bs r4bs_4720_2928(yy[28], yy[29], single[15], double[15], neg[15], pp_15_59); - r4bs r4bs_4720_3056(yy[26], yy[27], single[16], double[16], neg[16], pp_16_59); - fullAdd_x FA_4720_3184(int_11_59, int_10_59, pp_14_59, pp_15_59, pp_16_59); - r4bs r4bs_4720_3400(yy[24], yy[25], single[17], double[17], neg[17], pp_17_59); - r4bs r4bs_4720_3528(yy[22], yy[23], single[18], double[18], neg[18], pp_18_59); - r4bs r4bs_4720_3656(yy[20], yy[21], single[19], double[19], neg[19], pp_19_59); - fullAdd_x FA_4720_3784(int_13_59, int_12_59, pp_17_59, pp_18_59, pp_19_59); - r4bs r4bs_4720_4000(yy[18], yy[19], single[20], double[20], neg[20], pp_20_59); - r4bs r4bs_4720_4128(yy[16], yy[17], single[21], double[21], neg[21], pp_21_59); - r4bs r4bs_4720_4256(yy[14], yy[15], single[22], double[22], neg[22], pp_22_59); - fullAdd_x FA_4720_4384(int_15_59, int_14_59, pp_20_59, pp_21_59, pp_22_59); - r4bs r4bs_4720_4600(yy[12], yy[13], single[23], double[23], neg[23], pp_23_59); - r4bs r4bs_4720_4728(yy[10], yy[11], single[24], double[24], neg[24], pp_24_59); - r4bs r4bs_4720_4856(yy[8], yy[9], single[25], double[25], neg[25], pp_25_59); - fullAdd_x FA_4720_4984(int_17_59, int_16_59, pp_23_59, pp_24_59, pp_25_59); - r4bs r4bs_4720_5200(yy[6], yy[7], single[26], double[26], neg[26], pp_26_59); - r4bs r4bs_4720_5328(yy[4], yy[5], single[27], double[27], neg[27], pp_27_59); - r4bs r4bs_4720_5456(yy[2], yy[3], single[28], double[28], neg[28], pp_28_59); - fullAdd_x FA_4720_5584(int_19_59, int_18_59, pp_26_59, pp_27_59, pp_28_59); - r4bs r4bs_4720_5800(yy[0], yy[1], single[29], double[29], neg[29], pp_29_59); - fullAdd_x FA_4720_5928(int_21_59, int_20_59, pp_29_59, int_1_58, int_3_58); - fullAdd_x FA_4720_6144(int_23_59, int_22_59, int_5_58, int_7_58, int_9_58); - fullAdd_x FA_4720_6360(int_25_59, int_24_59, int_11_58, int_13_58, int_15_58); - fullAdd_x FA_4720_6576(int_27_59, int_26_59, int_17_58, int_19_58, int_0_59); - fullAdd_x FA_4720_6792(int_29_59, int_28_59, int_21_58, int_23_58, int_25_58); - fullAdd_x FA_4720_7008(int_31_59, int_30_59, int_27_58, int_2_59, int_4_59); - fullAdd_x FA_4720_7224(int_33_59, int_32_59, int_6_59, int_8_59, int_10_59); - fullAdd_x FA_4720_7440(int_35_59, int_34_59, int_12_59, int_14_59, int_16_59); - fullAdd_x FA_4720_7656(int_37_59, int_36_59, int_18_59, int_20_59, int_29_58); - fullAdd_x FA_4720_7872(int_39_59, int_38_59, int_31_58, int_33_58, int_35_58); - fullAdd_x FA_4720_8088(int_41_59, int_40_59, int_22_59, int_24_59, int_26_59); - fullAdd_x FA_4720_8304(int_43_59, int_42_59, int_37_58, int_39_58, int_41_58); - fullAdd_x FA_4720_8520(int_45_59, int_44_59, int_28_59, int_30_59, int_32_59); - fullAdd_x FA_4720_8736(int_47_59, int_46_59, int_34_59, int_36_59, int_43_58); - fullAdd_x FA_4720_8952(int_49_59, int_48_59, int_45_58, int_38_59, int_40_59); - fullAdd_x FA_4720_9168(int_51_59, int_50_59, int_47_58, int_49_58, int_42_59); - fullAdd_x FA_4720_9384(int_53_59, int_52_59, int_44_59, int_46_59, int_51_58); - fullAdd_x FA_4720_9600(int_55_59, int_54_59, int_48_59, int_53_58, int_50_59); - fullAdd_x FA_4720_9816(int_57_59, int_56_59, int_52_59, int_55_58, int_54_59); - assign Sum[59] = int_57_58; - assign Carry[59] = int_56_59; - - // Hardware for column 60 - - r4bs r4bs_4800_64(yy[59], yy[60], single[0], double[0], neg[0], pp_0_60); - halfAdd HA_4800_192(int_1_60, int_0_60, neg[30], pp_0_60); - r4bs r4bs_4800_272(yy[57], yy[58], single[1], double[1], neg[1], pp_1_60); - r4bs r4bs_4800_400(yy[55], yy[56], single[2], double[2], neg[2], pp_2_60); - r4bs r4bs_4800_528(yy[53], yy[54], single[3], double[3], neg[3], pp_3_60); - fullAdd_x FA_4800_656(int_3_60, int_2_60, pp_1_60, pp_2_60, pp_3_60); - r4bs r4bs_4800_872(yy[51], yy[52], single[4], double[4], neg[4], pp_4_60); - r4bs r4bs_4800_1000(yy[49], yy[50], single[5], double[5], neg[5], pp_5_60); - r4bs r4bs_4800_1128(yy[47], yy[48], single[6], double[6], neg[6], pp_6_60); - fullAdd_x FA_4800_1256(int_5_60, int_4_60, pp_4_60, pp_5_60, pp_6_60); - r4bs r4bs_4800_1472(yy[45], yy[46], single[7], double[7], neg[7], pp_7_60); - r4bs r4bs_4800_1600(yy[43], yy[44], single[8], double[8], neg[8], pp_8_60); - r4bs r4bs_4800_1728(yy[41], yy[42], single[9], double[9], neg[9], pp_9_60); - fullAdd_x FA_4800_1856(int_7_60, int_6_60, pp_7_60, pp_8_60, pp_9_60); - r4bs r4bs_4800_2072(yy[39], yy[40], single[10], double[10], neg[10], pp_10_60); - r4bs r4bs_4800_2200(yy[37], yy[38], single[11], double[11], neg[11], pp_11_60); - r4bs r4bs_4800_2328(yy[35], yy[36], single[12], double[12], neg[12], pp_12_60); - fullAdd_x FA_4800_2456(int_9_60, int_8_60, pp_10_60, pp_11_60, pp_12_60); - r4bs r4bs_4800_2672(yy[33], yy[34], single[13], double[13], neg[13], pp_13_60); - r4bs r4bs_4800_2800(yy[31], yy[32], single[14], double[14], neg[14], pp_14_60); - r4bs r4bs_4800_2928(yy[29], yy[30], single[15], double[15], neg[15], pp_15_60); - fullAdd_x FA_4800_3056(int_11_60, int_10_60, pp_13_60, pp_14_60, pp_15_60); - r4bs r4bs_4800_3272(yy[27], yy[28], single[16], double[16], neg[16], pp_16_60); - r4bs r4bs_4800_3400(yy[25], yy[26], single[17], double[17], neg[17], pp_17_60); - r4bs r4bs_4800_3528(yy[23], yy[24], single[18], double[18], neg[18], pp_18_60); - fullAdd_x FA_4800_3656(int_13_60, int_12_60, pp_16_60, pp_17_60, pp_18_60); - r4bs r4bs_4800_3872(yy[21], yy[22], single[19], double[19], neg[19], pp_19_60); - r4bs r4bs_4800_4000(yy[19], yy[20], single[20], double[20], neg[20], pp_20_60); - r4bs r4bs_4800_4128(yy[17], yy[18], single[21], double[21], neg[21], pp_21_60); - fullAdd_x FA_4800_4256(int_15_60, int_14_60, pp_19_60, pp_20_60, pp_21_60); - r4bs r4bs_4800_4472(yy[15], yy[16], single[22], double[22], neg[22], pp_22_60); - r4bs r4bs_4800_4600(yy[13], yy[14], single[23], double[23], neg[23], pp_23_60); - r4bs r4bs_4800_4728(yy[11], yy[12], single[24], double[24], neg[24], pp_24_60); - fullAdd_x FA_4800_4856(int_17_60, int_16_60, pp_22_60, pp_23_60, pp_24_60); - r4bs r4bs_4800_5072(yy[9], yy[10], single[25], double[25], neg[25], pp_25_60); - r4bs r4bs_4800_5200(yy[7], yy[8], single[26], double[26], neg[26], pp_26_60); - r4bs r4bs_4800_5328(yy[5], yy[6], single[27], double[27], neg[27], pp_27_60); - fullAdd_x FA_4800_5456(int_19_60, int_18_60, pp_25_60, pp_26_60, pp_27_60); - r4bs r4bs_4800_5672(yy[3], yy[4], single[28], double[28], neg[28], pp_28_60); - r4bs r4bs_4800_5800(yy[1], yy[2], single[29], double[29], neg[29], pp_29_60); - r4bs r4bs_4800_5928(gnd, yy[0], single[30], double[30], neg[30], pp_30_60); - fullAdd_x FA_4800_6056(int_21_60, int_20_60, pp_28_60, pp_29_60, pp_30_60); - fullAdd_x FA_4800_6272(int_23_60, int_22_60, int_1_59, int_3_59, int_5_59); - fullAdd_x FA_4800_6488(int_25_60, int_24_60, int_7_59, int_9_59, int_11_59); - fullAdd_x FA_4800_6704(int_27_60, int_26_60, int_13_59, int_15_59, int_17_59); - fullAdd_x FA_4800_6920(int_29_60, int_28_60, int_19_59, int_0_60, int_21_59); - fullAdd_x FA_4800_7136(int_31_60, int_30_60, int_23_59, int_25_59, int_27_59); - fullAdd_x FA_4800_7352(int_33_60, int_32_60, int_2_60, int_4_60, int_6_60); - fullAdd_x FA_4800_7568(int_35_60, int_34_60, int_8_60, int_10_60, int_12_60); - fullAdd_x FA_4800_7784(int_37_60, int_36_60, int_14_60, int_16_60, int_18_60); - fullAdd_x FA_4800_8000(int_39_60, int_38_60, int_20_60, int_29_59, int_31_59); - fullAdd_x FA_4800_8216(int_41_60, int_40_60, int_33_59, int_35_59, int_22_60); - fullAdd_x FA_4800_8432(int_43_60, int_42_60, int_24_60, int_26_60, int_28_60); - fullAdd_x FA_4800_8648(int_45_60, int_44_60, int_37_59, int_39_59, int_41_59); - fullAdd_x FA_4800_8864(int_47_60, int_46_60, int_30_60, int_32_60, int_34_60); - fullAdd_x FA_4800_9080(int_49_60, int_48_60, int_36_60, int_43_59, int_45_59); - fullAdd_x FA_4800_9296(int_51_60, int_50_60, int_38_60, int_40_60, int_42_60); - fullAdd_x FA_4800_9512(int_53_60, int_52_60, int_47_59, int_49_59, int_44_60); - fullAdd_x FA_4800_9728(int_55_60, int_54_60, int_46_60, int_51_59, int_48_60); - fullAdd_x FA_4800_9944(int_57_60, int_56_60, int_50_60, int_53_59, int_52_60); - fullAdd_x FA_4800_10160(int_59_60, int_58_60, int_55_59, int_54_60, int_56_60); - assign Sum[60] = int_57_59; - assign Carry[60] = int_58_60; - - // Hardware for column 61 - - r4bs r4bs_4880_64(yy[60], yy[61], single[0], double[0], neg[0], pp_0_61); - r4bs r4bs_4880_192(yy[58], yy[59], single[1], double[1], neg[1], pp_1_61); - halfAdd HA_4880_320(int_1_61, int_0_61, pp_0_61, pp_1_61); - r4bs r4bs_4880_400(yy[56], yy[57], single[2], double[2], neg[2], pp_2_61); - r4bs r4bs_4880_528(yy[54], yy[55], single[3], double[3], neg[3], pp_3_61); - r4bs r4bs_4880_656(yy[52], yy[53], single[4], double[4], neg[4], pp_4_61); - fullAdd_x FA_4880_784(int_3_61, int_2_61, pp_2_61, pp_3_61, pp_4_61); - r4bs r4bs_4880_1000(yy[50], yy[51], single[5], double[5], neg[5], pp_5_61); - r4bs r4bs_4880_1128(yy[48], yy[49], single[6], double[6], neg[6], pp_6_61); - r4bs r4bs_4880_1256(yy[46], yy[47], single[7], double[7], neg[7], pp_7_61); - fullAdd_x FA_4880_1384(int_5_61, int_4_61, pp_5_61, pp_6_61, pp_7_61); - r4bs r4bs_4880_1600(yy[44], yy[45], single[8], double[8], neg[8], pp_8_61); - r4bs r4bs_4880_1728(yy[42], yy[43], single[9], double[9], neg[9], pp_9_61); - r4bs r4bs_4880_1856(yy[40], yy[41], single[10], double[10], neg[10], pp_10_61); - fullAdd_x FA_4880_1984(int_7_61, int_6_61, pp_8_61, pp_9_61, pp_10_61); - r4bs r4bs_4880_2200(yy[38], yy[39], single[11], double[11], neg[11], pp_11_61); - r4bs r4bs_4880_2328(yy[36], yy[37], single[12], double[12], neg[12], pp_12_61); - r4bs r4bs_4880_2456(yy[34], yy[35], single[13], double[13], neg[13], pp_13_61); - fullAdd_x FA_4880_2584(int_9_61, int_8_61, pp_11_61, pp_12_61, pp_13_61); - r4bs r4bs_4880_2800(yy[32], yy[33], single[14], double[14], neg[14], pp_14_61); - r4bs r4bs_4880_2928(yy[30], yy[31], single[15], double[15], neg[15], pp_15_61); - r4bs r4bs_4880_3056(yy[28], yy[29], single[16], double[16], neg[16], pp_16_61); - fullAdd_x FA_4880_3184(int_11_61, int_10_61, pp_14_61, pp_15_61, pp_16_61); - r4bs r4bs_4880_3400(yy[26], yy[27], single[17], double[17], neg[17], pp_17_61); - r4bs r4bs_4880_3528(yy[24], yy[25], single[18], double[18], neg[18], pp_18_61); - r4bs r4bs_4880_3656(yy[22], yy[23], single[19], double[19], neg[19], pp_19_61); - fullAdd_x FA_4880_3784(int_13_61, int_12_61, pp_17_61, pp_18_61, pp_19_61); - r4bs r4bs_4880_4000(yy[20], yy[21], single[20], double[20], neg[20], pp_20_61); - r4bs r4bs_4880_4128(yy[18], yy[19], single[21], double[21], neg[21], pp_21_61); - r4bs r4bs_4880_4256(yy[16], yy[17], single[22], double[22], neg[22], pp_22_61); - fullAdd_x FA_4880_4384(int_15_61, int_14_61, pp_20_61, pp_21_61, pp_22_61); - r4bs r4bs_4880_4600(yy[14], yy[15], single[23], double[23], neg[23], pp_23_61); - r4bs r4bs_4880_4728(yy[12], yy[13], single[24], double[24], neg[24], pp_24_61); - r4bs r4bs_4880_4856(yy[10], yy[11], single[25], double[25], neg[25], pp_25_61); - fullAdd_x FA_4880_4984(int_17_61, int_16_61, pp_23_61, pp_24_61, pp_25_61); - r4bs r4bs_4880_5200(yy[8], yy[9], single[26], double[26], neg[26], pp_26_61); - r4bs r4bs_4880_5328(yy[6], yy[7], single[27], double[27], neg[27], pp_27_61); - r4bs r4bs_4880_5456(yy[4], yy[5], single[28], double[28], neg[28], pp_28_61); - fullAdd_x FA_4880_5584(int_19_61, int_18_61, pp_26_61, pp_27_61, pp_28_61); - r4bs r4bs_4880_5800(yy[2], yy[3], single[29], double[29], neg[29], pp_29_61); - r4bs r4bs_4880_5928(yy[0], yy[1], single[30], double[30], neg[30], pp_30_61); - fullAdd_x FA_4880_6056(int_21_61, int_20_61, pp_29_61, pp_30_61, int_1_60); - fullAdd_x FA_4880_6272(int_23_61, int_22_61, int_3_60, int_5_60, int_7_60); - fullAdd_x FA_4880_6488(int_25_61, int_24_61, int_9_60, int_11_60, int_13_60); - fullAdd_x FA_4880_6704(int_27_61, int_26_61, int_15_60, int_17_60, int_19_60); - fullAdd_x FA_4880_6920(int_29_61, int_28_61, int_21_60, int_0_61, int_23_60); - fullAdd_x FA_4880_7136(int_31_61, int_30_61, int_25_60, int_27_60, int_2_61); - fullAdd_x FA_4880_7352(int_33_61, int_32_61, int_4_61, int_6_61, int_8_61); - fullAdd_x FA_4880_7568(int_35_61, int_34_61, int_10_61, int_12_61, int_14_61); - fullAdd_x FA_4880_7784(int_37_61, int_36_61, int_16_61, int_18_61, int_20_61); - fullAdd_x FA_4880_8000(int_39_61, int_38_61, int_29_60, int_31_60, int_33_60); - fullAdd_x FA_4880_8216(int_41_61, int_40_61, int_35_60, int_37_60, int_22_61); - fullAdd_x FA_4880_8432(int_43_61, int_42_61, int_24_61, int_26_61, int_28_61); - fullAdd_x FA_4880_8648(int_45_61, int_44_61, int_39_60, int_41_60, int_43_60); - fullAdd_x FA_4880_8864(int_47_61, int_46_61, int_30_61, int_32_61, int_34_61); - fullAdd_x FA_4880_9080(int_49_61, int_48_61, int_36_61, int_45_60, int_47_60); - fullAdd_x FA_4880_9296(int_51_61, int_50_61, int_38_61, int_40_61, int_42_61); - fullAdd_x FA_4880_9512(int_53_61, int_52_61, int_49_60, int_51_60, int_44_61); - fullAdd_x FA_4880_9728(int_55_61, int_54_61, int_46_61, int_53_60, int_48_61); - fullAdd_x FA_4880_9944(int_57_61, int_56_61, int_50_61, int_55_60, int_52_61); - fullAdd_x FA_4880_10160(int_59_61, int_58_61, int_57_60, int_54_61, int_56_61); - assign Sum[61] = int_59_60; - assign Carry[61] = int_58_61; - - // Hardware for column 62 - - r4bs r4bs_4960_64(yy[61], yy[62], single[0], double[0], neg[0], pp_0_62); - halfAdd HA_4960_192(int_1_62, int_0_62, neg[31], pp_0_62); - r4bs r4bs_4960_272(yy[59], yy[60], single[1], double[1], neg[1], pp_1_62); - r4bs r4bs_4960_400(yy[57], yy[58], single[2], double[2], neg[2], pp_2_62); - r4bs r4bs_4960_528(yy[55], yy[56], single[3], double[3], neg[3], pp_3_62); - fullAdd_x FA_4960_656(int_3_62, int_2_62, pp_1_62, pp_2_62, pp_3_62); - r4bs r4bs_4960_872(yy[53], yy[54], single[4], double[4], neg[4], pp_4_62); - r4bs r4bs_4960_1000(yy[51], yy[52], single[5], double[5], neg[5], pp_5_62); - r4bs r4bs_4960_1128(yy[49], yy[50], single[6], double[6], neg[6], pp_6_62); - fullAdd_x FA_4960_1256(int_5_62, int_4_62, pp_4_62, pp_5_62, pp_6_62); - r4bs r4bs_4960_1472(yy[47], yy[48], single[7], double[7], neg[7], pp_7_62); - r4bs r4bs_4960_1600(yy[45], yy[46], single[8], double[8], neg[8], pp_8_62); - r4bs r4bs_4960_1728(yy[43], yy[44], single[9], double[9], neg[9], pp_9_62); - fullAdd_x FA_4960_1856(int_7_62, int_6_62, pp_7_62, pp_8_62, pp_9_62); - r4bs r4bs_4960_2072(yy[41], yy[42], single[10], double[10], neg[10], pp_10_62); - r4bs r4bs_4960_2200(yy[39], yy[40], single[11], double[11], neg[11], pp_11_62); - r4bs r4bs_4960_2328(yy[37], yy[38], single[12], double[12], neg[12], pp_12_62); - fullAdd_x FA_4960_2456(int_9_62, int_8_62, pp_10_62, pp_11_62, pp_12_62); - r4bs r4bs_4960_2672(yy[35], yy[36], single[13], double[13], neg[13], pp_13_62); - r4bs r4bs_4960_2800(yy[33], yy[34], single[14], double[14], neg[14], pp_14_62); - r4bs r4bs_4960_2928(yy[31], yy[32], single[15], double[15], neg[15], pp_15_62); - fullAdd_x FA_4960_3056(int_11_62, int_10_62, pp_13_62, pp_14_62, pp_15_62); - r4bs r4bs_4960_3272(yy[29], yy[30], single[16], double[16], neg[16], pp_16_62); - r4bs r4bs_4960_3400(yy[27], yy[28], single[17], double[17], neg[17], pp_17_62); - r4bs r4bs_4960_3528(yy[25], yy[26], single[18], double[18], neg[18], pp_18_62); - fullAdd_x FA_4960_3656(int_13_62, int_12_62, pp_16_62, pp_17_62, pp_18_62); - r4bs r4bs_4960_3872(yy[23], yy[24], single[19], double[19], neg[19], pp_19_62); - r4bs r4bs_4960_4000(yy[21], yy[22], single[20], double[20], neg[20], pp_20_62); - r4bs r4bs_4960_4128(yy[19], yy[20], single[21], double[21], neg[21], pp_21_62); - fullAdd_x FA_4960_4256(int_15_62, int_14_62, pp_19_62, pp_20_62, pp_21_62); - r4bs r4bs_4960_4472(yy[17], yy[18], single[22], double[22], neg[22], pp_22_62); - r4bs r4bs_4960_4600(yy[15], yy[16], single[23], double[23], neg[23], pp_23_62); - r4bs r4bs_4960_4728(yy[13], yy[14], single[24], double[24], neg[24], pp_24_62); - fullAdd_x FA_4960_4856(int_17_62, int_16_62, pp_22_62, pp_23_62, pp_24_62); - r4bs r4bs_4960_5072(yy[11], yy[12], single[25], double[25], neg[25], pp_25_62); - r4bs r4bs_4960_5200(yy[9], yy[10], single[26], double[26], neg[26], pp_26_62); - r4bs r4bs_4960_5328(yy[7], yy[8], single[27], double[27], neg[27], pp_27_62); - fullAdd_x FA_4960_5456(int_19_62, int_18_62, pp_25_62, pp_26_62, pp_27_62); - r4bs r4bs_4960_5672(yy[5], yy[6], single[28], double[28], neg[28], pp_28_62); - r4bs r4bs_4960_5800(yy[3], yy[4], single[29], double[29], neg[29], pp_29_62); - r4bs r4bs_4960_5928(yy[1], yy[2], single[30], double[30], neg[30], pp_30_62); - fullAdd_x FA_4960_6056(int_21_62, int_20_62, pp_28_62, pp_29_62, pp_30_62); - r4bs r4bs_4960_6272(gnd, yy[0], single[31], double[31], neg[31], pp_31_62); - fullAdd_x FA_4960_6400(int_23_62, int_22_62, pp_31_62, int_1_61, int_3_61); - fullAdd_x FA_4960_6616(int_25_62, int_24_62, int_5_61, int_7_61, int_9_61); - fullAdd_x FA_4960_6832(int_27_62, int_26_62, int_11_61, int_13_61, int_15_61); - fullAdd_x FA_4960_7048(int_29_62, int_28_62, int_17_61, int_19_61, int_0_62); - fullAdd_x FA_4960_7264(int_31_62, int_30_62, int_21_61, int_23_61, int_25_61); - fullAdd_x FA_4960_7480(int_33_62, int_32_62, int_27_61, int_2_62, int_4_62); - fullAdd_x FA_4960_7696(int_35_62, int_34_62, int_6_62, int_8_62, int_10_62); - fullAdd_x FA_4960_7912(int_37_62, int_36_62, int_12_62, int_14_62, int_16_62); - fullAdd_x FA_4960_8128(int_39_62, int_38_62, int_18_62, int_20_62, int_22_62); - fullAdd_x FA_4960_8344(int_41_62, int_40_62, int_29_61, int_31_61, int_33_61); - fullAdd_x FA_4960_8560(int_43_62, int_42_62, int_35_61, int_37_61, int_24_62); - fullAdd_x FA_4960_8776(int_45_62, int_44_62, int_26_62, int_28_62, int_39_61); - fullAdd_x FA_4960_8992(int_47_62, int_46_62, int_41_61, int_43_61, int_30_62); - fullAdd_x FA_4960_9208(int_49_62, int_48_62, int_32_62, int_34_62, int_36_62); - fullAdd_x FA_4960_9424(int_51_62, int_50_62, int_38_62, int_45_61, int_47_61); - fullAdd_x FA_4960_9640(int_53_62, int_52_62, int_40_62, int_42_62, int_44_62); - fullAdd_x FA_4960_9856(int_55_62, int_54_62, int_49_61, int_51_61, int_46_62); - fullAdd_x FA_4960_10072(int_57_62, int_56_62, int_48_62, int_53_61, int_50_62); - fullAdd_x FA_4960_10288(int_59_62, int_58_62, int_52_62, int_55_61, int_54_62); - fullAdd_x FA_4960_10504(int_61_62, int_60_62, int_57_61, int_56_62, int_58_62); - assign Sum[62] = int_59_61; - assign Carry[62] = int_60_62; - - // Hardware for column 63 - - r4bs r4bs_5040_64(yy[62], yy[63], single[0], double[0], neg[0], pp_0_63); - r4bs r4bs_5040_192(yy[60], yy[61], single[1], double[1], neg[1], pp_1_63); - halfAdd HA_5040_320(int_1_63, int_0_63, pp_0_63, pp_1_63); - r4bs r4bs_5040_400(yy[58], yy[59], single[2], double[2], neg[2], pp_2_63); - r4bs r4bs_5040_528(yy[56], yy[57], single[3], double[3], neg[3], pp_3_63); - r4bs r4bs_5040_656(yy[54], yy[55], single[4], double[4], neg[4], pp_4_63); - fullAdd_x FA_5040_784(int_3_63, int_2_63, pp_2_63, pp_3_63, pp_4_63); - r4bs r4bs_5040_1000(yy[52], yy[53], single[5], double[5], neg[5], pp_5_63); - r4bs r4bs_5040_1128(yy[50], yy[51], single[6], double[6], neg[6], pp_6_63); - r4bs r4bs_5040_1256(yy[48], yy[49], single[7], double[7], neg[7], pp_7_63); - fullAdd_x FA_5040_1384(int_5_63, int_4_63, pp_5_63, pp_6_63, pp_7_63); - r4bs r4bs_5040_1600(yy[46], yy[47], single[8], double[8], neg[8], pp_8_63); - r4bs r4bs_5040_1728(yy[44], yy[45], single[9], double[9], neg[9], pp_9_63); - r4bs r4bs_5040_1856(yy[42], yy[43], single[10], double[10], neg[10], pp_10_63); - fullAdd_x FA_5040_1984(int_7_63, int_6_63, pp_8_63, pp_9_63, pp_10_63); - r4bs r4bs_5040_2200(yy[40], yy[41], single[11], double[11], neg[11], pp_11_63); - r4bs r4bs_5040_2328(yy[38], yy[39], single[12], double[12], neg[12], pp_12_63); - r4bs r4bs_5040_2456(yy[36], yy[37], single[13], double[13], neg[13], pp_13_63); - fullAdd_x FA_5040_2584(int_9_63, int_8_63, pp_11_63, pp_12_63, pp_13_63); - r4bs r4bs_5040_2800(yy[34], yy[35], single[14], double[14], neg[14], pp_14_63); - r4bs r4bs_5040_2928(yy[32], yy[33], single[15], double[15], neg[15], pp_15_63); - r4bs r4bs_5040_3056(yy[30], yy[31], single[16], double[16], neg[16], pp_16_63); - fullAdd_x FA_5040_3184(int_11_63, int_10_63, pp_14_63, pp_15_63, pp_16_63); - r4bs r4bs_5040_3400(yy[28], yy[29], single[17], double[17], neg[17], pp_17_63); - r4bs r4bs_5040_3528(yy[26], yy[27], single[18], double[18], neg[18], pp_18_63); - r4bs r4bs_5040_3656(yy[24], yy[25], single[19], double[19], neg[19], pp_19_63); - fullAdd_x FA_5040_3784(int_13_63, int_12_63, pp_17_63, pp_18_63, pp_19_63); - r4bs r4bs_5040_4000(yy[22], yy[23], single[20], double[20], neg[20], pp_20_63); - r4bs r4bs_5040_4128(yy[20], yy[21], single[21], double[21], neg[21], pp_21_63); - r4bs r4bs_5040_4256(yy[18], yy[19], single[22], double[22], neg[22], pp_22_63); - fullAdd_x FA_5040_4384(int_15_63, int_14_63, pp_20_63, pp_21_63, pp_22_63); - r4bs r4bs_5040_4600(yy[16], yy[17], single[23], double[23], neg[23], pp_23_63); - r4bs r4bs_5040_4728(yy[14], yy[15], single[24], double[24], neg[24], pp_24_63); - r4bs r4bs_5040_4856(yy[12], yy[13], single[25], double[25], neg[25], pp_25_63); - fullAdd_x FA_5040_4984(int_17_63, int_16_63, pp_23_63, pp_24_63, pp_25_63); - r4bs r4bs_5040_5200(yy[10], yy[11], single[26], double[26], neg[26], pp_26_63); - r4bs r4bs_5040_5328(yy[8], yy[9], single[27], double[27], neg[27], pp_27_63); - r4bs r4bs_5040_5456(yy[6], yy[7], single[28], double[28], neg[28], pp_28_63); - fullAdd_x FA_5040_5584(int_19_63, int_18_63, pp_26_63, pp_27_63, pp_28_63); - r4bs r4bs_5040_5800(yy[4], yy[5], single[29], double[29], neg[29], pp_29_63); - r4bs r4bs_5040_5928(yy[2], yy[3], single[30], double[30], neg[30], pp_30_63); - r4bs r4bs_5040_6056(yy[0], yy[1], single[31], double[31], neg[31], pp_31_63); - fullAdd_x FA_5040_6184(int_21_63, int_20_63, pp_29_63, pp_30_63, pp_31_63); - fullAdd_x FA_5040_6400(int_23_63, int_22_63, int_1_62, int_3_62, int_5_62); - fullAdd_x FA_5040_6616(int_25_63, int_24_63, int_7_62, int_9_62, int_11_62); - fullAdd_x FA_5040_6832(int_27_63, int_26_63, int_13_62, int_15_62, int_17_62); - fullAdd_x FA_5040_7048(int_29_63, int_28_63, int_19_62, int_21_62, int_0_63); - fullAdd_x FA_5040_7264(int_31_63, int_30_63, int_23_62, int_25_62, int_27_62); - fullAdd_x FA_5040_7480(int_33_63, int_32_63, int_29_62, int_2_63, int_4_63); - fullAdd_x FA_5040_7696(int_35_63, int_34_63, int_6_63, int_8_63, int_10_63); - fullAdd_x FA_5040_7912(int_37_63, int_36_63, int_12_63, int_14_63, int_16_63); - fullAdd_x FA_5040_8128(int_39_63, int_38_63, int_18_63, int_20_63, int_31_62); - fullAdd_x FA_5040_8344(int_41_63, int_40_63, int_33_62, int_35_62, int_37_62); - fullAdd_x FA_5040_8560(int_43_63, int_42_63, int_22_63, int_24_63, int_26_63); - fullAdd_x FA_5040_8776(int_45_63, int_44_63, int_28_63, int_39_62, int_41_62); - fullAdd_x FA_5040_8992(int_47_63, int_46_63, int_43_62, int_30_63, int_32_63); - fullAdd_x FA_5040_9208(int_49_63, int_48_63, int_34_63, int_36_63, int_38_63); - fullAdd_x FA_5040_9424(int_51_63, int_50_63, int_45_62, int_47_62, int_49_62); - fullAdd_x FA_5040_9640(int_53_63, int_52_63, int_40_63, int_42_63, int_44_63); - fullAdd_x FA_5040_9856(int_55_63, int_54_63, int_51_62, int_53_62, int_46_63); - fullAdd_x FA_5040_10072(int_57_63, int_56_63, int_48_63, int_55_62, int_50_63); - fullAdd_x FA_5040_10288(int_59_63, int_58_63, int_52_63, int_57_62, int_54_63); - fullAdd_x FA_5040_10504(int_61_63, int_60_63, int_59_62, int_56_63, int_58_63); - assign Sum[63] = int_61_62; - assign Carry[63] = int_60_63; - - // Hardware for column 64 - - r4bs r4bs_5120_0(yy[63], gnd, single[0], double[0], neg[0], pp_0_64); - r4bs r4bs_5120_128(yy[61], yy[62], single[1], double[1], neg[1], pp_1_64); - r4bs r4bs_5120_256(yy[59], yy[60], single[2], double[2], neg[2], pp_2_64); - fullAdd_x FA_5120_384(int_1_64, int_0_64, pp_0_64, pp_1_64, pp_2_64); - r4bs r4bs_5120_600(yy[57], yy[58], single[3], double[3], neg[3], pp_3_64); - r4bs r4bs_5120_728(yy[55], yy[56], single[4], double[4], neg[4], pp_4_64); - r4bs r4bs_5120_856(yy[53], yy[54], single[5], double[5], neg[5], pp_5_64); - fullAdd_x FA_5120_984(int_3_64, int_2_64, pp_3_64, pp_4_64, pp_5_64); - r4bs r4bs_5120_1200(yy[51], yy[52], single[6], double[6], neg[6], pp_6_64); - r4bs r4bs_5120_1328(yy[49], yy[50], single[7], double[7], neg[7], pp_7_64); - r4bs r4bs_5120_1456(yy[47], yy[48], single[8], double[8], neg[8], pp_8_64); - fullAdd_x FA_5120_1584(int_5_64, int_4_64, pp_6_64, pp_7_64, pp_8_64); - r4bs r4bs_5120_1800(yy[45], yy[46], single[9], double[9], neg[9], pp_9_64); - r4bs r4bs_5120_1928(yy[43], yy[44], single[10], double[10], neg[10], pp_10_64); - r4bs r4bs_5120_2056(yy[41], yy[42], single[11], double[11], neg[11], pp_11_64); - fullAdd_x FA_5120_2184(int_7_64, int_6_64, pp_9_64, pp_10_64, pp_11_64); - r4bs r4bs_5120_2400(yy[39], yy[40], single[12], double[12], neg[12], pp_12_64); - r4bs r4bs_5120_2528(yy[37], yy[38], single[13], double[13], neg[13], pp_13_64); - r4bs r4bs_5120_2656(yy[35], yy[36], single[14], double[14], neg[14], pp_14_64); - fullAdd_x FA_5120_2784(int_9_64, int_8_64, pp_12_64, pp_13_64, pp_14_64); - r4bs r4bs_5120_3000(yy[33], yy[34], single[15], double[15], neg[15], pp_15_64); - r4bs r4bs_5120_3128(yy[31], yy[32], single[16], double[16], neg[16], pp_16_64); - r4bs r4bs_5120_3256(yy[29], yy[30], single[17], double[17], neg[17], pp_17_64); - fullAdd_x FA_5120_3384(int_11_64, int_10_64, pp_15_64, pp_16_64, pp_17_64); - r4bs r4bs_5120_3600(yy[27], yy[28], single[18], double[18], neg[18], pp_18_64); - r4bs r4bs_5120_3728(yy[25], yy[26], single[19], double[19], neg[19], pp_19_64); - r4bs r4bs_5120_3856(yy[23], yy[24], single[20], double[20], neg[20], pp_20_64); - fullAdd_x FA_5120_3984(int_13_64, int_12_64, pp_18_64, pp_19_64, pp_20_64); - r4bs r4bs_5120_4200(yy[21], yy[22], single[21], double[21], neg[21], pp_21_64); - r4bs r4bs_5120_4328(yy[19], yy[20], single[22], double[22], neg[22], pp_22_64); - r4bs r4bs_5120_4456(yy[17], yy[18], single[23], double[23], neg[23], pp_23_64); - fullAdd_x FA_5120_4584(int_15_64, int_14_64, pp_21_64, pp_22_64, pp_23_64); - r4bs r4bs_5120_4800(yy[15], yy[16], single[24], double[24], neg[24], pp_24_64); - r4bs r4bs_5120_4928(yy[13], yy[14], single[25], double[25], neg[25], pp_25_64); - r4bs r4bs_5120_5056(yy[11], yy[12], single[26], double[26], neg[26], pp_26_64); - fullAdd_x FA_5120_5184(int_17_64, int_16_64, pp_24_64, pp_25_64, pp_26_64); - r4bs r4bs_5120_5400(yy[9], yy[10], single[27], double[27], neg[27], pp_27_64); - r4bs r4bs_5120_5528(yy[7], yy[8], single[28], double[28], neg[28], pp_28_64); - r4bs r4bs_5120_5656(yy[5], yy[6], single[29], double[29], neg[29], pp_29_64); - fullAdd_x FA_5120_5784(int_19_64, int_18_64, pp_27_64, pp_28_64, pp_29_64); - r4bs r4bs_5120_6000(yy[3], yy[4], single[30], double[30], neg[30], pp_30_64); - r4bs r4bs_5120_6128(yy[1], yy[2], single[31], double[31], neg[31], pp_31_64); - r4bs r4bs_5120_6256(gnd, yy[0], single[32], double[32], neg[32], pp_32_64); - fullAdd_x FA_5120_6384(int_21_64, int_20_64, pp_30_64, pp_31_64, pp_32_64); - fullAdd_x FA_5120_6600(int_23_64, int_22_64, int_1_63, int_3_63, int_5_63); - fullAdd_x FA_5120_6816(int_25_64, int_24_64, int_7_63, int_9_63, int_11_63); - fullAdd_x FA_5120_7032(int_27_64, int_26_64, int_13_63, int_15_63, int_17_63); - fullAdd_x FA_5120_7248(int_29_64, int_28_64, int_19_63, int_21_63, int_23_63); - fullAdd_x FA_5120_7464(int_31_64, int_30_64, int_25_63, int_27_63, int_29_63); - fullAdd_x FA_5120_7680(int_33_64, int_32_64, int_0_64, int_2_64, int_4_64); - fullAdd_x FA_5120_7896(int_35_64, int_34_64, int_6_64, int_8_64, int_10_64); - fullAdd_x FA_5120_8112(int_37_64, int_36_64, int_12_64, int_14_64, int_16_64); - fullAdd_x FA_5120_8328(int_39_64, int_38_64, int_18_64, int_20_64, int_31_63); - fullAdd_x FA_5120_8544(int_41_64, int_40_64, int_33_63, int_35_63, int_37_63); - fullAdd_x FA_5120_8760(int_43_64, int_42_64, int_22_64, int_24_64, int_26_64); - fullAdd_x FA_5120_8976(int_45_64, int_44_64, int_28_64, int_39_63, int_41_63); - fullAdd_x FA_5120_9192(int_47_64, int_46_64, int_43_63, int_30_64, int_32_64); - fullAdd_x FA_5120_9408(int_49_64, int_48_64, int_34_64, int_36_64, int_38_64); - fullAdd_x FA_5120_9624(int_51_64, int_50_64, int_45_63, int_47_63, int_49_63); - fullAdd_x FA_5120_9840(int_53_64, int_52_64, int_40_64, int_42_64, int_51_63); - fullAdd_x FA_5120_10056(int_55_64, int_54_64, int_44_64, int_46_64, int_48_64); - fullAdd_x FA_5120_10272(int_57_64, int_56_64, int_53_63, int_55_63, int_50_64); - fullAdd_x FA_5120_10488(int_59_64, int_58_64, int_52_64, int_57_63, int_54_64); - fullAdd_x FA_5120_10704(int_61_64, int_60_64, int_59_63, int_56_64, int_58_64); - assign Sum[64] = int_61_63; - assign Carry[64] = int_60_64; - - // Hardware for column 65 - - r4bs r4bs_5200_0(yy[62], yy[63], single[1], double[1], neg[1], pp_1_65); - r4bs r4bs_5200_128(yy[60], yy[61], single[2], double[2], neg[2], pp_2_65); - fullAdd_x FA_5200_256(int_1_65, int_0_65, neg[0], pp_1_65, pp_2_65); - r4bs r4bs_5200_472(yy[58], yy[59], single[3], double[3], neg[3], pp_3_65); - r4bs r4bs_5200_600(yy[56], yy[57], single[4], double[4], neg[4], pp_4_65); - r4bs r4bs_5200_728(yy[54], yy[55], single[5], double[5], neg[5], pp_5_65); - fullAdd_x FA_5200_856(int_3_65, int_2_65, pp_3_65, pp_4_65, pp_5_65); - r4bs r4bs_5200_1072(yy[52], yy[53], single[6], double[6], neg[6], pp_6_65); - r4bs r4bs_5200_1200(yy[50], yy[51], single[7], double[7], neg[7], pp_7_65); - r4bs r4bs_5200_1328(yy[48], yy[49], single[8], double[8], neg[8], pp_8_65); - fullAdd_x FA_5200_1456(int_5_65, int_4_65, pp_6_65, pp_7_65, pp_8_65); - r4bs r4bs_5200_1672(yy[46], yy[47], single[9], double[9], neg[9], pp_9_65); - r4bs r4bs_5200_1800(yy[44], yy[45], single[10], double[10], neg[10], pp_10_65); - r4bs r4bs_5200_1928(yy[42], yy[43], single[11], double[11], neg[11], pp_11_65); - fullAdd_x FA_5200_2056(int_7_65, int_6_65, pp_9_65, pp_10_65, pp_11_65); - r4bs r4bs_5200_2272(yy[40], yy[41], single[12], double[12], neg[12], pp_12_65); - r4bs r4bs_5200_2400(yy[38], yy[39], single[13], double[13], neg[13], pp_13_65); - r4bs r4bs_5200_2528(yy[36], yy[37], single[14], double[14], neg[14], pp_14_65); - fullAdd_x FA_5200_2656(int_9_65, int_8_65, pp_12_65, pp_13_65, pp_14_65); - r4bs r4bs_5200_2872(yy[34], yy[35], single[15], double[15], neg[15], pp_15_65); - r4bs r4bs_5200_3000(yy[32], yy[33], single[16], double[16], neg[16], pp_16_65); - r4bs r4bs_5200_3128(yy[30], yy[31], single[17], double[17], neg[17], pp_17_65); - fullAdd_x FA_5200_3256(int_11_65, int_10_65, pp_15_65, pp_16_65, pp_17_65); - r4bs r4bs_5200_3472(yy[28], yy[29], single[18], double[18], neg[18], pp_18_65); - r4bs r4bs_5200_3600(yy[26], yy[27], single[19], double[19], neg[19], pp_19_65); - r4bs r4bs_5200_3728(yy[24], yy[25], single[20], double[20], neg[20], pp_20_65); - fullAdd_x FA_5200_3856(int_13_65, int_12_65, pp_18_65, pp_19_65, pp_20_65); - r4bs r4bs_5200_4072(yy[22], yy[23], single[21], double[21], neg[21], pp_21_65); - r4bs r4bs_5200_4200(yy[20], yy[21], single[22], double[22], neg[22], pp_22_65); - r4bs r4bs_5200_4328(yy[18], yy[19], single[23], double[23], neg[23], pp_23_65); - fullAdd_x FA_5200_4456(int_15_65, int_14_65, pp_21_65, pp_22_65, pp_23_65); - r4bs r4bs_5200_4672(yy[16], yy[17], single[24], double[24], neg[24], pp_24_65); - r4bs r4bs_5200_4800(yy[14], yy[15], single[25], double[25], neg[25], pp_25_65); - r4bs r4bs_5200_4928(yy[12], yy[13], single[26], double[26], neg[26], pp_26_65); - fullAdd_x FA_5200_5056(int_17_65, int_16_65, pp_24_65, pp_25_65, pp_26_65); - r4bs r4bs_5200_5272(yy[10], yy[11], single[27], double[27], neg[27], pp_27_65); - r4bs r4bs_5200_5400(yy[8], yy[9], single[28], double[28], neg[28], pp_28_65); - r4bs r4bs_5200_5528(yy[6], yy[7], single[29], double[29], neg[29], pp_29_65); - fullAdd_x FA_5200_5656(int_19_65, int_18_65, pp_27_65, pp_28_65, pp_29_65); - r4bs r4bs_5200_5872(yy[4], yy[5], single[30], double[30], neg[30], pp_30_65); - r4bs r4bs_5200_6000(yy[2], yy[3], single[31], double[31], neg[31], pp_31_65); - r4bs r4bs_5200_6128(yy[0], yy[1], single[32], double[32], neg[32], pp_32_65); - fullAdd_x FA_5200_6256(int_21_65, int_20_65, pp_30_65, pp_31_65, pp_32_65); - fullAdd_x FA_5200_6472(int_23_65, int_22_65, int_1_64, int_3_64, int_5_64); - fullAdd_x FA_5200_6688(int_25_65, int_24_65, int_7_64, int_9_64, int_11_64); - fullAdd_x FA_5200_6904(int_27_65, int_26_65, int_13_64, int_15_64, int_17_64); - fullAdd_x FA_5200_7120(int_29_65, int_28_65, int_19_64, int_21_64, int_23_64); - fullAdd_x FA_5200_7336(int_31_65, int_30_65, int_25_64, int_27_64, int_0_65); - fullAdd_x FA_5200_7552(int_33_65, int_32_65, int_2_65, int_4_65, int_6_65); - fullAdd_x FA_5200_7768(int_35_65, int_34_65, int_8_65, int_10_65, int_12_65); - fullAdd_x FA_5200_7984(int_37_65, int_36_65, int_14_65, int_16_65, int_18_65); - fullAdd_x FA_5200_8200(int_39_65, int_38_65, int_20_65, int_29_64, int_31_64); - fullAdd_x FA_5200_8416(int_41_65, int_40_65, int_33_64, int_35_64, int_37_64); - fullAdd_x FA_5200_8632(int_43_65, int_42_65, int_22_65, int_24_65, int_26_65); - fullAdd_x FA_5200_8848(int_45_65, int_44_65, int_28_65, int_39_64, int_41_64); - fullAdd_x FA_5200_9064(int_47_65, int_46_65, int_43_64, int_30_65, int_32_65); - fullAdd_x FA_5200_9280(int_49_65, int_48_65, int_34_65, int_36_65, int_45_64); - fullAdd_x FA_5200_9496(int_51_65, int_50_65, int_47_64, int_49_64, int_38_65); - fullAdd_x FA_5200_9712(int_53_65, int_52_65, int_40_65, int_42_65, int_51_64); - fullAdd_x FA_5200_9928(int_55_65, int_54_65, int_44_65, int_46_65, int_48_65); - fullAdd_x FA_5200_10144(int_57_65, int_56_65, int_53_64, int_55_64, int_50_65); - fullAdd_x FA_5200_10360(int_59_65, int_58_65, int_52_65, int_57_64, int_54_65); - fullAdd_x FA_5200_10576(int_61_65, int_60_65, int_59_64, int_56_65, int_58_65); - assign Sum[65] = int_61_64; - assign Carry[65] = int_60_65; - - // Hardware for column 66 - - r4bs r4bs_5280_0(yy[63], gnd, single[1], double[1], neg[1], pp_1_66); - r4bs r4bs_5280_128(yy[61], yy[62], single[2], double[2], neg[2], pp_2_66); - fullAdd_x FA_5280_256(int_1_66, int_0_66, neg[0], pp_1_66, pp_2_66); - r4bs r4bs_5280_472(yy[59], yy[60], single[3], double[3], neg[3], pp_3_66); - r4bs r4bs_5280_600(yy[57], yy[58], single[4], double[4], neg[4], pp_4_66); - r4bs r4bs_5280_728(yy[55], yy[56], single[5], double[5], neg[5], pp_5_66); - fullAdd_x FA_5280_856(int_3_66, int_2_66, pp_3_66, pp_4_66, pp_5_66); - r4bs r4bs_5280_1072(yy[53], yy[54], single[6], double[6], neg[6], pp_6_66); - r4bs r4bs_5280_1200(yy[51], yy[52], single[7], double[7], neg[7], pp_7_66); - r4bs r4bs_5280_1328(yy[49], yy[50], single[8], double[8], neg[8], pp_8_66); - fullAdd_x FA_5280_1456(int_5_66, int_4_66, pp_6_66, pp_7_66, pp_8_66); - r4bs r4bs_5280_1672(yy[47], yy[48], single[9], double[9], neg[9], pp_9_66); - r4bs r4bs_5280_1800(yy[45], yy[46], single[10], double[10], neg[10], pp_10_66); - r4bs r4bs_5280_1928(yy[43], yy[44], single[11], double[11], neg[11], pp_11_66); - fullAdd_x FA_5280_2056(int_7_66, int_6_66, pp_9_66, pp_10_66, pp_11_66); - r4bs r4bs_5280_2272(yy[41], yy[42], single[12], double[12], neg[12], pp_12_66); - r4bs r4bs_5280_2400(yy[39], yy[40], single[13], double[13], neg[13], pp_13_66); - r4bs r4bs_5280_2528(yy[37], yy[38], single[14], double[14], neg[14], pp_14_66); - fullAdd_x FA_5280_2656(int_9_66, int_8_66, pp_12_66, pp_13_66, pp_14_66); - r4bs r4bs_5280_2872(yy[35], yy[36], single[15], double[15], neg[15], pp_15_66); - r4bs r4bs_5280_3000(yy[33], yy[34], single[16], double[16], neg[16], pp_16_66); - r4bs r4bs_5280_3128(yy[31], yy[32], single[17], double[17], neg[17], pp_17_66); - fullAdd_x FA_5280_3256(int_11_66, int_10_66, pp_15_66, pp_16_66, pp_17_66); - r4bs r4bs_5280_3472(yy[29], yy[30], single[18], double[18], neg[18], pp_18_66); - r4bs r4bs_5280_3600(yy[27], yy[28], single[19], double[19], neg[19], pp_19_66); - r4bs r4bs_5280_3728(yy[25], yy[26], single[20], double[20], neg[20], pp_20_66); - fullAdd_x FA_5280_3856(int_13_66, int_12_66, pp_18_66, pp_19_66, pp_20_66); - r4bs r4bs_5280_4072(yy[23], yy[24], single[21], double[21], neg[21], pp_21_66); - r4bs r4bs_5280_4200(yy[21], yy[22], single[22], double[22], neg[22], pp_22_66); - r4bs r4bs_5280_4328(yy[19], yy[20], single[23], double[23], neg[23], pp_23_66); - fullAdd_x FA_5280_4456(int_15_66, int_14_66, pp_21_66, pp_22_66, pp_23_66); - r4bs r4bs_5280_4672(yy[17], yy[18], single[24], double[24], neg[24], pp_24_66); - r4bs r4bs_5280_4800(yy[15], yy[16], single[25], double[25], neg[25], pp_25_66); - r4bs r4bs_5280_4928(yy[13], yy[14], single[26], double[26], neg[26], pp_26_66); - fullAdd_x FA_5280_5056(int_17_66, int_16_66, pp_24_66, pp_25_66, pp_26_66); - r4bs r4bs_5280_5272(yy[11], yy[12], single[27], double[27], neg[27], pp_27_66); - r4bs r4bs_5280_5400(yy[9], yy[10], single[28], double[28], neg[28], pp_28_66); - r4bs r4bs_5280_5528(yy[7], yy[8], single[29], double[29], neg[29], pp_29_66); - fullAdd_x FA_5280_5656(int_19_66, int_18_66, pp_27_66, pp_28_66, pp_29_66); - r4bs r4bs_5280_5872(yy[5], yy[6], single[30], double[30], neg[30], pp_30_66); - r4bs r4bs_5280_6000(yy[3], yy[4], single[31], double[31], neg[31], pp_31_66); - r4bs r4bs_5280_6128(yy[1], yy[2], single[32], double[32], neg[32], pp_32_66); - fullAdd_x FA_5280_6256(int_21_66, int_20_66, pp_30_66, pp_31_66, pp_32_66); - fullAdd_x FA_5280_6472(int_23_66, int_22_66, int_1_65, int_3_65, int_5_65); - fullAdd_x FA_5280_6688(int_25_66, int_24_66, int_7_65, int_9_65, int_11_65); - fullAdd_x FA_5280_6904(int_27_66, int_26_66, int_13_65, int_15_65, int_17_65); - fullAdd_x FA_5280_7120(int_29_66, int_28_66, int_19_65, int_21_65, int_23_65); - fullAdd_x FA_5280_7336(int_31_66, int_30_66, int_25_65, int_27_65, int_0_66); - fullAdd_x FA_5280_7552(int_33_66, int_32_66, int_2_66, int_4_66, int_6_66); - fullAdd_x FA_5280_7768(int_35_66, int_34_66, int_8_66, int_10_66, int_12_66); - fullAdd_x FA_5280_7984(int_37_66, int_36_66, int_14_66, int_16_66, int_18_66); - fullAdd_x FA_5280_8200(int_39_66, int_38_66, int_20_66, int_29_65, int_31_65); - fullAdd_x FA_5280_8416(int_41_66, int_40_66, int_33_65, int_35_65, int_37_65); - fullAdd_x FA_5280_8632(int_43_66, int_42_66, int_22_66, int_24_66, int_26_66); - fullAdd_x FA_5280_8848(int_45_66, int_44_66, int_28_66, int_39_65, int_41_65); - fullAdd_x FA_5280_9064(int_47_66, int_46_66, int_43_65, int_30_66, int_32_66); - fullAdd_x FA_5280_9280(int_49_66, int_48_66, int_34_66, int_36_66, int_45_65); - fullAdd_x FA_5280_9496(int_51_66, int_50_66, int_47_65, int_38_66, int_40_66); - fullAdd_x FA_5280_9712(int_53_66, int_52_66, int_42_66, int_49_65, int_51_65); - fullAdd_x FA_5280_9928(int_55_66, int_54_66, int_44_66, int_46_66, int_48_66); - fullAdd_x FA_5280_10144(int_57_66, int_56_66, int_53_65, int_55_65, int_50_66); - fullAdd_x FA_5280_10360(int_59_66, int_58_66, int_57_65, int_52_66, int_54_66); - fullAdd_x FA_5280_10576(int_61_66, int_60_66, int_59_65, int_56_66, int_58_66); - assign Sum[66] = int_61_65; - assign Carry[66] = int_60_66; - - // Hardware for column 67 - - r4bs r4bs_5360_0(yy[62], yy[63], single[2], double[2], neg[2], pp_2_67); - fullAdd_x FA_5360_128(int_1_67, int_0_67, negbar[0], negbar[1], pp_2_67); - r4bs r4bs_5360_344(yy[60], yy[61], single[3], double[3], neg[3], pp_3_67); - r4bs r4bs_5360_472(yy[58], yy[59], single[4], double[4], neg[4], pp_4_67); - r4bs r4bs_5360_600(yy[56], yy[57], single[5], double[5], neg[5], pp_5_67); - fullAdd_x FA_5360_728(int_3_67, int_2_67, pp_3_67, pp_4_67, pp_5_67); - r4bs r4bs_5360_944(yy[54], yy[55], single[6], double[6], neg[6], pp_6_67); - r4bs r4bs_5360_1072(yy[52], yy[53], single[7], double[7], neg[7], pp_7_67); - r4bs r4bs_5360_1200(yy[50], yy[51], single[8], double[8], neg[8], pp_8_67); - fullAdd_x FA_5360_1328(int_5_67, int_4_67, pp_6_67, pp_7_67, pp_8_67); - r4bs r4bs_5360_1544(yy[48], yy[49], single[9], double[9], neg[9], pp_9_67); - r4bs r4bs_5360_1672(yy[46], yy[47], single[10], double[10], neg[10], pp_10_67); - r4bs r4bs_5360_1800(yy[44], yy[45], single[11], double[11], neg[11], pp_11_67); - fullAdd_x FA_5360_1928(int_7_67, int_6_67, pp_9_67, pp_10_67, pp_11_67); - r4bs r4bs_5360_2144(yy[42], yy[43], single[12], double[12], neg[12], pp_12_67); - r4bs r4bs_5360_2272(yy[40], yy[41], single[13], double[13], neg[13], pp_13_67); - r4bs r4bs_5360_2400(yy[38], yy[39], single[14], double[14], neg[14], pp_14_67); - fullAdd_x FA_5360_2528(int_9_67, int_8_67, pp_12_67, pp_13_67, pp_14_67); - r4bs r4bs_5360_2744(yy[36], yy[37], single[15], double[15], neg[15], pp_15_67); - r4bs r4bs_5360_2872(yy[34], yy[35], single[16], double[16], neg[16], pp_16_67); - r4bs r4bs_5360_3000(yy[32], yy[33], single[17], double[17], neg[17], pp_17_67); - fullAdd_x FA_5360_3128(int_11_67, int_10_67, pp_15_67, pp_16_67, pp_17_67); - r4bs r4bs_5360_3344(yy[30], yy[31], single[18], double[18], neg[18], pp_18_67); - r4bs r4bs_5360_3472(yy[28], yy[29], single[19], double[19], neg[19], pp_19_67); - r4bs r4bs_5360_3600(yy[26], yy[27], single[20], double[20], neg[20], pp_20_67); - fullAdd_x FA_5360_3728(int_13_67, int_12_67, pp_18_67, pp_19_67, pp_20_67); - r4bs r4bs_5360_3944(yy[24], yy[25], single[21], double[21], neg[21], pp_21_67); - r4bs r4bs_5360_4072(yy[22], yy[23], single[22], double[22], neg[22], pp_22_67); - r4bs r4bs_5360_4200(yy[20], yy[21], single[23], double[23], neg[23], pp_23_67); - fullAdd_x FA_5360_4328(int_15_67, int_14_67, pp_21_67, pp_22_67, pp_23_67); - r4bs r4bs_5360_4544(yy[18], yy[19], single[24], double[24], neg[24], pp_24_67); - r4bs r4bs_5360_4672(yy[16], yy[17], single[25], double[25], neg[25], pp_25_67); - r4bs r4bs_5360_4800(yy[14], yy[15], single[26], double[26], neg[26], pp_26_67); - fullAdd_x FA_5360_4928(int_17_67, int_16_67, pp_24_67, pp_25_67, pp_26_67); - r4bs r4bs_5360_5144(yy[12], yy[13], single[27], double[27], neg[27], pp_27_67); - r4bs r4bs_5360_5272(yy[10], yy[11], single[28], double[28], neg[28], pp_28_67); - r4bs r4bs_5360_5400(yy[8], yy[9], single[29], double[29], neg[29], pp_29_67); - fullAdd_x FA_5360_5528(int_19_67, int_18_67, pp_27_67, pp_28_67, pp_29_67); - r4bs r4bs_5360_5744(yy[6], yy[7], single[30], double[30], neg[30], pp_30_67); - r4bs r4bs_5360_5872(yy[4], yy[5], single[31], double[31], neg[31], pp_31_67); - r4bs r4bs_5360_6000(yy[2], yy[3], single[32], double[32], neg[32], pp_32_67); - fullAdd_x FA_5360_6128(int_21_67, int_20_67, pp_30_67, pp_31_67, pp_32_67); - fullAdd_x FA_5360_6344(int_23_67, int_22_67, int_1_66, int_3_66, int_5_66); - fullAdd_x FA_5360_6560(int_25_67, int_24_67, int_7_66, int_9_66, int_11_66); - fullAdd_x FA_5360_6776(int_27_67, int_26_67, int_13_66, int_15_66, int_17_66); - fullAdd_x FA_5360_6992(int_29_67, int_28_67, int_19_66, int_21_66, int_0_67); - fullAdd_x FA_5360_7208(int_31_67, int_30_67, int_23_66, int_25_66, int_27_66); - fullAdd_x FA_5360_7424(int_33_67, int_32_67, int_2_67, int_4_67, int_6_67); - fullAdd_x FA_5360_7640(int_35_67, int_34_67, int_8_67, int_10_67, int_12_67); - fullAdd_x FA_5360_7856(int_37_67, int_36_67, int_14_67, int_16_67, int_18_67); - fullAdd_x FA_5360_8072(int_39_67, int_38_67, int_20_67, int_29_66, int_31_66); - fullAdd_x FA_5360_8288(int_41_67, int_40_67, int_33_66, int_35_66, int_37_66); - fullAdd_x FA_5360_8504(int_43_67, int_42_67, int_22_67, int_24_67, int_26_67); - fullAdd_x FA_5360_8720(int_45_67, int_44_67, int_28_67, int_39_66, int_41_66); - fullAdd_x FA_5360_8936(int_47_67, int_46_67, int_43_66, int_30_67, int_32_67); - fullAdd_x FA_5360_9152(int_49_67, int_48_67, int_34_67, int_36_67, int_45_66); - fullAdd_x FA_5360_9368(int_51_67, int_50_67, int_47_66, int_38_67, int_40_67); - fullAdd_x FA_5360_9584(int_53_67, int_52_67, int_42_67, int_49_66, int_51_66); - fullAdd_x FA_5360_9800(int_55_67, int_54_67, int_44_67, int_46_67, int_48_67); - fullAdd_x FA_5360_10016(int_57_67, int_56_67, int_53_66, int_55_66, int_50_67); - fullAdd_x FA_5360_10232(int_59_67, int_58_67, int_57_66, int_52_67, int_54_67); - fullAdd_x FA_5360_10448(int_61_67, int_60_67, int_59_66, int_56_67, int_58_67); - assign Sum[67] = int_61_66; - assign Carry[67] = int_60_67; - - // Hardware for column 68 - - r4bs r4bs_5440_0(yy[63], gnd, single[2], double[2], neg[2], pp_2_68); - halfAdd HA_5440_128(int_1_68, int_0_68, 1'b1, pp_2_68); - r4bs r4bs_5440_208(yy[61], yy[62], single[3], double[3], neg[3], pp_3_68); - r4bs r4bs_5440_336(yy[59], yy[60], single[4], double[4], neg[4], pp_4_68); - r4bs r4bs_5440_464(yy[57], yy[58], single[5], double[5], neg[5], pp_5_68); - fullAdd_x FA_5440_592(int_3_68, int_2_68, pp_3_68, pp_4_68, pp_5_68); - r4bs r4bs_5440_808(yy[55], yy[56], single[6], double[6], neg[6], pp_6_68); - r4bs r4bs_5440_936(yy[53], yy[54], single[7], double[7], neg[7], pp_7_68); - r4bs r4bs_5440_1064(yy[51], yy[52], single[8], double[8], neg[8], pp_8_68); - fullAdd_x FA_5440_1192(int_5_68, int_4_68, pp_6_68, pp_7_68, pp_8_68); - r4bs r4bs_5440_1408(yy[49], yy[50], single[9], double[9], neg[9], pp_9_68); - r4bs r4bs_5440_1536(yy[47], yy[48], single[10], double[10], neg[10], pp_10_68); - r4bs r4bs_5440_1664(yy[45], yy[46], single[11], double[11], neg[11], pp_11_68); - fullAdd_x FA_5440_1792(int_7_68, int_6_68, pp_9_68, pp_10_68, pp_11_68); - r4bs r4bs_5440_2008(yy[43], yy[44], single[12], double[12], neg[12], pp_12_68); - r4bs r4bs_5440_2136(yy[41], yy[42], single[13], double[13], neg[13], pp_13_68); - r4bs r4bs_5440_2264(yy[39], yy[40], single[14], double[14], neg[14], pp_14_68); - fullAdd_x FA_5440_2392(int_9_68, int_8_68, pp_12_68, pp_13_68, pp_14_68); - r4bs r4bs_5440_2608(yy[37], yy[38], single[15], double[15], neg[15], pp_15_68); - r4bs r4bs_5440_2736(yy[35], yy[36], single[16], double[16], neg[16], pp_16_68); - r4bs r4bs_5440_2864(yy[33], yy[34], single[17], double[17], neg[17], pp_17_68); - fullAdd_x FA_5440_2992(int_11_68, int_10_68, pp_15_68, pp_16_68, pp_17_68); - r4bs r4bs_5440_3208(yy[31], yy[32], single[18], double[18], neg[18], pp_18_68); - r4bs r4bs_5440_3336(yy[29], yy[30], single[19], double[19], neg[19], pp_19_68); - r4bs r4bs_5440_3464(yy[27], yy[28], single[20], double[20], neg[20], pp_20_68); - fullAdd_x FA_5440_3592(int_13_68, int_12_68, pp_18_68, pp_19_68, pp_20_68); - r4bs r4bs_5440_3808(yy[25], yy[26], single[21], double[21], neg[21], pp_21_68); - r4bs r4bs_5440_3936(yy[23], yy[24], single[22], double[22], neg[22], pp_22_68); - r4bs r4bs_5440_4064(yy[21], yy[22], single[23], double[23], neg[23], pp_23_68); - fullAdd_x FA_5440_4192(int_15_68, int_14_68, pp_21_68, pp_22_68, pp_23_68); - r4bs r4bs_5440_4408(yy[19], yy[20], single[24], double[24], neg[24], pp_24_68); - r4bs r4bs_5440_4536(yy[17], yy[18], single[25], double[25], neg[25], pp_25_68); - r4bs r4bs_5440_4664(yy[15], yy[16], single[26], double[26], neg[26], pp_26_68); - fullAdd_x FA_5440_4792(int_17_68, int_16_68, pp_24_68, pp_25_68, pp_26_68); - r4bs r4bs_5440_5008(yy[13], yy[14], single[27], double[27], neg[27], pp_27_68); - r4bs r4bs_5440_5136(yy[11], yy[12], single[28], double[28], neg[28], pp_28_68); - r4bs r4bs_5440_5264(yy[9], yy[10], single[29], double[29], neg[29], pp_29_68); - fullAdd_x FA_5440_5392(int_19_68, int_18_68, pp_27_68, pp_28_68, pp_29_68); - r4bs r4bs_5440_5608(yy[7], yy[8], single[30], double[30], neg[30], pp_30_68); - r4bs r4bs_5440_5736(yy[5], yy[6], single[31], double[31], neg[31], pp_31_68); - r4bs r4bs_5440_5864(yy[3], yy[4], single[32], double[32], neg[32], pp_32_68); - fullAdd_x FA_5440_5992(int_21_68, int_20_68, pp_30_68, pp_31_68, pp_32_68); - fullAdd_x FA_5440_6208(int_23_68, int_22_68, int_1_67, int_3_67, int_5_67); - fullAdd_x FA_5440_6424(int_25_68, int_24_68, int_7_67, int_9_67, int_11_67); - fullAdd_x FA_5440_6640(int_27_68, int_26_68, int_13_67, int_15_67, int_17_67); - fullAdd_x FA_5440_6856(int_29_68, int_28_68, int_19_67, int_21_67, int_0_68); - fullAdd_x FA_5440_7072(int_31_68, int_30_68, int_23_67, int_25_67, int_27_67); - fullAdd_x FA_5440_7288(int_33_68, int_32_68, int_29_67, int_2_68, int_4_68); - fullAdd_x FA_5440_7504(int_35_68, int_34_68, int_6_68, int_8_68, int_10_68); - fullAdd_x FA_5440_7720(int_37_68, int_36_68, int_12_68, int_14_68, int_16_68); - fullAdd_x FA_5440_7936(int_39_68, int_38_68, int_18_68, int_20_68, int_31_67); - fullAdd_x FA_5440_8152(int_41_68, int_40_68, int_33_67, int_35_67, int_37_67); - fullAdd_x FA_5440_8368(int_43_68, int_42_68, int_22_68, int_24_68, int_26_68); - fullAdd_x FA_5440_8584(int_45_68, int_44_68, int_28_68, int_39_67, int_41_67); - fullAdd_x FA_5440_8800(int_47_68, int_46_68, int_43_67, int_30_68, int_32_68); - fullAdd_x FA_5440_9016(int_49_68, int_48_68, int_34_68, int_36_68, int_38_68); - fullAdd_x FA_5440_9232(int_51_68, int_50_68, int_45_67, int_47_67, int_40_68); - fullAdd_x FA_5440_9448(int_53_68, int_52_68, int_42_68, int_49_67, int_51_67); - fullAdd_x FA_5440_9664(int_55_68, int_54_68, int_44_68, int_46_68, int_48_68); - fullAdd_x FA_5440_9880(int_57_68, int_56_68, int_53_67, int_55_67, int_50_68); - fullAdd_x FA_5440_10096(int_59_68, int_58_68, int_57_67, int_52_68, int_54_68); - fullAdd_x FA_5440_10312(int_61_68, int_60_68, int_59_67, int_56_68, int_58_68); - assign Sum[68] = int_61_67; - assign Carry[68] = int_60_68; - - // Hardware for column 69 - - r4bs r4bs_5520_0(yy[62], yy[63], single[3], double[3], neg[3], pp_3_69); - r4bs r4bs_5520_128(yy[60], yy[61], single[4], double[4], neg[4], pp_4_69); - fullAdd_x FA_5520_256(int_1_69, int_0_69, negbar[2], pp_3_69, pp_4_69); - r4bs r4bs_5520_472(yy[58], yy[59], single[5], double[5], neg[5], pp_5_69); - r4bs r4bs_5520_600(yy[56], yy[57], single[6], double[6], neg[6], pp_6_69); - r4bs r4bs_5520_728(yy[54], yy[55], single[7], double[7], neg[7], pp_7_69); - fullAdd_x FA_5520_856(int_3_69, int_2_69, pp_5_69, pp_6_69, pp_7_69); - r4bs r4bs_5520_1072(yy[52], yy[53], single[8], double[8], neg[8], pp_8_69); - r4bs r4bs_5520_1200(yy[50], yy[51], single[9], double[9], neg[9], pp_9_69); - r4bs r4bs_5520_1328(yy[48], yy[49], single[10], double[10], neg[10], pp_10_69); - fullAdd_x FA_5520_1456(int_5_69, int_4_69, pp_8_69, pp_9_69, pp_10_69); - r4bs r4bs_5520_1672(yy[46], yy[47], single[11], double[11], neg[11], pp_11_69); - r4bs r4bs_5520_1800(yy[44], yy[45], single[12], double[12], neg[12], pp_12_69); - r4bs r4bs_5520_1928(yy[42], yy[43], single[13], double[13], neg[13], pp_13_69); - fullAdd_x FA_5520_2056(int_7_69, int_6_69, pp_11_69, pp_12_69, pp_13_69); - r4bs r4bs_5520_2272(yy[40], yy[41], single[14], double[14], neg[14], pp_14_69); - r4bs r4bs_5520_2400(yy[38], yy[39], single[15], double[15], neg[15], pp_15_69); - r4bs r4bs_5520_2528(yy[36], yy[37], single[16], double[16], neg[16], pp_16_69); - fullAdd_x FA_5520_2656(int_9_69, int_8_69, pp_14_69, pp_15_69, pp_16_69); - r4bs r4bs_5520_2872(yy[34], yy[35], single[17], double[17], neg[17], pp_17_69); - r4bs r4bs_5520_3000(yy[32], yy[33], single[18], double[18], neg[18], pp_18_69); - r4bs r4bs_5520_3128(yy[30], yy[31], single[19], double[19], neg[19], pp_19_69); - fullAdd_x FA_5520_3256(int_11_69, int_10_69, pp_17_69, pp_18_69, pp_19_69); - r4bs r4bs_5520_3472(yy[28], yy[29], single[20], double[20], neg[20], pp_20_69); - r4bs r4bs_5520_3600(yy[26], yy[27], single[21], double[21], neg[21], pp_21_69); - r4bs r4bs_5520_3728(yy[24], yy[25], single[22], double[22], neg[22], pp_22_69); - fullAdd_x FA_5520_3856(int_13_69, int_12_69, pp_20_69, pp_21_69, pp_22_69); - r4bs r4bs_5520_4072(yy[22], yy[23], single[23], double[23], neg[23], pp_23_69); - r4bs r4bs_5520_4200(yy[20], yy[21], single[24], double[24], neg[24], pp_24_69); - r4bs r4bs_5520_4328(yy[18], yy[19], single[25], double[25], neg[25], pp_25_69); - fullAdd_x FA_5520_4456(int_15_69, int_14_69, pp_23_69, pp_24_69, pp_25_69); - r4bs r4bs_5520_4672(yy[16], yy[17], single[26], double[26], neg[26], pp_26_69); - r4bs r4bs_5520_4800(yy[14], yy[15], single[27], double[27], neg[27], pp_27_69); - r4bs r4bs_5520_4928(yy[12], yy[13], single[28], double[28], neg[28], pp_28_69); - fullAdd_x FA_5520_5056(int_17_69, int_16_69, pp_26_69, pp_27_69, pp_28_69); - r4bs r4bs_5520_5272(yy[10], yy[11], single[29], double[29], neg[29], pp_29_69); - r4bs r4bs_5520_5400(yy[8], yy[9], single[30], double[30], neg[30], pp_30_69); - r4bs r4bs_5520_5528(yy[6], yy[7], single[31], double[31], neg[31], pp_31_69); - fullAdd_x FA_5520_5656(int_19_69, int_18_69, pp_29_69, pp_30_69, pp_31_69); - r4bs r4bs_5520_5872(yy[4], yy[5], single[32], double[32], neg[32], pp_32_69); - fullAdd_x FA_5520_6000(int_21_69, int_20_69, pp_32_69, int_1_68, int_3_68); - fullAdd_x FA_5520_6216(int_23_69, int_22_69, int_5_68, int_7_68, int_9_68); - fullAdd_x FA_5520_6432(int_25_69, int_24_69, int_11_68, int_13_68, int_15_68); - fullAdd_x FA_5520_6648(int_27_69, int_26_69, int_17_68, int_19_68, int_21_68); - fullAdd_x FA_5520_6864(int_29_69, int_28_69, int_23_68, int_25_68, int_27_68); - fullAdd_x FA_5520_7080(int_31_69, int_30_69, int_29_68, int_0_69, int_2_69); - fullAdd_x FA_5520_7296(int_33_69, int_32_69, int_4_69, int_6_69, int_8_69); - fullAdd_x FA_5520_7512(int_35_69, int_34_69, int_10_69, int_12_69, int_14_69); - fullAdd_x FA_5520_7728(int_37_69, int_36_69, int_16_69, int_18_69, int_20_69); - fullAdd_x FA_5520_7944(int_39_69, int_38_69, int_31_68, int_33_68, int_35_68); - fullAdd_x FA_5520_8160(int_41_69, int_40_69, int_37_68, int_22_69, int_24_69); - fullAdd_x FA_5520_8376(int_43_69, int_42_69, int_26_69, int_39_68, int_41_68); - fullAdd_x FA_5520_8592(int_45_69, int_44_69, int_43_68, int_28_69, int_30_69); - fullAdd_x FA_5520_8808(int_47_69, int_46_69, int_32_69, int_34_69, int_36_69); - fullAdd_x FA_5520_9024(int_49_69, int_48_69, int_45_68, int_47_68, int_49_68); - fullAdd_x FA_5520_9240(int_51_69, int_50_69, int_38_69, int_40_69, int_51_68); - fullAdd_x FA_5520_9456(int_53_69, int_52_69, int_42_69, int_44_69, int_46_69); - fullAdd_x FA_5520_9672(int_55_69, int_54_69, int_53_68, int_55_68, int_48_69); - fullAdd_x FA_5520_9888(int_57_69, int_56_69, int_50_69, int_57_68, int_52_69); - fullAdd_x FA_5520_10104(int_59_69, int_58_69, int_59_68, int_54_69, int_56_69); - assign Sum[69] = int_61_68; - assign Carry[69] = int_58_69; - - // Hardware for column 70 - - r4bs r4bs_5600_0(yy[63], gnd, single[3], double[3], neg[3], pp_3_70); - halfAdd HA_5600_128(int_1_70, int_0_70, 1'b1, pp_3_70); - r4bs r4bs_5600_208(yy[61], yy[62], single[4], double[4], neg[4], pp_4_70); - r4bs r4bs_5600_336(yy[59], yy[60], single[5], double[5], neg[5], pp_5_70); - r4bs r4bs_5600_464(yy[57], yy[58], single[6], double[6], neg[6], pp_6_70); - fullAdd_x FA_5600_592(int_3_70, int_2_70, pp_4_70, pp_5_70, pp_6_70); - r4bs r4bs_5600_808(yy[55], yy[56], single[7], double[7], neg[7], pp_7_70); - r4bs r4bs_5600_936(yy[53], yy[54], single[8], double[8], neg[8], pp_8_70); - r4bs r4bs_5600_1064(yy[51], yy[52], single[9], double[9], neg[9], pp_9_70); - fullAdd_x FA_5600_1192(int_5_70, int_4_70, pp_7_70, pp_8_70, pp_9_70); - r4bs r4bs_5600_1408(yy[49], yy[50], single[10], double[10], neg[10], pp_10_70); - r4bs r4bs_5600_1536(yy[47], yy[48], single[11], double[11], neg[11], pp_11_70); - r4bs r4bs_5600_1664(yy[45], yy[46], single[12], double[12], neg[12], pp_12_70); - fullAdd_x FA_5600_1792(int_7_70, int_6_70, pp_10_70, pp_11_70, pp_12_70); - r4bs r4bs_5600_2008(yy[43], yy[44], single[13], double[13], neg[13], pp_13_70); - r4bs r4bs_5600_2136(yy[41], yy[42], single[14], double[14], neg[14], pp_14_70); - r4bs r4bs_5600_2264(yy[39], yy[40], single[15], double[15], neg[15], pp_15_70); - fullAdd_x FA_5600_2392(int_9_70, int_8_70, pp_13_70, pp_14_70, pp_15_70); - r4bs r4bs_5600_2608(yy[37], yy[38], single[16], double[16], neg[16], pp_16_70); - r4bs r4bs_5600_2736(yy[35], yy[36], single[17], double[17], neg[17], pp_17_70); - r4bs r4bs_5600_2864(yy[33], yy[34], single[18], double[18], neg[18], pp_18_70); - fullAdd_x FA_5600_2992(int_11_70, int_10_70, pp_16_70, pp_17_70, pp_18_70); - r4bs r4bs_5600_3208(yy[31], yy[32], single[19], double[19], neg[19], pp_19_70); - r4bs r4bs_5600_3336(yy[29], yy[30], single[20], double[20], neg[20], pp_20_70); - r4bs r4bs_5600_3464(yy[27], yy[28], single[21], double[21], neg[21], pp_21_70); - fullAdd_x FA_5600_3592(int_13_70, int_12_70, pp_19_70, pp_20_70, pp_21_70); - r4bs r4bs_5600_3808(yy[25], yy[26], single[22], double[22], neg[22], pp_22_70); - r4bs r4bs_5600_3936(yy[23], yy[24], single[23], double[23], neg[23], pp_23_70); - r4bs r4bs_5600_4064(yy[21], yy[22], single[24], double[24], neg[24], pp_24_70); - fullAdd_x FA_5600_4192(int_15_70, int_14_70, pp_22_70, pp_23_70, pp_24_70); - r4bs r4bs_5600_4408(yy[19], yy[20], single[25], double[25], neg[25], pp_25_70); - r4bs r4bs_5600_4536(yy[17], yy[18], single[26], double[26], neg[26], pp_26_70); - r4bs r4bs_5600_4664(yy[15], yy[16], single[27], double[27], neg[27], pp_27_70); - fullAdd_x FA_5600_4792(int_17_70, int_16_70, pp_25_70, pp_26_70, pp_27_70); - r4bs r4bs_5600_5008(yy[13], yy[14], single[28], double[28], neg[28], pp_28_70); - r4bs r4bs_5600_5136(yy[11], yy[12], single[29], double[29], neg[29], pp_29_70); - r4bs r4bs_5600_5264(yy[9], yy[10], single[30], double[30], neg[30], pp_30_70); - fullAdd_x FA_5600_5392(int_19_70, int_18_70, pp_28_70, pp_29_70, pp_30_70); - r4bs r4bs_5600_5608(yy[7], yy[8], single[31], double[31], neg[31], pp_31_70); - r4bs r4bs_5600_5736(yy[5], yy[6], single[32], double[32], neg[32], pp_32_70); - fullAdd_x FA_5600_5864(int_21_70, int_20_70, pp_31_70, pp_32_70, int_1_69); - fullAdd_x FA_5600_6080(int_23_70, int_22_70, int_3_69, int_5_69, int_7_69); - fullAdd_x FA_5600_6296(int_25_70, int_24_70, int_9_69, int_11_69, int_13_69); - fullAdd_x FA_5600_6512(int_27_70, int_26_70, int_15_69, int_17_69, int_19_69); - fullAdd_x FA_5600_6728(int_29_70, int_28_70, int_0_70, int_21_69, int_23_69); - fullAdd_x FA_5600_6944(int_31_70, int_30_70, int_25_69, int_27_69, int_2_70); - fullAdd_x FA_5600_7160(int_33_70, int_32_70, int_4_70, int_6_70, int_8_70); - fullAdd_x FA_5600_7376(int_35_70, int_34_70, int_10_70, int_12_70, int_14_70); - fullAdd_x FA_5600_7592(int_37_70, int_36_70, int_16_70, int_18_70, int_20_70); - fullAdd_x FA_5600_7808(int_39_70, int_38_70, int_29_69, int_31_69, int_33_69); - fullAdd_x FA_5600_8024(int_41_70, int_40_70, int_35_69, int_22_70, int_24_70); - fullAdd_x FA_5600_8240(int_43_70, int_42_70, int_26_70, int_37_69, int_39_69); - fullAdd_x FA_5600_8456(int_45_70, int_44_70, int_41_69, int_28_70, int_30_70); - fullAdd_x FA_5600_8672(int_47_70, int_46_70, int_32_70, int_34_70, int_36_70); - fullAdd_x FA_5600_8888(int_49_70, int_48_70, int_43_69, int_45_69, int_47_69); - fullAdd_x FA_5600_9104(int_51_70, int_50_70, int_38_70, int_40_70, int_42_70); - fullAdd_x FA_5600_9320(int_53_70, int_52_70, int_49_69, int_44_70, int_46_70); - fullAdd_x FA_5600_9536(int_55_70, int_54_70, int_51_69, int_53_69, int_48_70); - fullAdd_x FA_5600_9752(int_57_70, int_56_70, int_50_70, int_55_69, int_52_70); - fullAdd_x FA_5600_9968(int_59_70, int_58_70, int_57_69, int_54_70, int_56_70); - assign Sum[70] = int_59_69; - assign Carry[70] = int_58_70; - - // Hardware for column 71 - - r4bs r4bs_5680_0(yy[62], yy[63], single[4], double[4], neg[4], pp_4_71); - r4bs r4bs_5680_128(yy[60], yy[61], single[5], double[5], neg[5], pp_5_71); - fullAdd_x FA_5680_256(int_1_71, int_0_71, negbar[3], pp_4_71, pp_5_71); - r4bs r4bs_5680_472(yy[58], yy[59], single[6], double[6], neg[6], pp_6_71); - r4bs r4bs_5680_600(yy[56], yy[57], single[7], double[7], neg[7], pp_7_71); - r4bs r4bs_5680_728(yy[54], yy[55], single[8], double[8], neg[8], pp_8_71); - fullAdd_x FA_5680_856(int_3_71, int_2_71, pp_6_71, pp_7_71, pp_8_71); - r4bs r4bs_5680_1072(yy[52], yy[53], single[9], double[9], neg[9], pp_9_71); - r4bs r4bs_5680_1200(yy[50], yy[51], single[10], double[10], neg[10], pp_10_71); - r4bs r4bs_5680_1328(yy[48], yy[49], single[11], double[11], neg[11], pp_11_71); - fullAdd_x FA_5680_1456(int_5_71, int_4_71, pp_9_71, pp_10_71, pp_11_71); - r4bs r4bs_5680_1672(yy[46], yy[47], single[12], double[12], neg[12], pp_12_71); - r4bs r4bs_5680_1800(yy[44], yy[45], single[13], double[13], neg[13], pp_13_71); - r4bs r4bs_5680_1928(yy[42], yy[43], single[14], double[14], neg[14], pp_14_71); - fullAdd_x FA_5680_2056(int_7_71, int_6_71, pp_12_71, pp_13_71, pp_14_71); - r4bs r4bs_5680_2272(yy[40], yy[41], single[15], double[15], neg[15], pp_15_71); - r4bs r4bs_5680_2400(yy[38], yy[39], single[16], double[16], neg[16], pp_16_71); - r4bs r4bs_5680_2528(yy[36], yy[37], single[17], double[17], neg[17], pp_17_71); - fullAdd_x FA_5680_2656(int_9_71, int_8_71, pp_15_71, pp_16_71, pp_17_71); - r4bs r4bs_5680_2872(yy[34], yy[35], single[18], double[18], neg[18], pp_18_71); - r4bs r4bs_5680_3000(yy[32], yy[33], single[19], double[19], neg[19], pp_19_71); - r4bs r4bs_5680_3128(yy[30], yy[31], single[20], double[20], neg[20], pp_20_71); - fullAdd_x FA_5680_3256(int_11_71, int_10_71, pp_18_71, pp_19_71, pp_20_71); - r4bs r4bs_5680_3472(yy[28], yy[29], single[21], double[21], neg[21], pp_21_71); - r4bs r4bs_5680_3600(yy[26], yy[27], single[22], double[22], neg[22], pp_22_71); - r4bs r4bs_5680_3728(yy[24], yy[25], single[23], double[23], neg[23], pp_23_71); - fullAdd_x FA_5680_3856(int_13_71, int_12_71, pp_21_71, pp_22_71, pp_23_71); - r4bs r4bs_5680_4072(yy[22], yy[23], single[24], double[24], neg[24], pp_24_71); - r4bs r4bs_5680_4200(yy[20], yy[21], single[25], double[25], neg[25], pp_25_71); - r4bs r4bs_5680_4328(yy[18], yy[19], single[26], double[26], neg[26], pp_26_71); - fullAdd_x FA_5680_4456(int_15_71, int_14_71, pp_24_71, pp_25_71, pp_26_71); - r4bs r4bs_5680_4672(yy[16], yy[17], single[27], double[27], neg[27], pp_27_71); - r4bs r4bs_5680_4800(yy[14], yy[15], single[28], double[28], neg[28], pp_28_71); - r4bs r4bs_5680_4928(yy[12], yy[13], single[29], double[29], neg[29], pp_29_71); - fullAdd_x FA_5680_5056(int_17_71, int_16_71, pp_27_71, pp_28_71, pp_29_71); - r4bs r4bs_5680_5272(yy[10], yy[11], single[30], double[30], neg[30], pp_30_71); - r4bs r4bs_5680_5400(yy[8], yy[9], single[31], double[31], neg[31], pp_31_71); - r4bs r4bs_5680_5528(yy[6], yy[7], single[32], double[32], neg[32], pp_32_71); - fullAdd_x FA_5680_5656(int_19_71, int_18_71, pp_30_71, pp_31_71, pp_32_71); - fullAdd_x FA_5680_5872(int_21_71, int_20_71, int_1_70, int_3_70, int_5_70); - fullAdd_x FA_5680_6088(int_23_71, int_22_71, int_7_70, int_9_70, int_11_70); - fullAdd_x FA_5680_6304(int_25_71, int_24_71, int_13_70, int_15_70, int_17_70); - fullAdd_x FA_5680_6520(int_27_71, int_26_71, int_19_70, int_21_70, int_23_70); - fullAdd_x FA_5680_6736(int_29_71, int_28_71, int_25_70, int_27_70, int_0_71); - fullAdd_x FA_5680_6952(int_31_71, int_30_71, int_2_71, int_4_71, int_6_71); - fullAdd_x FA_5680_7168(int_33_71, int_32_71, int_8_71, int_10_71, int_12_71); - fullAdd_x FA_5680_7384(int_35_71, int_34_71, int_14_71, int_16_71, int_18_71); - fullAdd_x FA_5680_7600(int_37_71, int_36_71, int_29_70, int_31_70, int_33_70); - fullAdd_x FA_5680_7816(int_39_71, int_38_71, int_35_70, int_37_70, int_20_71); - fullAdd_x FA_5680_8032(int_41_71, int_40_71, int_22_71, int_24_71, int_39_70); - fullAdd_x FA_5680_8248(int_43_71, int_42_71, int_41_70, int_26_71, int_28_71); - fullAdd_x FA_5680_8464(int_45_71, int_44_71, int_30_71, int_32_71, int_34_71); - fullAdd_x FA_5680_8680(int_47_71, int_46_71, int_43_70, int_45_70, int_47_70); - fullAdd_x FA_5680_8896(int_49_71, int_48_71, int_36_71, int_38_71, int_40_71); - fullAdd_x FA_5680_9112(int_51_71, int_50_71, int_49_70, int_42_71, int_44_71); - fullAdd_x FA_5680_9328(int_53_71, int_52_71, int_51_70, int_53_70, int_46_71); - fullAdd_x FA_5680_9544(int_55_71, int_54_71, int_48_71, int_55_70, int_50_71); - fullAdd_x FA_5680_9760(int_57_71, int_56_71, int_57_70, int_52_71, int_54_71); - assign Sum[71] = int_59_70; - assign Carry[71] = int_56_71; - - // Hardware for column 72 - - r4bs r4bs_5760_0(yy[63], gnd, single[4], double[4], neg[4], pp_4_72); - halfAdd HA_5760_128(int_1_72, int_0_72, 1'b1, pp_4_72); - r4bs r4bs_5760_208(yy[61], yy[62], single[5], double[5], neg[5], pp_5_72); - r4bs r4bs_5760_336(yy[59], yy[60], single[6], double[6], neg[6], pp_6_72); - r4bs r4bs_5760_464(yy[57], yy[58], single[7], double[7], neg[7], pp_7_72); - fullAdd_x FA_5760_592(int_3_72, int_2_72, pp_5_72, pp_6_72, pp_7_72); - r4bs r4bs_5760_808(yy[55], yy[56], single[8], double[8], neg[8], pp_8_72); - r4bs r4bs_5760_936(yy[53], yy[54], single[9], double[9], neg[9], pp_9_72); - r4bs r4bs_5760_1064(yy[51], yy[52], single[10], double[10], neg[10], pp_10_72); - fullAdd_x FA_5760_1192(int_5_72, int_4_72, pp_8_72, pp_9_72, pp_10_72); - r4bs r4bs_5760_1408(yy[49], yy[50], single[11], double[11], neg[11], pp_11_72); - r4bs r4bs_5760_1536(yy[47], yy[48], single[12], double[12], neg[12], pp_12_72); - r4bs r4bs_5760_1664(yy[45], yy[46], single[13], double[13], neg[13], pp_13_72); - fullAdd_x FA_5760_1792(int_7_72, int_6_72, pp_11_72, pp_12_72, pp_13_72); - r4bs r4bs_5760_2008(yy[43], yy[44], single[14], double[14], neg[14], pp_14_72); - r4bs r4bs_5760_2136(yy[41], yy[42], single[15], double[15], neg[15], pp_15_72); - r4bs r4bs_5760_2264(yy[39], yy[40], single[16], double[16], neg[16], pp_16_72); - fullAdd_x FA_5760_2392(int_9_72, int_8_72, pp_14_72, pp_15_72, pp_16_72); - r4bs r4bs_5760_2608(yy[37], yy[38], single[17], double[17], neg[17], pp_17_72); - r4bs r4bs_5760_2736(yy[35], yy[36], single[18], double[18], neg[18], pp_18_72); - r4bs r4bs_5760_2864(yy[33], yy[34], single[19], double[19], neg[19], pp_19_72); - fullAdd_x FA_5760_2992(int_11_72, int_10_72, pp_17_72, pp_18_72, pp_19_72); - r4bs r4bs_5760_3208(yy[31], yy[32], single[20], double[20], neg[20], pp_20_72); - r4bs r4bs_5760_3336(yy[29], yy[30], single[21], double[21], neg[21], pp_21_72); - r4bs r4bs_5760_3464(yy[27], yy[28], single[22], double[22], neg[22], pp_22_72); - fullAdd_x FA_5760_3592(int_13_72, int_12_72, pp_20_72, pp_21_72, pp_22_72); - r4bs r4bs_5760_3808(yy[25], yy[26], single[23], double[23], neg[23], pp_23_72); - r4bs r4bs_5760_3936(yy[23], yy[24], single[24], double[24], neg[24], pp_24_72); - r4bs r4bs_5760_4064(yy[21], yy[22], single[25], double[25], neg[25], pp_25_72); - fullAdd_x FA_5760_4192(int_15_72, int_14_72, pp_23_72, pp_24_72, pp_25_72); - r4bs r4bs_5760_4408(yy[19], yy[20], single[26], double[26], neg[26], pp_26_72); - r4bs r4bs_5760_4536(yy[17], yy[18], single[27], double[27], neg[27], pp_27_72); - r4bs r4bs_5760_4664(yy[15], yy[16], single[28], double[28], neg[28], pp_28_72); - fullAdd_x FA_5760_4792(int_17_72, int_16_72, pp_26_72, pp_27_72, pp_28_72); - r4bs r4bs_5760_5008(yy[13], yy[14], single[29], double[29], neg[29], pp_29_72); - r4bs r4bs_5760_5136(yy[11], yy[12], single[30], double[30], neg[30], pp_30_72); - r4bs r4bs_5760_5264(yy[9], yy[10], single[31], double[31], neg[31], pp_31_72); - fullAdd_x FA_5760_5392(int_19_72, int_18_72, pp_29_72, pp_30_72, pp_31_72); - r4bs r4bs_5760_5608(yy[7], yy[8], single[32], double[32], neg[32], pp_32_72); - fullAdd_x FA_5760_5736(int_21_72, int_20_72, pp_32_72, int_1_71, int_3_71); - fullAdd_x FA_5760_5952(int_23_72, int_22_72, int_5_71, int_7_71, int_9_71); - fullAdd_x FA_5760_6168(int_25_72, int_24_72, int_11_71, int_13_71, int_15_71); - fullAdd_x FA_5760_6384(int_27_72, int_26_72, int_17_71, int_19_71, int_0_72); - fullAdd_x FA_5760_6600(int_29_72, int_28_72, int_21_71, int_23_71, int_25_71); - fullAdd_x FA_5760_6816(int_31_72, int_30_72, int_2_72, int_4_72, int_6_72); - fullAdd_x FA_5760_7032(int_33_72, int_32_72, int_8_72, int_10_72, int_12_72); - fullAdd_x FA_5760_7248(int_35_72, int_34_72, int_14_72, int_16_72, int_18_72); - fullAdd_x FA_5760_7464(int_37_72, int_36_72, int_27_71, int_29_71, int_31_71); - fullAdd_x FA_5760_7680(int_39_72, int_38_72, int_33_71, int_35_71, int_20_72); - fullAdd_x FA_5760_7896(int_41_72, int_40_72, int_22_72, int_24_72, int_26_72); - fullAdd_x FA_5760_8112(int_43_72, int_42_72, int_37_71, int_39_71, int_28_72); - fullAdd_x FA_5760_8328(int_45_72, int_44_72, int_30_72, int_32_72, int_34_72); - fullAdd_x FA_5760_8544(int_47_72, int_46_72, int_41_71, int_43_71, int_45_71); - fullAdd_x FA_5760_8760(int_49_72, int_48_72, int_36_72, int_38_72, int_40_72); - fullAdd_x FA_5760_8976(int_51_72, int_50_72, int_47_71, int_49_71, int_42_72); - fullAdd_x FA_5760_9192(int_53_72, int_52_72, int_44_72, int_51_71, int_46_72); - fullAdd_x FA_5760_9408(int_55_72, int_54_72, int_48_72, int_53_71, int_50_72); - fullAdd_x FA_5760_9624(int_57_72, int_56_72, int_55_71, int_52_72, int_54_72); - assign Sum[72] = int_57_71; - assign Carry[72] = int_56_72; - - // Hardware for column 73 - - r4bs r4bs_5840_0(yy[62], yy[63], single[5], double[5], neg[5], pp_5_73); - r4bs r4bs_5840_128(yy[60], yy[61], single[6], double[6], neg[6], pp_6_73); - fullAdd_x FA_5840_256(int_1_73, int_0_73, negbar[4], pp_5_73, pp_6_73); - r4bs r4bs_5840_472(yy[58], yy[59], single[7], double[7], neg[7], pp_7_73); - r4bs r4bs_5840_600(yy[56], yy[57], single[8], double[8], neg[8], pp_8_73); - r4bs r4bs_5840_728(yy[54], yy[55], single[9], double[9], neg[9], pp_9_73); - fullAdd_x FA_5840_856(int_3_73, int_2_73, pp_7_73, pp_8_73, pp_9_73); - r4bs r4bs_5840_1072(yy[52], yy[53], single[10], double[10], neg[10], pp_10_73); - r4bs r4bs_5840_1200(yy[50], yy[51], single[11], double[11], neg[11], pp_11_73); - r4bs r4bs_5840_1328(yy[48], yy[49], single[12], double[12], neg[12], pp_12_73); - fullAdd_x FA_5840_1456(int_5_73, int_4_73, pp_10_73, pp_11_73, pp_12_73); - r4bs r4bs_5840_1672(yy[46], yy[47], single[13], double[13], neg[13], pp_13_73); - r4bs r4bs_5840_1800(yy[44], yy[45], single[14], double[14], neg[14], pp_14_73); - r4bs r4bs_5840_1928(yy[42], yy[43], single[15], double[15], neg[15], pp_15_73); - fullAdd_x FA_5840_2056(int_7_73, int_6_73, pp_13_73, pp_14_73, pp_15_73); - r4bs r4bs_5840_2272(yy[40], yy[41], single[16], double[16], neg[16], pp_16_73); - r4bs r4bs_5840_2400(yy[38], yy[39], single[17], double[17], neg[17], pp_17_73); - r4bs r4bs_5840_2528(yy[36], yy[37], single[18], double[18], neg[18], pp_18_73); - fullAdd_x FA_5840_2656(int_9_73, int_8_73, pp_16_73, pp_17_73, pp_18_73); - r4bs r4bs_5840_2872(yy[34], yy[35], single[19], double[19], neg[19], pp_19_73); - r4bs r4bs_5840_3000(yy[32], yy[33], single[20], double[20], neg[20], pp_20_73); - r4bs r4bs_5840_3128(yy[30], yy[31], single[21], double[21], neg[21], pp_21_73); - fullAdd_x FA_5840_3256(int_11_73, int_10_73, pp_19_73, pp_20_73, pp_21_73); - r4bs r4bs_5840_3472(yy[28], yy[29], single[22], double[22], neg[22], pp_22_73); - r4bs r4bs_5840_3600(yy[26], yy[27], single[23], double[23], neg[23], pp_23_73); - r4bs r4bs_5840_3728(yy[24], yy[25], single[24], double[24], neg[24], pp_24_73); - fullAdd_x FA_5840_3856(int_13_73, int_12_73, pp_22_73, pp_23_73, pp_24_73); - r4bs r4bs_5840_4072(yy[22], yy[23], single[25], double[25], neg[25], pp_25_73); - r4bs r4bs_5840_4200(yy[20], yy[21], single[26], double[26], neg[26], pp_26_73); - r4bs r4bs_5840_4328(yy[18], yy[19], single[27], double[27], neg[27], pp_27_73); - fullAdd_x FA_5840_4456(int_15_73, int_14_73, pp_25_73, pp_26_73, pp_27_73); - r4bs r4bs_5840_4672(yy[16], yy[17], single[28], double[28], neg[28], pp_28_73); - r4bs r4bs_5840_4800(yy[14], yy[15], single[29], double[29], neg[29], pp_29_73); - r4bs r4bs_5840_4928(yy[12], yy[13], single[30], double[30], neg[30], pp_30_73); - fullAdd_x FA_5840_5056(int_17_73, int_16_73, pp_28_73, pp_29_73, pp_30_73); - r4bs r4bs_5840_5272(yy[10], yy[11], single[31], double[31], neg[31], pp_31_73); - r4bs r4bs_5840_5400(yy[8], yy[9], single[32], double[32], neg[32], pp_32_73); - fullAdd_x FA_5840_5528(int_19_73, int_18_73, pp_31_73, pp_32_73, int_1_72); - fullAdd_x FA_5840_5744(int_21_73, int_20_73, int_3_72, int_5_72, int_7_72); - fullAdd_x FA_5840_5960(int_23_73, int_22_73, int_9_72, int_11_72, int_13_72); - fullAdd_x FA_5840_6176(int_25_73, int_24_73, int_15_72, int_17_72, int_19_72); - fullAdd_x FA_5840_6392(int_27_73, int_26_73, int_21_72, int_23_72, int_25_72); - fullAdd_x FA_5840_6608(int_29_73, int_28_73, int_27_72, int_0_73, int_2_73); - fullAdd_x FA_5840_6824(int_31_73, int_30_73, int_4_73, int_6_73, int_8_73); - fullAdd_x FA_5840_7040(int_33_73, int_32_73, int_10_73, int_12_73, int_14_73); - fullAdd_x FA_5840_7256(int_35_73, int_34_73, int_16_73, int_18_73, int_29_72); - fullAdd_x FA_5840_7472(int_37_73, int_36_73, int_31_72, int_33_72, int_35_72); - fullAdd_x FA_5840_7688(int_39_73, int_38_73, int_20_73, int_22_73, int_24_73); - fullAdd_x FA_5840_7904(int_41_73, int_40_73, int_37_72, int_39_72, int_41_72); - fullAdd_x FA_5840_8120(int_43_73, int_42_73, int_26_73, int_28_73, int_30_73); - fullAdd_x FA_5840_8336(int_45_73, int_44_73, int_32_73, int_34_73, int_43_72); - fullAdd_x FA_5840_8552(int_47_73, int_46_73, int_45_72, int_36_73, int_38_73); - fullAdd_x FA_5840_8768(int_49_73, int_48_73, int_47_72, int_49_72, int_40_73); - fullAdd_x FA_5840_8984(int_51_73, int_50_73, int_42_73, int_44_73, int_51_72); - fullAdd_x FA_5840_9200(int_53_73, int_52_73, int_46_73, int_53_72, int_48_73); - fullAdd_x FA_5840_9416(int_55_73, int_54_73, int_50_73, int_55_72, int_52_73); - assign Sum[73] = int_57_72; - assign Carry[73] = int_54_73; - - // Hardware for column 74 - - r4bs r4bs_5920_0(yy[63], gnd, single[5], double[5], neg[5], pp_5_74); - halfAdd HA_5920_128(int_1_74, int_0_74, 1'b1, pp_5_74); - r4bs r4bs_5920_208(yy[61], yy[62], single[6], double[6], neg[6], pp_6_74); - r4bs r4bs_5920_336(yy[59], yy[60], single[7], double[7], neg[7], pp_7_74); - r4bs r4bs_5920_464(yy[57], yy[58], single[8], double[8], neg[8], pp_8_74); - fullAdd_x FA_5920_592(int_3_74, int_2_74, pp_6_74, pp_7_74, pp_8_74); - r4bs r4bs_5920_808(yy[55], yy[56], single[9], double[9], neg[9], pp_9_74); - r4bs r4bs_5920_936(yy[53], yy[54], single[10], double[10], neg[10], pp_10_74); - r4bs r4bs_5920_1064(yy[51], yy[52], single[11], double[11], neg[11], pp_11_74); - fullAdd_x FA_5920_1192(int_5_74, int_4_74, pp_9_74, pp_10_74, pp_11_74); - r4bs r4bs_5920_1408(yy[49], yy[50], single[12], double[12], neg[12], pp_12_74); - r4bs r4bs_5920_1536(yy[47], yy[48], single[13], double[13], neg[13], pp_13_74); - r4bs r4bs_5920_1664(yy[45], yy[46], single[14], double[14], neg[14], pp_14_74); - fullAdd_x FA_5920_1792(int_7_74, int_6_74, pp_12_74, pp_13_74, pp_14_74); - r4bs r4bs_5920_2008(yy[43], yy[44], single[15], double[15], neg[15], pp_15_74); - r4bs r4bs_5920_2136(yy[41], yy[42], single[16], double[16], neg[16], pp_16_74); - r4bs r4bs_5920_2264(yy[39], yy[40], single[17], double[17], neg[17], pp_17_74); - fullAdd_x FA_5920_2392(int_9_74, int_8_74, pp_15_74, pp_16_74, pp_17_74); - r4bs r4bs_5920_2608(yy[37], yy[38], single[18], double[18], neg[18], pp_18_74); - r4bs r4bs_5920_2736(yy[35], yy[36], single[19], double[19], neg[19], pp_19_74); - r4bs r4bs_5920_2864(yy[33], yy[34], single[20], double[20], neg[20], pp_20_74); - fullAdd_x FA_5920_2992(int_11_74, int_10_74, pp_18_74, pp_19_74, pp_20_74); - r4bs r4bs_5920_3208(yy[31], yy[32], single[21], double[21], neg[21], pp_21_74); - r4bs r4bs_5920_3336(yy[29], yy[30], single[22], double[22], neg[22], pp_22_74); - r4bs r4bs_5920_3464(yy[27], yy[28], single[23], double[23], neg[23], pp_23_74); - fullAdd_x FA_5920_3592(int_13_74, int_12_74, pp_21_74, pp_22_74, pp_23_74); - r4bs r4bs_5920_3808(yy[25], yy[26], single[24], double[24], neg[24], pp_24_74); - r4bs r4bs_5920_3936(yy[23], yy[24], single[25], double[25], neg[25], pp_25_74); - r4bs r4bs_5920_4064(yy[21], yy[22], single[26], double[26], neg[26], pp_26_74); - fullAdd_x FA_5920_4192(int_15_74, int_14_74, pp_24_74, pp_25_74, pp_26_74); - r4bs r4bs_5920_4408(yy[19], yy[20], single[27], double[27], neg[27], pp_27_74); - r4bs r4bs_5920_4536(yy[17], yy[18], single[28], double[28], neg[28], pp_28_74); - r4bs r4bs_5920_4664(yy[15], yy[16], single[29], double[29], neg[29], pp_29_74); - fullAdd_x FA_5920_4792(int_17_74, int_16_74, pp_27_74, pp_28_74, pp_29_74); - r4bs r4bs_5920_5008(yy[13], yy[14], single[30], double[30], neg[30], pp_30_74); - r4bs r4bs_5920_5136(yy[11], yy[12], single[31], double[31], neg[31], pp_31_74); - r4bs r4bs_5920_5264(yy[9], yy[10], single[32], double[32], neg[32], pp_32_74); - fullAdd_x FA_5920_5392(int_19_74, int_18_74, pp_30_74, pp_31_74, pp_32_74); - fullAdd_x FA_5920_5608(int_21_74, int_20_74, int_1_73, int_3_73, int_5_73); - fullAdd_x FA_5920_5824(int_23_74, int_22_74, int_7_73, int_9_73, int_11_73); - fullAdd_x FA_5920_6040(int_25_74, int_24_74, int_13_73, int_15_73, int_17_73); - fullAdd_x FA_5920_6256(int_27_74, int_26_74, int_0_74, int_19_73, int_21_73); - fullAdd_x FA_5920_6472(int_29_74, int_28_74, int_23_73, int_25_73, int_2_74); - fullAdd_x FA_5920_6688(int_31_74, int_30_74, int_4_74, int_6_74, int_8_74); - fullAdd_x FA_5920_6904(int_33_74, int_32_74, int_10_74, int_12_74, int_14_74); - fullAdd_x FA_5920_7120(int_35_74, int_34_74, int_16_74, int_18_74, int_27_73); - fullAdd_x FA_5920_7336(int_37_74, int_36_74, int_29_73, int_31_73, int_33_73); - fullAdd_x FA_5920_7552(int_39_74, int_38_74, int_20_74, int_22_74, int_24_74); - fullAdd_x FA_5920_7768(int_41_74, int_40_74, int_26_74, int_35_73, int_37_73); - fullAdd_x FA_5920_7984(int_43_74, int_42_74, int_39_73, int_28_74, int_30_74); - fullAdd_x FA_5920_8200(int_45_74, int_44_74, int_32_74, int_34_74, int_41_73); - fullAdd_x FA_5920_8416(int_47_74, int_46_74, int_43_73, int_36_74, int_38_74); - fullAdd_x FA_5920_8632(int_49_74, int_48_74, int_45_73, int_47_73, int_40_74); - fullAdd_x FA_5920_8848(int_51_74, int_50_74, int_42_74, int_44_74, int_49_73); - fullAdd_x FA_5920_9064(int_53_74, int_52_74, int_46_74, int_51_73, int_48_74); - fullAdd_x FA_5920_9280(int_55_74, int_54_74, int_50_74, int_53_73, int_52_74); - assign Sum[74] = int_55_73; - assign Carry[74] = int_54_74; - - // Hardware for column 75 - - r4bs r4bs_6000_0(yy[62], yy[63], single[6], double[6], neg[6], pp_6_75); - r4bs r4bs_6000_128(yy[60], yy[61], single[7], double[7], neg[7], pp_7_75); - fullAdd_x FA_6000_256(int_1_75, int_0_75, negbar[5], pp_6_75, pp_7_75); - r4bs r4bs_6000_472(yy[58], yy[59], single[8], double[8], neg[8], pp_8_75); - r4bs r4bs_6000_600(yy[56], yy[57], single[9], double[9], neg[9], pp_9_75); - r4bs r4bs_6000_728(yy[54], yy[55], single[10], double[10], neg[10], pp_10_75); - fullAdd_x FA_6000_856(int_3_75, int_2_75, pp_8_75, pp_9_75, pp_10_75); - r4bs r4bs_6000_1072(yy[52], yy[53], single[11], double[11], neg[11], pp_11_75); - r4bs r4bs_6000_1200(yy[50], yy[51], single[12], double[12], neg[12], pp_12_75); - r4bs r4bs_6000_1328(yy[48], yy[49], single[13], double[13], neg[13], pp_13_75); - fullAdd_x FA_6000_1456(int_5_75, int_4_75, pp_11_75, pp_12_75, pp_13_75); - r4bs r4bs_6000_1672(yy[46], yy[47], single[14], double[14], neg[14], pp_14_75); - r4bs r4bs_6000_1800(yy[44], yy[45], single[15], double[15], neg[15], pp_15_75); - r4bs r4bs_6000_1928(yy[42], yy[43], single[16], double[16], neg[16], pp_16_75); - fullAdd_x FA_6000_2056(int_7_75, int_6_75, pp_14_75, pp_15_75, pp_16_75); - r4bs r4bs_6000_2272(yy[40], yy[41], single[17], double[17], neg[17], pp_17_75); - r4bs r4bs_6000_2400(yy[38], yy[39], single[18], double[18], neg[18], pp_18_75); - r4bs r4bs_6000_2528(yy[36], yy[37], single[19], double[19], neg[19], pp_19_75); - fullAdd_x FA_6000_2656(int_9_75, int_8_75, pp_17_75, pp_18_75, pp_19_75); - r4bs r4bs_6000_2872(yy[34], yy[35], single[20], double[20], neg[20], pp_20_75); - r4bs r4bs_6000_3000(yy[32], yy[33], single[21], double[21], neg[21], pp_21_75); - r4bs r4bs_6000_3128(yy[30], yy[31], single[22], double[22], neg[22], pp_22_75); - fullAdd_x FA_6000_3256(int_11_75, int_10_75, pp_20_75, pp_21_75, pp_22_75); - r4bs r4bs_6000_3472(yy[28], yy[29], single[23], double[23], neg[23], pp_23_75); - r4bs r4bs_6000_3600(yy[26], yy[27], single[24], double[24], neg[24], pp_24_75); - r4bs r4bs_6000_3728(yy[24], yy[25], single[25], double[25], neg[25], pp_25_75); - fullAdd_x FA_6000_3856(int_13_75, int_12_75, pp_23_75, pp_24_75, pp_25_75); - r4bs r4bs_6000_4072(yy[22], yy[23], single[26], double[26], neg[26], pp_26_75); - r4bs r4bs_6000_4200(yy[20], yy[21], single[27], double[27], neg[27], pp_27_75); - r4bs r4bs_6000_4328(yy[18], yy[19], single[28], double[28], neg[28], pp_28_75); - fullAdd_x FA_6000_4456(int_15_75, int_14_75, pp_26_75, pp_27_75, pp_28_75); - r4bs r4bs_6000_4672(yy[16], yy[17], single[29], double[29], neg[29], pp_29_75); - r4bs r4bs_6000_4800(yy[14], yy[15], single[30], double[30], neg[30], pp_30_75); - r4bs r4bs_6000_4928(yy[12], yy[13], single[31], double[31], neg[31], pp_31_75); - fullAdd_x FA_6000_5056(int_17_75, int_16_75, pp_29_75, pp_30_75, pp_31_75); - r4bs r4bs_6000_5272(yy[10], yy[11], single[32], double[32], neg[32], pp_32_75); - fullAdd_x FA_6000_5400(int_19_75, int_18_75, pp_32_75, int_1_74, int_3_74); - fullAdd_x FA_6000_5616(int_21_75, int_20_75, int_5_74, int_7_74, int_9_74); - fullAdd_x FA_6000_5832(int_23_75, int_22_75, int_11_74, int_13_74, int_15_74); - fullAdd_x FA_6000_6048(int_25_75, int_24_75, int_17_74, int_19_74, int_21_74); - fullAdd_x FA_6000_6264(int_27_75, int_26_75, int_23_74, int_25_74, int_0_75); - fullAdd_x FA_6000_6480(int_29_75, int_28_75, int_2_75, int_4_75, int_6_75); - fullAdd_x FA_6000_6696(int_31_75, int_30_75, int_8_75, int_10_75, int_12_75); - fullAdd_x FA_6000_6912(int_33_75, int_32_75, int_14_75, int_16_75, int_18_75); - fullAdd_x FA_6000_7128(int_35_75, int_34_75, int_27_74, int_29_74, int_31_74); - fullAdd_x FA_6000_7344(int_37_75, int_36_75, int_33_74, int_20_75, int_22_75); - fullAdd_x FA_6000_7560(int_39_75, int_38_75, int_24_75, int_35_74, int_37_74); - fullAdd_x FA_6000_7776(int_41_75, int_40_75, int_39_74, int_26_75, int_28_75); - fullAdd_x FA_6000_7992(int_43_75, int_42_75, int_30_75, int_32_75, int_41_74); - fullAdd_x FA_6000_8208(int_45_75, int_44_75, int_43_74, int_34_75, int_36_75); - fullAdd_x FA_6000_8424(int_47_75, int_46_75, int_45_74, int_47_74, int_38_75); - fullAdd_x FA_6000_8640(int_49_75, int_48_75, int_40_75, int_42_75, int_49_74); - fullAdd_x FA_6000_8856(int_51_75, int_50_75, int_44_75, int_51_74, int_46_75); - fullAdd_x FA_6000_9072(int_53_75, int_52_75, int_48_75, int_53_74, int_50_75); - assign Sum[75] = int_55_74; - assign Carry[75] = int_52_75; - - // Hardware for column 76 - - r4bs r4bs_6080_0(yy[63], gnd, single[6], double[6], neg[6], pp_6_76); - halfAdd HA_6080_128(int_1_76, int_0_76, 1'b1, pp_6_76); - r4bs r4bs_6080_208(yy[61], yy[62], single[7], double[7], neg[7], pp_7_76); - r4bs r4bs_6080_336(yy[59], yy[60], single[8], double[8], neg[8], pp_8_76); - r4bs r4bs_6080_464(yy[57], yy[58], single[9], double[9], neg[9], pp_9_76); - fullAdd_x FA_6080_592(int_3_76, int_2_76, pp_7_76, pp_8_76, pp_9_76); - r4bs r4bs_6080_808(yy[55], yy[56], single[10], double[10], neg[10], pp_10_76); - r4bs r4bs_6080_936(yy[53], yy[54], single[11], double[11], neg[11], pp_11_76); - r4bs r4bs_6080_1064(yy[51], yy[52], single[12], double[12], neg[12], pp_12_76); - fullAdd_x FA_6080_1192(int_5_76, int_4_76, pp_10_76, pp_11_76, pp_12_76); - r4bs r4bs_6080_1408(yy[49], yy[50], single[13], double[13], neg[13], pp_13_76); - r4bs r4bs_6080_1536(yy[47], yy[48], single[14], double[14], neg[14], pp_14_76); - r4bs r4bs_6080_1664(yy[45], yy[46], single[15], double[15], neg[15], pp_15_76); - fullAdd_x FA_6080_1792(int_7_76, int_6_76, pp_13_76, pp_14_76, pp_15_76); - r4bs r4bs_6080_2008(yy[43], yy[44], single[16], double[16], neg[16], pp_16_76); - r4bs r4bs_6080_2136(yy[41], yy[42], single[17], double[17], neg[17], pp_17_76); - r4bs r4bs_6080_2264(yy[39], yy[40], single[18], double[18], neg[18], pp_18_76); - fullAdd_x FA_6080_2392(int_9_76, int_8_76, pp_16_76, pp_17_76, pp_18_76); - r4bs r4bs_6080_2608(yy[37], yy[38], single[19], double[19], neg[19], pp_19_76); - r4bs r4bs_6080_2736(yy[35], yy[36], single[20], double[20], neg[20], pp_20_76); - r4bs r4bs_6080_2864(yy[33], yy[34], single[21], double[21], neg[21], pp_21_76); - fullAdd_x FA_6080_2992(int_11_76, int_10_76, pp_19_76, pp_20_76, pp_21_76); - r4bs r4bs_6080_3208(yy[31], yy[32], single[22], double[22], neg[22], pp_22_76); - r4bs r4bs_6080_3336(yy[29], yy[30], single[23], double[23], neg[23], pp_23_76); - r4bs r4bs_6080_3464(yy[27], yy[28], single[24], double[24], neg[24], pp_24_76); - fullAdd_x FA_6080_3592(int_13_76, int_12_76, pp_22_76, pp_23_76, pp_24_76); - r4bs r4bs_6080_3808(yy[25], yy[26], single[25], double[25], neg[25], pp_25_76); - r4bs r4bs_6080_3936(yy[23], yy[24], single[26], double[26], neg[26], pp_26_76); - r4bs r4bs_6080_4064(yy[21], yy[22], single[27], double[27], neg[27], pp_27_76); - fullAdd_x FA_6080_4192(int_15_76, int_14_76, pp_25_76, pp_26_76, pp_27_76); - r4bs r4bs_6080_4408(yy[19], yy[20], single[28], double[28], neg[28], pp_28_76); - r4bs r4bs_6080_4536(yy[17], yy[18], single[29], double[29], neg[29], pp_29_76); - r4bs r4bs_6080_4664(yy[15], yy[16], single[30], double[30], neg[30], pp_30_76); - fullAdd_x FA_6080_4792(int_17_76, int_16_76, pp_28_76, pp_29_76, pp_30_76); - r4bs r4bs_6080_5008(yy[13], yy[14], single[31], double[31], neg[31], pp_31_76); - r4bs r4bs_6080_5136(yy[11], yy[12], single[32], double[32], neg[32], pp_32_76); - fullAdd_x FA_6080_5264(int_19_76, int_18_76, pp_31_76, pp_32_76, int_1_75); - fullAdd_x FA_6080_5480(int_21_76, int_20_76, int_3_75, int_5_75, int_7_75); - fullAdd_x FA_6080_5696(int_23_76, int_22_76, int_9_75, int_11_75, int_13_75); - fullAdd_x FA_6080_5912(int_25_76, int_24_76, int_15_75, int_17_75, int_0_76); - fullAdd_x FA_6080_6128(int_27_76, int_26_76, int_19_75, int_21_75, int_23_75); - fullAdd_x FA_6080_6344(int_29_76, int_28_76, int_2_76, int_4_76, int_6_76); - fullAdd_x FA_6080_6560(int_31_76, int_30_76, int_8_76, int_10_76, int_12_76); - fullAdd_x FA_6080_6776(int_33_76, int_32_76, int_14_76, int_16_76, int_18_76); - fullAdd_x FA_6080_6992(int_35_76, int_34_76, int_25_75, int_27_75, int_29_75); - fullAdd_x FA_6080_7208(int_37_76, int_36_76, int_31_75, int_20_76, int_22_76); - fullAdd_x FA_6080_7424(int_39_76, int_38_76, int_24_76, int_33_75, int_35_75); - fullAdd_x FA_6080_7640(int_41_76, int_40_76, int_37_75, int_26_76, int_28_76); - fullAdd_x FA_6080_7856(int_43_76, int_42_76, int_30_76, int_32_76, int_39_75); - fullAdd_x FA_6080_8072(int_45_76, int_44_76, int_41_75, int_34_76, int_36_76); - fullAdd_x FA_6080_8288(int_47_76, int_46_76, int_38_76, int_43_75, int_45_75); - fullAdd_x FA_6080_8504(int_49_76, int_48_76, int_40_76, int_42_76, int_47_75); - fullAdd_x FA_6080_8720(int_51_76, int_50_76, int_44_76, int_49_75, int_46_76); - fullAdd_x FA_6080_8936(int_53_76, int_52_76, int_48_76, int_51_75, int_50_76); - assign Sum[76] = int_53_75; - assign Carry[76] = int_52_76; - - // Hardware for column 77 - - r4bs r4bs_6160_0(yy[62], yy[63], single[7], double[7], neg[7], pp_7_77); - r4bs r4bs_6160_128(yy[60], yy[61], single[8], double[8], neg[8], pp_8_77); - fullAdd_x FA_6160_256(int_1_77, int_0_77, negbar[6], pp_7_77, pp_8_77); - r4bs r4bs_6160_472(yy[58], yy[59], single[9], double[9], neg[9], pp_9_77); - r4bs r4bs_6160_600(yy[56], yy[57], single[10], double[10], neg[10], pp_10_77); - r4bs r4bs_6160_728(yy[54], yy[55], single[11], double[11], neg[11], pp_11_77); - fullAdd_x FA_6160_856(int_3_77, int_2_77, pp_9_77, pp_10_77, pp_11_77); - r4bs r4bs_6160_1072(yy[52], yy[53], single[12], double[12], neg[12], pp_12_77); - r4bs r4bs_6160_1200(yy[50], yy[51], single[13], double[13], neg[13], pp_13_77); - r4bs r4bs_6160_1328(yy[48], yy[49], single[14], double[14], neg[14], pp_14_77); - fullAdd_x FA_6160_1456(int_5_77, int_4_77, pp_12_77, pp_13_77, pp_14_77); - r4bs r4bs_6160_1672(yy[46], yy[47], single[15], double[15], neg[15], pp_15_77); - r4bs r4bs_6160_1800(yy[44], yy[45], single[16], double[16], neg[16], pp_16_77); - r4bs r4bs_6160_1928(yy[42], yy[43], single[17], double[17], neg[17], pp_17_77); - fullAdd_x FA_6160_2056(int_7_77, int_6_77, pp_15_77, pp_16_77, pp_17_77); - r4bs r4bs_6160_2272(yy[40], yy[41], single[18], double[18], neg[18], pp_18_77); - r4bs r4bs_6160_2400(yy[38], yy[39], single[19], double[19], neg[19], pp_19_77); - r4bs r4bs_6160_2528(yy[36], yy[37], single[20], double[20], neg[20], pp_20_77); - fullAdd_x FA_6160_2656(int_9_77, int_8_77, pp_18_77, pp_19_77, pp_20_77); - r4bs r4bs_6160_2872(yy[34], yy[35], single[21], double[21], neg[21], pp_21_77); - r4bs r4bs_6160_3000(yy[32], yy[33], single[22], double[22], neg[22], pp_22_77); - r4bs r4bs_6160_3128(yy[30], yy[31], single[23], double[23], neg[23], pp_23_77); - fullAdd_x FA_6160_3256(int_11_77, int_10_77, pp_21_77, pp_22_77, pp_23_77); - r4bs r4bs_6160_3472(yy[28], yy[29], single[24], double[24], neg[24], pp_24_77); - r4bs r4bs_6160_3600(yy[26], yy[27], single[25], double[25], neg[25], pp_25_77); - r4bs r4bs_6160_3728(yy[24], yy[25], single[26], double[26], neg[26], pp_26_77); - fullAdd_x FA_6160_3856(int_13_77, int_12_77, pp_24_77, pp_25_77, pp_26_77); - r4bs r4bs_6160_4072(yy[22], yy[23], single[27], double[27], neg[27], pp_27_77); - r4bs r4bs_6160_4200(yy[20], yy[21], single[28], double[28], neg[28], pp_28_77); - r4bs r4bs_6160_4328(yy[18], yy[19], single[29], double[29], neg[29], pp_29_77); - fullAdd_x FA_6160_4456(int_15_77, int_14_77, pp_27_77, pp_28_77, pp_29_77); - r4bs r4bs_6160_4672(yy[16], yy[17], single[30], double[30], neg[30], pp_30_77); - r4bs r4bs_6160_4800(yy[14], yy[15], single[31], double[31], neg[31], pp_31_77); - r4bs r4bs_6160_4928(yy[12], yy[13], single[32], double[32], neg[32], pp_32_77); - fullAdd_x FA_6160_5056(int_17_77, int_16_77, pp_30_77, pp_31_77, pp_32_77); - fullAdd_x FA_6160_5272(int_19_77, int_18_77, int_1_76, int_3_76, int_5_76); - fullAdd_x FA_6160_5488(int_21_77, int_20_77, int_7_76, int_9_76, int_11_76); - fullAdd_x FA_6160_5704(int_23_77, int_22_77, int_13_76, int_15_76, int_17_76); - fullAdd_x FA_6160_5920(int_25_77, int_24_77, int_19_76, int_21_76, int_23_76); - fullAdd_x FA_6160_6136(int_27_77, int_26_77, int_25_76, int_0_77, int_2_77); - fullAdd_x FA_6160_6352(int_29_77, int_28_77, int_4_77, int_6_77, int_8_77); - fullAdd_x FA_6160_6568(int_31_77, int_30_77, int_10_77, int_12_77, int_14_77); - fullAdd_x FA_6160_6784(int_33_77, int_32_77, int_16_77, int_27_76, int_29_76); - fullAdd_x FA_6160_7000(int_35_77, int_34_77, int_31_76, int_33_76, int_18_77); - fullAdd_x FA_6160_7216(int_37_77, int_36_77, int_20_77, int_22_77, int_35_76); - fullAdd_x FA_6160_7432(int_39_77, int_38_77, int_37_76, int_24_77, int_26_77); - fullAdd_x FA_6160_7648(int_41_77, int_40_77, int_28_77, int_30_77, int_39_76); - fullAdd_x FA_6160_7864(int_43_77, int_42_77, int_41_76, int_32_77, int_34_77); - fullAdd_x FA_6160_8080(int_45_77, int_44_77, int_36_77, int_43_76, int_45_76); - fullAdd_x FA_6160_8296(int_47_77, int_46_77, int_38_77, int_40_77, int_47_76); - fullAdd_x FA_6160_8512(int_49_77, int_48_77, int_42_77, int_49_76, int_44_77); - fullAdd_x FA_6160_8728(int_51_77, int_50_77, int_46_77, int_51_76, int_48_77); - assign Sum[77] = int_53_76; - assign Carry[77] = int_50_77; - - // Hardware for column 78 - - r4bs r4bs_6240_0(yy[63], gnd, single[7], double[7], neg[7], pp_7_78); - halfAdd HA_6240_128(int_1_78, int_0_78, 1'b1, pp_7_78); - r4bs r4bs_6240_208(yy[61], yy[62], single[8], double[8], neg[8], pp_8_78); - r4bs r4bs_6240_336(yy[59], yy[60], single[9], double[9], neg[9], pp_9_78); - r4bs r4bs_6240_464(yy[57], yy[58], single[10], double[10], neg[10], pp_10_78); - fullAdd_x FA_6240_592(int_3_78, int_2_78, pp_8_78, pp_9_78, pp_10_78); - r4bs r4bs_6240_808(yy[55], yy[56], single[11], double[11], neg[11], pp_11_78); - r4bs r4bs_6240_936(yy[53], yy[54], single[12], double[12], neg[12], pp_12_78); - r4bs r4bs_6240_1064(yy[51], yy[52], single[13], double[13], neg[13], pp_13_78); - fullAdd_x FA_6240_1192(int_5_78, int_4_78, pp_11_78, pp_12_78, pp_13_78); - r4bs r4bs_6240_1408(yy[49], yy[50], single[14], double[14], neg[14], pp_14_78); - r4bs r4bs_6240_1536(yy[47], yy[48], single[15], double[15], neg[15], pp_15_78); - r4bs r4bs_6240_1664(yy[45], yy[46], single[16], double[16], neg[16], pp_16_78); - fullAdd_x FA_6240_1792(int_7_78, int_6_78, pp_14_78, pp_15_78, pp_16_78); - r4bs r4bs_6240_2008(yy[43], yy[44], single[17], double[17], neg[17], pp_17_78); - r4bs r4bs_6240_2136(yy[41], yy[42], single[18], double[18], neg[18], pp_18_78); - r4bs r4bs_6240_2264(yy[39], yy[40], single[19], double[19], neg[19], pp_19_78); - fullAdd_x FA_6240_2392(int_9_78, int_8_78, pp_17_78, pp_18_78, pp_19_78); - r4bs r4bs_6240_2608(yy[37], yy[38], single[20], double[20], neg[20], pp_20_78); - r4bs r4bs_6240_2736(yy[35], yy[36], single[21], double[21], neg[21], pp_21_78); - r4bs r4bs_6240_2864(yy[33], yy[34], single[22], double[22], neg[22], pp_22_78); - fullAdd_x FA_6240_2992(int_11_78, int_10_78, pp_20_78, pp_21_78, pp_22_78); - r4bs r4bs_6240_3208(yy[31], yy[32], single[23], double[23], neg[23], pp_23_78); - r4bs r4bs_6240_3336(yy[29], yy[30], single[24], double[24], neg[24], pp_24_78); - r4bs r4bs_6240_3464(yy[27], yy[28], single[25], double[25], neg[25], pp_25_78); - fullAdd_x FA_6240_3592(int_13_78, int_12_78, pp_23_78, pp_24_78, pp_25_78); - r4bs r4bs_6240_3808(yy[25], yy[26], single[26], double[26], neg[26], pp_26_78); - r4bs r4bs_6240_3936(yy[23], yy[24], single[27], double[27], neg[27], pp_27_78); - r4bs r4bs_6240_4064(yy[21], yy[22], single[28], double[28], neg[28], pp_28_78); - fullAdd_x FA_6240_4192(int_15_78, int_14_78, pp_26_78, pp_27_78, pp_28_78); - r4bs r4bs_6240_4408(yy[19], yy[20], single[29], double[29], neg[29], pp_29_78); - r4bs r4bs_6240_4536(yy[17], yy[18], single[30], double[30], neg[30], pp_30_78); - r4bs r4bs_6240_4664(yy[15], yy[16], single[31], double[31], neg[31], pp_31_78); - fullAdd_x FA_6240_4792(int_17_78, int_16_78, pp_29_78, pp_30_78, pp_31_78); - r4bs r4bs_6240_5008(yy[13], yy[14], single[32], double[32], neg[32], pp_32_78); - fullAdd_x FA_6240_5136(int_19_78, int_18_78, pp_32_78, int_1_77, int_3_77); - fullAdd_x FA_6240_5352(int_21_78, int_20_78, int_5_77, int_7_77, int_9_77); - fullAdd_x FA_6240_5568(int_23_78, int_22_78, int_11_77, int_13_77, int_15_77); - fullAdd_x FA_6240_5784(int_25_78, int_24_78, int_17_77, int_0_78, int_19_77); - fullAdd_x FA_6240_6000(int_27_78, int_26_78, int_21_77, int_23_77, int_2_78); - fullAdd_x FA_6240_6216(int_29_78, int_28_78, int_4_78, int_6_78, int_8_78); - fullAdd_x FA_6240_6432(int_31_78, int_30_78, int_10_78, int_12_78, int_14_78); - fullAdd_x FA_6240_6648(int_33_78, int_32_78, int_16_78, int_25_77, int_27_77); - fullAdd_x FA_6240_6864(int_35_78, int_34_78, int_29_77, int_31_77, int_18_78); - fullAdd_x FA_6240_7080(int_37_78, int_36_78, int_20_78, int_22_78, int_24_78); - fullAdd_x FA_6240_7296(int_39_78, int_38_78, int_33_77, int_35_77, int_26_78); - fullAdd_x FA_6240_7512(int_41_78, int_40_78, int_28_78, int_30_78, int_37_77); - fullAdd_x FA_6240_7728(int_43_78, int_42_78, int_39_77, int_32_78, int_34_78); - fullAdd_x FA_6240_7944(int_45_78, int_44_78, int_36_78, int_41_77, int_43_77); - fullAdd_x FA_6240_8160(int_47_78, int_46_78, int_38_78, int_40_78, int_45_77); - fullAdd_x FA_6240_8376(int_49_78, int_48_78, int_42_78, int_47_77, int_44_78); - fullAdd_x FA_6240_8592(int_51_78, int_50_78, int_46_78, int_49_77, int_48_78); - assign Sum[78] = int_51_77; - assign Carry[78] = int_50_78; - - // Hardware for column 79 - - r4bs r4bs_6320_0(yy[62], yy[63], single[8], double[8], neg[8], pp_8_79); - r4bs r4bs_6320_128(yy[60], yy[61], single[9], double[9], neg[9], pp_9_79); - fullAdd_x FA_6320_256(int_1_79, int_0_79, negbar[7], pp_8_79, pp_9_79); - r4bs r4bs_6320_472(yy[58], yy[59], single[10], double[10], neg[10], pp_10_79); - r4bs r4bs_6320_600(yy[56], yy[57], single[11], double[11], neg[11], pp_11_79); - r4bs r4bs_6320_728(yy[54], yy[55], single[12], double[12], neg[12], pp_12_79); - fullAdd_x FA_6320_856(int_3_79, int_2_79, pp_10_79, pp_11_79, pp_12_79); - r4bs r4bs_6320_1072(yy[52], yy[53], single[13], double[13], neg[13], pp_13_79); - r4bs r4bs_6320_1200(yy[50], yy[51], single[14], double[14], neg[14], pp_14_79); - r4bs r4bs_6320_1328(yy[48], yy[49], single[15], double[15], neg[15], pp_15_79); - fullAdd_x FA_6320_1456(int_5_79, int_4_79, pp_13_79, pp_14_79, pp_15_79); - r4bs r4bs_6320_1672(yy[46], yy[47], single[16], double[16], neg[16], pp_16_79); - r4bs r4bs_6320_1800(yy[44], yy[45], single[17], double[17], neg[17], pp_17_79); - r4bs r4bs_6320_1928(yy[42], yy[43], single[18], double[18], neg[18], pp_18_79); - fullAdd_x FA_6320_2056(int_7_79, int_6_79, pp_16_79, pp_17_79, pp_18_79); - r4bs r4bs_6320_2272(yy[40], yy[41], single[19], double[19], neg[19], pp_19_79); - r4bs r4bs_6320_2400(yy[38], yy[39], single[20], double[20], neg[20], pp_20_79); - r4bs r4bs_6320_2528(yy[36], yy[37], single[21], double[21], neg[21], pp_21_79); - fullAdd_x FA_6320_2656(int_9_79, int_8_79, pp_19_79, pp_20_79, pp_21_79); - r4bs r4bs_6320_2872(yy[34], yy[35], single[22], double[22], neg[22], pp_22_79); - r4bs r4bs_6320_3000(yy[32], yy[33], single[23], double[23], neg[23], pp_23_79); - r4bs r4bs_6320_3128(yy[30], yy[31], single[24], double[24], neg[24], pp_24_79); - fullAdd_x FA_6320_3256(int_11_79, int_10_79, pp_22_79, pp_23_79, pp_24_79); - r4bs r4bs_6320_3472(yy[28], yy[29], single[25], double[25], neg[25], pp_25_79); - r4bs r4bs_6320_3600(yy[26], yy[27], single[26], double[26], neg[26], pp_26_79); - r4bs r4bs_6320_3728(yy[24], yy[25], single[27], double[27], neg[27], pp_27_79); - fullAdd_x FA_6320_3856(int_13_79, int_12_79, pp_25_79, pp_26_79, pp_27_79); - r4bs r4bs_6320_4072(yy[22], yy[23], single[28], double[28], neg[28], pp_28_79); - r4bs r4bs_6320_4200(yy[20], yy[21], single[29], double[29], neg[29], pp_29_79); - r4bs r4bs_6320_4328(yy[18], yy[19], single[30], double[30], neg[30], pp_30_79); - fullAdd_x FA_6320_4456(int_15_79, int_14_79, pp_28_79, pp_29_79, pp_30_79); - r4bs r4bs_6320_4672(yy[16], yy[17], single[31], double[31], neg[31], pp_31_79); - r4bs r4bs_6320_4800(yy[14], yy[15], single[32], double[32], neg[32], pp_32_79); - fullAdd_x FA_6320_4928(int_17_79, int_16_79, pp_31_79, pp_32_79, int_1_78); - fullAdd_x FA_6320_5144(int_19_79, int_18_79, int_3_78, int_5_78, int_7_78); - fullAdd_x FA_6320_5360(int_21_79, int_20_79, int_9_78, int_11_78, int_13_78); - fullAdd_x FA_6320_5576(int_23_79, int_22_79, int_15_78, int_17_78, int_19_78); - fullAdd_x FA_6320_5792(int_25_79, int_24_79, int_21_78, int_23_78, int_0_79); - fullAdd_x FA_6320_6008(int_27_79, int_26_79, int_2_79, int_4_79, int_6_79); - fullAdd_x FA_6320_6224(int_29_79, int_28_79, int_8_79, int_10_79, int_12_79); - fullAdd_x FA_6320_6440(int_31_79, int_30_79, int_14_79, int_16_79, int_25_78); - fullAdd_x FA_6320_6656(int_33_79, int_32_79, int_27_78, int_29_78, int_31_78); - fullAdd_x FA_6320_6872(int_35_79, int_34_79, int_18_79, int_20_79, int_22_79); - fullAdd_x FA_6320_7088(int_37_79, int_36_79, int_33_78, int_35_78, int_37_78); - fullAdd_x FA_6320_7304(int_39_79, int_38_79, int_24_79, int_26_79, int_28_79); - fullAdd_x FA_6320_7520(int_41_79, int_40_79, int_30_79, int_39_78, int_32_79); - fullAdd_x FA_6320_7736(int_43_79, int_42_79, int_34_79, int_41_78, int_43_78); - fullAdd_x FA_6320_7952(int_45_79, int_44_79, int_36_79, int_38_79, int_45_78); - fullAdd_x FA_6320_8168(int_47_79, int_46_79, int_40_79, int_47_78, int_42_79); - fullAdd_x FA_6320_8384(int_49_79, int_48_79, int_44_79, int_49_78, int_46_79); - assign Sum[79] = int_51_78; - assign Carry[79] = int_48_79; - - // Hardware for column 80 - - r4bs r4bs_6400_0(yy[63], gnd, single[8], double[8], neg[8], pp_8_80); - halfAdd HA_6400_128(int_1_80, int_0_80, 1'b1, pp_8_80); - r4bs r4bs_6400_208(yy[61], yy[62], single[9], double[9], neg[9], pp_9_80); - r4bs r4bs_6400_336(yy[59], yy[60], single[10], double[10], neg[10], pp_10_80); - r4bs r4bs_6400_464(yy[57], yy[58], single[11], double[11], neg[11], pp_11_80); - fullAdd_x FA_6400_592(int_3_80, int_2_80, pp_9_80, pp_10_80, pp_11_80); - r4bs r4bs_6400_808(yy[55], yy[56], single[12], double[12], neg[12], pp_12_80); - r4bs r4bs_6400_936(yy[53], yy[54], single[13], double[13], neg[13], pp_13_80); - r4bs r4bs_6400_1064(yy[51], yy[52], single[14], double[14], neg[14], pp_14_80); - fullAdd_x FA_6400_1192(int_5_80, int_4_80, pp_12_80, pp_13_80, pp_14_80); - r4bs r4bs_6400_1408(yy[49], yy[50], single[15], double[15], neg[15], pp_15_80); - r4bs r4bs_6400_1536(yy[47], yy[48], single[16], double[16], neg[16], pp_16_80); - r4bs r4bs_6400_1664(yy[45], yy[46], single[17], double[17], neg[17], pp_17_80); - fullAdd_x FA_6400_1792(int_7_80, int_6_80, pp_15_80, pp_16_80, pp_17_80); - r4bs r4bs_6400_2008(yy[43], yy[44], single[18], double[18], neg[18], pp_18_80); - r4bs r4bs_6400_2136(yy[41], yy[42], single[19], double[19], neg[19], pp_19_80); - r4bs r4bs_6400_2264(yy[39], yy[40], single[20], double[20], neg[20], pp_20_80); - fullAdd_x FA_6400_2392(int_9_80, int_8_80, pp_18_80, pp_19_80, pp_20_80); - r4bs r4bs_6400_2608(yy[37], yy[38], single[21], double[21], neg[21], pp_21_80); - r4bs r4bs_6400_2736(yy[35], yy[36], single[22], double[22], neg[22], pp_22_80); - r4bs r4bs_6400_2864(yy[33], yy[34], single[23], double[23], neg[23], pp_23_80); - fullAdd_x FA_6400_2992(int_11_80, int_10_80, pp_21_80, pp_22_80, pp_23_80); - r4bs r4bs_6400_3208(yy[31], yy[32], single[24], double[24], neg[24], pp_24_80); - r4bs r4bs_6400_3336(yy[29], yy[30], single[25], double[25], neg[25], pp_25_80); - r4bs r4bs_6400_3464(yy[27], yy[28], single[26], double[26], neg[26], pp_26_80); - fullAdd_x FA_6400_3592(int_13_80, int_12_80, pp_24_80, pp_25_80, pp_26_80); - r4bs r4bs_6400_3808(yy[25], yy[26], single[27], double[27], neg[27], pp_27_80); - r4bs r4bs_6400_3936(yy[23], yy[24], single[28], double[28], neg[28], pp_28_80); - r4bs r4bs_6400_4064(yy[21], yy[22], single[29], double[29], neg[29], pp_29_80); - fullAdd_x FA_6400_4192(int_15_80, int_14_80, pp_27_80, pp_28_80, pp_29_80); - r4bs r4bs_6400_4408(yy[19], yy[20], single[30], double[30], neg[30], pp_30_80); - r4bs r4bs_6400_4536(yy[17], yy[18], single[31], double[31], neg[31], pp_31_80); - r4bs r4bs_6400_4664(yy[15], yy[16], single[32], double[32], neg[32], pp_32_80); - fullAdd_x FA_6400_4792(int_17_80, int_16_80, pp_30_80, pp_31_80, pp_32_80); - fullAdd_x FA_6400_5008(int_19_80, int_18_80, int_1_79, int_3_79, int_5_79); - fullAdd_x FA_6400_5224(int_21_80, int_20_80, int_7_79, int_9_79, int_11_79); - fullAdd_x FA_6400_5440(int_23_80, int_22_80, int_13_79, int_15_79, int_0_80); - fullAdd_x FA_6400_5656(int_25_80, int_24_80, int_17_79, int_19_79, int_21_79); - fullAdd_x FA_6400_5872(int_27_80, int_26_80, int_2_80, int_4_80, int_6_80); - fullAdd_x FA_6400_6088(int_29_80, int_28_80, int_8_80, int_10_80, int_12_80); - fullAdd_x FA_6400_6304(int_31_80, int_30_80, int_14_80, int_16_80, int_23_79); - fullAdd_x FA_6400_6520(int_33_80, int_32_80, int_25_79, int_27_79, int_29_79); - fullAdd_x FA_6400_6736(int_35_80, int_34_80, int_18_80, int_20_80, int_22_80); - fullAdd_x FA_6400_6952(int_37_80, int_36_80, int_31_79, int_33_79, int_35_79); - fullAdd_x FA_6400_7168(int_39_80, int_38_80, int_24_80, int_26_80, int_28_80); - fullAdd_x FA_6400_7384(int_41_80, int_40_80, int_30_80, int_37_79, int_39_79); - fullAdd_x FA_6400_7600(int_43_80, int_42_80, int_32_80, int_34_80, int_41_79); - fullAdd_x FA_6400_7816(int_45_80, int_44_80, int_36_80, int_38_80, int_43_79); - fullAdd_x FA_6400_8032(int_47_80, int_46_80, int_40_80, int_42_80, int_45_79); - fullAdd_x FA_6400_8248(int_49_80, int_48_80, int_44_80, int_47_79, int_46_80); - assign Sum[80] = int_49_79; - assign Carry[80] = int_48_80; - - // Hardware for column 81 - - r4bs r4bs_6480_0(yy[62], yy[63], single[9], double[9], neg[9], pp_9_81); - r4bs r4bs_6480_128(yy[60], yy[61], single[10], double[10], neg[10], pp_10_81); - fullAdd_x FA_6480_256(int_1_81, int_0_81, negbar[8], pp_9_81, pp_10_81); - r4bs r4bs_6480_472(yy[58], yy[59], single[11], double[11], neg[11], pp_11_81); - r4bs r4bs_6480_600(yy[56], yy[57], single[12], double[12], neg[12], pp_12_81); - r4bs r4bs_6480_728(yy[54], yy[55], single[13], double[13], neg[13], pp_13_81); - fullAdd_x FA_6480_856(int_3_81, int_2_81, pp_11_81, pp_12_81, pp_13_81); - r4bs r4bs_6480_1072(yy[52], yy[53], single[14], double[14], neg[14], pp_14_81); - r4bs r4bs_6480_1200(yy[50], yy[51], single[15], double[15], neg[15], pp_15_81); - r4bs r4bs_6480_1328(yy[48], yy[49], single[16], double[16], neg[16], pp_16_81); - fullAdd_x FA_6480_1456(int_5_81, int_4_81, pp_14_81, pp_15_81, pp_16_81); - r4bs r4bs_6480_1672(yy[46], yy[47], single[17], double[17], neg[17], pp_17_81); - r4bs r4bs_6480_1800(yy[44], yy[45], single[18], double[18], neg[18], pp_18_81); - r4bs r4bs_6480_1928(yy[42], yy[43], single[19], double[19], neg[19], pp_19_81); - fullAdd_x FA_6480_2056(int_7_81, int_6_81, pp_17_81, pp_18_81, pp_19_81); - r4bs r4bs_6480_2272(yy[40], yy[41], single[20], double[20], neg[20], pp_20_81); - r4bs r4bs_6480_2400(yy[38], yy[39], single[21], double[21], neg[21], pp_21_81); - r4bs r4bs_6480_2528(yy[36], yy[37], single[22], double[22], neg[22], pp_22_81); - fullAdd_x FA_6480_2656(int_9_81, int_8_81, pp_20_81, pp_21_81, pp_22_81); - r4bs r4bs_6480_2872(yy[34], yy[35], single[23], double[23], neg[23], pp_23_81); - r4bs r4bs_6480_3000(yy[32], yy[33], single[24], double[24], neg[24], pp_24_81); - r4bs r4bs_6480_3128(yy[30], yy[31], single[25], double[25], neg[25], pp_25_81); - fullAdd_x FA_6480_3256(int_11_81, int_10_81, pp_23_81, pp_24_81, pp_25_81); - r4bs r4bs_6480_3472(yy[28], yy[29], single[26], double[26], neg[26], pp_26_81); - r4bs r4bs_6480_3600(yy[26], yy[27], single[27], double[27], neg[27], pp_27_81); - r4bs r4bs_6480_3728(yy[24], yy[25], single[28], double[28], neg[28], pp_28_81); - fullAdd_x FA_6480_3856(int_13_81, int_12_81, pp_26_81, pp_27_81, pp_28_81); - r4bs r4bs_6480_4072(yy[22], yy[23], single[29], double[29], neg[29], pp_29_81); - r4bs r4bs_6480_4200(yy[20], yy[21], single[30], double[30], neg[30], pp_30_81); - r4bs r4bs_6480_4328(yy[18], yy[19], single[31], double[31], neg[31], pp_31_81); - fullAdd_x FA_6480_4456(int_15_81, int_14_81, pp_29_81, pp_30_81, pp_31_81); - r4bs r4bs_6480_4672(yy[16], yy[17], single[32], double[32], neg[32], pp_32_81); - fullAdd_x FA_6480_4800(int_17_81, int_16_81, pp_32_81, int_1_80, int_3_80); - fullAdd_x FA_6480_5016(int_19_81, int_18_81, int_5_80, int_7_80, int_9_80); - fullAdd_x FA_6480_5232(int_21_81, int_20_81, int_11_80, int_13_80, int_15_80); - fullAdd_x FA_6480_5448(int_23_81, int_22_81, int_17_80, int_19_80, int_21_80); - fullAdd_x FA_6480_5664(int_25_81, int_24_81, int_23_80, int_0_81, int_2_81); - fullAdd_x FA_6480_5880(int_27_81, int_26_81, int_4_81, int_6_81, int_8_81); - fullAdd_x FA_6480_6096(int_29_81, int_28_81, int_10_81, int_12_81, int_14_81); - fullAdd_x FA_6480_6312(int_31_81, int_30_81, int_16_81, int_25_80, int_27_80); - fullAdd_x FA_6480_6528(int_33_81, int_32_81, int_29_80, int_18_81, int_20_81); - fullAdd_x FA_6480_6744(int_35_81, int_34_81, int_31_80, int_33_80, int_35_80); - fullAdd_x FA_6480_6960(int_37_81, int_36_81, int_22_81, int_24_81, int_26_81); - fullAdd_x FA_6480_7176(int_39_81, int_38_81, int_28_81, int_37_80, int_39_80); - fullAdd_x FA_6480_7392(int_41_81, int_40_81, int_30_81, int_32_81, int_41_80); - fullAdd_x FA_6480_7608(int_43_81, int_42_81, int_34_81, int_36_81, int_43_80); - fullAdd_x FA_6480_7824(int_45_81, int_44_81, int_38_81, int_40_81, int_45_80); - fullAdd_x FA_6480_8040(int_47_81, int_46_81, int_42_81, int_47_80, int_44_81); - assign Sum[81] = int_49_80; - assign Carry[81] = int_46_81; - - // Hardware for column 82 - - r4bs r4bs_6560_0(yy[63], gnd, single[9], double[9], neg[9], pp_9_82); - halfAdd HA_6560_128(int_1_82, int_0_82, 1'b1, pp_9_82); - r4bs r4bs_6560_208(yy[61], yy[62], single[10], double[10], neg[10], pp_10_82); - r4bs r4bs_6560_336(yy[59], yy[60], single[11], double[11], neg[11], pp_11_82); - r4bs r4bs_6560_464(yy[57], yy[58], single[12], double[12], neg[12], pp_12_82); - fullAdd_x FA_6560_592(int_3_82, int_2_82, pp_10_82, pp_11_82, pp_12_82); - r4bs r4bs_6560_808(yy[55], yy[56], single[13], double[13], neg[13], pp_13_82); - r4bs r4bs_6560_936(yy[53], yy[54], single[14], double[14], neg[14], pp_14_82); - r4bs r4bs_6560_1064(yy[51], yy[52], single[15], double[15], neg[15], pp_15_82); - fullAdd_x FA_6560_1192(int_5_82, int_4_82, pp_13_82, pp_14_82, pp_15_82); - r4bs r4bs_6560_1408(yy[49], yy[50], single[16], double[16], neg[16], pp_16_82); - r4bs r4bs_6560_1536(yy[47], yy[48], single[17], double[17], neg[17], pp_17_82); - r4bs r4bs_6560_1664(yy[45], yy[46], single[18], double[18], neg[18], pp_18_82); - fullAdd_x FA_6560_1792(int_7_82, int_6_82, pp_16_82, pp_17_82, pp_18_82); - r4bs r4bs_6560_2008(yy[43], yy[44], single[19], double[19], neg[19], pp_19_82); - r4bs r4bs_6560_2136(yy[41], yy[42], single[20], double[20], neg[20], pp_20_82); - r4bs r4bs_6560_2264(yy[39], yy[40], single[21], double[21], neg[21], pp_21_82); - fullAdd_x FA_6560_2392(int_9_82, int_8_82, pp_19_82, pp_20_82, pp_21_82); - r4bs r4bs_6560_2608(yy[37], yy[38], single[22], double[22], neg[22], pp_22_82); - r4bs r4bs_6560_2736(yy[35], yy[36], single[23], double[23], neg[23], pp_23_82); - r4bs r4bs_6560_2864(yy[33], yy[34], single[24], double[24], neg[24], pp_24_82); - fullAdd_x FA_6560_2992(int_11_82, int_10_82, pp_22_82, pp_23_82, pp_24_82); - r4bs r4bs_6560_3208(yy[31], yy[32], single[25], double[25], neg[25], pp_25_82); - r4bs r4bs_6560_3336(yy[29], yy[30], single[26], double[26], neg[26], pp_26_82); - r4bs r4bs_6560_3464(yy[27], yy[28], single[27], double[27], neg[27], pp_27_82); - fullAdd_x FA_6560_3592(int_13_82, int_12_82, pp_25_82, pp_26_82, pp_27_82); - r4bs r4bs_6560_3808(yy[25], yy[26], single[28], double[28], neg[28], pp_28_82); - r4bs r4bs_6560_3936(yy[23], yy[24], single[29], double[29], neg[29], pp_29_82); - r4bs r4bs_6560_4064(yy[21], yy[22], single[30], double[30], neg[30], pp_30_82); - fullAdd_x FA_6560_4192(int_15_82, int_14_82, pp_28_82, pp_29_82, pp_30_82); - r4bs r4bs_6560_4408(yy[19], yy[20], single[31], double[31], neg[31], pp_31_82); - r4bs r4bs_6560_4536(yy[17], yy[18], single[32], double[32], neg[32], pp_32_82); - fullAdd_x FA_6560_4664(int_17_82, int_16_82, pp_31_82, pp_32_82, int_1_81); - fullAdd_x FA_6560_4880(int_19_82, int_18_82, int_3_81, int_5_81, int_7_81); - fullAdd_x FA_6560_5096(int_21_82, int_20_82, int_9_81, int_11_81, int_13_81); - fullAdd_x FA_6560_5312(int_23_82, int_22_82, int_15_81, int_0_82, int_17_81); - fullAdd_x FA_6560_5528(int_25_82, int_24_82, int_19_81, int_21_81, int_2_82); - fullAdd_x FA_6560_5744(int_27_82, int_26_82, int_4_82, int_6_82, int_8_82); - fullAdd_x FA_6560_5960(int_29_82, int_28_82, int_10_82, int_12_82, int_14_82); - fullAdd_x FA_6560_6176(int_31_82, int_30_82, int_16_82, int_23_81, int_25_81); - fullAdd_x FA_6560_6392(int_33_82, int_32_82, int_27_81, int_29_81, int_18_82); - fullAdd_x FA_6560_6608(int_35_82, int_34_82, int_20_82, int_22_82, int_31_81); - fullAdd_x FA_6560_6824(int_37_82, int_36_82, int_33_81, int_24_82, int_26_82); - fullAdd_x FA_6560_7040(int_39_82, int_38_82, int_28_82, int_35_81, int_37_81); - fullAdd_x FA_6560_7256(int_41_82, int_40_82, int_30_82, int_32_82, int_34_82); - fullAdd_x FA_6560_7472(int_43_82, int_42_82, int_39_81, int_36_82, int_41_81); - fullAdd_x FA_6560_7688(int_45_82, int_44_82, int_38_82, int_40_82, int_43_81); - fullAdd_x FA_6560_7904(int_47_82, int_46_82, int_42_82, int_45_81, int_44_82); - assign Sum[82] = int_47_81; - assign Carry[82] = int_46_82; - - // Hardware for column 83 - - r4bs r4bs_6640_0(yy[62], yy[63], single[10], double[10], neg[10], pp_10_83); - r4bs r4bs_6640_128(yy[60], yy[61], single[11], double[11], neg[11], pp_11_83); - fullAdd_x FA_6640_256(int_1_83, int_0_83, negbar[9], pp_10_83, pp_11_83); - r4bs r4bs_6640_472(yy[58], yy[59], single[12], double[12], neg[12], pp_12_83); - r4bs r4bs_6640_600(yy[56], yy[57], single[13], double[13], neg[13], pp_13_83); - r4bs r4bs_6640_728(yy[54], yy[55], single[14], double[14], neg[14], pp_14_83); - fullAdd_x FA_6640_856(int_3_83, int_2_83, pp_12_83, pp_13_83, pp_14_83); - r4bs r4bs_6640_1072(yy[52], yy[53], single[15], double[15], neg[15], pp_15_83); - r4bs r4bs_6640_1200(yy[50], yy[51], single[16], double[16], neg[16], pp_16_83); - r4bs r4bs_6640_1328(yy[48], yy[49], single[17], double[17], neg[17], pp_17_83); - fullAdd_x FA_6640_1456(int_5_83, int_4_83, pp_15_83, pp_16_83, pp_17_83); - r4bs r4bs_6640_1672(yy[46], yy[47], single[18], double[18], neg[18], pp_18_83); - r4bs r4bs_6640_1800(yy[44], yy[45], single[19], double[19], neg[19], pp_19_83); - r4bs r4bs_6640_1928(yy[42], yy[43], single[20], double[20], neg[20], pp_20_83); - fullAdd_x FA_6640_2056(int_7_83, int_6_83, pp_18_83, pp_19_83, pp_20_83); - r4bs r4bs_6640_2272(yy[40], yy[41], single[21], double[21], neg[21], pp_21_83); - r4bs r4bs_6640_2400(yy[38], yy[39], single[22], double[22], neg[22], pp_22_83); - r4bs r4bs_6640_2528(yy[36], yy[37], single[23], double[23], neg[23], pp_23_83); - fullAdd_x FA_6640_2656(int_9_83, int_8_83, pp_21_83, pp_22_83, pp_23_83); - r4bs r4bs_6640_2872(yy[34], yy[35], single[24], double[24], neg[24], pp_24_83); - r4bs r4bs_6640_3000(yy[32], yy[33], single[25], double[25], neg[25], pp_25_83); - r4bs r4bs_6640_3128(yy[30], yy[31], single[26], double[26], neg[26], pp_26_83); - fullAdd_x FA_6640_3256(int_11_83, int_10_83, pp_24_83, pp_25_83, pp_26_83); - r4bs r4bs_6640_3472(yy[28], yy[29], single[27], double[27], neg[27], pp_27_83); - r4bs r4bs_6640_3600(yy[26], yy[27], single[28], double[28], neg[28], pp_28_83); - r4bs r4bs_6640_3728(yy[24], yy[25], single[29], double[29], neg[29], pp_29_83); - fullAdd_x FA_6640_3856(int_13_83, int_12_83, pp_27_83, pp_28_83, pp_29_83); - r4bs r4bs_6640_4072(yy[22], yy[23], single[30], double[30], neg[30], pp_30_83); - r4bs r4bs_6640_4200(yy[20], yy[21], single[31], double[31], neg[31], pp_31_83); - r4bs r4bs_6640_4328(yy[18], yy[19], single[32], double[32], neg[32], pp_32_83); - fullAdd_x FA_6640_4456(int_15_83, int_14_83, pp_30_83, pp_31_83, pp_32_83); - fullAdd_x FA_6640_4672(int_17_83, int_16_83, int_1_82, int_3_82, int_5_82); - fullAdd_x FA_6640_4888(int_19_83, int_18_83, int_7_82, int_9_82, int_11_82); - fullAdd_x FA_6640_5104(int_21_83, int_20_83, int_13_82, int_15_82, int_17_82); - fullAdd_x FA_6640_5320(int_23_83, int_22_83, int_19_82, int_21_82, int_0_83); - fullAdd_x FA_6640_5536(int_25_83, int_24_83, int_2_83, int_4_83, int_6_83); - fullAdd_x FA_6640_5752(int_27_83, int_26_83, int_8_83, int_10_83, int_12_83); - fullAdd_x FA_6640_5968(int_29_83, int_28_83, int_14_83, int_23_82, int_25_82); - fullAdd_x FA_6640_6184(int_31_83, int_30_83, int_27_82, int_29_82, int_16_83); - fullAdd_x FA_6640_6400(int_33_83, int_32_83, int_18_83, int_20_83, int_31_82); - fullAdd_x FA_6640_6616(int_35_83, int_34_83, int_33_82, int_22_83, int_24_83); - fullAdd_x FA_6640_6832(int_37_83, int_36_83, int_26_83, int_35_82, int_37_82); - fullAdd_x FA_6640_7048(int_39_83, int_38_83, int_28_83, int_30_83, int_32_83); - fullAdd_x FA_6640_7264(int_41_83, int_40_83, int_39_82, int_41_82, int_34_83); - fullAdd_x FA_6640_7480(int_43_83, int_42_83, int_36_83, int_38_83, int_43_82); - fullAdd_x FA_6640_7696(int_45_83, int_44_83, int_40_83, int_45_82, int_42_83); - assign Sum[83] = int_47_82; - assign Carry[83] = int_44_83; - - // Hardware for column 84 - - r4bs r4bs_6720_0(yy[63], gnd, single[10], double[10], neg[10], pp_10_84); - halfAdd HA_6720_128(int_1_84, int_0_84, 1'b1, pp_10_84); - r4bs r4bs_6720_208(yy[61], yy[62], single[11], double[11], neg[11], pp_11_84); - r4bs r4bs_6720_336(yy[59], yy[60], single[12], double[12], neg[12], pp_12_84); - r4bs r4bs_6720_464(yy[57], yy[58], single[13], double[13], neg[13], pp_13_84); - fullAdd_x FA_6720_592(int_3_84, int_2_84, pp_11_84, pp_12_84, pp_13_84); - r4bs r4bs_6720_808(yy[55], yy[56], single[14], double[14], neg[14], pp_14_84); - r4bs r4bs_6720_936(yy[53], yy[54], single[15], double[15], neg[15], pp_15_84); - r4bs r4bs_6720_1064(yy[51], yy[52], single[16], double[16], neg[16], pp_16_84); - fullAdd_x FA_6720_1192(int_5_84, int_4_84, pp_14_84, pp_15_84, pp_16_84); - r4bs r4bs_6720_1408(yy[49], yy[50], single[17], double[17], neg[17], pp_17_84); - r4bs r4bs_6720_1536(yy[47], yy[48], single[18], double[18], neg[18], pp_18_84); - r4bs r4bs_6720_1664(yy[45], yy[46], single[19], double[19], neg[19], pp_19_84); - fullAdd_x FA_6720_1792(int_7_84, int_6_84, pp_17_84, pp_18_84, pp_19_84); - r4bs r4bs_6720_2008(yy[43], yy[44], single[20], double[20], neg[20], pp_20_84); - r4bs r4bs_6720_2136(yy[41], yy[42], single[21], double[21], neg[21], pp_21_84); - r4bs r4bs_6720_2264(yy[39], yy[40], single[22], double[22], neg[22], pp_22_84); - fullAdd_x FA_6720_2392(int_9_84, int_8_84, pp_20_84, pp_21_84, pp_22_84); - r4bs r4bs_6720_2608(yy[37], yy[38], single[23], double[23], neg[23], pp_23_84); - r4bs r4bs_6720_2736(yy[35], yy[36], single[24], double[24], neg[24], pp_24_84); - r4bs r4bs_6720_2864(yy[33], yy[34], single[25], double[25], neg[25], pp_25_84); - fullAdd_x FA_6720_2992(int_11_84, int_10_84, pp_23_84, pp_24_84, pp_25_84); - r4bs r4bs_6720_3208(yy[31], yy[32], single[26], double[26], neg[26], pp_26_84); - r4bs r4bs_6720_3336(yy[29], yy[30], single[27], double[27], neg[27], pp_27_84); - r4bs r4bs_6720_3464(yy[27], yy[28], single[28], double[28], neg[28], pp_28_84); - fullAdd_x FA_6720_3592(int_13_84, int_12_84, pp_26_84, pp_27_84, pp_28_84); - r4bs r4bs_6720_3808(yy[25], yy[26], single[29], double[29], neg[29], pp_29_84); - r4bs r4bs_6720_3936(yy[23], yy[24], single[30], double[30], neg[30], pp_30_84); - r4bs r4bs_6720_4064(yy[21], yy[22], single[31], double[31], neg[31], pp_31_84); - fullAdd_x FA_6720_4192(int_15_84, int_14_84, pp_29_84, pp_30_84, pp_31_84); - r4bs r4bs_6720_4408(yy[19], yy[20], single[32], double[32], neg[32], pp_32_84); - fullAdd_x FA_6720_4536(int_17_84, int_16_84, pp_32_84, int_1_83, int_3_83); - fullAdd_x FA_6720_4752(int_19_84, int_18_84, int_5_83, int_7_83, int_9_83); - fullAdd_x FA_6720_4968(int_21_84, int_20_84, int_11_83, int_13_83, int_15_83); - fullAdd_x FA_6720_5184(int_23_84, int_22_84, int_0_84, int_17_83, int_19_83); - fullAdd_x FA_6720_5400(int_25_84, int_24_84, int_2_84, int_4_84, int_6_84); - fullAdd_x FA_6720_5616(int_27_84, int_26_84, int_8_84, int_10_84, int_12_84); - fullAdd_x FA_6720_5832(int_29_84, int_28_84, int_14_84, int_21_83, int_23_83); - fullAdd_x FA_6720_6048(int_31_84, int_30_84, int_25_83, int_27_83, int_16_84); - fullAdd_x FA_6720_6264(int_33_84, int_32_84, int_18_84, int_20_84, int_29_83); - fullAdd_x FA_6720_6480(int_35_84, int_34_84, int_31_83, int_22_84, int_24_84); - fullAdd_x FA_6720_6696(int_37_84, int_36_84, int_26_84, int_33_83, int_35_83); - fullAdd_x FA_6720_6912(int_39_84, int_38_84, int_28_84, int_30_84, int_32_84); - fullAdd_x FA_6720_7128(int_41_84, int_40_84, int_37_83, int_39_83, int_34_84); - fullAdd_x FA_6720_7344(int_43_84, int_42_84, int_41_83, int_36_84, int_38_84); - fullAdd_x FA_6720_7560(int_45_84, int_44_84, int_40_84, int_43_83, int_42_84); - assign Sum[84] = int_45_83; - assign Carry[84] = int_44_84; - - // Hardware for column 85 - - r4bs r4bs_6800_0(yy[62], yy[63], single[11], double[11], neg[11], pp_11_85); - r4bs r4bs_6800_128(yy[60], yy[61], single[12], double[12], neg[12], pp_12_85); - fullAdd_x FA_6800_256(int_1_85, int_0_85, negbar[10], pp_11_85, pp_12_85); - r4bs r4bs_6800_472(yy[58], yy[59], single[13], double[13], neg[13], pp_13_85); - r4bs r4bs_6800_600(yy[56], yy[57], single[14], double[14], neg[14], pp_14_85); - r4bs r4bs_6800_728(yy[54], yy[55], single[15], double[15], neg[15], pp_15_85); - fullAdd_x FA_6800_856(int_3_85, int_2_85, pp_13_85, pp_14_85, pp_15_85); - r4bs r4bs_6800_1072(yy[52], yy[53], single[16], double[16], neg[16], pp_16_85); - r4bs r4bs_6800_1200(yy[50], yy[51], single[17], double[17], neg[17], pp_17_85); - r4bs r4bs_6800_1328(yy[48], yy[49], single[18], double[18], neg[18], pp_18_85); - fullAdd_x FA_6800_1456(int_5_85, int_4_85, pp_16_85, pp_17_85, pp_18_85); - r4bs r4bs_6800_1672(yy[46], yy[47], single[19], double[19], neg[19], pp_19_85); - r4bs r4bs_6800_1800(yy[44], yy[45], single[20], double[20], neg[20], pp_20_85); - r4bs r4bs_6800_1928(yy[42], yy[43], single[21], double[21], neg[21], pp_21_85); - fullAdd_x FA_6800_2056(int_7_85, int_6_85, pp_19_85, pp_20_85, pp_21_85); - r4bs r4bs_6800_2272(yy[40], yy[41], single[22], double[22], neg[22], pp_22_85); - r4bs r4bs_6800_2400(yy[38], yy[39], single[23], double[23], neg[23], pp_23_85); - r4bs r4bs_6800_2528(yy[36], yy[37], single[24], double[24], neg[24], pp_24_85); - fullAdd_x FA_6800_2656(int_9_85, int_8_85, pp_22_85, pp_23_85, pp_24_85); - r4bs r4bs_6800_2872(yy[34], yy[35], single[25], double[25], neg[25], pp_25_85); - r4bs r4bs_6800_3000(yy[32], yy[33], single[26], double[26], neg[26], pp_26_85); - r4bs r4bs_6800_3128(yy[30], yy[31], single[27], double[27], neg[27], pp_27_85); - fullAdd_x FA_6800_3256(int_11_85, int_10_85, pp_25_85, pp_26_85, pp_27_85); - r4bs r4bs_6800_3472(yy[28], yy[29], single[28], double[28], neg[28], pp_28_85); - r4bs r4bs_6800_3600(yy[26], yy[27], single[29], double[29], neg[29], pp_29_85); - r4bs r4bs_6800_3728(yy[24], yy[25], single[30], double[30], neg[30], pp_30_85); - fullAdd_x FA_6800_3856(int_13_85, int_12_85, pp_28_85, pp_29_85, pp_30_85); - r4bs r4bs_6800_4072(yy[22], yy[23], single[31], double[31], neg[31], pp_31_85); - r4bs r4bs_6800_4200(yy[20], yy[21], single[32], double[32], neg[32], pp_32_85); - fullAdd_x FA_6800_4328(int_15_85, int_14_85, pp_31_85, pp_32_85, int_1_84); - fullAdd_x FA_6800_4544(int_17_85, int_16_85, int_3_84, int_5_84, int_7_84); - fullAdd_x FA_6800_4760(int_19_85, int_18_85, int_9_84, int_11_84, int_13_84); - fullAdd_x FA_6800_4976(int_21_85, int_20_85, int_15_84, int_17_84, int_19_84); - fullAdd_x FA_6800_5192(int_23_85, int_22_85, int_21_84, int_0_85, int_2_85); - fullAdd_x FA_6800_5408(int_25_85, int_24_85, int_4_85, int_6_85, int_8_85); - fullAdd_x FA_6800_5624(int_27_85, int_26_85, int_10_85, int_12_85, int_14_85); - fullAdd_x FA_6800_5840(int_29_85, int_28_85, int_23_84, int_25_84, int_27_84); - fullAdd_x FA_6800_6056(int_31_85, int_30_85, int_16_85, int_18_85, int_29_84); - fullAdd_x FA_6800_6272(int_33_85, int_32_85, int_31_84, int_20_85, int_22_85); - fullAdd_x FA_6800_6488(int_35_85, int_34_85, int_24_85, int_26_85, int_33_84); - fullAdd_x FA_6800_6704(int_37_85, int_36_85, int_35_84, int_28_85, int_30_85); - fullAdd_x FA_6800_6920(int_39_85, int_38_85, int_37_84, int_39_84, int_32_85); - fullAdd_x FA_6800_7136(int_41_85, int_40_85, int_34_85, int_41_84, int_36_85); - fullAdd_x FA_6800_7352(int_43_85, int_42_85, int_43_84, int_38_85, int_40_85); - assign Sum[85] = int_45_84; - assign Carry[85] = int_42_85; - - // Hardware for column 86 - - r4bs r4bs_6880_0(yy[63], gnd, single[11], double[11], neg[11], pp_11_86); - halfAdd HA_6880_128(int_1_86, int_0_86, 1'b1, pp_11_86); - r4bs r4bs_6880_208(yy[61], yy[62], single[12], double[12], neg[12], pp_12_86); - r4bs r4bs_6880_336(yy[59], yy[60], single[13], double[13], neg[13], pp_13_86); - r4bs r4bs_6880_464(yy[57], yy[58], single[14], double[14], neg[14], pp_14_86); - fullAdd_x FA_6880_592(int_3_86, int_2_86, pp_12_86, pp_13_86, pp_14_86); - r4bs r4bs_6880_808(yy[55], yy[56], single[15], double[15], neg[15], pp_15_86); - r4bs r4bs_6880_936(yy[53], yy[54], single[16], double[16], neg[16], pp_16_86); - r4bs r4bs_6880_1064(yy[51], yy[52], single[17], double[17], neg[17], pp_17_86); - fullAdd_x FA_6880_1192(int_5_86, int_4_86, pp_15_86, pp_16_86, pp_17_86); - r4bs r4bs_6880_1408(yy[49], yy[50], single[18], double[18], neg[18], pp_18_86); - r4bs r4bs_6880_1536(yy[47], yy[48], single[19], double[19], neg[19], pp_19_86); - r4bs r4bs_6880_1664(yy[45], yy[46], single[20], double[20], neg[20], pp_20_86); - fullAdd_x FA_6880_1792(int_7_86, int_6_86, pp_18_86, pp_19_86, pp_20_86); - r4bs r4bs_6880_2008(yy[43], yy[44], single[21], double[21], neg[21], pp_21_86); - r4bs r4bs_6880_2136(yy[41], yy[42], single[22], double[22], neg[22], pp_22_86); - r4bs r4bs_6880_2264(yy[39], yy[40], single[23], double[23], neg[23], pp_23_86); - fullAdd_x FA_6880_2392(int_9_86, int_8_86, pp_21_86, pp_22_86, pp_23_86); - r4bs r4bs_6880_2608(yy[37], yy[38], single[24], double[24], neg[24], pp_24_86); - r4bs r4bs_6880_2736(yy[35], yy[36], single[25], double[25], neg[25], pp_25_86); - r4bs r4bs_6880_2864(yy[33], yy[34], single[26], double[26], neg[26], pp_26_86); - fullAdd_x FA_6880_2992(int_11_86, int_10_86, pp_24_86, pp_25_86, pp_26_86); - r4bs r4bs_6880_3208(yy[31], yy[32], single[27], double[27], neg[27], pp_27_86); - r4bs r4bs_6880_3336(yy[29], yy[30], single[28], double[28], neg[28], pp_28_86); - r4bs r4bs_6880_3464(yy[27], yy[28], single[29], double[29], neg[29], pp_29_86); - fullAdd_x FA_6880_3592(int_13_86, int_12_86, pp_27_86, pp_28_86, pp_29_86); - r4bs r4bs_6880_3808(yy[25], yy[26], single[30], double[30], neg[30], pp_30_86); - r4bs r4bs_6880_3936(yy[23], yy[24], single[31], double[31], neg[31], pp_31_86); - r4bs r4bs_6880_4064(yy[21], yy[22], single[32], double[32], neg[32], pp_32_86); - fullAdd_x FA_6880_4192(int_15_86, int_14_86, pp_30_86, pp_31_86, pp_32_86); - fullAdd_x FA_6880_4408(int_17_86, int_16_86, int_1_85, int_3_85, int_5_85); - fullAdd_x FA_6880_4624(int_19_86, int_18_86, int_7_85, int_9_85, int_11_85); - fullAdd_x FA_6880_4840(int_21_86, int_20_86, int_13_85, int_0_86, int_15_85); - fullAdd_x FA_6880_5056(int_23_86, int_22_86, int_17_85, int_19_85, int_2_86); - fullAdd_x FA_6880_5272(int_25_86, int_24_86, int_4_86, int_6_86, int_8_86); - fullAdd_x FA_6880_5488(int_27_86, int_26_86, int_10_86, int_12_86, int_14_86); - fullAdd_x FA_6880_5704(int_29_86, int_28_86, int_21_85, int_23_85, int_25_85); - fullAdd_x FA_6880_5920(int_31_86, int_30_86, int_27_85, int_16_86, int_18_86); - fullAdd_x FA_6880_6136(int_33_86, int_32_86, int_20_86, int_29_85, int_22_86); - fullAdd_x FA_6880_6352(int_35_86, int_34_86, int_24_86, int_26_86, int_31_85); - fullAdd_x FA_6880_6568(int_37_86, int_36_86, int_33_85, int_28_86, int_30_86); - fullAdd_x FA_6880_6784(int_39_86, int_38_86, int_35_85, int_37_85, int_32_86); - fullAdd_x FA_6880_7000(int_41_86, int_40_86, int_34_86, int_39_85, int_36_86); - fullAdd_x FA_6880_7216(int_43_86, int_42_86, int_41_85, int_38_86, int_40_86); - assign Sum[86] = int_43_85; - assign Carry[86] = int_42_86; - - // Hardware for column 87 - - r4bs r4bs_6960_0(yy[62], yy[63], single[12], double[12], neg[12], pp_12_87); - r4bs r4bs_6960_128(yy[60], yy[61], single[13], double[13], neg[13], pp_13_87); - fullAdd_x FA_6960_256(int_1_87, int_0_87, negbar[11], pp_12_87, pp_13_87); - r4bs r4bs_6960_472(yy[58], yy[59], single[14], double[14], neg[14], pp_14_87); - r4bs r4bs_6960_600(yy[56], yy[57], single[15], double[15], neg[15], pp_15_87); - r4bs r4bs_6960_728(yy[54], yy[55], single[16], double[16], neg[16], pp_16_87); - fullAdd_x FA_6960_856(int_3_87, int_2_87, pp_14_87, pp_15_87, pp_16_87); - r4bs r4bs_6960_1072(yy[52], yy[53], single[17], double[17], neg[17], pp_17_87); - r4bs r4bs_6960_1200(yy[50], yy[51], single[18], double[18], neg[18], pp_18_87); - r4bs r4bs_6960_1328(yy[48], yy[49], single[19], double[19], neg[19], pp_19_87); - fullAdd_x FA_6960_1456(int_5_87, int_4_87, pp_17_87, pp_18_87, pp_19_87); - r4bs r4bs_6960_1672(yy[46], yy[47], single[20], double[20], neg[20], pp_20_87); - r4bs r4bs_6960_1800(yy[44], yy[45], single[21], double[21], neg[21], pp_21_87); - r4bs r4bs_6960_1928(yy[42], yy[43], single[22], double[22], neg[22], pp_22_87); - fullAdd_x FA_6960_2056(int_7_87, int_6_87, pp_20_87, pp_21_87, pp_22_87); - r4bs r4bs_6960_2272(yy[40], yy[41], single[23], double[23], neg[23], pp_23_87); - r4bs r4bs_6960_2400(yy[38], yy[39], single[24], double[24], neg[24], pp_24_87); - r4bs r4bs_6960_2528(yy[36], yy[37], single[25], double[25], neg[25], pp_25_87); - fullAdd_x FA_6960_2656(int_9_87, int_8_87, pp_23_87, pp_24_87, pp_25_87); - r4bs r4bs_6960_2872(yy[34], yy[35], single[26], double[26], neg[26], pp_26_87); - r4bs r4bs_6960_3000(yy[32], yy[33], single[27], double[27], neg[27], pp_27_87); - r4bs r4bs_6960_3128(yy[30], yy[31], single[28], double[28], neg[28], pp_28_87); - fullAdd_x FA_6960_3256(int_11_87, int_10_87, pp_26_87, pp_27_87, pp_28_87); - r4bs r4bs_6960_3472(yy[28], yy[29], single[29], double[29], neg[29], pp_29_87); - r4bs r4bs_6960_3600(yy[26], yy[27], single[30], double[30], neg[30], pp_30_87); - r4bs r4bs_6960_3728(yy[24], yy[25], single[31], double[31], neg[31], pp_31_87); - fullAdd_x FA_6960_3856(int_13_87, int_12_87, pp_29_87, pp_30_87, pp_31_87); - r4bs r4bs_6960_4072(yy[22], yy[23], single[32], double[32], neg[32], pp_32_87); - fullAdd_x FA_6960_4200(int_15_87, int_14_87, pp_32_87, int_1_86, int_3_86); - fullAdd_x FA_6960_4416(int_17_87, int_16_87, int_5_86, int_7_86, int_9_86); - fullAdd_x FA_6960_4632(int_19_87, int_18_87, int_11_86, int_13_86, int_15_86); - fullAdd_x FA_6960_4848(int_21_87, int_20_87, int_17_86, int_19_86, int_0_87); - fullAdd_x FA_6960_5064(int_23_87, int_22_87, int_2_87, int_4_87, int_6_87); - fullAdd_x FA_6960_5280(int_25_87, int_24_87, int_8_87, int_10_87, int_12_87); - fullAdd_x FA_6960_5496(int_27_87, int_26_87, int_21_86, int_14_87, int_23_86); - fullAdd_x FA_6960_5712(int_29_87, int_28_87, int_25_86, int_27_86, int_16_87); - fullAdd_x FA_6960_5928(int_31_87, int_30_87, int_18_87, int_29_86, int_31_86); - fullAdd_x FA_6960_6144(int_33_87, int_32_87, int_20_87, int_22_87, int_24_87); - fullAdd_x FA_6960_6360(int_35_87, int_34_87, int_26_87, int_33_86, int_28_87); - fullAdd_x FA_6960_6576(int_37_87, int_36_87, int_35_86, int_37_86, int_30_87); - fullAdd_x FA_6960_6792(int_39_87, int_38_87, int_32_87, int_39_86, int_34_87); - fullAdd_x FA_6960_7008(int_41_87, int_40_87, int_41_86, int_36_87, int_38_87); - assign Sum[87] = int_43_86; - assign Carry[87] = int_40_87; - - // Hardware for column 88 - - r4bs r4bs_7040_0(yy[63], gnd, single[12], double[12], neg[12], pp_12_88); - halfAdd HA_7040_128(int_1_88, int_0_88, 1'b1, pp_12_88); - r4bs r4bs_7040_208(yy[61], yy[62], single[13], double[13], neg[13], pp_13_88); - r4bs r4bs_7040_336(yy[59], yy[60], single[14], double[14], neg[14], pp_14_88); - r4bs r4bs_7040_464(yy[57], yy[58], single[15], double[15], neg[15], pp_15_88); - fullAdd_x FA_7040_592(int_3_88, int_2_88, pp_13_88, pp_14_88, pp_15_88); - r4bs r4bs_7040_808(yy[55], yy[56], single[16], double[16], neg[16], pp_16_88); - r4bs r4bs_7040_936(yy[53], yy[54], single[17], double[17], neg[17], pp_17_88); - r4bs r4bs_7040_1064(yy[51], yy[52], single[18], double[18], neg[18], pp_18_88); - fullAdd_x FA_7040_1192(int_5_88, int_4_88, pp_16_88, pp_17_88, pp_18_88); - r4bs r4bs_7040_1408(yy[49], yy[50], single[19], double[19], neg[19], pp_19_88); - r4bs r4bs_7040_1536(yy[47], yy[48], single[20], double[20], neg[20], pp_20_88); - r4bs r4bs_7040_1664(yy[45], yy[46], single[21], double[21], neg[21], pp_21_88); - fullAdd_x FA_7040_1792(int_7_88, int_6_88, pp_19_88, pp_20_88, pp_21_88); - r4bs r4bs_7040_2008(yy[43], yy[44], single[22], double[22], neg[22], pp_22_88); - r4bs r4bs_7040_2136(yy[41], yy[42], single[23], double[23], neg[23], pp_23_88); - r4bs r4bs_7040_2264(yy[39], yy[40], single[24], double[24], neg[24], pp_24_88); - fullAdd_x FA_7040_2392(int_9_88, int_8_88, pp_22_88, pp_23_88, pp_24_88); - r4bs r4bs_7040_2608(yy[37], yy[38], single[25], double[25], neg[25], pp_25_88); - r4bs r4bs_7040_2736(yy[35], yy[36], single[26], double[26], neg[26], pp_26_88); - r4bs r4bs_7040_2864(yy[33], yy[34], single[27], double[27], neg[27], pp_27_88); - fullAdd_x FA_7040_2992(int_11_88, int_10_88, pp_25_88, pp_26_88, pp_27_88); - r4bs r4bs_7040_3208(yy[31], yy[32], single[28], double[28], neg[28], pp_28_88); - r4bs r4bs_7040_3336(yy[29], yy[30], single[29], double[29], neg[29], pp_29_88); - r4bs r4bs_7040_3464(yy[27], yy[28], single[30], double[30], neg[30], pp_30_88); - fullAdd_x FA_7040_3592(int_13_88, int_12_88, pp_28_88, pp_29_88, pp_30_88); - r4bs r4bs_7040_3808(yy[25], yy[26], single[31], double[31], neg[31], pp_31_88); - r4bs r4bs_7040_3936(yy[23], yy[24], single[32], double[32], neg[32], pp_32_88); - fullAdd_x FA_7040_4064(int_15_88, int_14_88, pp_31_88, pp_32_88, int_1_87); - fullAdd_x FA_7040_4280(int_17_88, int_16_88, int_3_87, int_5_87, int_7_87); - fullAdd_x FA_7040_4496(int_19_88, int_18_88, int_9_87, int_11_87, int_13_87); - fullAdd_x FA_7040_4712(int_21_88, int_20_88, int_0_88, int_15_87, int_17_87); - fullAdd_x FA_7040_4928(int_23_88, int_22_88, int_19_87, int_2_88, int_4_88); - fullAdd_x FA_7040_5144(int_25_88, int_24_88, int_6_88, int_8_88, int_10_88); - fullAdd_x FA_7040_5360(int_27_88, int_26_88, int_12_88, int_14_88, int_21_87); - fullAdd_x FA_7040_5576(int_29_88, int_28_88, int_23_87, int_25_87, int_16_88); - fullAdd_x FA_7040_5792(int_31_88, int_30_88, int_18_88, int_27_87, int_29_87); - fullAdd_x FA_7040_6008(int_33_88, int_32_88, int_20_88, int_22_88, int_24_88); - fullAdd_x FA_7040_6224(int_35_88, int_34_88, int_26_88, int_31_87, int_33_87); - fullAdd_x FA_7040_6440(int_37_88, int_36_88, int_28_88, int_35_87, int_30_88); - fullAdd_x FA_7040_6656(int_39_88, int_38_88, int_32_88, int_37_87, int_34_88); - fullAdd_x FA_7040_6872(int_41_88, int_40_88, int_39_87, int_36_88, int_38_88); - assign Sum[88] = int_41_87; - assign Carry[88] = int_40_88; - - // Hardware for column 89 - - r4bs r4bs_7120_0(yy[62], yy[63], single[13], double[13], neg[13], pp_13_89); - r4bs r4bs_7120_128(yy[60], yy[61], single[14], double[14], neg[14], pp_14_89); - fullAdd_x FA_7120_256(int_1_89, int_0_89, negbar[12], pp_13_89, pp_14_89); - r4bs r4bs_7120_472(yy[58], yy[59], single[15], double[15], neg[15], pp_15_89); - r4bs r4bs_7120_600(yy[56], yy[57], single[16], double[16], neg[16], pp_16_89); - r4bs r4bs_7120_728(yy[54], yy[55], single[17], double[17], neg[17], pp_17_89); - fullAdd_x FA_7120_856(int_3_89, int_2_89, pp_15_89, pp_16_89, pp_17_89); - r4bs r4bs_7120_1072(yy[52], yy[53], single[18], double[18], neg[18], pp_18_89); - r4bs r4bs_7120_1200(yy[50], yy[51], single[19], double[19], neg[19], pp_19_89); - r4bs r4bs_7120_1328(yy[48], yy[49], single[20], double[20], neg[20], pp_20_89); - fullAdd_x FA_7120_1456(int_5_89, int_4_89, pp_18_89, pp_19_89, pp_20_89); - r4bs r4bs_7120_1672(yy[46], yy[47], single[21], double[21], neg[21], pp_21_89); - r4bs r4bs_7120_1800(yy[44], yy[45], single[22], double[22], neg[22], pp_22_89); - r4bs r4bs_7120_1928(yy[42], yy[43], single[23], double[23], neg[23], pp_23_89); - fullAdd_x FA_7120_2056(int_7_89, int_6_89, pp_21_89, pp_22_89, pp_23_89); - r4bs r4bs_7120_2272(yy[40], yy[41], single[24], double[24], neg[24], pp_24_89); - r4bs r4bs_7120_2400(yy[38], yy[39], single[25], double[25], neg[25], pp_25_89); - r4bs r4bs_7120_2528(yy[36], yy[37], single[26], double[26], neg[26], pp_26_89); - fullAdd_x FA_7120_2656(int_9_89, int_8_89, pp_24_89, pp_25_89, pp_26_89); - r4bs r4bs_7120_2872(yy[34], yy[35], single[27], double[27], neg[27], pp_27_89); - r4bs r4bs_7120_3000(yy[32], yy[33], single[28], double[28], neg[28], pp_28_89); - r4bs r4bs_7120_3128(yy[30], yy[31], single[29], double[29], neg[29], pp_29_89); - fullAdd_x FA_7120_3256(int_11_89, int_10_89, pp_27_89, pp_28_89, pp_29_89); - r4bs r4bs_7120_3472(yy[28], yy[29], single[30], double[30], neg[30], pp_30_89); - r4bs r4bs_7120_3600(yy[26], yy[27], single[31], double[31], neg[31], pp_31_89); - r4bs r4bs_7120_3728(yy[24], yy[25], single[32], double[32], neg[32], pp_32_89); - fullAdd_x FA_7120_3856(int_13_89, int_12_89, pp_30_89, pp_31_89, pp_32_89); - fullAdd_x FA_7120_4072(int_15_89, int_14_89, int_1_88, int_3_88, int_5_88); - fullAdd_x FA_7120_4288(int_17_89, int_16_89, int_7_88, int_9_88, int_11_88); - fullAdd_x FA_7120_4504(int_19_89, int_18_89, int_13_88, int_15_88, int_17_88); - fullAdd_x FA_7120_4720(int_21_89, int_20_89, int_19_88, int_0_89, int_2_89); - fullAdd_x FA_7120_4936(int_23_89, int_22_89, int_4_89, int_6_89, int_8_89); - fullAdd_x FA_7120_5152(int_25_89, int_24_89, int_10_89, int_12_89, int_21_88); - fullAdd_x FA_7120_5368(int_27_89, int_26_89, int_23_88, int_25_88, int_14_89); - fullAdd_x FA_7120_5584(int_29_89, int_28_89, int_16_89, int_27_88, int_29_88); - fullAdd_x FA_7120_5800(int_31_89, int_30_89, int_18_89, int_20_89, int_22_89); - fullAdd_x FA_7120_6016(int_33_89, int_32_89, int_24_89, int_31_88, int_33_88); - fullAdd_x FA_7120_6232(int_35_89, int_34_89, int_26_89, int_35_88, int_28_89); - fullAdd_x FA_7120_6448(int_37_89, int_36_89, int_30_89, int_37_88, int_32_89); - fullAdd_x FA_7120_6664(int_39_89, int_38_89, int_39_88, int_34_89, int_36_89); - assign Sum[89] = int_41_88; - assign Carry[89] = int_38_89; - - // Hardware for column 90 - - r4bs r4bs_7200_0(yy[63], gnd, single[13], double[13], neg[13], pp_13_90); - halfAdd HA_7200_128(int_1_90, int_0_90, 1'b1, pp_13_90); - r4bs r4bs_7200_208(yy[61], yy[62], single[14], double[14], neg[14], pp_14_90); - r4bs r4bs_7200_336(yy[59], yy[60], single[15], double[15], neg[15], pp_15_90); - r4bs r4bs_7200_464(yy[57], yy[58], single[16], double[16], neg[16], pp_16_90); - fullAdd_x FA_7200_592(int_3_90, int_2_90, pp_14_90, pp_15_90, pp_16_90); - r4bs r4bs_7200_808(yy[55], yy[56], single[17], double[17], neg[17], pp_17_90); - r4bs r4bs_7200_936(yy[53], yy[54], single[18], double[18], neg[18], pp_18_90); - r4bs r4bs_7200_1064(yy[51], yy[52], single[19], double[19], neg[19], pp_19_90); - fullAdd_x FA_7200_1192(int_5_90, int_4_90, pp_17_90, pp_18_90, pp_19_90); - r4bs r4bs_7200_1408(yy[49], yy[50], single[20], double[20], neg[20], pp_20_90); - r4bs r4bs_7200_1536(yy[47], yy[48], single[21], double[21], neg[21], pp_21_90); - r4bs r4bs_7200_1664(yy[45], yy[46], single[22], double[22], neg[22], pp_22_90); - fullAdd_x FA_7200_1792(int_7_90, int_6_90, pp_20_90, pp_21_90, pp_22_90); - r4bs r4bs_7200_2008(yy[43], yy[44], single[23], double[23], neg[23], pp_23_90); - r4bs r4bs_7200_2136(yy[41], yy[42], single[24], double[24], neg[24], pp_24_90); - r4bs r4bs_7200_2264(yy[39], yy[40], single[25], double[25], neg[25], pp_25_90); - fullAdd_x FA_7200_2392(int_9_90, int_8_90, pp_23_90, pp_24_90, pp_25_90); - r4bs r4bs_7200_2608(yy[37], yy[38], single[26], double[26], neg[26], pp_26_90); - r4bs r4bs_7200_2736(yy[35], yy[36], single[27], double[27], neg[27], pp_27_90); - r4bs r4bs_7200_2864(yy[33], yy[34], single[28], double[28], neg[28], pp_28_90); - fullAdd_x FA_7200_2992(int_11_90, int_10_90, pp_26_90, pp_27_90, pp_28_90); - r4bs r4bs_7200_3208(yy[31], yy[32], single[29], double[29], neg[29], pp_29_90); - r4bs r4bs_7200_3336(yy[29], yy[30], single[30], double[30], neg[30], pp_30_90); - r4bs r4bs_7200_3464(yy[27], yy[28], single[31], double[31], neg[31], pp_31_90); - fullAdd_x FA_7200_3592(int_13_90, int_12_90, pp_29_90, pp_30_90, pp_31_90); - r4bs r4bs_7200_3808(yy[25], yy[26], single[32], double[32], neg[32], pp_32_90); - fullAdd_x FA_7200_3936(int_15_90, int_14_90, pp_32_90, int_1_89, int_3_89); - fullAdd_x FA_7200_4152(int_17_90, int_16_90, int_5_89, int_7_89, int_9_89); - fullAdd_x FA_7200_4368(int_19_90, int_18_90, int_11_89, int_13_89, int_0_90); - fullAdd_x FA_7200_4584(int_21_90, int_20_90, int_15_89, int_17_89, int_2_90); - fullAdd_x FA_7200_4800(int_23_90, int_22_90, int_4_90, int_6_90, int_8_90); - fullAdd_x FA_7200_5016(int_25_90, int_24_90, int_10_90, int_12_90, int_19_89); - fullAdd_x FA_7200_5232(int_27_90, int_26_90, int_21_89, int_23_89, int_14_90); - fullAdd_x FA_7200_5448(int_29_90, int_28_90, int_16_90, int_18_90, int_25_89); - fullAdd_x FA_7200_5664(int_31_90, int_30_90, int_27_89, int_20_90, int_22_90); - fullAdd_x FA_7200_5880(int_33_90, int_32_90, int_24_90, int_29_89, int_31_89); - fullAdd_x FA_7200_6096(int_35_90, int_34_90, int_26_90, int_28_90, int_33_89); - fullAdd_x FA_7200_6312(int_37_90, int_36_90, int_30_90, int_35_89, int_32_90); - fullAdd_x FA_7200_6528(int_39_90, int_38_90, int_34_90, int_37_89, int_36_90); - assign Sum[90] = int_39_89; - assign Carry[90] = int_38_90; - - // Hardware for column 91 - - r4bs r4bs_7280_0(yy[62], yy[63], single[14], double[14], neg[14], pp_14_91); - r4bs r4bs_7280_128(yy[60], yy[61], single[15], double[15], neg[15], pp_15_91); - fullAdd_x FA_7280_256(int_1_91, int_0_91, negbar[13], pp_14_91, pp_15_91); - r4bs r4bs_7280_472(yy[58], yy[59], single[16], double[16], neg[16], pp_16_91); - r4bs r4bs_7280_600(yy[56], yy[57], single[17], double[17], neg[17], pp_17_91); - r4bs r4bs_7280_728(yy[54], yy[55], single[18], double[18], neg[18], pp_18_91); - fullAdd_x FA_7280_856(int_3_91, int_2_91, pp_16_91, pp_17_91, pp_18_91); - r4bs r4bs_7280_1072(yy[52], yy[53], single[19], double[19], neg[19], pp_19_91); - r4bs r4bs_7280_1200(yy[50], yy[51], single[20], double[20], neg[20], pp_20_91); - r4bs r4bs_7280_1328(yy[48], yy[49], single[21], double[21], neg[21], pp_21_91); - fullAdd_x FA_7280_1456(int_5_91, int_4_91, pp_19_91, pp_20_91, pp_21_91); - r4bs r4bs_7280_1672(yy[46], yy[47], single[22], double[22], neg[22], pp_22_91); - r4bs r4bs_7280_1800(yy[44], yy[45], single[23], double[23], neg[23], pp_23_91); - r4bs r4bs_7280_1928(yy[42], yy[43], single[24], double[24], neg[24], pp_24_91); - fullAdd_x FA_7280_2056(int_7_91, int_6_91, pp_22_91, pp_23_91, pp_24_91); - r4bs r4bs_7280_2272(yy[40], yy[41], single[25], double[25], neg[25], pp_25_91); - r4bs r4bs_7280_2400(yy[38], yy[39], single[26], double[26], neg[26], pp_26_91); - r4bs r4bs_7280_2528(yy[36], yy[37], single[27], double[27], neg[27], pp_27_91); - fullAdd_x FA_7280_2656(int_9_91, int_8_91, pp_25_91, pp_26_91, pp_27_91); - r4bs r4bs_7280_2872(yy[34], yy[35], single[28], double[28], neg[28], pp_28_91); - r4bs r4bs_7280_3000(yy[32], yy[33], single[29], double[29], neg[29], pp_29_91); - r4bs r4bs_7280_3128(yy[30], yy[31], single[30], double[30], neg[30], pp_30_91); - fullAdd_x FA_7280_3256(int_11_91, int_10_91, pp_28_91, pp_29_91, pp_30_91); - r4bs r4bs_7280_3472(yy[28], yy[29], single[31], double[31], neg[31], pp_31_91); - r4bs r4bs_7280_3600(yy[26], yy[27], single[32], double[32], neg[32], pp_32_91); - fullAdd_x FA_7280_3728(int_13_91, int_12_91, pp_31_91, pp_32_91, int_1_90); - fullAdd_x FA_7280_3944(int_15_91, int_14_91, int_3_90, int_5_90, int_7_90); - fullAdd_x FA_7280_4160(int_17_91, int_16_91, int_9_90, int_11_90, int_13_90); - fullAdd_x FA_7280_4376(int_19_91, int_18_91, int_15_90, int_17_90, int_19_90); - fullAdd_x FA_7280_4592(int_21_91, int_20_91, int_0_91, int_2_91, int_4_91); - fullAdd_x FA_7280_4808(int_23_91, int_22_91, int_6_91, int_8_91, int_10_91); - fullAdd_x FA_7280_5024(int_25_91, int_24_91, int_12_91, int_21_90, int_23_90); - fullAdd_x FA_7280_5240(int_27_91, int_26_91, int_14_91, int_16_91, int_25_90); - fullAdd_x FA_7280_5456(int_29_91, int_28_91, int_27_90, int_18_91, int_20_91); - fullAdd_x FA_7280_5672(int_31_91, int_30_91, int_22_91, int_29_90, int_31_90); - fullAdd_x FA_7280_5888(int_33_91, int_32_91, int_24_91, int_26_91, int_33_90); - fullAdd_x FA_7280_6104(int_35_91, int_34_91, int_28_91, int_35_90, int_30_91); - fullAdd_x FA_7280_6320(int_37_91, int_36_91, int_32_91, int_37_90, int_34_91); - assign Sum[91] = int_39_90; - assign Carry[91] = int_36_91; - - // Hardware for column 92 - - r4bs r4bs_7360_0(yy[63], gnd, single[14], double[14], neg[14], pp_14_92); - halfAdd HA_7360_128(int_1_92, int_0_92, 1'b1, pp_14_92); - r4bs r4bs_7360_208(yy[61], yy[62], single[15], double[15], neg[15], pp_15_92); - r4bs r4bs_7360_336(yy[59], yy[60], single[16], double[16], neg[16], pp_16_92); - r4bs r4bs_7360_464(yy[57], yy[58], single[17], double[17], neg[17], pp_17_92); - fullAdd_x FA_7360_592(int_3_92, int_2_92, pp_15_92, pp_16_92, pp_17_92); - r4bs r4bs_7360_808(yy[55], yy[56], single[18], double[18], neg[18], pp_18_92); - r4bs r4bs_7360_936(yy[53], yy[54], single[19], double[19], neg[19], pp_19_92); - r4bs r4bs_7360_1064(yy[51], yy[52], single[20], double[20], neg[20], pp_20_92); - fullAdd_x FA_7360_1192(int_5_92, int_4_92, pp_18_92, pp_19_92, pp_20_92); - r4bs r4bs_7360_1408(yy[49], yy[50], single[21], double[21], neg[21], pp_21_92); - r4bs r4bs_7360_1536(yy[47], yy[48], single[22], double[22], neg[22], pp_22_92); - r4bs r4bs_7360_1664(yy[45], yy[46], single[23], double[23], neg[23], pp_23_92); - fullAdd_x FA_7360_1792(int_7_92, int_6_92, pp_21_92, pp_22_92, pp_23_92); - r4bs r4bs_7360_2008(yy[43], yy[44], single[24], double[24], neg[24], pp_24_92); - r4bs r4bs_7360_2136(yy[41], yy[42], single[25], double[25], neg[25], pp_25_92); - r4bs r4bs_7360_2264(yy[39], yy[40], single[26], double[26], neg[26], pp_26_92); - fullAdd_x FA_7360_2392(int_9_92, int_8_92, pp_24_92, pp_25_92, pp_26_92); - r4bs r4bs_7360_2608(yy[37], yy[38], single[27], double[27], neg[27], pp_27_92); - r4bs r4bs_7360_2736(yy[35], yy[36], single[28], double[28], neg[28], pp_28_92); - r4bs r4bs_7360_2864(yy[33], yy[34], single[29], double[29], neg[29], pp_29_92); - fullAdd_x FA_7360_2992(int_11_92, int_10_92, pp_27_92, pp_28_92, pp_29_92); - r4bs r4bs_7360_3208(yy[31], yy[32], single[30], double[30], neg[30], pp_30_92); - r4bs r4bs_7360_3336(yy[29], yy[30], single[31], double[31], neg[31], pp_31_92); - r4bs r4bs_7360_3464(yy[27], yy[28], single[32], double[32], neg[32], pp_32_92); - fullAdd_x FA_7360_3592(int_13_92, int_12_92, pp_30_92, pp_31_92, pp_32_92); - fullAdd_x FA_7360_3808(int_15_92, int_14_92, int_1_91, int_3_91, int_5_91); - fullAdd_x FA_7360_4024(int_17_92, int_16_92, int_7_91, int_9_91, int_11_91); - fullAdd_x FA_7360_4240(int_19_92, int_18_92, int_0_92, int_13_91, int_15_91); - fullAdd_x FA_7360_4456(int_21_92, int_20_92, int_17_91, int_2_92, int_4_92); - fullAdd_x FA_7360_4672(int_23_92, int_22_92, int_6_92, int_8_92, int_10_92); - fullAdd_x FA_7360_4888(int_25_92, int_24_92, int_12_92, int_19_91, int_21_91); - fullAdd_x FA_7360_5104(int_27_92, int_26_92, int_23_91, int_14_92, int_16_92); - fullAdd_x FA_7360_5320(int_29_92, int_28_92, int_18_92, int_25_91, int_20_92); - fullAdd_x FA_7360_5536(int_31_92, int_30_92, int_22_92, int_27_91, int_29_91); - fullAdd_x FA_7360_5752(int_33_92, int_32_92, int_24_92, int_26_92, int_31_91); - fullAdd_x FA_7360_5968(int_35_92, int_34_92, int_28_92, int_33_91, int_30_92); - fullAdd_x FA_7360_6184(int_37_92, int_36_92, int_32_92, int_35_91, int_34_92); - assign Sum[92] = int_37_91; - assign Carry[92] = int_36_92; - - // Hardware for column 93 - - r4bs r4bs_7440_0(yy[62], yy[63], single[15], double[15], neg[15], pp_15_93); - r4bs r4bs_7440_128(yy[60], yy[61], single[16], double[16], neg[16], pp_16_93); - fullAdd_x FA_7440_256(int_1_93, int_0_93, negbar[14], pp_15_93, pp_16_93); - r4bs r4bs_7440_472(yy[58], yy[59], single[17], double[17], neg[17], pp_17_93); - r4bs r4bs_7440_600(yy[56], yy[57], single[18], double[18], neg[18], pp_18_93); - r4bs r4bs_7440_728(yy[54], yy[55], single[19], double[19], neg[19], pp_19_93); - fullAdd_x FA_7440_856(int_3_93, int_2_93, pp_17_93, pp_18_93, pp_19_93); - r4bs r4bs_7440_1072(yy[52], yy[53], single[20], double[20], neg[20], pp_20_93); - r4bs r4bs_7440_1200(yy[50], yy[51], single[21], double[21], neg[21], pp_21_93); - r4bs r4bs_7440_1328(yy[48], yy[49], single[22], double[22], neg[22], pp_22_93); - fullAdd_x FA_7440_1456(int_5_93, int_4_93, pp_20_93, pp_21_93, pp_22_93); - r4bs r4bs_7440_1672(yy[46], yy[47], single[23], double[23], neg[23], pp_23_93); - r4bs r4bs_7440_1800(yy[44], yy[45], single[24], double[24], neg[24], pp_24_93); - r4bs r4bs_7440_1928(yy[42], yy[43], single[25], double[25], neg[25], pp_25_93); - fullAdd_x FA_7440_2056(int_7_93, int_6_93, pp_23_93, pp_24_93, pp_25_93); - r4bs r4bs_7440_2272(yy[40], yy[41], single[26], double[26], neg[26], pp_26_93); - r4bs r4bs_7440_2400(yy[38], yy[39], single[27], double[27], neg[27], pp_27_93); - r4bs r4bs_7440_2528(yy[36], yy[37], single[28], double[28], neg[28], pp_28_93); - fullAdd_x FA_7440_2656(int_9_93, int_8_93, pp_26_93, pp_27_93, pp_28_93); - r4bs r4bs_7440_2872(yy[34], yy[35], single[29], double[29], neg[29], pp_29_93); - r4bs r4bs_7440_3000(yy[32], yy[33], single[30], double[30], neg[30], pp_30_93); - r4bs r4bs_7440_3128(yy[30], yy[31], single[31], double[31], neg[31], pp_31_93); - fullAdd_x FA_7440_3256(int_11_93, int_10_93, pp_29_93, pp_30_93, pp_31_93); - r4bs r4bs_7440_3472(yy[28], yy[29], single[32], double[32], neg[32], pp_32_93); - fullAdd_x FA_7440_3600(int_13_93, int_12_93, pp_32_93, int_1_92, int_3_92); - fullAdd_x FA_7440_3816(int_15_93, int_14_93, int_5_92, int_7_92, int_9_92); - fullAdd_x FA_7440_4032(int_17_93, int_16_93, int_11_92, int_13_92, int_15_92); - fullAdd_x FA_7440_4248(int_19_93, int_18_93, int_17_92, int_0_93, int_2_93); - fullAdd_x FA_7440_4464(int_21_93, int_20_93, int_4_93, int_6_93, int_8_93); - fullAdd_x FA_7440_4680(int_23_93, int_22_93, int_10_93, int_12_93, int_19_92); - fullAdd_x FA_7440_4896(int_25_93, int_24_93, int_21_92, int_23_92, int_14_93); - fullAdd_x FA_7440_5112(int_27_93, int_26_93, int_16_93, int_25_92, int_27_92); - fullAdd_x FA_7440_5328(int_29_93, int_28_93, int_18_93, int_20_93, int_22_93); - fullAdd_x FA_7440_5544(int_31_93, int_30_93, int_29_92, int_24_93, int_31_92); - fullAdd_x FA_7440_5760(int_33_93, int_32_93, int_26_93, int_28_93, int_33_92); - fullAdd_x FA_7440_5976(int_35_93, int_34_93, int_30_93, int_35_92, int_32_93); - assign Sum[93] = int_37_92; - assign Carry[93] = int_34_93; - - // Hardware for column 94 - - r4bs r4bs_7520_0(yy[63], gnd, single[15], double[15], neg[15], pp_15_94); - halfAdd HA_7520_128(int_1_94, int_0_94, 1'b1, pp_15_94); - r4bs r4bs_7520_208(yy[61], yy[62], single[16], double[16], neg[16], pp_16_94); - r4bs r4bs_7520_336(yy[59], yy[60], single[17], double[17], neg[17], pp_17_94); - r4bs r4bs_7520_464(yy[57], yy[58], single[18], double[18], neg[18], pp_18_94); - fullAdd_x FA_7520_592(int_3_94, int_2_94, pp_16_94, pp_17_94, pp_18_94); - r4bs r4bs_7520_808(yy[55], yy[56], single[19], double[19], neg[19], pp_19_94); - r4bs r4bs_7520_936(yy[53], yy[54], single[20], double[20], neg[20], pp_20_94); - r4bs r4bs_7520_1064(yy[51], yy[52], single[21], double[21], neg[21], pp_21_94); - fullAdd_x FA_7520_1192(int_5_94, int_4_94, pp_19_94, pp_20_94, pp_21_94); - r4bs r4bs_7520_1408(yy[49], yy[50], single[22], double[22], neg[22], pp_22_94); - r4bs r4bs_7520_1536(yy[47], yy[48], single[23], double[23], neg[23], pp_23_94); - r4bs r4bs_7520_1664(yy[45], yy[46], single[24], double[24], neg[24], pp_24_94); - fullAdd_x FA_7520_1792(int_7_94, int_6_94, pp_22_94, pp_23_94, pp_24_94); - r4bs r4bs_7520_2008(yy[43], yy[44], single[25], double[25], neg[25], pp_25_94); - r4bs r4bs_7520_2136(yy[41], yy[42], single[26], double[26], neg[26], pp_26_94); - r4bs r4bs_7520_2264(yy[39], yy[40], single[27], double[27], neg[27], pp_27_94); - fullAdd_x FA_7520_2392(int_9_94, int_8_94, pp_25_94, pp_26_94, pp_27_94); - r4bs r4bs_7520_2608(yy[37], yy[38], single[28], double[28], neg[28], pp_28_94); - r4bs r4bs_7520_2736(yy[35], yy[36], single[29], double[29], neg[29], pp_29_94); - r4bs r4bs_7520_2864(yy[33], yy[34], single[30], double[30], neg[30], pp_30_94); - fullAdd_x FA_7520_2992(int_11_94, int_10_94, pp_28_94, pp_29_94, pp_30_94); - r4bs r4bs_7520_3208(yy[31], yy[32], single[31], double[31], neg[31], pp_31_94); - r4bs r4bs_7520_3336(yy[29], yy[30], single[32], double[32], neg[32], pp_32_94); - fullAdd_x FA_7520_3464(int_13_94, int_12_94, pp_31_94, pp_32_94, int_1_93); - fullAdd_x FA_7520_3680(int_15_94, int_14_94, int_3_93, int_5_93, int_7_93); - fullAdd_x FA_7520_3896(int_17_94, int_16_94, int_9_93, int_11_93, int_0_94); - fullAdd_x FA_7520_4112(int_19_94, int_18_94, int_13_93, int_15_93, int_2_94); - fullAdd_x FA_7520_4328(int_21_94, int_20_94, int_4_94, int_6_94, int_8_94); - fullAdd_x FA_7520_4544(int_23_94, int_22_94, int_10_94, int_12_94, int_17_93); - fullAdd_x FA_7520_4760(int_25_94, int_24_94, int_19_93, int_21_93, int_14_94); - fullAdd_x FA_7520_4976(int_27_94, int_26_94, int_16_94, int_23_93, int_25_93); - fullAdd_x FA_7520_5192(int_29_94, int_28_94, int_18_94, int_20_94, int_22_94); - fullAdd_x FA_7520_5408(int_31_94, int_30_94, int_27_93, int_24_94, int_29_93); - fullAdd_x FA_7520_5624(int_33_94, int_32_94, int_26_94, int_28_94, int_31_93); - fullAdd_x FA_7520_5840(int_35_94, int_34_94, int_30_94, int_33_93, int_32_94); - assign Sum[94] = int_35_93; - assign Carry[94] = int_34_94; - - // Hardware for column 95 - - r4bs r4bs_7600_0(yy[62], yy[63], single[16], double[16], neg[16], pp_16_95); - r4bs r4bs_7600_128(yy[60], yy[61], single[17], double[17], neg[17], pp_17_95); - fullAdd_x FA_7600_256(int_1_95, int_0_95, negbar[15], pp_16_95, pp_17_95); - r4bs r4bs_7600_472(yy[58], yy[59], single[18], double[18], neg[18], pp_18_95); - r4bs r4bs_7600_600(yy[56], yy[57], single[19], double[19], neg[19], pp_19_95); - r4bs r4bs_7600_728(yy[54], yy[55], single[20], double[20], neg[20], pp_20_95); - fullAdd_x FA_7600_856(int_3_95, int_2_95, pp_18_95, pp_19_95, pp_20_95); - r4bs r4bs_7600_1072(yy[52], yy[53], single[21], double[21], neg[21], pp_21_95); - r4bs r4bs_7600_1200(yy[50], yy[51], single[22], double[22], neg[22], pp_22_95); - r4bs r4bs_7600_1328(yy[48], yy[49], single[23], double[23], neg[23], pp_23_95); - fullAdd_x FA_7600_1456(int_5_95, int_4_95, pp_21_95, pp_22_95, pp_23_95); - r4bs r4bs_7600_1672(yy[46], yy[47], single[24], double[24], neg[24], pp_24_95); - r4bs r4bs_7600_1800(yy[44], yy[45], single[25], double[25], neg[25], pp_25_95); - r4bs r4bs_7600_1928(yy[42], yy[43], single[26], double[26], neg[26], pp_26_95); - fullAdd_x FA_7600_2056(int_7_95, int_6_95, pp_24_95, pp_25_95, pp_26_95); - r4bs r4bs_7600_2272(yy[40], yy[41], single[27], double[27], neg[27], pp_27_95); - r4bs r4bs_7600_2400(yy[38], yy[39], single[28], double[28], neg[28], pp_28_95); - r4bs r4bs_7600_2528(yy[36], yy[37], single[29], double[29], neg[29], pp_29_95); - fullAdd_x FA_7600_2656(int_9_95, int_8_95, pp_27_95, pp_28_95, pp_29_95); - r4bs r4bs_7600_2872(yy[34], yy[35], single[30], double[30], neg[30], pp_30_95); - r4bs r4bs_7600_3000(yy[32], yy[33], single[31], double[31], neg[31], pp_31_95); - r4bs r4bs_7600_3128(yy[30], yy[31], single[32], double[32], neg[32], pp_32_95); - fullAdd_x FA_7600_3256(int_11_95, int_10_95, pp_30_95, pp_31_95, pp_32_95); - fullAdd_x FA_7600_3472(int_13_95, int_12_95, int_1_94, int_3_94, int_5_94); - fullAdd_x FA_7600_3688(int_15_95, int_14_95, int_7_94, int_9_94, int_11_94); - fullAdd_x FA_7600_3904(int_17_95, int_16_95, int_13_94, int_15_94, int_17_94); - fullAdd_x FA_7600_4120(int_19_95, int_18_95, int_0_95, int_2_95, int_4_95); - fullAdd_x FA_7600_4336(int_21_95, int_20_95, int_6_95, int_8_95, int_10_95); - fullAdd_x FA_7600_4552(int_23_95, int_22_95, int_19_94, int_21_94, int_12_95); - fullAdd_x FA_7600_4768(int_25_95, int_24_95, int_14_95, int_23_94, int_25_94); - fullAdd_x FA_7600_4984(int_27_95, int_26_95, int_16_95, int_18_95, int_20_95); - fullAdd_x FA_7600_5200(int_29_95, int_28_95, int_27_94, int_29_94, int_22_95); - fullAdd_x FA_7600_5416(int_31_95, int_30_95, int_24_95, int_26_95, int_31_94); - fullAdd_x FA_7600_5632(int_33_95, int_32_95, int_28_95, int_33_94, int_30_95); - assign Sum[95] = int_35_94; - assign Carry[95] = int_32_95; - - // Hardware for column 96 - - r4bs r4bs_7680_0(yy[63], gnd, single[16], double[16], neg[16], pp_16_96); - halfAdd HA_7680_128(int_1_96, int_0_96, 1'b1, pp_16_96); - r4bs r4bs_7680_208(yy[61], yy[62], single[17], double[17], neg[17], pp_17_96); - r4bs r4bs_7680_336(yy[59], yy[60], single[18], double[18], neg[18], pp_18_96); - r4bs r4bs_7680_464(yy[57], yy[58], single[19], double[19], neg[19], pp_19_96); - fullAdd_x FA_7680_592(int_3_96, int_2_96, pp_17_96, pp_18_96, pp_19_96); - r4bs r4bs_7680_808(yy[55], yy[56], single[20], double[20], neg[20], pp_20_96); - r4bs r4bs_7680_936(yy[53], yy[54], single[21], double[21], neg[21], pp_21_96); - r4bs r4bs_7680_1064(yy[51], yy[52], single[22], double[22], neg[22], pp_22_96); - fullAdd_x FA_7680_1192(int_5_96, int_4_96, pp_20_96, pp_21_96, pp_22_96); - r4bs r4bs_7680_1408(yy[49], yy[50], single[23], double[23], neg[23], pp_23_96); - r4bs r4bs_7680_1536(yy[47], yy[48], single[24], double[24], neg[24], pp_24_96); - r4bs r4bs_7680_1664(yy[45], yy[46], single[25], double[25], neg[25], pp_25_96); - fullAdd_x FA_7680_1792(int_7_96, int_6_96, pp_23_96, pp_24_96, pp_25_96); - r4bs r4bs_7680_2008(yy[43], yy[44], single[26], double[26], neg[26], pp_26_96); - r4bs r4bs_7680_2136(yy[41], yy[42], single[27], double[27], neg[27], pp_27_96); - r4bs r4bs_7680_2264(yy[39], yy[40], single[28], double[28], neg[28], pp_28_96); - fullAdd_x FA_7680_2392(int_9_96, int_8_96, pp_26_96, pp_27_96, pp_28_96); - r4bs r4bs_7680_2608(yy[37], yy[38], single[29], double[29], neg[29], pp_29_96); - r4bs r4bs_7680_2736(yy[35], yy[36], single[30], double[30], neg[30], pp_30_96); - r4bs r4bs_7680_2864(yy[33], yy[34], single[31], double[31], neg[31], pp_31_96); - fullAdd_x FA_7680_2992(int_11_96, int_10_96, pp_29_96, pp_30_96, pp_31_96); - r4bs r4bs_7680_3208(yy[31], yy[32], single[32], double[32], neg[32], pp_32_96); - fullAdd_x FA_7680_3336(int_13_96, int_12_96, pp_32_96, int_1_95, int_3_95); - fullAdd_x FA_7680_3552(int_15_96, int_14_96, int_5_95, int_7_95, int_9_95); - fullAdd_x FA_7680_3768(int_17_96, int_16_96, int_11_95, int_0_96, int_13_95); - fullAdd_x FA_7680_3984(int_19_96, int_18_96, int_15_95, int_2_96, int_4_96); - fullAdd_x FA_7680_4200(int_21_96, int_20_96, int_6_96, int_8_96, int_10_96); - fullAdd_x FA_7680_4416(int_23_96, int_22_96, int_17_95, int_19_95, int_21_95); - fullAdd_x FA_7680_4632(int_25_96, int_24_96, int_12_96, int_14_96, int_16_96); - fullAdd_x FA_7680_4848(int_27_96, int_26_96, int_23_95, int_18_96, int_20_96); - fullAdd_x FA_7680_5064(int_29_96, int_28_96, int_25_95, int_27_95, int_22_96); - fullAdd_x FA_7680_5280(int_31_96, int_30_96, int_24_96, int_29_95, int_26_96); - fullAdd_x FA_7680_5496(int_33_96, int_32_96, int_28_96, int_31_95, int_30_96); - assign Sum[96] = int_33_95; - assign Carry[96] = int_32_96; - - // Hardware for column 97 - - r4bs r4bs_7760_0(yy[62], yy[63], single[17], double[17], neg[17], pp_17_97); - r4bs r4bs_7760_128(yy[60], yy[61], single[18], double[18], neg[18], pp_18_97); - fullAdd_x FA_7760_256(int_1_97, int_0_97, negbar[16], pp_17_97, pp_18_97); - r4bs r4bs_7760_472(yy[58], yy[59], single[19], double[19], neg[19], pp_19_97); - r4bs r4bs_7760_600(yy[56], yy[57], single[20], double[20], neg[20], pp_20_97); - r4bs r4bs_7760_728(yy[54], yy[55], single[21], double[21], neg[21], pp_21_97); - fullAdd_x FA_7760_856(int_3_97, int_2_97, pp_19_97, pp_20_97, pp_21_97); - r4bs r4bs_7760_1072(yy[52], yy[53], single[22], double[22], neg[22], pp_22_97); - r4bs r4bs_7760_1200(yy[50], yy[51], single[23], double[23], neg[23], pp_23_97); - r4bs r4bs_7760_1328(yy[48], yy[49], single[24], double[24], neg[24], pp_24_97); - fullAdd_x FA_7760_1456(int_5_97, int_4_97, pp_22_97, pp_23_97, pp_24_97); - r4bs r4bs_7760_1672(yy[46], yy[47], single[25], double[25], neg[25], pp_25_97); - r4bs r4bs_7760_1800(yy[44], yy[45], single[26], double[26], neg[26], pp_26_97); - r4bs r4bs_7760_1928(yy[42], yy[43], single[27], double[27], neg[27], pp_27_97); - fullAdd_x FA_7760_2056(int_7_97, int_6_97, pp_25_97, pp_26_97, pp_27_97); - r4bs r4bs_7760_2272(yy[40], yy[41], single[28], double[28], neg[28], pp_28_97); - r4bs r4bs_7760_2400(yy[38], yy[39], single[29], double[29], neg[29], pp_29_97); - r4bs r4bs_7760_2528(yy[36], yy[37], single[30], double[30], neg[30], pp_30_97); - fullAdd_x FA_7760_2656(int_9_97, int_8_97, pp_28_97, pp_29_97, pp_30_97); - r4bs r4bs_7760_2872(yy[34], yy[35], single[31], double[31], neg[31], pp_31_97); - r4bs r4bs_7760_3000(yy[32], yy[33], single[32], double[32], neg[32], pp_32_97); - fullAdd_x FA_7760_3128(int_11_97, int_10_97, pp_31_97, pp_32_97, int_1_96); - fullAdd_x FA_7760_3344(int_13_97, int_12_97, int_3_96, int_5_96, int_7_96); - fullAdd_x FA_7760_3560(int_15_97, int_14_97, int_9_96, int_11_96, int_13_96); - fullAdd_x FA_7760_3776(int_17_97, int_16_97, int_15_96, int_0_97, int_2_97); - fullAdd_x FA_7760_3992(int_19_97, int_18_97, int_4_97, int_6_97, int_8_97); - fullAdd_x FA_7760_4208(int_21_97, int_20_97, int_10_97, int_17_96, int_19_96); - fullAdd_x FA_7760_4424(int_23_97, int_22_97, int_21_96, int_12_97, int_14_97); - fullAdd_x FA_7760_4640(int_25_97, int_24_97, int_23_96, int_25_96, int_16_97); - fullAdd_x FA_7760_4856(int_27_97, int_26_97, int_18_97, int_27_96, int_20_97); - fullAdd_x FA_7760_5072(int_29_97, int_28_97, int_22_97, int_29_96, int_24_97); - fullAdd_x FA_7760_5288(int_31_97, int_30_97, int_31_96, int_26_97, int_28_97); - assign Sum[97] = int_33_96; - assign Carry[97] = int_30_97; - - // Hardware for column 98 - - r4bs r4bs_7840_0(yy[63], gnd, single[17], double[17], neg[17], pp_17_98); - halfAdd HA_7840_128(int_1_98, int_0_98, 1'b1, pp_17_98); - r4bs r4bs_7840_208(yy[61], yy[62], single[18], double[18], neg[18], pp_18_98); - r4bs r4bs_7840_336(yy[59], yy[60], single[19], double[19], neg[19], pp_19_98); - r4bs r4bs_7840_464(yy[57], yy[58], single[20], double[20], neg[20], pp_20_98); - fullAdd_x FA_7840_592(int_3_98, int_2_98, pp_18_98, pp_19_98, pp_20_98); - r4bs r4bs_7840_808(yy[55], yy[56], single[21], double[21], neg[21], pp_21_98); - r4bs r4bs_7840_936(yy[53], yy[54], single[22], double[22], neg[22], pp_22_98); - r4bs r4bs_7840_1064(yy[51], yy[52], single[23], double[23], neg[23], pp_23_98); - fullAdd_x FA_7840_1192(int_5_98, int_4_98, pp_21_98, pp_22_98, pp_23_98); - r4bs r4bs_7840_1408(yy[49], yy[50], single[24], double[24], neg[24], pp_24_98); - r4bs r4bs_7840_1536(yy[47], yy[48], single[25], double[25], neg[25], pp_25_98); - r4bs r4bs_7840_1664(yy[45], yy[46], single[26], double[26], neg[26], pp_26_98); - fullAdd_x FA_7840_1792(int_7_98, int_6_98, pp_24_98, pp_25_98, pp_26_98); - r4bs r4bs_7840_2008(yy[43], yy[44], single[27], double[27], neg[27], pp_27_98); - r4bs r4bs_7840_2136(yy[41], yy[42], single[28], double[28], neg[28], pp_28_98); - r4bs r4bs_7840_2264(yy[39], yy[40], single[29], double[29], neg[29], pp_29_98); - fullAdd_x FA_7840_2392(int_9_98, int_8_98, pp_27_98, pp_28_98, pp_29_98); - r4bs r4bs_7840_2608(yy[37], yy[38], single[30], double[30], neg[30], pp_30_98); - r4bs r4bs_7840_2736(yy[35], yy[36], single[31], double[31], neg[31], pp_31_98); - r4bs r4bs_7840_2864(yy[33], yy[34], single[32], double[32], neg[32], pp_32_98); - fullAdd_x FA_7840_2992(int_11_98, int_10_98, pp_30_98, pp_31_98, pp_32_98); - fullAdd_x FA_7840_3208(int_13_98, int_12_98, int_1_97, int_3_97, int_5_97); - fullAdd_x FA_7840_3424(int_15_98, int_14_98, int_7_97, int_9_97, int_0_98); - fullAdd_x FA_7840_3640(int_17_98, int_16_98, int_11_97, int_13_97, int_2_98); - fullAdd_x FA_7840_3856(int_19_98, int_18_98, int_4_98, int_6_98, int_8_98); - fullAdd_x FA_7840_4072(int_21_98, int_20_98, int_10_98, int_15_97, int_17_97); - fullAdd_x FA_7840_4288(int_23_98, int_22_98, int_19_97, int_12_98, int_14_98); - fullAdd_x FA_7840_4504(int_25_98, int_24_98, int_21_97, int_23_97, int_16_98); - fullAdd_x FA_7840_4720(int_27_98, int_26_98, int_18_98, int_25_97, int_20_98); - fullAdd_x FA_7840_4936(int_29_98, int_28_98, int_22_98, int_27_97, int_24_98); - fullAdd_x FA_7840_5152(int_31_98, int_30_98, int_29_97, int_26_98, int_28_98); - assign Sum[98] = int_31_97; - assign Carry[98] = int_30_98; - - // Hardware for column 99 - - r4bs r4bs_7920_0(yy[62], yy[63], single[18], double[18], neg[18], pp_18_99); - r4bs r4bs_7920_128(yy[60], yy[61], single[19], double[19], neg[19], pp_19_99); - fullAdd_x FA_7920_256(int_1_99, int_0_99, negbar[17], pp_18_99, pp_19_99); - r4bs r4bs_7920_472(yy[58], yy[59], single[20], double[20], neg[20], pp_20_99); - r4bs r4bs_7920_600(yy[56], yy[57], single[21], double[21], neg[21], pp_21_99); - r4bs r4bs_7920_728(yy[54], yy[55], single[22], double[22], neg[22], pp_22_99); - fullAdd_x FA_7920_856(int_3_99, int_2_99, pp_20_99, pp_21_99, pp_22_99); - r4bs r4bs_7920_1072(yy[52], yy[53], single[23], double[23], neg[23], pp_23_99); - r4bs r4bs_7920_1200(yy[50], yy[51], single[24], double[24], neg[24], pp_24_99); - r4bs r4bs_7920_1328(yy[48], yy[49], single[25], double[25], neg[25], pp_25_99); - fullAdd_x FA_7920_1456(int_5_99, int_4_99, pp_23_99, pp_24_99, pp_25_99); - r4bs r4bs_7920_1672(yy[46], yy[47], single[26], double[26], neg[26], pp_26_99); - r4bs r4bs_7920_1800(yy[44], yy[45], single[27], double[27], neg[27], pp_27_99); - r4bs r4bs_7920_1928(yy[42], yy[43], single[28], double[28], neg[28], pp_28_99); - fullAdd_x FA_7920_2056(int_7_99, int_6_99, pp_26_99, pp_27_99, pp_28_99); - r4bs r4bs_7920_2272(yy[40], yy[41], single[29], double[29], neg[29], pp_29_99); - r4bs r4bs_7920_2400(yy[38], yy[39], single[30], double[30], neg[30], pp_30_99); - r4bs r4bs_7920_2528(yy[36], yy[37], single[31], double[31], neg[31], pp_31_99); - fullAdd_x FA_7920_2656(int_9_99, int_8_99, pp_29_99, pp_30_99, pp_31_99); - r4bs r4bs_7920_2872(yy[34], yy[35], single[32], double[32], neg[32], pp_32_99); - fullAdd_x FA_7920_3000(int_11_99, int_10_99, pp_32_99, int_1_98, int_3_98); - fullAdd_x FA_7920_3216(int_13_99, int_12_99, int_5_98, int_7_98, int_9_98); - fullAdd_x FA_7920_3432(int_15_99, int_14_99, int_11_98, int_13_98, int_15_98); - fullAdd_x FA_7920_3648(int_17_99, int_16_99, int_0_99, int_2_99, int_4_99); - fullAdd_x FA_7920_3864(int_19_99, int_18_99, int_6_99, int_8_99, int_10_99); - fullAdd_x FA_7920_4080(int_21_99, int_20_99, int_17_98, int_19_98, int_12_99); - fullAdd_x FA_7920_4296(int_23_99, int_22_99, int_21_98, int_23_98, int_14_99); - fullAdd_x FA_7920_4512(int_25_99, int_24_99, int_16_99, int_18_99, int_25_98); - fullAdd_x FA_7920_4728(int_27_99, int_26_99, int_20_99, int_27_98, int_22_99); - fullAdd_x FA_7920_4944(int_29_99, int_28_99, int_24_99, int_29_98, int_26_99); - assign Sum[99] = int_31_98; - assign Carry[99] = int_28_99; - - // Hardware for column 100 - - r4bs r4bs_8000_0(yy[63], gnd, single[18], double[18], neg[18], pp_18_100); - halfAdd HA_8000_128(int_1_100, int_0_100, 1'b1, pp_18_100); - r4bs r4bs_8000_208(yy[61], yy[62], single[19], double[19], neg[19], pp_19_100); - r4bs r4bs_8000_336(yy[59], yy[60], single[20], double[20], neg[20], pp_20_100); - r4bs r4bs_8000_464(yy[57], yy[58], single[21], double[21], neg[21], pp_21_100); - fullAdd_x FA_8000_592(int_3_100, int_2_100, pp_19_100, pp_20_100, pp_21_100); - r4bs r4bs_8000_808(yy[55], yy[56], single[22], double[22], neg[22], pp_22_100); - r4bs r4bs_8000_936(yy[53], yy[54], single[23], double[23], neg[23], pp_23_100); - r4bs r4bs_8000_1064(yy[51], yy[52], single[24], double[24], neg[24], pp_24_100); - fullAdd_x FA_8000_1192(int_5_100, int_4_100, pp_22_100, pp_23_100, pp_24_100); - r4bs r4bs_8000_1408(yy[49], yy[50], single[25], double[25], neg[25], pp_25_100); - r4bs r4bs_8000_1536(yy[47], yy[48], single[26], double[26], neg[26], pp_26_100); - r4bs r4bs_8000_1664(yy[45], yy[46], single[27], double[27], neg[27], pp_27_100); - fullAdd_x FA_8000_1792(int_7_100, int_6_100, pp_25_100, pp_26_100, pp_27_100); - r4bs r4bs_8000_2008(yy[43], yy[44], single[28], double[28], neg[28], pp_28_100); - r4bs r4bs_8000_2136(yy[41], yy[42], single[29], double[29], neg[29], pp_29_100); - r4bs r4bs_8000_2264(yy[39], yy[40], single[30], double[30], neg[30], pp_30_100); - fullAdd_x FA_8000_2392(int_9_100, int_8_100, pp_28_100, pp_29_100, pp_30_100); - r4bs r4bs_8000_2608(yy[37], yy[38], single[31], double[31], neg[31], pp_31_100); - r4bs r4bs_8000_2736(yy[35], yy[36], single[32], double[32], neg[32], pp_32_100); - fullAdd_x FA_8000_2864(int_11_100, int_10_100, pp_31_100, pp_32_100, int_1_99); - fullAdd_x FA_8000_3080(int_13_100, int_12_100, int_3_99, int_5_99, int_7_99); - fullAdd_x FA_8000_3296(int_15_100, int_14_100, int_9_99, int_0_100, int_11_99); - fullAdd_x FA_8000_3512(int_17_100, int_16_100, int_13_99, int_2_100, int_4_100); - fullAdd_x FA_8000_3728(int_19_100, int_18_100, int_6_100, int_8_100, int_10_100); - fullAdd_x FA_8000_3944(int_21_100, int_20_100, int_15_99, int_17_99, int_12_100); - fullAdd_x FA_8000_4160(int_23_100, int_22_100, int_14_100, int_19_99, int_21_99); - fullAdd_x FA_8000_4376(int_25_100, int_24_100, int_16_100, int_18_100, int_23_99); - fullAdd_x FA_8000_4592(int_27_100, int_26_100, int_20_100, int_22_100, int_25_99); - fullAdd_x FA_8000_4808(int_29_100, int_28_100, int_24_100, int_27_99, int_26_100); - assign Sum[100] = int_29_99; - assign Carry[100] = int_28_100; - - // Hardware for column 101 - - r4bs r4bs_8080_0(yy[62], yy[63], single[19], double[19], neg[19], pp_19_101); - r4bs r4bs_8080_128(yy[60], yy[61], single[20], double[20], neg[20], pp_20_101); - fullAdd_x FA_8080_256(int_1_101, int_0_101, negbar[18], pp_19_101, pp_20_101); - r4bs r4bs_8080_472(yy[58], yy[59], single[21], double[21], neg[21], pp_21_101); - r4bs r4bs_8080_600(yy[56], yy[57], single[22], double[22], neg[22], pp_22_101); - r4bs r4bs_8080_728(yy[54], yy[55], single[23], double[23], neg[23], pp_23_101); - fullAdd_x FA_8080_856(int_3_101, int_2_101, pp_21_101, pp_22_101, pp_23_101); - r4bs r4bs_8080_1072(yy[52], yy[53], single[24], double[24], neg[24], pp_24_101); - r4bs r4bs_8080_1200(yy[50], yy[51], single[25], double[25], neg[25], pp_25_101); - r4bs r4bs_8080_1328(yy[48], yy[49], single[26], double[26], neg[26], pp_26_101); - fullAdd_x FA_8080_1456(int_5_101, int_4_101, pp_24_101, pp_25_101, pp_26_101); - r4bs r4bs_8080_1672(yy[46], yy[47], single[27], double[27], neg[27], pp_27_101); - r4bs r4bs_8080_1800(yy[44], yy[45], single[28], double[28], neg[28], pp_28_101); - r4bs r4bs_8080_1928(yy[42], yy[43], single[29], double[29], neg[29], pp_29_101); - fullAdd_x FA_8080_2056(int_7_101, int_6_101, pp_27_101, pp_28_101, pp_29_101); - r4bs r4bs_8080_2272(yy[40], yy[41], single[30], double[30], neg[30], pp_30_101); - r4bs r4bs_8080_2400(yy[38], yy[39], single[31], double[31], neg[31], pp_31_101); - r4bs r4bs_8080_2528(yy[36], yy[37], single[32], double[32], neg[32], pp_32_101); - fullAdd_x FA_8080_2656(int_9_101, int_8_101, pp_30_101, pp_31_101, pp_32_101); - fullAdd_x FA_8080_2872(int_11_101, int_10_101, int_1_100, int_3_100, int_5_100); - fullAdd_x FA_8080_3088(int_13_101, int_12_101, int_7_100, int_9_100, int_11_100); - fullAdd_x FA_8080_3304(int_15_101, int_14_101, int_13_100, int_0_101, int_2_101); - fullAdd_x FA_8080_3520(int_17_101, int_16_101, int_4_101, int_6_101, int_8_101); - fullAdd_x FA_8080_3736(int_19_101, int_18_101, int_15_100, int_17_100, int_19_100); - fullAdd_x FA_8080_3952(int_21_101, int_20_101, int_10_101, int_12_101, int_21_100); - fullAdd_x FA_8080_4168(int_23_101, int_22_101, int_14_101, int_16_101, int_23_100); - fullAdd_x FA_8080_4384(int_25_101, int_24_101, int_18_101, int_20_101, int_25_100); - fullAdd_x FA_8080_4600(int_27_101, int_26_101, int_22_101, int_27_100, int_24_101); - assign Sum[101] = int_29_100; - assign Carry[101] = int_26_101; - - // Hardware for column 102 - - r4bs r4bs_8160_0(yy[63], gnd, single[19], double[19], neg[19], pp_19_102); - halfAdd HA_8160_128(int_1_102, int_0_102, 1'b1, pp_19_102); - r4bs r4bs_8160_208(yy[61], yy[62], single[20], double[20], neg[20], pp_20_102); - r4bs r4bs_8160_336(yy[59], yy[60], single[21], double[21], neg[21], pp_21_102); - r4bs r4bs_8160_464(yy[57], yy[58], single[22], double[22], neg[22], pp_22_102); - fullAdd_x FA_8160_592(int_3_102, int_2_102, pp_20_102, pp_21_102, pp_22_102); - r4bs r4bs_8160_808(yy[55], yy[56], single[23], double[23], neg[23], pp_23_102); - r4bs r4bs_8160_936(yy[53], yy[54], single[24], double[24], neg[24], pp_24_102); - r4bs r4bs_8160_1064(yy[51], yy[52], single[25], double[25], neg[25], pp_25_102); - fullAdd_x FA_8160_1192(int_5_102, int_4_102, pp_23_102, pp_24_102, pp_25_102); - r4bs r4bs_8160_1408(yy[49], yy[50], single[26], double[26], neg[26], pp_26_102); - r4bs r4bs_8160_1536(yy[47], yy[48], single[27], double[27], neg[27], pp_27_102); - r4bs r4bs_8160_1664(yy[45], yy[46], single[28], double[28], neg[28], pp_28_102); - fullAdd_x FA_8160_1792(int_7_102, int_6_102, pp_26_102, pp_27_102, pp_28_102); - r4bs r4bs_8160_2008(yy[43], yy[44], single[29], double[29], neg[29], pp_29_102); - r4bs r4bs_8160_2136(yy[41], yy[42], single[30], double[30], neg[30], pp_30_102); - r4bs r4bs_8160_2264(yy[39], yy[40], single[31], double[31], neg[31], pp_31_102); - fullAdd_x FA_8160_2392(int_9_102, int_8_102, pp_29_102, pp_30_102, pp_31_102); - r4bs r4bs_8160_2608(yy[37], yy[38], single[32], double[32], neg[32], pp_32_102); - fullAdd_x FA_8160_2736(int_11_102, int_10_102, pp_32_102, int_1_101, int_3_101); - fullAdd_x FA_8160_2952(int_13_102, int_12_102, int_5_101, int_7_101, int_9_101); - fullAdd_x FA_8160_3168(int_15_102, int_14_102, int_0_102, int_11_101, int_2_102); - fullAdd_x FA_8160_3384(int_17_102, int_16_102, int_4_102, int_6_102, int_8_102); - fullAdd_x FA_8160_3600(int_19_102, int_18_102, int_13_101, int_15_101, int_17_101); - fullAdd_x FA_8160_3816(int_21_102, int_20_102, int_10_102, int_12_102, int_19_101); - fullAdd_x FA_8160_4032(int_23_102, int_22_102, int_14_102, int_16_102, int_21_101); - fullAdd_x FA_8160_4248(int_25_102, int_24_102, int_18_102, int_20_102, int_23_101); - fullAdd_x FA_8160_4464(int_27_102, int_26_102, int_22_102, int_25_101, int_24_102); - assign Sum[102] = int_27_101; - assign Carry[102] = int_26_102; - - // Hardware for column 103 - - r4bs r4bs_8240_0(yy[62], yy[63], single[20], double[20], neg[20], pp_20_103); - r4bs r4bs_8240_128(yy[60], yy[61], single[21], double[21], neg[21], pp_21_103); - fullAdd_x FA_8240_256(int_1_103, int_0_103, negbar[19], pp_20_103, pp_21_103); - r4bs r4bs_8240_472(yy[58], yy[59], single[22], double[22], neg[22], pp_22_103); - r4bs r4bs_8240_600(yy[56], yy[57], single[23], double[23], neg[23], pp_23_103); - r4bs r4bs_8240_728(yy[54], yy[55], single[24], double[24], neg[24], pp_24_103); - fullAdd_x FA_8240_856(int_3_103, int_2_103, pp_22_103, pp_23_103, pp_24_103); - r4bs r4bs_8240_1072(yy[52], yy[53], single[25], double[25], neg[25], pp_25_103); - r4bs r4bs_8240_1200(yy[50], yy[51], single[26], double[26], neg[26], pp_26_103); - r4bs r4bs_8240_1328(yy[48], yy[49], single[27], double[27], neg[27], pp_27_103); - fullAdd_x FA_8240_1456(int_5_103, int_4_103, pp_25_103, pp_26_103, pp_27_103); - r4bs r4bs_8240_1672(yy[46], yy[47], single[28], double[28], neg[28], pp_28_103); - r4bs r4bs_8240_1800(yy[44], yy[45], single[29], double[29], neg[29], pp_29_103); - r4bs r4bs_8240_1928(yy[42], yy[43], single[30], double[30], neg[30], pp_30_103); - fullAdd_x FA_8240_2056(int_7_103, int_6_103, pp_28_103, pp_29_103, pp_30_103); - r4bs r4bs_8240_2272(yy[40], yy[41], single[31], double[31], neg[31], pp_31_103); - r4bs r4bs_8240_2400(yy[38], yy[39], single[32], double[32], neg[32], pp_32_103); - fullAdd_x FA_8240_2528(int_9_103, int_8_103, pp_31_103, pp_32_103, int_1_102); - fullAdd_x FA_8240_2744(int_11_103, int_10_103, int_3_102, int_5_102, int_7_102); - fullAdd_x FA_8240_2960(int_13_103, int_12_103, int_9_102, int_11_102, int_13_102); - fullAdd_x FA_8240_3176(int_15_103, int_14_103, int_0_103, int_2_103, int_4_103); - fullAdd_x FA_8240_3392(int_17_103, int_16_103, int_6_103, int_8_103, int_15_102); - fullAdd_x FA_8240_3608(int_19_103, int_18_103, int_17_102, int_10_103, int_19_102); - fullAdd_x FA_8240_3824(int_21_103, int_20_103, int_12_103, int_14_103, int_16_103); - fullAdd_x FA_8240_4040(int_23_103, int_22_103, int_21_102, int_18_103, int_23_102); - fullAdd_x FA_8240_4256(int_25_103, int_24_103, int_20_103, int_25_102, int_22_103); - assign Sum[103] = int_27_102; - assign Carry[103] = int_24_103; - - // Hardware for column 104 - - r4bs r4bs_8320_0(yy[63], gnd, single[20], double[20], neg[20], pp_20_104); - halfAdd HA_8320_128(int_1_104, int_0_104, 1'b1, pp_20_104); - r4bs r4bs_8320_208(yy[61], yy[62], single[21], double[21], neg[21], pp_21_104); - r4bs r4bs_8320_336(yy[59], yy[60], single[22], double[22], neg[22], pp_22_104); - r4bs r4bs_8320_464(yy[57], yy[58], single[23], double[23], neg[23], pp_23_104); - fullAdd_x FA_8320_592(int_3_104, int_2_104, pp_21_104, pp_22_104, pp_23_104); - r4bs r4bs_8320_808(yy[55], yy[56], single[24], double[24], neg[24], pp_24_104); - r4bs r4bs_8320_936(yy[53], yy[54], single[25], double[25], neg[25], pp_25_104); - r4bs r4bs_8320_1064(yy[51], yy[52], single[26], double[26], neg[26], pp_26_104); - fullAdd_x FA_8320_1192(int_5_104, int_4_104, pp_24_104, pp_25_104, pp_26_104); - r4bs r4bs_8320_1408(yy[49], yy[50], single[27], double[27], neg[27], pp_27_104); - r4bs r4bs_8320_1536(yy[47], yy[48], single[28], double[28], neg[28], pp_28_104); - r4bs r4bs_8320_1664(yy[45], yy[46], single[29], double[29], neg[29], pp_29_104); - fullAdd_x FA_8320_1792(int_7_104, int_6_104, pp_27_104, pp_28_104, pp_29_104); - r4bs r4bs_8320_2008(yy[43], yy[44], single[30], double[30], neg[30], pp_30_104); - r4bs r4bs_8320_2136(yy[41], yy[42], single[31], double[31], neg[31], pp_31_104); - r4bs r4bs_8320_2264(yy[39], yy[40], single[32], double[32], neg[32], pp_32_104); - fullAdd_x FA_8320_2392(int_9_104, int_8_104, pp_30_104, pp_31_104, pp_32_104); - fullAdd_x FA_8320_2608(int_11_104, int_10_104, int_1_103, int_3_103, int_5_103); - fullAdd_x FA_8320_2824(int_13_104, int_12_104, int_7_103, int_0_104, int_9_103); - fullAdd_x FA_8320_3040(int_15_104, int_14_104, int_11_103, int_2_104, int_4_104); - fullAdd_x FA_8320_3256(int_17_104, int_16_104, int_6_104, int_8_104, int_13_103); - fullAdd_x FA_8320_3472(int_19_104, int_18_104, int_15_103, int_10_104, int_12_104); - fullAdd_x FA_8320_3688(int_21_104, int_20_104, int_17_103, int_14_104, int_16_104); - fullAdd_x FA_8320_3904(int_23_104, int_22_104, int_19_103, int_21_103, int_18_104); - fullAdd_x FA_8320_4120(int_25_104, int_24_104, int_20_104, int_23_103, int_22_104); - assign Sum[104] = int_25_103; - assign Carry[104] = int_24_104; - - // Hardware for column 105 - - r4bs r4bs_8400_0(yy[62], yy[63], single[21], double[21], neg[21], pp_21_105); - r4bs r4bs_8400_128(yy[60], yy[61], single[22], double[22], neg[22], pp_22_105); - fullAdd_x FA_8400_256(int_1_105, int_0_105, negbar[20], pp_21_105, pp_22_105); - r4bs r4bs_8400_472(yy[58], yy[59], single[23], double[23], neg[23], pp_23_105); - r4bs r4bs_8400_600(yy[56], yy[57], single[24], double[24], neg[24], pp_24_105); - r4bs r4bs_8400_728(yy[54], yy[55], single[25], double[25], neg[25], pp_25_105); - fullAdd_x FA_8400_856(int_3_105, int_2_105, pp_23_105, pp_24_105, pp_25_105); - r4bs r4bs_8400_1072(yy[52], yy[53], single[26], double[26], neg[26], pp_26_105); - r4bs r4bs_8400_1200(yy[50], yy[51], single[27], double[27], neg[27], pp_27_105); - r4bs r4bs_8400_1328(yy[48], yy[49], single[28], double[28], neg[28], pp_28_105); - fullAdd_x FA_8400_1456(int_5_105, int_4_105, pp_26_105, pp_27_105, pp_28_105); - r4bs r4bs_8400_1672(yy[46], yy[47], single[29], double[29], neg[29], pp_29_105); - r4bs r4bs_8400_1800(yy[44], yy[45], single[30], double[30], neg[30], pp_30_105); - r4bs r4bs_8400_1928(yy[42], yy[43], single[31], double[31], neg[31], pp_31_105); - fullAdd_x FA_8400_2056(int_7_105, int_6_105, pp_29_105, pp_30_105, pp_31_105); - r4bs r4bs_8400_2272(yy[40], yy[41], single[32], double[32], neg[32], pp_32_105); - fullAdd_x FA_8400_2400(int_9_105, int_8_105, pp_32_105, int_1_104, int_3_104); - fullAdd_x FA_8400_2616(int_11_105, int_10_105, int_5_104, int_7_104, int_9_104); - fullAdd_x FA_8400_2832(int_13_105, int_12_105, int_11_104, int_0_105, int_2_105); - fullAdd_x FA_8400_3048(int_15_105, int_14_105, int_4_105, int_6_105, int_13_104); - fullAdd_x FA_8400_3264(int_17_105, int_16_105, int_8_105, int_15_104, int_10_105); - fullAdd_x FA_8400_3480(int_19_105, int_18_105, int_17_104, int_19_104, int_12_105); - fullAdd_x FA_8400_3696(int_21_105, int_20_105, int_14_105, int_21_104, int_16_105); - fullAdd_x FA_8400_3912(int_23_105, int_22_105, int_23_104, int_18_105, int_20_105); - assign Sum[105] = int_25_104; - assign Carry[105] = int_22_105; - - // Hardware for column 106 - - r4bs r4bs_8480_0(yy[63], gnd, single[21], double[21], neg[21], pp_21_106); - halfAdd HA_8480_128(int_1_106, int_0_106, 1'b1, pp_21_106); - r4bs r4bs_8480_208(yy[61], yy[62], single[22], double[22], neg[22], pp_22_106); - r4bs r4bs_8480_336(yy[59], yy[60], single[23], double[23], neg[23], pp_23_106); - r4bs r4bs_8480_464(yy[57], yy[58], single[24], double[24], neg[24], pp_24_106); - fullAdd_x FA_8480_592(int_3_106, int_2_106, pp_22_106, pp_23_106, pp_24_106); - r4bs r4bs_8480_808(yy[55], yy[56], single[25], double[25], neg[25], pp_25_106); - r4bs r4bs_8480_936(yy[53], yy[54], single[26], double[26], neg[26], pp_26_106); - r4bs r4bs_8480_1064(yy[51], yy[52], single[27], double[27], neg[27], pp_27_106); - fullAdd_x FA_8480_1192(int_5_106, int_4_106, pp_25_106, pp_26_106, pp_27_106); - r4bs r4bs_8480_1408(yy[49], yy[50], single[28], double[28], neg[28], pp_28_106); - r4bs r4bs_8480_1536(yy[47], yy[48], single[29], double[29], neg[29], pp_29_106); - r4bs r4bs_8480_1664(yy[45], yy[46], single[30], double[30], neg[30], pp_30_106); - fullAdd_x FA_8480_1792(int_7_106, int_6_106, pp_28_106, pp_29_106, pp_30_106); - r4bs r4bs_8480_2008(yy[43], yy[44], single[31], double[31], neg[31], pp_31_106); - r4bs r4bs_8480_2136(yy[41], yy[42], single[32], double[32], neg[32], pp_32_106); - fullAdd_x FA_8480_2264(int_9_106, int_8_106, pp_31_106, pp_32_106, int_1_105); - fullAdd_x FA_8480_2480(int_11_106, int_10_106, int_3_105, int_5_105, int_7_105); - fullAdd_x FA_8480_2696(int_13_106, int_12_106, int_0_106, int_9_105, int_11_105); - fullAdd_x FA_8480_2912(int_15_106, int_14_106, int_2_106, int_4_106, int_6_106); - fullAdd_x FA_8480_3128(int_17_106, int_16_106, int_8_106, int_13_105, int_10_106); - fullAdd_x FA_8480_3344(int_19_106, int_18_106, int_15_105, int_17_105, int_12_106); - fullAdd_x FA_8480_3560(int_21_106, int_20_106, int_14_106, int_19_105, int_16_106); - fullAdd_x FA_8480_3776(int_23_106, int_22_106, int_21_105, int_18_106, int_20_106); - assign Sum[106] = int_23_105; - assign Carry[106] = int_22_106; - - // Hardware for column 107 - - r4bs r4bs_8560_0(yy[62], yy[63], single[22], double[22], neg[22], pp_22_107); - r4bs r4bs_8560_128(yy[60], yy[61], single[23], double[23], neg[23], pp_23_107); - fullAdd_x FA_8560_256(int_1_107, int_0_107, negbar[21], pp_22_107, pp_23_107); - r4bs r4bs_8560_472(yy[58], yy[59], single[24], double[24], neg[24], pp_24_107); - r4bs r4bs_8560_600(yy[56], yy[57], single[25], double[25], neg[25], pp_25_107); - r4bs r4bs_8560_728(yy[54], yy[55], single[26], double[26], neg[26], pp_26_107); - fullAdd_x FA_8560_856(int_3_107, int_2_107, pp_24_107, pp_25_107, pp_26_107); - r4bs r4bs_8560_1072(yy[52], yy[53], single[27], double[27], neg[27], pp_27_107); - r4bs r4bs_8560_1200(yy[50], yy[51], single[28], double[28], neg[28], pp_28_107); - r4bs r4bs_8560_1328(yy[48], yy[49], single[29], double[29], neg[29], pp_29_107); - fullAdd_x FA_8560_1456(int_5_107, int_4_107, pp_27_107, pp_28_107, pp_29_107); - r4bs r4bs_8560_1672(yy[46], yy[47], single[30], double[30], neg[30], pp_30_107); - r4bs r4bs_8560_1800(yy[44], yy[45], single[31], double[31], neg[31], pp_31_107); - r4bs r4bs_8560_1928(yy[42], yy[43], single[32], double[32], neg[32], pp_32_107); - fullAdd_x FA_8560_2056(int_7_107, int_6_107, pp_30_107, pp_31_107, pp_32_107); - fullAdd_x FA_8560_2272(int_9_107, int_8_107, int_1_106, int_3_106, int_5_106); - fullAdd_x FA_8560_2488(int_11_107, int_10_107, int_7_106, int_9_106, int_11_106); - fullAdd_x FA_8560_2704(int_13_107, int_12_107, int_0_107, int_2_107, int_4_107); - fullAdd_x FA_8560_2920(int_15_107, int_14_107, int_6_107, int_13_106, int_15_106); - fullAdd_x FA_8560_3136(int_17_107, int_16_107, int_8_107, int_17_106, int_10_107); - fullAdd_x FA_8560_3352(int_19_107, int_18_107, int_12_107, int_19_106, int_14_107); - fullAdd_x FA_8560_3568(int_21_107, int_20_107, int_21_106, int_16_107, int_18_107); - assign Sum[107] = int_23_106; - assign Carry[107] = int_20_107; - - // Hardware for column 108 - - r4bs r4bs_8640_0(yy[63], gnd, single[22], double[22], neg[22], pp_22_108); - halfAdd HA_8640_128(int_1_108, int_0_108, 1'b1, pp_22_108); - r4bs r4bs_8640_208(yy[61], yy[62], single[23], double[23], neg[23], pp_23_108); - r4bs r4bs_8640_336(yy[59], yy[60], single[24], double[24], neg[24], pp_24_108); - r4bs r4bs_8640_464(yy[57], yy[58], single[25], double[25], neg[25], pp_25_108); - fullAdd_x FA_8640_592(int_3_108, int_2_108, pp_23_108, pp_24_108, pp_25_108); - r4bs r4bs_8640_808(yy[55], yy[56], single[26], double[26], neg[26], pp_26_108); - r4bs r4bs_8640_936(yy[53], yy[54], single[27], double[27], neg[27], pp_27_108); - r4bs r4bs_8640_1064(yy[51], yy[52], single[28], double[28], neg[28], pp_28_108); - fullAdd_x FA_8640_1192(int_5_108, int_4_108, pp_26_108, pp_27_108, pp_28_108); - r4bs r4bs_8640_1408(yy[49], yy[50], single[29], double[29], neg[29], pp_29_108); - r4bs r4bs_8640_1536(yy[47], yy[48], single[30], double[30], neg[30], pp_30_108); - r4bs r4bs_8640_1664(yy[45], yy[46], single[31], double[31], neg[31], pp_31_108); - fullAdd_x FA_8640_1792(int_7_108, int_6_108, pp_29_108, pp_30_108, pp_31_108); - r4bs r4bs_8640_2008(yy[43], yy[44], single[32], double[32], neg[32], pp_32_108); - fullAdd_x FA_8640_2136(int_9_108, int_8_108, pp_32_108, int_1_107, int_3_107); - fullAdd_x FA_8640_2352(int_11_108, int_10_108, int_5_107, int_7_107, int_0_108); - fullAdd_x FA_8640_2568(int_13_108, int_12_108, int_9_107, int_2_108, int_4_108); - fullAdd_x FA_8640_2784(int_15_108, int_14_108, int_6_108, int_11_107, int_13_107); - fullAdd_x FA_8640_3000(int_17_108, int_16_108, int_8_108, int_10_108, int_15_107); - fullAdd_x FA_8640_3216(int_19_108, int_18_108, int_12_108, int_17_107, int_14_108); - fullAdd_x FA_8640_3432(int_21_108, int_20_108, int_16_108, int_19_107, int_18_108); - assign Sum[108] = int_21_107; - assign Carry[108] = int_20_108; - - // Hardware for column 109 - - r4bs r4bs_8720_0(yy[62], yy[63], single[23], double[23], neg[23], pp_23_109); - r4bs r4bs_8720_128(yy[60], yy[61], single[24], double[24], neg[24], pp_24_109); - fullAdd_x FA_8720_256(int_1_109, int_0_109, negbar[22], pp_23_109, pp_24_109); - r4bs r4bs_8720_472(yy[58], yy[59], single[25], double[25], neg[25], pp_25_109); - r4bs r4bs_8720_600(yy[56], yy[57], single[26], double[26], neg[26], pp_26_109); - r4bs r4bs_8720_728(yy[54], yy[55], single[27], double[27], neg[27], pp_27_109); - fullAdd_x FA_8720_856(int_3_109, int_2_109, pp_25_109, pp_26_109, pp_27_109); - r4bs r4bs_8720_1072(yy[52], yy[53], single[28], double[28], neg[28], pp_28_109); - r4bs r4bs_8720_1200(yy[50], yy[51], single[29], double[29], neg[29], pp_29_109); - r4bs r4bs_8720_1328(yy[48], yy[49], single[30], double[30], neg[30], pp_30_109); - fullAdd_x FA_8720_1456(int_5_109, int_4_109, pp_28_109, pp_29_109, pp_30_109); - r4bs r4bs_8720_1672(yy[46], yy[47], single[31], double[31], neg[31], pp_31_109); - r4bs r4bs_8720_1800(yy[44], yy[45], single[32], double[32], neg[32], pp_32_109); - fullAdd_x FA_8720_1928(int_7_109, int_6_109, pp_31_109, pp_32_109, int_1_108); - fullAdd_x FA_8720_2144(int_9_109, int_8_109, int_3_108, int_5_108, int_7_108); - fullAdd_x FA_8720_2360(int_11_109, int_10_109, int_9_108, int_11_108, int_0_109); - fullAdd_x FA_8720_2576(int_13_109, int_12_109, int_2_109, int_4_109, int_6_109); - fullAdd_x FA_8720_2792(int_15_109, int_14_109, int_13_108, int_8_109, int_15_108); - fullAdd_x FA_8720_3008(int_17_109, int_16_109, int_10_109, int_12_109, int_17_108); - fullAdd_x FA_8720_3224(int_19_109, int_18_109, int_14_109, int_19_108, int_16_109); - assign Sum[109] = int_21_108; - assign Carry[109] = int_18_109; - - // Hardware for column 110 - - r4bs r4bs_8800_0(yy[63], gnd, single[23], double[23], neg[23], pp_23_110); - halfAdd HA_8800_128(int_1_110, int_0_110, 1'b1, pp_23_110); - r4bs r4bs_8800_208(yy[61], yy[62], single[24], double[24], neg[24], pp_24_110); - r4bs r4bs_8800_336(yy[59], yy[60], single[25], double[25], neg[25], pp_25_110); - r4bs r4bs_8800_464(yy[57], yy[58], single[26], double[26], neg[26], pp_26_110); - fullAdd_x FA_8800_592(int_3_110, int_2_110, pp_24_110, pp_25_110, pp_26_110); - r4bs r4bs_8800_808(yy[55], yy[56], single[27], double[27], neg[27], pp_27_110); - r4bs r4bs_8800_936(yy[53], yy[54], single[28], double[28], neg[28], pp_28_110); - r4bs r4bs_8800_1064(yy[51], yy[52], single[29], double[29], neg[29], pp_29_110); - fullAdd_x FA_8800_1192(int_5_110, int_4_110, pp_27_110, pp_28_110, pp_29_110); - r4bs r4bs_8800_1408(yy[49], yy[50], single[30], double[30], neg[30], pp_30_110); - r4bs r4bs_8800_1536(yy[47], yy[48], single[31], double[31], neg[31], pp_31_110); - r4bs r4bs_8800_1664(yy[45], yy[46], single[32], double[32], neg[32], pp_32_110); - fullAdd_x FA_8800_1792(int_7_110, int_6_110, pp_30_110, pp_31_110, pp_32_110); - fullAdd_x FA_8800_2008(int_9_110, int_8_110, int_1_109, int_3_109, int_5_109); - fullAdd_x FA_8800_2224(int_11_110, int_10_110, int_0_110, int_7_109, int_9_109); - fullAdd_x FA_8800_2440(int_13_110, int_12_110, int_2_110, int_4_110, int_6_110); - fullAdd_x FA_8800_2656(int_15_110, int_14_110, int_11_109, int_13_109, int_8_110); - fullAdd_x FA_8800_2872(int_17_110, int_16_110, int_10_110, int_12_110, int_15_109); - fullAdd_x FA_8800_3088(int_19_110, int_18_110, int_14_110, int_17_109, int_16_110); - assign Sum[110] = int_19_109; - assign Carry[110] = int_18_110; - - // Hardware for column 111 - - r4bs r4bs_8880_0(yy[62], yy[63], single[24], double[24], neg[24], pp_24_111); - r4bs r4bs_8880_128(yy[60], yy[61], single[25], double[25], neg[25], pp_25_111); - fullAdd_x FA_8880_256(int_1_111, int_0_111, negbar[23], pp_24_111, pp_25_111); - r4bs r4bs_8880_472(yy[58], yy[59], single[26], double[26], neg[26], pp_26_111); - r4bs r4bs_8880_600(yy[56], yy[57], single[27], double[27], neg[27], pp_27_111); - r4bs r4bs_8880_728(yy[54], yy[55], single[28], double[28], neg[28], pp_28_111); - fullAdd_x FA_8880_856(int_3_111, int_2_111, pp_26_111, pp_27_111, pp_28_111); - r4bs r4bs_8880_1072(yy[52], yy[53], single[29], double[29], neg[29], pp_29_111); - r4bs r4bs_8880_1200(yy[50], yy[51], single[30], double[30], neg[30], pp_30_111); - r4bs r4bs_8880_1328(yy[48], yy[49], single[31], double[31], neg[31], pp_31_111); - fullAdd_x FA_8880_1456(int_5_111, int_4_111, pp_29_111, pp_30_111, pp_31_111); - r4bs r4bs_8880_1672(yy[46], yy[47], single[32], double[32], neg[32], pp_32_111); - fullAdd_x FA_8880_1800(int_7_111, int_6_111, pp_32_111, int_1_110, int_3_110); - fullAdd_x FA_8880_2016(int_9_111, int_8_111, int_5_110, int_7_110, int_9_110); - fullAdd_x FA_8880_2232(int_11_111, int_10_111, int_0_111, int_2_111, int_4_111); - fullAdd_x FA_8880_2448(int_13_111, int_12_111, int_6_111, int_11_110, int_13_110); - fullAdd_x FA_8880_2664(int_15_111, int_14_111, int_8_111, int_15_110, int_10_111); - fullAdd_x FA_8880_2880(int_17_111, int_16_111, int_12_111, int_17_110, int_14_111); - assign Sum[111] = int_19_110; - assign Carry[111] = int_16_111; - - // Hardware for column 112 - - r4bs r4bs_8960_0(yy[63], gnd, single[24], double[24], neg[24], pp_24_112); - halfAdd HA_8960_128(int_1_112, int_0_112, 1'b1, pp_24_112); - r4bs r4bs_8960_208(yy[61], yy[62], single[25], double[25], neg[25], pp_25_112); - r4bs r4bs_8960_336(yy[59], yy[60], single[26], double[26], neg[26], pp_26_112); - r4bs r4bs_8960_464(yy[57], yy[58], single[27], double[27], neg[27], pp_27_112); - fullAdd_x FA_8960_592(int_3_112, int_2_112, pp_25_112, pp_26_112, pp_27_112); - r4bs r4bs_8960_808(yy[55], yy[56], single[28], double[28], neg[28], pp_28_112); - r4bs r4bs_8960_936(yy[53], yy[54], single[29], double[29], neg[29], pp_29_112); - r4bs r4bs_8960_1064(yy[51], yy[52], single[30], double[30], neg[30], pp_30_112); - fullAdd_x FA_8960_1192(int_5_112, int_4_112, pp_28_112, pp_29_112, pp_30_112); - r4bs r4bs_8960_1408(yy[49], yy[50], single[31], double[31], neg[31], pp_31_112); - r4bs r4bs_8960_1536(yy[47], yy[48], single[32], double[32], neg[32], pp_32_112); - fullAdd_x FA_8960_1664(int_7_112, int_6_112, pp_31_112, pp_32_112, int_1_111); - fullAdd_x FA_8960_1880(int_9_112, int_8_112, int_3_111, int_5_111, int_0_112); - fullAdd_x FA_8960_2096(int_11_112, int_10_112, int_7_111, int_2_112, int_4_112); - fullAdd_x FA_8960_2312(int_13_112, int_12_112, int_6_112, int_9_111, int_11_111); - fullAdd_x FA_8960_2528(int_15_112, int_14_112, int_8_112, int_13_111, int_10_112); - fullAdd_x FA_8960_2744(int_17_112, int_16_112, int_15_111, int_12_112, int_14_112); - assign Sum[112] = int_17_111; - assign Carry[112] = int_16_112; - - // Hardware for column 113 - - r4bs r4bs_9040_0(yy[62], yy[63], single[25], double[25], neg[25], pp_25_113); - r4bs r4bs_9040_128(yy[60], yy[61], single[26], double[26], neg[26], pp_26_113); - fullAdd_x FA_9040_256(int_1_113, int_0_113, negbar[24], pp_25_113, pp_26_113); - r4bs r4bs_9040_472(yy[58], yy[59], single[27], double[27], neg[27], pp_27_113); - r4bs r4bs_9040_600(yy[56], yy[57], single[28], double[28], neg[28], pp_28_113); - r4bs r4bs_9040_728(yy[54], yy[55], single[29], double[29], neg[29], pp_29_113); - fullAdd_x FA_9040_856(int_3_113, int_2_113, pp_27_113, pp_28_113, pp_29_113); - r4bs r4bs_9040_1072(yy[52], yy[53], single[30], double[30], neg[30], pp_30_113); - r4bs r4bs_9040_1200(yy[50], yy[51], single[31], double[31], neg[31], pp_31_113); - r4bs r4bs_9040_1328(yy[48], yy[49], single[32], double[32], neg[32], pp_32_113); - fullAdd_x FA_9040_1456(int_5_113, int_4_113, pp_30_113, pp_31_113, pp_32_113); - fullAdd_x FA_9040_1672(int_7_113, int_6_113, int_1_112, int_3_112, int_5_112); - fullAdd_x FA_9040_1888(int_9_113, int_8_113, int_7_112, int_9_112, int_0_113); - fullAdd_x FA_9040_2104(int_11_113, int_10_113, int_2_113, int_4_113, int_11_112); - fullAdd_x FA_9040_2320(int_13_113, int_12_113, int_6_113, int_13_112, int_8_113); - fullAdd_x FA_9040_2536(int_15_113, int_14_113, int_10_113, int_15_112, int_12_113); - assign Sum[113] = int_17_112; - assign Carry[113] = int_14_113; - - // Hardware for column 114 - - r4bs r4bs_9120_0(yy[63], gnd, single[25], double[25], neg[25], pp_25_114); - halfAdd HA_9120_128(int_1_114, int_0_114, 1'b1, pp_25_114); - r4bs r4bs_9120_208(yy[61], yy[62], single[26], double[26], neg[26], pp_26_114); - r4bs r4bs_9120_336(yy[59], yy[60], single[27], double[27], neg[27], pp_27_114); - r4bs r4bs_9120_464(yy[57], yy[58], single[28], double[28], neg[28], pp_28_114); - fullAdd_x FA_9120_592(int_3_114, int_2_114, pp_26_114, pp_27_114, pp_28_114); - r4bs r4bs_9120_808(yy[55], yy[56], single[29], double[29], neg[29], pp_29_114); - r4bs r4bs_9120_936(yy[53], yy[54], single[30], double[30], neg[30], pp_30_114); - r4bs r4bs_9120_1064(yy[51], yy[52], single[31], double[31], neg[31], pp_31_114); - fullAdd_x FA_9120_1192(int_5_114, int_4_114, pp_29_114, pp_30_114, pp_31_114); - r4bs r4bs_9120_1408(yy[49], yy[50], single[32], double[32], neg[32], pp_32_114); - fullAdd_x FA_9120_1536(int_7_114, int_6_114, pp_32_114, int_1_113, int_3_113); - fullAdd_x FA_9120_1752(int_9_114, int_8_114, int_5_113, int_0_114, int_7_113); - fullAdd_x FA_9120_1968(int_11_114, int_10_114, int_2_114, int_4_114, int_9_113); - fullAdd_x FA_9120_2184(int_13_114, int_12_114, int_6_114, int_8_114, int_11_113); - fullAdd_x FA_9120_2400(int_15_114, int_14_114, int_10_114, int_13_113, int_12_114); - assign Sum[114] = int_15_113; - assign Carry[114] = int_14_114; - - // Hardware for column 115 - - r4bs r4bs_9200_0(yy[62], yy[63], single[26], double[26], neg[26], pp_26_115); - r4bs r4bs_9200_128(yy[60], yy[61], single[27], double[27], neg[27], pp_27_115); - fullAdd_x FA_9200_256(int_1_115, int_0_115, negbar[25], pp_26_115, pp_27_115); - r4bs r4bs_9200_472(yy[58], yy[59], single[28], double[28], neg[28], pp_28_115); - r4bs r4bs_9200_600(yy[56], yy[57], single[29], double[29], neg[29], pp_29_115); - r4bs r4bs_9200_728(yy[54], yy[55], single[30], double[30], neg[30], pp_30_115); - fullAdd_x FA_9200_856(int_3_115, int_2_115, pp_28_115, pp_29_115, pp_30_115); - r4bs r4bs_9200_1072(yy[52], yy[53], single[31], double[31], neg[31], pp_31_115); - r4bs r4bs_9200_1200(yy[50], yy[51], single[32], double[32], neg[32], pp_32_115); - fullAdd_x FA_9200_1328(int_5_115, int_4_115, pp_31_115, pp_32_115, int_1_114); - fullAdd_x FA_9200_1544(int_7_115, int_6_115, int_3_114, int_5_114, int_7_114); - fullAdd_x FA_9200_1760(int_9_115, int_8_115, int_0_115, int_2_115, int_4_115); - fullAdd_x FA_9200_1976(int_11_115, int_10_115, int_9_114, int_6_115, int_11_114); - fullAdd_x FA_9200_2192(int_13_115, int_12_115, int_8_115, int_13_114, int_10_115); - assign Sum[115] = int_15_114; - assign Carry[115] = int_12_115; - - // Hardware for column 116 - - r4bs r4bs_9280_0(yy[63], gnd, single[26], double[26], neg[26], pp_26_116); - halfAdd HA_9280_128(int_1_116, int_0_116, 1'b1, pp_26_116); - r4bs r4bs_9280_208(yy[61], yy[62], single[27], double[27], neg[27], pp_27_116); - r4bs r4bs_9280_336(yy[59], yy[60], single[28], double[28], neg[28], pp_28_116); - r4bs r4bs_9280_464(yy[57], yy[58], single[29], double[29], neg[29], pp_29_116); - fullAdd_x FA_9280_592(int_3_116, int_2_116, pp_27_116, pp_28_116, pp_29_116); - r4bs r4bs_9280_808(yy[55], yy[56], single[30], double[30], neg[30], pp_30_116); - r4bs r4bs_9280_936(yy[53], yy[54], single[31], double[31], neg[31], pp_31_116); - r4bs r4bs_9280_1064(yy[51], yy[52], single[32], double[32], neg[32], pp_32_116); - fullAdd_x FA_9280_1192(int_5_116, int_4_116, pp_30_116, pp_31_116, pp_32_116); - fullAdd_x FA_9280_1408(int_7_116, int_6_116, int_1_115, int_3_115, int_0_116); - fullAdd_x FA_9280_1624(int_9_116, int_8_116, int_5_115, int_2_116, int_4_116); - fullAdd_x FA_9280_1840(int_11_116, int_10_116, int_7_115, int_9_115, int_6_116); - fullAdd_x FA_9280_2056(int_13_116, int_12_116, int_8_116, int_11_115, int_10_116); - assign Sum[116] = int_13_115; - assign Carry[116] = int_12_116; - - // Hardware for column 117 - - r4bs r4bs_9360_0(yy[62], yy[63], single[27], double[27], neg[27], pp_27_117); - r4bs r4bs_9360_128(yy[60], yy[61], single[28], double[28], neg[28], pp_28_117); - fullAdd_x FA_9360_256(int_1_117, int_0_117, negbar[26], pp_27_117, pp_28_117); - r4bs r4bs_9360_472(yy[58], yy[59], single[29], double[29], neg[29], pp_29_117); - r4bs r4bs_9360_600(yy[56], yy[57], single[30], double[30], neg[30], pp_30_117); - r4bs r4bs_9360_728(yy[54], yy[55], single[31], double[31], neg[31], pp_31_117); - fullAdd_x FA_9360_856(int_3_117, int_2_117, pp_29_117, pp_30_117, pp_31_117); - r4bs r4bs_9360_1072(yy[52], yy[53], single[32], double[32], neg[32], pp_32_117); - fullAdd_x FA_9360_1200(int_5_117, int_4_117, pp_32_117, int_1_116, int_3_116); - fullAdd_x FA_9360_1416(int_7_117, int_6_117, int_5_116, int_7_116, int_0_117); - fullAdd_x FA_9360_1632(int_9_117, int_8_117, int_2_117, int_4_117, int_9_116); - fullAdd_x FA_9360_1848(int_11_117, int_10_117, int_11_116, int_6_117, int_8_117); - assign Sum[117] = int_13_116; - assign Carry[117] = int_10_117; - - // Hardware for column 118 - - r4bs r4bs_9440_0(yy[63], gnd, single[27], double[27], neg[27], pp_27_118); - halfAdd HA_9440_128(int_1_118, int_0_118, 1'b1, pp_27_118); - r4bs r4bs_9440_208(yy[61], yy[62], single[28], double[28], neg[28], pp_28_118); - r4bs r4bs_9440_336(yy[59], yy[60], single[29], double[29], neg[29], pp_29_118); - r4bs r4bs_9440_464(yy[57], yy[58], single[30], double[30], neg[30], pp_30_118); - fullAdd_x FA_9440_592(int_3_118, int_2_118, pp_28_118, pp_29_118, pp_30_118); - r4bs r4bs_9440_808(yy[55], yy[56], single[31], double[31], neg[31], pp_31_118); - r4bs r4bs_9440_936(yy[53], yy[54], single[32], double[32], neg[32], pp_32_118); - fullAdd_x FA_9440_1064(int_5_118, int_4_118, pp_31_118, pp_32_118, int_1_117); - fullAdd_x FA_9440_1280(int_7_118, int_6_118, int_3_117, int_0_118, int_5_117); - fullAdd_x FA_9440_1496(int_9_118, int_8_118, int_2_118, int_4_118, int_7_117); - fullAdd_x FA_9440_1712(int_11_118, int_10_118, int_6_118, int_9_117, int_8_118); - assign Sum[118] = int_11_117; - assign Carry[118] = int_10_118; - - // Hardware for column 119 - - r4bs r4bs_9520_0(yy[62], yy[63], single[28], double[28], neg[28], pp_28_119); - r4bs r4bs_9520_128(yy[60], yy[61], single[29], double[29], neg[29], pp_29_119); - fullAdd_x FA_9520_256(int_1_119, int_0_119, negbar[27], pp_28_119, pp_29_119); - r4bs r4bs_9520_472(yy[58], yy[59], single[30], double[30], neg[30], pp_30_119); - r4bs r4bs_9520_600(yy[56], yy[57], single[31], double[31], neg[31], pp_31_119); - r4bs r4bs_9520_728(yy[54], yy[55], single[32], double[32], neg[32], pp_32_119); - fullAdd_x FA_9520_856(int_3_119, int_2_119, pp_30_119, pp_31_119, pp_32_119); - fullAdd_x FA_9520_1072(int_5_119, int_4_119, int_1_118, int_3_118, int_5_118); - fullAdd_x FA_9520_1288(int_7_119, int_6_119, int_0_119, int_2_119, int_7_118); - fullAdd_x FA_9520_1504(int_9_119, int_8_119, int_4_119, int_9_118, int_6_119); - assign Sum[119] = int_11_118; - assign Carry[119] = int_8_119; - - // Hardware for column 120 - - r4bs r4bs_9600_0(yy[63], gnd, single[28], double[28], neg[28], pp_28_120); - halfAdd HA_9600_128(int_1_120, int_0_120, 1'b1, pp_28_120); - r4bs r4bs_9600_208(yy[61], yy[62], single[29], double[29], neg[29], pp_29_120); - r4bs r4bs_9600_336(yy[59], yy[60], single[30], double[30], neg[30], pp_30_120); - r4bs r4bs_9600_464(yy[57], yy[58], single[31], double[31], neg[31], pp_31_120); - fullAdd_x FA_9600_592(int_3_120, int_2_120, pp_29_120, pp_30_120, pp_31_120); - r4bs r4bs_9600_808(yy[55], yy[56], single[32], double[32], neg[32], pp_32_120); - fullAdd_x FA_9600_936(int_5_120, int_4_120, pp_32_120, int_1_119, int_3_119); - fullAdd_x FA_9600_1152(int_7_120, int_6_120, int_0_120, int_2_120, int_5_119); - fullAdd_x FA_9600_1368(int_9_120, int_8_120, int_4_120, int_7_119, int_6_120); - assign Sum[120] = int_9_119; - assign Carry[120] = int_8_120; - - // Hardware for column 121 - - r4bs r4bs_9680_0(yy[62], yy[63], single[29], double[29], neg[29], pp_29_121); - r4bs r4bs_9680_128(yy[60], yy[61], single[30], double[30], neg[30], pp_30_121); - fullAdd_x FA_9680_256(int_1_121, int_0_121, negbar[28], pp_29_121, pp_30_121); - r4bs r4bs_9680_472(yy[58], yy[59], single[31], double[31], neg[31], pp_31_121); - r4bs r4bs_9680_600(yy[56], yy[57], single[32], double[32], neg[32], pp_32_121); - fullAdd_x FA_9680_728(int_3_121, int_2_121, pp_31_121, pp_32_121, int_1_120); - fullAdd_x FA_9680_944(int_5_121, int_4_121, int_3_120, int_5_120, int_0_121); - fullAdd_x FA_9680_1160(int_7_121, int_6_121, int_2_121, int_7_120, int_4_121); - assign Sum[121] = int_9_120; - assign Carry[121] = int_6_121; - - // Hardware for column 122 - - r4bs r4bs_9760_0(yy[63], gnd, single[29], double[29], neg[29], pp_29_122); - halfAdd HA_9760_128(int_1_122, int_0_122, 1'b1, pp_29_122); - r4bs r4bs_9760_208(yy[61], yy[62], single[30], double[30], neg[30], pp_30_122); - r4bs r4bs_9760_336(yy[59], yy[60], single[31], double[31], neg[31], pp_31_122); - r4bs r4bs_9760_464(yy[57], yy[58], single[32], double[32], neg[32], pp_32_122); - fullAdd_x FA_9760_592(int_3_122, int_2_122, pp_30_122, pp_31_122, pp_32_122); - fullAdd_x FA_9760_808(int_5_122, int_4_122, int_1_121, int_0_122, int_3_121); - fullAdd_x FA_9760_1024(int_7_122, int_6_122, int_2_122, int_5_121, int_4_122); - assign Sum[122] = int_7_121; - assign Carry[122] = int_6_122; - - // Hardware for column 123 - - r4bs r4bs_9840_0(yy[62], yy[63], single[30], double[30], neg[30], pp_30_123); - r4bs r4bs_9840_128(yy[60], yy[61], single[31], double[31], neg[31], pp_31_123); - fullAdd_x FA_9840_256(int_1_123, int_0_123, negbar[29], pp_30_123, pp_31_123); - r4bs r4bs_9840_472(yy[58], yy[59], single[32], double[32], neg[32], pp_32_123); - fullAdd_x FA_9840_600(int_3_123, int_2_123, pp_32_123, int_1_122, int_3_122); - fullAdd_x FA_9840_816(int_5_123, int_4_123, int_0_123, int_5_122, int_2_123); - assign Sum[123] = int_7_122; - assign Carry[123] = int_4_123; - - // Hardware for column 124 - - r4bs r4bs_9920_0(yy[63], gnd, single[30], double[30], neg[30], pp_30_124); - halfAdd HA_9920_128(int_1_124, int_0_124, 1'b1, pp_30_124); - r4bs r4bs_9920_208(yy[61], yy[62], single[31], double[31], neg[31], pp_31_124); - r4bs r4bs_9920_336(yy[59], yy[60], single[32], double[32], neg[32], pp_32_124); - fullAdd_x FA_9920_464(int_3_124, int_2_124, pp_31_124, pp_32_124, int_1_123); - fullAdd_x FA_9920_680(int_5_124, int_4_124, int_0_124, int_3_123, int_2_124); - assign Sum[124] = int_5_123; - assign Carry[124] = int_4_124; - - // Hardware for column 125 - - r4bs r4bs_10000_0(yy[62], yy[63], single[31], double[31], neg[31], pp_31_125); - r4bs r4bs_10000_128(yy[60], yy[61], single[32], double[32], neg[32], pp_32_125); - fullAdd_x FA_10000_256(int_1_125, int_0_125, negbar[30], pp_31_125, pp_32_125); - fullAdd_x FA_10000_472(int_3_125, int_2_125, int_1_124, int_3_124, int_0_125); - assign Sum[125] = int_5_124; - assign Carry[125] = int_2_125; - - // Hardware for column 126 - - r4bs r4bs_10080_0(yy[63], gnd, single[31], double[31], neg[31], pp_31_126); - halfAdd HA_10080_128(int_1_126, int_0_126, 1'b1, pp_31_126); - r4bs r4bs_10080_208(yy[61], yy[62], single[32], double[32], neg[32], pp_32_126); - fullAdd_x FA_10080_336(int_3_126, int_2_126, pp_32_126, int_1_125, int_0_126); - assign Sum[126] = int_3_125; - assign Carry[126] = int_2_126; - - // Hardware for column 127 - - r4bs r4bs_10160_0(yy[62], yy[63], single[32], double[32], neg[32], pp_32_127); - xor3 xor_10160_128(negbar[31], pp_32_127, int_1_126, int_0_127); - assign Sum[127] = int_3_126; - assign Carry[127] = int_0_127; - -endmodule // multiplier - -// Extra Modules - -module aaoi(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = !(in1&in2) & !(in3&in4); - -endmodule // aaoi - - -module halfAdd(cout,s,a,b); - - output cout; - output s; - input a; - input b; - - and2 carryComp0_0(cout,a,b); - xor2 sumComp_0_40(a,b,s); - -endmodule // halfAdd - - -// booth_encoder_r4 takes in X[2:0], which corresponds to X_(2n-1) to X_(2n+1) -// it outputs control signals to a Booth selector that cause the selector to -// send out the correct partial product - -module r4bs(y1,y0,sing,doub,neg,pp); - - input y1; - input y0; - input sing; - input doub; - input neg; - output pp; - - wire aaoiRes; - - aaoi usppgen_0_0(aaoiRes,doub,y1,sing,y0); - xnor2 ppinverter_0_40(aaoiRes,neg,pp); - -endmodule // r4bs - - -module r4be(x0,x1,x2,sing,doub,neg); - - input x0; - input x1; - input x2; - output sing; - output doub; - output neg; - - wire singRes; - wire doubRes; - - wire x0b; - wire x1b; - wire x2b; - - wire nandaRes; - wire nandbRes; - - assign neg = x2; - assign sing = x0^x1; - assign x0b = ~x0; - assign x1b = ~x1; - assign x2b = ~x2; - - // Nand structure = see Bewick - assign nandaRes = ~(x0 & x1 & x2b); - assign nandbRes = ~(x0b & x1b & x2); - assign doub = ~(nandaRes & nandbRes); - -endmodule // r4be - - -// Use maj and two xor2's, with cin being late -module fullAdd_xc(cout, s, a, b, cin); - - output cout; - output s; - input a; - input b; - input cin; - - wire xorRes; - - xor2 XOR1_0_0(a,b,xorRes); - xor2 XOR2_0_56(xorRes,cin,s); - maj MAJ_0_112(cout,a,b,cin); - -endmodule // fullAdd_xc - - -module maj(y, a, b, c); - - output y; - input a; - input b; - input c; - - wire min; - - min mincomp_0_0(min,a,b,c); - inverter outinv_0_32(y,min); - -endmodule // maj - -// 4:2 Weinberger compressor -module fourtwo_x(t, S, C, X, Y, Z, W, t_1); - - output t;//fast cout - output S; - output C;//slow cout - - input X;//two xor delays to s - input Y;//three xor delays to s - input Z;//three xor delays to s - input W;//two xor delays to s - input t_1;//two xor delayts to s - - wire intermediate; - - fullAdd_xc firstCSA_0_0(t,intermediate,Y,Z,X); - fullAdd_xc secondCSA_0_160(C,S,W,t_1,intermediate); - -endmodule // fourtwo_x - -module inverter(egress, in); - - output egress; - input in; - - assign egress = ~in; - -endmodule // inverter - -module buffer(egress, in); - - output egress; - input in; - - assign egress = in; - -endmodule // buffer - -module subxor(egress,in1,in1_b,in2,in2_b); - - output egress; - input in1; - input in1_b; - input in2; - input in2_b; - - assign egress = (~(in2_b&in1_b)) & (~(in2&in1)); - -endmodule // subxor - -module xnor2(a,b,y); - input a; - input b; - output y; - - assign y = ~(a^b); - -endmodule // xnor2 - -module xor2(a,b,y); - input a; - input b; - output y; - - wire a_b; - wire b_b; - - - inverter inva_0_0(a_b,a); - inverter invb_0_16(b_b,b); - - subxor sub_0_32(y,a,a_b,b,b_b); - -endmodule // xor2 - -module xor3(a,b,c,y); - - input a; - input b; - input c; - output y; - - assign y = a^b^c; - -endmodule // xor3 - -module xor3c(egress,in1,in2,in3,in4,in5,in6); - - output egress; - input in1; - input in2; - input in3; - input in4; - input in5; - input in6; - - assign egress = (~in6&~in4&~in2) | (~in5&~in3&~in2) | (~in5&~in4&~in1) | - (~in6&~in3&~in1); - -endmodule // xor3c - -module fullAdd_x(cout,sum,a,b,c); - - output cout; - output sum; - input a; - input b; - input c; - - wire ab; - wire bb; - wire cb; - - inverter ainv_0_0(ab,a); - inverter binv_0_16(bb,b); - inverter cinv_0_32(cb,c); - - xor3c sumcomp_0_48(sum,a,ab,b,bb,c,cb); - maj majcomp_0_144(cout,a,b,c); - -endmodule // fullAdd_x - -module nand2(egress,in1,in2); - - output egress; - input in1; - input in2; - - assign egress = ~(in1&in2); - -endmodule // nand2 - -module nand3(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - wire a,b; - - assign egress = ~(in1&in2&in3); - -endmodule // nand3 - -module and3(y,a,b,c); - - output y; - input a; - input b; - input c; - - assign y = a&b&c; - -endmodule // and3 - -module and2(y,a,b); - - output y; - input a; - input b; - - assign y = a&b; - -endmodule // and2 - -module nor2(egress,in1,in2); - - output egress; - input in1; - input in2; - - assign egress = ~(in1|in2); - -endmodule // nor2 - -module or2(y,a,b); - - output y; - input a; - input b; - - assign y = a|b; - -endmodule // or2 - -module nor3(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in1|in2|in3); - -endmodule // nor3 - -module nand5(egress,in1,in2,in3,in4,in5); - - output egress; - input in1; - input in2; - input in3; - input in4; - input in5; - - assign egress = ~(in1&in2&in3&in4&in5); - -endmodule // nand5 - -module and5(y,a,b,c,d,e); - - output y; - input a; - input b; - input c; - input d; - input e; - - assign y = a&b&c&d&e; - -endmodule // and5 - -module nand4(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = ~(in1&in2&in3&in4); - -endmodule // nand4 - -module and4(y,a,b,c,d); - - output y; - input a; - input b; - input c; - input d; - - assign y = a&b&c&d; - -endmodule // and4 - -module oai(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in3 & (in1|in2)); - -endmodule // oai - -module aoi(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in3 | (in1&in2)); - -endmodule // aoi - -module min(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~in3&~in2 | ~in3&~in1 | ~in2&~in1; - -endmodule // min - -module sum_b(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = ~in4&(~(in3&in2&in1)) | ~(in3|in2|in1); - -endmodule // sum_b - -module fullAdd_i(cout_b,sum_b,a,b,c); - - output cout_b; - output sum_b; - input a; - input b; - input c; - - min carry_0_0(cout_b,a,b,c); - sum_b sum_0_32(sum_b,a,b,c,cout_b); - -endmodule // fullAdd_i - -module fullAdd(cout,s,a,b,c); - - output cout; - output s; - input a; - input b; - input c; - wire cout_b; - wire sum_b; - - fullAdd_i adder_0_0(cout_b,sum_b,a,b,c); - inverter couti_0_96(cout,cout_b); - inverter sumi_0_112(s,sum_b); - -endmodule // fullAdd - -module blackCell(g_i_j, p_i_j, g_i_k, p_i_k, g_kneg1_j, p_kneg1_j); - - output g_i_j; - output p_i_j; - input g_i_k; - input p_i_k; - input g_kneg1_j; - input p_kneg1_j; - - grayCell grayCell_0_0(g_i_j, g_i_k, p_i_k, g_kneg1_j); - and2 and_0_48(p_i_j, p_i_k, p_kneg1_j); - -endmodule // blackCell - -module grayCell(g_i_j, g_i_k, p_i_k, g_kneg1_j); - - output g_i_j; - input g_i_k; - input p_i_k; - input g_kneg1_j; - - wire intermediate; - - aoi andorinv_0_0(intermediate,p_i_k,g_kneg1_j,g_i_k); - inverter inv_0_32(g_i_j,intermediate); - -endmodule // grayCell - diff --git a/wally-pipelined/src/fpu/dev/rounder_denorm.v b/wally-pipelined/src/fpu/dev/rounder_denorm.v deleted file mode 100755 index 6f7b8f3ed..000000000 --- a/wally-pipelined/src/fpu/dev/rounder_denorm.v +++ /dev/null @@ -1,265 +0,0 @@ -// The rounder takes as inputs a 64-bit value to be rounded, A, the -// exponent of the value to be rounded, the sign of the final result, Sign, -// the precision of the results, P, and the two-bit rounding mode, rm. -// It produces a rounded 52-bit result, Z, the exponent of the rounded -// result, Z_exp, and a flag that indicates if the result was rounded, -// Inexact. The rounding mode has the following values. -// rm Modee -// 00 round-to-nearest-even -// 01 round-toward-zero -// 10 round-toward-plus infinity -// 11 round-toward-minus infinity -// The rounding algorithm determines if '1' should be added to the -// truncated signficant result, based on three significant bits -// (least (L), round (R) and sticky (S)), the rounding mode (rm) -// and the sign of the final result (Sign). Visually, L and R appear as -// xxxxxL,Rxxxxxxx -// where , denotes the rounding boundary. S is the logical OR of all the -// bits to the right of R. - -module rounder (Result, DenormIO, Flags, rm, P, OvEn, - UnEn, exp_valid, sel_inv, Invalid, DenormIn, convert, Asign, Aexp, - norm_shift, A, exponent_postsum, A_Norm, B_Norm, exp_A_unmodified, exp_B_unmodified, - normal_overflow, normal_underflow, swap, op_type, sum); - - input [2:0] rm; - input P; - input OvEn; - input UnEn; - input exp_valid; - input [3:0] sel_inv; - input Invalid; - input DenormIn; - input convert; - input Asign; - input [10:0] Aexp; - input [5:0] norm_shift; - input [63:0] A; - input [10:0] exponent_postsum; - input A_Norm; - input B_Norm; - input [11:0] exp_A_unmodified; - input [11:0] exp_B_unmodified; - input normal_overflow; - input normal_underflow; - input swap; - input [3:0] op_type; - input [63:0] sum; - - output [63:0] Result; - output DenormIO; - output [4:0] Flags; - - wire Rsign; - wire Sticky_out; - wire [51:0] ShiftMant; - wire [63:0] ShiftMant_64; - wire [10:0] Rexp; - wire [10:0] Rexp_denorm; - wire [11:0] Texp; //Parallelized for denorm exponent - wire [11:0] Texp_addone; //results - wire [11:0] Texp_subone; - wire [51:0] Rmant; - wire [51:0] Tmant; - wire Rzero; - wire VSS = 1'b0; - wire VDD = 1'b1; - wire [51:0] B; // Value used to add the "ones" - wire [11:0] B_12_overflow; // Value used to add one to exponent - wire [11:0] B_12_underflow; // Value used to subtract one from exponent - wire S_SP; // Single precision sticky bit - wire S_DP; // Double precision sticky bit - wire S; // Actual sticky bit - wire R; // Round bit - wire L; // Least significant bit - wire add_one; // '1' if one should be added - wire UnFlow_SP, UnFlow_DP, UnderFlow; - wire OvFlow_SP, OvFlow_DP, OverFlow; - wire Inexact; - wire Round_zero; - wire Infinite; - wire VeryLarge; - wire Largest; - wire Adj_exp; - wire Valid; - wire NaN; - wire Cout; - wire Cout_overflow; - wire Texp_l7z; - wire Texp_l7o; - wire OvCon; - - // Determine the sticky bits for double and single precision - assign S_DP= A[9]|A[8]|A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]; - assign S_SP = S_DP |A[38]|A[37]|A[36]|A[35]|A[34]|A[33]|A[32]|A[31]|A[30]| - A[29]|A[28]|A[27]|A[26]|A[25]|A[24]|A[23]|A[22]|A[21]|A[20]| - A[19]|A[18]|A[17]|A[16]|A[15]|A[14]|A[13]|A[12]|A[11]|A[10]; - - // Set the least (L), round (R), and sticky (S) bits based on - // the precision. - assign {L, R, S} = P ? {A[40],A[39],S_SP} : {A[11],A[10],S_DP}; - - // Add one if ((the rounding mode is round-to-nearest) and (R is one) and - // (S or L is one)) or ((the rounding mode is towards plus or minus - // infinity (rm[1] = 1)) and (the sign and rm[0] are the same) and - // (R or S is one)). - - assign add_one = ~rm[2] & ((~rm[1]&~rm[0]&R&(L|S)) | (rm[1]&(Asign^~rm[0])&(R|S))) | (rm[2] & R); - - // Add one using a 52-bit adder. The one is added to the LSB B[0] for - // double precision or to B[29] for single precision. - // This could be simplified by using a specialized adder. - // The current adder is actually 64-bits. The leading one - // for normalized results in not included in the addition. - assign B = {{22{VSS}}, add_one&P, {28{VSS}}, add_one&~P}; - assign B_12_overflow = {8'h0, 3'b0, normal_overflow}; - assign B_12_underflow = {8'h0, 3'b0, normal_underflow}; - - cla52 add1(Tmant, Cout, A[62:11], B); - - cla12 add1_exp(Texp_addone, Cout_overflow, Texp, B_12_overflow); - - cla_sub12 sub1_exp(Texp_subone, Texp, B_12_underflow); - - // Now that rounding is done, we compute the final exponent - // and test for special cases. - - // Compute the value of the exponent by subtracting the shift - // value from the previous exponent and then adding 2 + cout. - // If needed this could be optimized to used a specialized - // adder. - - assign Texp = DenormIn ? ({1'b0, exponent_postsum}) : ({VSS, Aexp} - {{6{VSS}}, norm_shift} +{{10{VSS}}, VDD, Cout}); - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o; - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11] is one) or Texp[10] to - // Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = Texp[11] | ~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = (~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z)); - - // Set the overflow and underflow flags. They should not be set if - // the input was infinite or NaN or the output of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]); - assign NaN = ~sel_inv[2]&~sel_inv[1]& sel_inv[0]; - assign UnderFlow = ((P & UnFlow_SP | UnFlow_DP)&Valid&exp_valid) | - (~Aexp[10]&Aexp[9]&Aexp[8]&Aexp[7]&~Aexp[6] - &~Aexp[5]&~Aexp[4]&~Aexp[3]&~Aexp[2] - &~Aexp[1]&~Aexp[0]&sel_inv[3]); - assign OverFlow = (P & OvFlow_SP | OvFlow_DP)&Valid&~UnderFlow&exp_valid; - - // The DenormIO is set if underflow has occurred or if their was a - // denormalized input. - assign DenormIO = DenormIn | UnderFlow; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (R|S|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {UnderFlow, VSS, OverFlow, Invalid, Inexact}; - - // Determine the final result. - - // The sign of the final result is one if the result is not zero and - // the sign of A is one, or if the result is zero and the the rounding - // mode is round-to-minus infinity. The final result is zero, if exp_valid - // is zero. If underflow occurs, then the result is set to zero. - // - // For Zero (goes equally for subtraction although - // signs may alter operands sign): - // -0 + -0 = -0 (always) - // +0 + +0 = +0 (always) - // -0 + +0 = +0 (for RN, RZ, RU) - // -0 + +0 = -0 (for RD) - assign Rzero = ~exp_valid | UnderFlow; - assign Rsign = DenormIn ? - ( ~(op_type[2] | op_type[1] | op_type[0]) ? - ( (sum[63] & (A_Norm | B_Norm) & (exp_A_unmodified[11] ^ exp_B_unmodified[11])) ? - ~Asign : Asign) - : ( ((A_Norm ^ B_Norm) & (exp_A_unmodified[11] ~^ exp_B_unmodified[11])) ? - (normal_underflow ? ~Asign : Asign) : Asign) - ) - : ( ((Asign&exp_valid | - (sel_inv[2]&~sel_inv[1]&sel_inv[0]&rm[1]&rm[0] | - sel_inv[2]&sel_inv[1]&~sel_inv[0] | - ~exp_valid&rm[1]&rm[0]&~sel_inv[2] | - UnderFlow&rm[1]&rm[0]) & ~convert) & ~sel_inv[3]) | - (Asign & sel_inv[3]) ); - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~Asign&rm[0] | Asign&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | (~sel_inv[2] & sel_inv[1]); - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn & ~convert; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // The denormalized rounded exponent uses the overflow/underflow values - // computed in the fpadd component to round the exponent up or down - // Depending on the operation and the signs of the orignal operands, - // underflow may or may not be needed to round. - assign Rexp_denorm = DenormIn ? - ((~op_type[2] & ~op_type[1] & op_type[0]) ? - ( ((A_Norm != B_Norm) & (exp_A_unmodified[11] == exp_B_unmodified[11])) ? - ( (normal_overflow == normal_underflow) ? Texp[10:0] : (normal_overflow ? Texp_addone[10:0] : Texp_subone[10:0]) ) - : ( normal_overflow ? Texp_addone[10:0] : Texp[10:0] ) ) - : ( ((A_Norm != B_Norm) & (exp_A_unmodified[11] != exp_B_unmodified[11])) ? - ( (normal_overflow == normal_underflow) ? Texp[10:0] : (normal_overflow ? Texp_addone[10:0] : Texp_subone[10:0]) ) - : ( normal_overflow ? Texp_addone[10:0] : Texp[10:0] ) ) - ) : - (op_type[3]) ? exp_A_unmodified : Rexp; - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - // If operation is denormalized, take the mantissa directly from - // its normalized value. - assign Rmant[51] = Largest | NaN | (Tmant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = {51{Largest}} | (Tmant[50:0]&{51{~Infinite&Valid&~Rzero}}); - - assign ShiftMant = A[51:0]; - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - assign OvCon = OverFlow & OvEn & convert; - - assign Result = (op_type[3]) ? {A[63:0]} : (DenormIn ? {Rsign, Rexp_denorm, ShiftMant} : ((P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{VSS}}} - : {Rsign, Rexp, Rmant})); - -endmodule // rounder - diff --git a/wally-pipelined/src/fpu/dev/rounder_div.v b/wally-pipelined/src/fpu/dev/rounder_div.v deleted file mode 100755 index fa676eec8..000000000 --- a/wally-pipelined/src/fpu/dev/rounder_div.v +++ /dev/null @@ -1,187 +0,0 @@ -// -// The rounder takes as inputs a 64-bit value to be rounded, A, the -// exponent of the value to be rounded, the sign of the final result, Sign, -// the precision of the results, P, and the two-bit rounding mode, rm. -// It produces a rounded 52-bit result, Z, the exponent of the rounded -// result, Z_exp, and a flag that indicates if the result was rounded, -// Inexact. The rounding mode has the following values. -// rm Modee -// 00 round-to-nearest-even -// 01 round-toward-zero -// 10 round-toward-plus infinity -// 11 round-toward-minus infinity -// - -module rounder_div (Result, DenormIO, Flags, rm, P, OvEn, - UnEn, exp_diff, sel_inv, Invalid, DenormIn, - SignR, q1, qm1, qp1, q0, qm0, qp0, regr_out); - - input [1:0] rm; - input P; - input OvEn; - input UnEn; - input [12:0] exp_diff; - input [2:0] sel_inv; - input Invalid; - input DenormIn; - input SignR; - - input [63:0] q1; - input [63:0] qm1; - input [63:0] qp1; - input [63:0] q0; - input [63:0] qm0; - input [63:0] qp0; - input [127:0] regr_out; - - output [63:0] Result; - output DenormIO; - output [4:0] Flags; - - supply1 vdd; - supply0 vss; - - wire Rsign; - wire [10:0] Rexp; - wire [12:0] Texp; - wire [51:0] Rmant; - wire [63:0] Tmant; - wire [51:0] Smant; - wire Rzero; - wire Gdp, Gsp, G; - wire UnFlow_SP, UnFlow_DP, UnderFlow; - wire OvFlow_SP, OvFlow_DP, OverFlow; - wire Inexact; - wire Round_zero; - wire Infinite; - wire VeryLarge; - wire Largest; - wire Div0; - wire Adj_exp; - wire Valid; - wire NaN; - wire Texp_l7z; - wire Texp_l7o; - wire OvCon; - wire [1:0] mux_mant; - wire sign_rem; - wire [63:0] q, qm, qp; - wire exp_ovf, exp_ovfSP, exp_ovfDP; - - // Remainder = 0? - assign zero_rem = ~(|regr_out); - // Remainder Sign - assign sign_rem = ~regr_out[127]; - // choose correct Guard bit [1,2) or [0,1) - assign Gdp = q1[63] ? q1[10] : q0[10]; - assign Gsp = q1[63] ? q1[39] : q0[39]; - assign G = P ? Gsp : Gdp; - // Selection of Rounding (from logic/switching) - assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) | - (!rm[1]&!rm[0]&G&!sign_rem) | - (SignR&rm[1]&rm[0]&!zero_rem&!sign_rem) | - (!SignR&rm[1]&!rm[0]&!zero_rem&!sign_rem); - assign mux_mant[0] = (!SignR&rm[0]&!G&!zero_rem&sign_rem) | - (!rm[1]&rm[0]&!G&!zero_rem&sign_rem) | - (SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem); - - // Which Q? - mux2 #(64) mx1 (q0, q1, q1[63], q); - mux2 #(64) mx2 (qm0, qm1, q1[63], qm); - mux2 #(64) mx3 (qp0, qp1, q1[63], qp); - // Choose Q, Q+1, Q-1 - mux3 #(64) mx4 (q, qm, qp, mux_mant, Tmant); - assign Smant = Tmant[62:11]; - // Compute the value of the exponent - // exponent is modified if we choose: - // 1.) we choose any qm0, qp0, q0 (since we shift mant) - // 2.) we choose qp and we overflow (for RU) - assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})}; - assign Texp = exp_diff - {{13{vss}}, ~q1[63]} + {{13{vss}}, mux_mant[1]&qp1[63]&~exp_ovf}; - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = (~Texp[12]&Texp[11]) | (Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o); - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11]/Texp[10] is one) or - // Texp[10] to Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = (Texp[12]&Texp[11]) | ~Texp[11]&~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = ~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z); - - // Set the overflow and underflow flags. They should not be set if - // the input was infinite or NaN or the output of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]); - assign NaN = ~sel_inv[1]& sel_inv[0]; - assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid; - assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid; - assign Div0 = sel_inv[2]&sel_inv[1]&~sel_inv[0]; - - // The DenormIO is set if underflow has occurred or if their was a - // denormalized input. - assign DenormIO = DenormIn | UnderFlow; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (G|~zero_rem|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {Inexact, UnderFlow, OverFlow, Div0, Invalid}; - - // Determine sign - assign Rzero = UnderFlow | (~sel_inv[2]&sel_inv[1]&sel_inv[0]); - assign Rsign = SignR; - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~SignR&rm[0] | SignR&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | sel_inv[1]; - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = {51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}}); - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - assign OvCon = OverFlow & OvEn; - assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{vss}}} - : {Rsign, Rexp, Rmant}; - -endmodule // rounder - diff --git a/wally-pipelined/src/fpu/dev/shifter_denorm.v b/wally-pipelined/src/fpu/dev/shifter_denorm.v deleted file mode 100755 index ed2083816..000000000 --- a/wally-pipelined/src/fpu/dev/shifter_denorm.v +++ /dev/null @@ -1,162 +0,0 @@ - -// MJS - This module implements a 57-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand alignment. - -module mux21x57 (Z, A, B, Sel); - - input [56:0] A; - input [56:0] B; - input Sel; - - output [56:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x57 - -// MJS - This module implements a 64-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand normalization. - -module mux21x64 (Z, A, B, Sel); - - input [63:0] A; - input [63:0] B; - input Sel; - - output [63:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x64 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 64-bit 2-to-1 muxes. The -// barrel shifter takes a 64-bit input A and shifts it left by up to -// 63-bits, as specified by Shift, to produce a 63-bit output Z. -// Bits to the right are filled with zeros. -// The 64 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bit shifts. - -module barrel_shifter_l64 (Z, A, Shift); - - input [63:0] A; - input [5:0] Shift; - - wire [63:0] stage1; - wire [63:0] stage2; - wire [63:0] stage3; - wire [63:0] stage4; - wire [63:0] stage5; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - - output [63:0] Z; - - mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]); - mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]); - mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]); - mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]); - mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]); - mux21x64 mx06(Z , stage5, {stage5[62:0], onezero}, Shift[0]); - -endmodule // barrel_shifter_l63 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 57-bit 2-to-1 muxes. The -// barrel shifter takes a 57-bit input A and right shifts it by up to -// 63-bits, as specified by Shift, to produce a 57-bit output Z. -// It also computes a Sticky bit, which is set to -// one if any of the bits that were shifted out was one. -// Bits shifted into the left are filled with zeros. -// The 63 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bits. - -module barrel_shifter_r57 (Z, Sticky, A, Shift); - - input [56:0] A; - input [5:0] Shift; - - output Sticky; - output [56:0] Z; - - wire [56:0] stage1; - wire [56:0] stage2; - wire [56:0] stage3; - wire [56:0] stage4; - wire [56:0] stage5; - wire [62:0] sixtythreezeros = 63'h0; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - wire [62:0] S; - - // Shift operations - mux21x57 mx01(stage1, A, {thirtytwozeros, A[56:32]}, Shift[5]); - mux21x57 mx02(stage2, stage1, {sixteenzeros, stage1[56:16]}, Shift[4]); - mux21x57 mx03(stage3, stage2, {eightzeros, stage2[56:8]}, Shift[3]); - mux21x57 mx04(stage4, stage3, {fourzeros, stage3[56:4]}, Shift[2]); - mux21x57 mx05(stage5, stage4, {twozeros, stage4[56:2]}, Shift[1]); - mux21x57 mx06(Z , stage5, {onezero, stage5[56:1]}, Shift[0]); - - // Sticky bit calculation. The Sticky bit is set to one if any of the - // bits that were shifter out were one - - assign S[31:0] = {32{Shift[5]}} & A[31:0]; - assign S[47:32] = {16{Shift[4]}} & stage1[15:0]; - assign S[55:48] = { 8{Shift[3]}} & stage2[7:0]; - assign S[59:56] = { 4{Shift[2]}} & stage3[3:0]; - assign S[61:60] = { 2{Shift[1]}} & stage4[1:0]; - assign S[62] = Shift[0] & stage5[0]; - assign Sticky = (S != sixtythreezeros); - -endmodule // barrel_shifter_r57 - -module barrel_shifter_r64 (Z, Sticky, A, Shift); - - input [63:0] A; - input [5:0] Shift; - - output Sticky; - output [63:0] Z; - - wire [63:0] stage1; - wire [63:0] stage2; - wire [63:0] stage3; - wire [63:0] stage4; - wire [63:0] stage5; - wire [62:0] sixtythreezeros = 63'h0; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - wire [62:0] S; - - // Shift operations - mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]); - mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]); - mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]); - mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]); - mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]); - mux21x64 mx06(Z , stage5, {onezero, stage5[63:1]}, Shift[0]); - - // Sticky bit calculation. The Sticky bit is set to one if any of the - // bits that were shifter out were one - - assign S[31:0] = {32{Shift[5]}} & A[31:0]; - assign S[47:32] = {16{Shift[4]}} & stage1[15:0]; - assign S[55:48] = { 8{Shift[3]}} & stage2[7:0]; - assign S[59:56] = { 4{Shift[2]}} & stage3[3:0]; - assign S[61:60] = { 2{Shift[1]}} & stage4[1:0]; - assign S[62] = Shift[0] & stage5[0]; - assign Sticky = (S != sixtythreezeros); - -endmodule // barrel_shifter_r64 diff --git a/wally-pipelined/src/fpu/dev/sk14.v b/wally-pipelined/src/fpu/dev/sk14.v deleted file mode 100755 index 8d2ee8cf4..000000000 --- a/wally-pipelined/src/fpu/dev/sk14.v +++ /dev/null @@ -1,112 +0,0 @@ -// Sklansky Prefix Adder - -module exp_add (cout, sum, a, b, cin); - input [13:0] a, b; - input cin; - output [13:0] sum; - output cout; - - wire [14:0] p,g; - wire [13:0] c; - -// pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; - -// prefix tree - sklansky prefix_tree(c, p[13:0], g[13:0]); - -// post-computation - assign sum=p[14:1]^c; - assign cout=g[14]|(p[14]&c[13]); - -endmodule - -module sklansky (c, p, g); - - input [14:0] p; - input [14:0] g; - output [14:1] c; - - - // parallel-prefix, Sklansky - // Stage 1: Generates G/P pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - // Stage 2: Generates G/P pairs that span 2 bits - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_6_4 (G_6_4, P_6_4, {g[6],G_5_4}, {p[6],P_5_4}); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_10_8 (G_10_8, P_10_8, {g[10],G_9_8}, {p[10],P_9_8}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - black b_14_12 (G_14_12, P_14_12, {g[14],G_13_12}, {p[14],P_13_12}); - black b_15_12 (G_15_12, P_15_12, {G_15_14,G_13_12}, {P_15_14,P_13_12}); - - // Stage 3: Generates G/P pairs that span 4 bits - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_6_0 (G_6_0, {G_6_4,G_3_0}, P_6_4); - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - black b_12_8 (G_12_8, P_12_8, {g[12],G_11_8}, {p[12],P_11_8}); - black b_13_8 (G_13_8, P_13_8, {G_13_12,G_11_8}, {P_13_12,P_11_8}); - black b_14_8 (G_14_8, P_14_8, {G_14_12,G_11_8}, {P_14_12,P_11_8}); - black b_15_8 (G_15_8, P_15_8, {G_15_12,G_11_8}, {P_15_12,P_11_8}); - - // Stage 4: Generates G/P pairs that span 8 bits - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_10_0 (G_10_0, {G_10_8,G_7_0}, P_10_8); - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - grey g_12_0 (G_12_0, {G_12_8,G_7_0}, P_12_8); - grey g_13_0 (G_13_0, {G_13_8,G_7_0}, P_13_8); - grey g_14_0 (G_14_0, {G_14_8,G_7_0}, P_14_8); - grey g_15_0 (G_15_0, {G_15_8,G_7_0}, P_15_8); - - - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; - - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; - -endmodule - - -// Black cell -module black(gout, pout, gin, pin); - - input [1:0] gin, pin; - output gout, pout; - - assign pout=pin[1]&pin[0]; - assign gout=gin[1]|(pin[1]&gin[0]); - -endmodule - -// Grey cell -module grey(gout, gin, pin); - - input[1:0] gin; - input pin; - output gout; - - assign gout=gin[1]|(pin&gin[0]); - -endmodule diff --git a/wally-pipelined/src/fpu/dev/tb_fpu.v b/wally-pipelined/src/fpu/dev/tb_fpu.v deleted file mode 100755 index 3f35c90b0..000000000 --- a/wally-pipelined/src/fpu/dev/tb_fpu.v +++ /dev/null @@ -1,94 +0,0 @@ -// testbench -module tb (); - - reg [63:0] op1; - reg [63:0] op2; - reg [2:0] rm; - reg [3:0] op_type; - reg P; - reg OvEn; - reg UnEn; - - wire [63:0] result; - wire [4:0] Flags; - wire Denorm; - - reg clk, tb_clk; - reg [63:0] yexpected, yexpected_next; - reg reset; - reg [63:0] vectornum, errors; // bookkeeping variables - reg [199:0] testvectors[49999:0]; // array of testvectors - reg [7:0] flags_expected, flags_expected_next; - - integer handle3; - integer desc3; - - // instantiate device under test - fpuadd_testpipe dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, clk); - - always - begin - clk = 1; - tb_clk = 1; - #5; - clk = 0; - #5; - clk = 1; - tb_clk = 0; - #5; - clk = 0; - #5; - end - - initial - begin - handle3 = $fopen("../../fpuaddcvt/test_vectors/f64_add_rne.txt"); - $readmemh("../../fpuaddcvt/test_vectors/f64_add_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1;#10;reset = 0; - //reset = 1; #30; reset = 0; - end - - always @(negedge tb_clk) - begin - desc3 = handle3; - #0 op_type = 4'b0000; - #0 P = 1'b0; - #0 rm = 3'b000; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {yexpected_next, flags_expected_next} = {yexpected, flags_expected}; - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on rising edge of clk - actual results calculated on - // negedge - // - // skip initial cycle - always @(posedge tb_clk) - if (~reset) - begin // skip during reset - #1; - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 200'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - $stop; - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/divconv.sv b/wally-pipelined/src/fpu/divconv.sv index 2f5a6df6b..8a853300b 100755 --- a/wally-pipelined/src/fpu/divconv.sv +++ b/wally-pipelined/src/fpu/divconv.sv @@ -36,6 +36,8 @@ module divconv (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_o logic [63:0] q_const, qp_const, qm_const; logic [63:0] d2, n2; logic [11:0] d3; + logic muxr_out; + logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; // Check if exponent is odd for sqrt // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA @@ -73,16 +75,23 @@ module divconv (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_o mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const); // CPA (from CSA)/Remainder addition/subtraction - adder #(128) cpa1 (Sum2, Carry2, muxr_out, mul_out, cout1); + // adder #(128) cpa1 (Sum2, Carry2, muxr_out, mul_out, cout1); + assign {cout1, mul_out} = Sum2 + Carry2 + muxr_out; // Assuming [1,2) - q1 - adder #(64) cpa2 (regb_out, q_const, 1'b0, q_out1, cout2); - adder #(64) cpa3 (regb_out, qp_const, 1'b0, qp_out1, cout3); - adder #(64) cpa4 (regb_out, qm_const, 1'b1, qm_out1, cout4); + // adder #(64) cpa2 (regb_out, q_const, 1'b0, q_out1, cout2); + assign {cout2, q_out1} = regb_out + q_const; + // adder #(64) cpa3 (regb_out, qp_const, 1'b0, qp_out1, cout3); + assign {cout3, qp_out1} = regb_out + qp_const; + // adder #(64) cpa4 (regb_out, qm_const, 1'b1, qm_out1, cout4); + assign {cout4, qm_out1} = regb_out + qm_const + 1'b1; // Assuming [0.5,1) - q0 - adder #(64) cpa5 ({regb_out[62:0], vss}, q_const, 1'b0, q_out0, cout5); - adder #(64) cpa6 ({regb_out[62:0], vss}, qp_const, 1'b0, qp_out0, cout6); - adder #(64) cpa7 ({regb_out[62:0], vss}, qm_const, 1'b1, qm_out0, cout7); + // adder #(64) cpa5 ({regb_out[62:0], vss}, q_const, 1'b0, q_out0, cout5); + assign {cout5, q_out0} = {regb_out[62:0], vss} + q_const; + // adder #(64) cpa6 ({regb_out[62:0], vss}, qp_const, 1'b0, qp_out0, cout6); + assign {cout6, qp_out0} = {regb_out[62:0], vss} + qp_const; + // adder #(64) cpa7 ({regb_out[62:0], vss}, qm_const, 1'b1, qm_out0, cout7); + assign {cout7, qm_out0} = {regb_out[62:0], vss} + qm_const + 1'b1; // One's complement instead of two's complement (for hw efficiency) assign three = {~mul_out[126], mul_out[126], ~mul_out[125:63]}; diff --git a/wally-pipelined/src/fpu/fdivsqrt.sv b/wally-pipelined/src/fpu/fdivsqrt.sv index 6d8da23f2..8510bcc55 100755 --- a/wally-pipelined/src/fpu/fdivsqrt.sv +++ b/wally-pipelined/src/fpu/fdivsqrt.sv @@ -1,256 +1,256 @@ -// -// File name : fpdiv -// Title : Floating-Point Divider/Square-Root -// project : FPU -// Library : fpdiv -// Author(s) : James E. Stine, Jr. -// Purpose : definition of main unit to floating-point div/sqrt -// notes : -// -// Copyright Oklahoma State University -// -// Basic Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Exponent Logic -// Step 4: Divide/Sqrt using Goldschmidt -// Step 5: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 6: Round the result.// -// Step 7: Put quotient/remainder onto output. -// +// // +// // File name : fpdiv +// // Title : Floating-Point Divider/Square-Root +// // project : FPU +// // Library : fpdiv +// // Author(s) : James E. Stine, Jr. +// // Purpose : definition of main unit to floating-point div/sqrt +// // notes : +// // +// // Copyright Oklahoma State University +// // +// // Basic Operations +// // +// // Step 1: Load operands, set flags, and convert SP to DP +// // Step 2: Check for special inputs ( +/- Infinity, NaN) +// // Step 3: Exponent Logic +// // Step 4: Divide/Sqrt using Goldschmidt +// // Step 5: Normalize the result.// +// // Shift left until normalized. Normalized when the value to the +// // left of the binrary point is 1. +// // Step 6: Round the result.// +// // Step 7: Put quotient/remainder onto output. +// // -// `timescale 1ps/1ps -module fdivsqrt (FDivSqrtDoneE, FDivResultM, FDivSqrtFlgM, DivInput1E, DivInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, - FDivStartE, reset, clk, FDivBusyE, HoldInputs); +// // `timescale 1ps/1ps +// module fdivsqrt (FDivSqrtDoneE, FDivResultM, FDivSqrtFlgM, DivInput1E, DivInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, +// FDivStartE, reset, clk, FDivBusyE, HoldInputs); - input [63:0] DivInput1E; // 1st input operand (A) - input [63:0] DivInput2E; // 2nd input operand (B) - input [2:0] FrmE; // Rounding mode - specify values - input DivOpType; // Function opcode - input FmtE; // Result Precision (0 for double, 1 for single) //***will need to swap this - input DivOvEn; // Overflow trap enabled - input DivUnEn; // Underflow trap enabled +// input [63:0] DivInput1E; // 1st input operand (A) +// input [63:0] DivInput2E; // 2nd input operand (B) +// input [2:0] FrmE; // Rounding mode - specify values +// input DivOpType; // Function opcode +// input FmtE; // Result Precision (0 for double, 1 for single) //***will need to swap this +// input DivOvEn; // Overflow trap enabled +// input DivUnEn; // Underflow trap enabled - input FDivStartE; - input reset; - input clk; +// input FDivStartE; +// input reset; +// input clk; - output [63:0] FDivResultM; // Result of operation - output [4:0] FDivSqrtFlgM; // IEEE exception flags - output FDivSqrtDoneE; - output FDivBusyE, HoldInputs; +// output [63:0] FDivResultM; // Result of operation +// output [4:0] FDivSqrtFlgM; // IEEE exception flags +// output FDivSqrtDoneE; +// output FDivBusyE, HoldInputs; - supply1 vdd; - supply0 vss; +// supply1 vdd; +// supply0 vss; - wire [63:0] Float1; - wire [63:0] Float2; - wire [63:0] IntValue; +// wire [63:0] Float1; +// wire [63:0] Float2; +// wire [63:0] IntValue; - wire DivDenormM; // DivDenormM on input or output - wire [12:0] exp1, exp2, expF; - wire [12:0] exp_diff, bias; - wire [13:0] exp_sqrt; - wire [12:0] exp_s; - wire [12:0] exp_c; +// wire DivDenormM; // DivDenormM on input or output +// wire [12:0] exp1, exp2, expF; +// wire [12:0] exp_diff, bias; +// wire [13:0] exp_sqrt; +// wire [12:0] exp_s; +// wire [12:0] exp_c; - wire [10:0] exponent, exp_pre; - wire [63:0] Result; - wire [52:0] mantissaA; - wire [52:0] mantissaB; - wire [63:0] sum, sum_tc, sum_corr, sum_norm; +// wire [10:0] exponent, exp_pre; +// wire [63:0] Result; +// wire [52:0] mantissaA; +// wire [52:0] mantissaB; +// wire [63:0] sum, sum_tc, sum_corr, sum_norm; - wire [5:0] align_shift; - wire [5:0] norm_shift; - wire [2:0] sel_inv; - wire op1_Norm, op2_Norm; - wire opA_Norm, opB_Norm; - wire Invalid; - wire DenormIn, DenormIO; - wire [4:0] FlagsIn; - wire exp_gt63; - wire Sticky_out; - wire signResult, sign_corr; - wire corr_sign; - wire zeroB; - wire convert; - wire swap; - wire sub; +// wire [5:0] align_shift; +// wire [5:0] norm_shift; +// wire [2:0] sel_inv; +// wire op1_Norm, op2_Norm; +// wire opA_Norm, opB_Norm; +// wire Invalid; +// wire DenormIn, DenormIO; +// wire [4:0] FlagsIn; +// wire exp_gt63; +// wire Sticky_out; +// wire signResult, sign_corr; +// wire corr_sign; +// wire zeroB; +// wire convert; +// wire swap; +// wire sub; - wire [63:0] q1, qm1, qp1, q0, qm0, qp0; - wire [63:0] rega_out, regb_out, regc_out, regd_out; - wire [127:0] regr_out; - wire [2:0] sel_muxa, sel_muxb; - wire sel_muxr; - wire load_rega, load_regb, load_regc, load_regd, load_regr, load_regs; +// wire [63:0] q1, qm1, qp1, q0, qm0, qp0; +// wire [63:0] rega_out, regb_out, regc_out, regd_out; +// wire [127:0] regr_out; +// wire [2:0] sel_muxa, sel_muxb; +// wire sel_muxr; +// wire load_rega, load_regb, load_regc, load_regd, load_regr, load_regs; - wire donev, sel_muxrv, sel_muxsv; - wire [1:0] sel_muxav, sel_muxbv; - wire load_regav, load_regbv, load_regcv; - wire load_regrv, load_regsv; +// wire donev, sel_muxrv, sel_muxsv; +// wire [1:0] sel_muxav, sel_muxbv; +// wire load_regav, load_regbv, load_regcv; +// wire load_regrv, load_regsv; - logic exp_cout1, exp_cout2, exp_odd, open; +// logic exp_cout1, exp_cout2, exp_odd, open; - // Convert the input operands to their appropriate forms based on - // the orignal operands, the DivOpType , and their precision FmtE. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - convert_inputs_div divconv1 (Float1, Float2, DivInput1E, DivInput2E, DivOpType, FmtE); +// // Convert the input operands to their appropriate forms based on +// // the orignal operands, the DivOpType , and their precision FmtE. +// // Single precision inputs are converted to double precision +// // and the sign of the first operand is set appropratiately based on +// // if the operation is absolute value or negation. +// convert_inputs_div divconv1 (Float1, Float2, DivInput1E, DivInput2E, DivOpType, FmtE); - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input FDivSqrtFlgM. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if DivInput1E and DivInput2E are not zero or denormalized. - // sub is one if the effective operation is subtaction. - exception_div divexc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, - Float1, Float2, DivOpType); +// // Test for exceptions and return the "Invalid Operation" and +// // "Denormalized" Input FDivSqrtFlgM. The "sel_inv" is used in +// // the third pipeline stage to select the result. Also, op1_Norm +// // and op2_Norm are one if DivInput1E and DivInput2E are not zero or denormalized. +// // sub is one if the effective operation is subtaction. +// exception_div divexc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, +// Float1, Float2, DivOpType); - // Determine Sign/Mantissa - assign signResult = ((Float1[63]^Float2[63])&~DivOpType) | Float1[63]&DivOpType; - assign mantissaA = {vdd, Float1[51:0]}; - assign mantissaB = {vdd, Float2[51:0]}; - // Perform Exponent Subtraction - expA - expB + Bias - assign exp1 = {2'b0, Float1[62:52]}; - assign exp2 = {2'b0, Float2[62:52]}; - // bias : DP = 2^{11-1}-1 = 1023 - assign bias = {3'h0, 10'h3FF}; - // Divide exponent - csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c); //***adder - exp_add explogic1 (exp_cout1, {open, exp_diff}, //***adder? - {vss, exp_s}, {vss, exp_c}, 1'b1); - // Sqrt exponent (check if exponent is odd) - assign exp_odd = Float1[52] ? vss : vdd; - exp_add explogic2 (exp_cout2, exp_sqrt, //***adder? - {vss, exp1}, {4'h0, 10'h3ff}, exp_odd); - // Choose correct exponent - assign expF = DivOpType ? exp_sqrt[13:1] : exp_diff; +// // Determine Sign/Mantissa +// assign signResult = ((Float1[63]^Float2[63])&~DivOpType) | Float1[63]&DivOpType; +// assign mantissaA = {vdd, Float1[51:0]}; +// assign mantissaB = {vdd, Float2[51:0]}; +// // Perform Exponent Subtraction - expA - expB + Bias +// assign exp1 = {2'b0, Float1[62:52]}; +// assign exp2 = {2'b0, Float2[62:52]}; +// // bias : DP = 2^{11-1}-1 = 1023 +// assign bias = {3'h0, 10'h3FF}; +// // Divide exponent +// csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c); //***adder +// exp_add explogic1 (exp_cout1, {open, exp_diff}, //***adder? +// {vss, exp_s}, {vss, exp_c}, 1'b1); +// // Sqrt exponent (check if exponent is odd) +// assign exp_odd = Float1[52] ? vss : vdd; +// exp_add explogic2 (exp_cout2, exp_sqrt, //***adder? +// {vss, exp1}, {4'h0, 10'h3ff}, exp_odd); +// // Choose correct exponent +// assign expF = DivOpType ? exp_sqrt[13:1] : exp_diff; - // Main Goldschmidt/Division Routine - divconv goldy (q1, qm1, qp1, q0, qm0, qp0, - rega_out, regb_out, regc_out, regd_out, - regr_out, mantissaB, mantissaA, - sel_muxa, sel_muxb, sel_muxr, - reset, clk, - load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, FmtE, DivOpType, exp_odd); +// // Main Goldschmidt/Division Routine +// divconv goldy (q1, qm1, qp1, q0, qm0, qp0, +// rega_out, regb_out, regc_out, regd_out, +// regr_out, mantissaB, mantissaA, +// sel_muxa, sel_muxb, sel_muxr, +// reset, clk, +// load_rega, load_regb, load_regc, load_regd, +// load_regr, load_regs, FmtE, DivOpType, exp_odd); - // FSM : control divider - fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, FDivStartE, DivOpType, FDivBusyE, HoldInputs); +// // FSM : control divider +// fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd, +// load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, +// clk, reset, FDivStartE, DivOpType, FDivBusyE, HoldInputs); - // Round the mantissa to a 52-bit value, with the leading one - // removed. The rounding units also handles special cases and - // set the exception flags. - //***add max magnitude and swap negitive and positive infinity - rounder_div divround1 (Result, DenormIO, FlagsIn, - FrmE, FmtE, DivOvEn, DivUnEn, expF, - sel_inv, Invalid, DenormIn, signResult, - q1, qm1, qp1, q0, qm0, qp0, regr_out); +// // Round the mantissa to a 52-bit value, with the leading one +// // removed. The rounding units also handles special cases and +// // set the exception flags. +// //***add max magnitude and swap negitive and positive infinity +// rounder_div divround1 (Result, DenormIO, FlagsIn, +// FrmE, FmtE, DivOvEn, DivUnEn, expF, +// sel_inv, Invalid, DenormIn, signResult, +// q1, qm1, qp1, q0, qm0, qp0, regr_out); - // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultM); - flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormM); - flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivSqrtFlgM); +// // Store the final result and the exception flags in registers. +// flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultM); +// flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormM); +// flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivSqrtFlgM); -endmodule // fpadd +// endmodule // fpadd -// -// Brent-Kung Prefix Adder -// (yes, it is 14 bits as my generator is broken for 13 bits :( -// assume, synthesizer will delete stuff not needed ) -// -module exp_add (cout, sum, a, b, cin); +// // +// // Brent-Kung Prefix Adder +// // (yes, it is 14 bits as my generator is broken for 13 bits :( +// // assume, synthesizer will delete stuff not needed ) +// // +// module exp_add (cout, sum, a, b, cin); - input [13:0] a, b; - input cin; +// input [13:0] a, b; +// input cin; - output [13:0] sum; - output cout; +// output [13:0] sum; +// output cout; - wire [14:0] p,g; - wire [13:0] c; +// wire [14:0] p,g; +// wire [13:0] c; - // pre-computation - assign p={a^b,1'b0}; - assign g={a&b, cin}; +// // pre-computation +// assign p={a^b,1'b0}; +// assign g={a&b, cin}; - // prefix tree - brent_kung prefix_tree(c, p[13:0], g[13:0]); +// // prefix tree +// brent_kung prefix_tree(c, p[13:0], g[13:0]); - // post-computation - assign sum=p[14:1]^c; - assign cout=g[14]|(p[14]&c[13]); +// // post-computation +// assign sum=p[14:1]^c; +// assign cout=g[14]|(p[14]&c[13]); -endmodule // exp_add +// endmodule // exp_add -module brent_kung (c, p, g); +// module brent_kung (c, p, g); - input [13:0] p; - input [13:0] g; - output [14:1] c; +// input [13:0] p; +// input [13:0] g; +// output [14:1] c; - logic G_1_0, G_3_2,G_5_4,G_7_6,G_9_8,G_11_10,G_13_12,G_3_0,G_7_4,G_11_8; - logic P_3_2,P_5_4,P_7_6,P_9_8,P_11_10,P_13_12,P_7_4,P_11_8; - logic G_7_0,G_11_0,G_5_0,G_9_0,G_13_0,G_2_0,G_4_0,G_6_0,G_8_0,G_10_0,G_12_0; - // parallel-prefix, Brent-Kung +// logic G_1_0, G_3_2,G_5_4,G_7_6,G_9_8,G_11_10,G_13_12,G_3_0,G_7_4,G_11_8; +// logic P_3_2,P_5_4,P_7_6,P_9_8,P_11_10,P_13_12,P_7_4,P_11_8; +// logic G_7_0,G_11_0,G_5_0,G_9_0,G_13_0,G_2_0,G_4_0,G_6_0,G_8_0,G_10_0,G_12_0; +// // parallel-prefix, Brent-Kung - // Stage 1: Generates G/FmtE pairs that span 1 bits - grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); - black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); - black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); - black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); - black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); - black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); - black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); +// // Stage 1: Generates G/FmtE pairs that span 1 bits +// grey b_1_0 (G_1_0, {g[1],g[0]}, p[1]); +// black b_3_2 (G_3_2, P_3_2, {g[3],g[2]}, {p[3],p[2]}); +// black b_5_4 (G_5_4, P_5_4, {g[5],g[4]}, {p[5],p[4]}); +// black b_7_6 (G_7_6, P_7_6, {g[7],g[6]}, {p[7],p[6]}); +// black b_9_8 (G_9_8, P_9_8, {g[9],g[8]}, {p[9],p[8]}); +// black b_11_10 (G_11_10, P_11_10, {g[11],g[10]}, {p[11],p[10]}); +// black b_13_12 (G_13_12, P_13_12, {g[13],g[12]}, {p[13],p[12]}); - // Stage 2: Generates G/FmtE pairs that span 2 bits - grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); - black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); - black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); +// // Stage 2: Generates G/FmtE pairs that span 2 bits +// grey g_3_0 (G_3_0, {G_3_2,G_1_0}, P_3_2); +// black b_7_4 (G_7_4, P_7_4, {G_7_6,G_5_4}, {P_7_6,P_5_4}); +// black b_11_8 (G_11_8, P_11_8, {G_11_10,G_9_8}, {P_11_10,P_9_8}); - // Stage 3: Generates G/FmtE pairs that span 4 bits - grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); +// // Stage 3: Generates G/FmtE pairs that span 4 bits +// grey g_7_0 (G_7_0, {G_7_4,G_3_0}, P_7_4); - // Stage 4: Generates G/FmtE pairs that span 8 bits +// // Stage 4: Generates G/FmtE pairs that span 8 bits - // Stage 5: Generates G/FmtE pairs that span 4 bits - grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); +// // Stage 5: Generates G/FmtE pairs that span 4 bits +// grey g_11_0 (G_11_0, {G_11_8,G_7_0}, P_11_8); - // Stage 6: Generates G/FmtE pairs that span 2 bits - grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); - grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); - grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12); +// // Stage 6: Generates G/FmtE pairs that span 2 bits +// grey g_5_0 (G_5_0, {G_5_4,G_3_0}, P_5_4); +// grey g_9_0 (G_9_0, {G_9_8,G_7_0}, P_9_8); +// grey g_13_0 (G_13_0, {G_13_12,G_11_0}, P_13_12); - // Last grey cell stage - grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); - grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); - grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); - grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); - grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); - grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); +// // Last grey cell stage +// grey g_2_0 (G_2_0, {g[2],G_1_0}, p[2]); +// grey g_4_0 (G_4_0, {g[4],G_3_0}, p[4]); +// grey g_6_0 (G_6_0, {g[6],G_5_0}, p[6]); +// grey g_8_0 (G_8_0, {g[8],G_7_0}, p[8]); +// grey g_10_0 (G_10_0, {g[10],G_9_0}, p[10]); +// grey g_12_0 (G_12_0, {g[12],G_11_0}, p[12]); - // Final Stage: Apply c_k+1=G_k_0 - assign c[1]=g[0]; - assign c[2]=G_1_0; - assign c[3]=G_2_0; - assign c[4]=G_3_0; - assign c[5]=G_4_0; - assign c[6]=G_5_0; - assign c[7]=G_6_0; - assign c[8]=G_7_0; - assign c[9]=G_8_0; +// // Final Stage: Apply c_k+1=G_k_0 +// assign c[1]=g[0]; +// assign c[2]=G_1_0; +// assign c[3]=G_2_0; +// assign c[4]=G_3_0; +// assign c[5]=G_4_0; +// assign c[6]=G_5_0; +// assign c[7]=G_6_0; +// assign c[8]=G_7_0; +// assign c[9]=G_8_0; - assign c[10]=G_9_0; - assign c[11]=G_10_0; - assign c[12]=G_11_0; - assign c[13]=G_12_0; - assign c[14]=G_13_0; +// assign c[10]=G_9_0; +// assign c[11]=G_10_0; +// assign c[12]=G_11_0; +// assign c[13]=G_12_0; +// assign c[14]=G_13_0; -endmodule // brent_kung +// endmodule // brent_kung diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index 5bf7785e1..d6361527b 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -465,7 +465,9 @@ module fma2( // - Don't set the underflow flag if the result was rounded up to a normal number assign FMAFlgM = {Invalid, 1'b0, Overflow, UnderflowFlag, Inexact}; - +// nf ne fraction and exponent bits +// nf 52 double nf is 11 +// u2.2nf - product unsigned 2 int bits diff --git a/wally-pipelined/src/fpu/fpadd/adder.v b/wally-pipelined/src/fpu/fpadd/adder.v deleted file mode 100755 index 3d4124af6..000000000 --- a/wally-pipelined/src/fpu/fpadd/adder.v +++ /dev/null @@ -1,758 +0,0 @@ -// The following module make up the basic building blocks that -// are used by the cla64, cla_sub64, and cla52. - -module INVBLOCK ( GIN, GOUT ); - - input GIN; - output GOUT; - - assign GOUT = ~ GIN; - -endmodule // INVBLOCK - - -module XXOR1 ( A, B, GIN, SUM ); - - input A; - input B; - input GIN; - output SUM; - - assign SUM = ( ~ (A ^ B)) ^ GIN; - -endmodule // XXOR1 - - -module BLOCK0 ( A, B, POUT, GOUT ); - - input A; - input B; - output POUT; - output GOUT; - - assign POUT = ~ (A | B); - assign GOUT = ~ (A & B); - -endmodule // BLOCK0 - - -module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 | PIN2); - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1 - - -module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 & PIN2); - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule // BLOCK2 - - -module BLOCK1A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1A - - -module BLOCK2A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule - -module PRESTAGE_64 ( A, B, CIN, POUT, GOUT ); - - input [0:63] A; - input [0:63] B; - input CIN; - - output [0:63] POUT; - output [0:64] GOUT; - - BLOCK0 U10 (A[0] , B[0] , POUT[0] , GOUT[1] ); - BLOCK0 U11 (A[1] , B[1] , POUT[1] , GOUT[2] ); - BLOCK0 U12 (A[2] , B[2] , POUT[2] , GOUT[3] ); - BLOCK0 U13 (A[3] , B[3] , POUT[3] , GOUT[4] ); - BLOCK0 U14 (A[4] , B[4] , POUT[4] , GOUT[5] ); - BLOCK0 U15 (A[5] , B[5] , POUT[5] , GOUT[6] ); - BLOCK0 U16 (A[6] , B[6] , POUT[6] , GOUT[7] ); - BLOCK0 U17 (A[7] , B[7] , POUT[7] , GOUT[8] ); - BLOCK0 U18 (A[8] , B[8] , POUT[8] , GOUT[9] ); - BLOCK0 U19 (A[9] , B[9] , POUT[9] , GOUT[10] ); - BLOCK0 U110 (A[10] , B[10] , POUT[10] , GOUT[11] ); - BLOCK0 U111 (A[11] , B[11] , POUT[11] , GOUT[12] ); - BLOCK0 U112 (A[12] , B[12] , POUT[12] , GOUT[13] ); - BLOCK0 U113 (A[13] , B[13] , POUT[13] , GOUT[14] ); - BLOCK0 U114 (A[14] , B[14] , POUT[14] , GOUT[15] ); - BLOCK0 U115 (A[15] , B[15] , POUT[15] , GOUT[16] ); - BLOCK0 U116 (A[16] , B[16] , POUT[16] , GOUT[17] ); - BLOCK0 U117 (A[17] , B[17] , POUT[17] , GOUT[18] ); - BLOCK0 U118 (A[18] , B[18] , POUT[18] , GOUT[19] ); - BLOCK0 U119 (A[19] , B[19] , POUT[19] , GOUT[20] ); - BLOCK0 U120 (A[20] , B[20] , POUT[20] , GOUT[21] ); - BLOCK0 U121 (A[21] , B[21] , POUT[21] , GOUT[22] ); - BLOCK0 U122 (A[22] , B[22] , POUT[22] , GOUT[23] ); - BLOCK0 U123 (A[23] , B[23] , POUT[23] , GOUT[24] ); - BLOCK0 U124 (A[24] , B[24] , POUT[24] , GOUT[25] ); - BLOCK0 U125 (A[25] , B[25] , POUT[25] , GOUT[26] ); - BLOCK0 U126 (A[26] , B[26] , POUT[26] , GOUT[27] ); - BLOCK0 U127 (A[27] , B[27] , POUT[27] , GOUT[28] ); - BLOCK0 U128 (A[28] , B[28] , POUT[28] , GOUT[29] ); - BLOCK0 U129 (A[29] , B[29] , POUT[29] , GOUT[30] ); - BLOCK0 U130 (A[30] , B[30] , POUT[30] , GOUT[31] ); - BLOCK0 U131 (A[31] , B[31] , POUT[31] , GOUT[32] ); - BLOCK0 U132 (A[32] , B[32] , POUT[32] , GOUT[33] ); - BLOCK0 U133 (A[33] , B[33] , POUT[33] , GOUT[34] ); - BLOCK0 U134 (A[34] , B[34] , POUT[34] , GOUT[35] ); - BLOCK0 U135 (A[35] , B[35] , POUT[35] , GOUT[36] ); - BLOCK0 U136 (A[36] , B[36] , POUT[36] , GOUT[37] ); - BLOCK0 U137 (A[37] , B[37] , POUT[37] , GOUT[38] ); - BLOCK0 U138 (A[38] , B[38] , POUT[38] , GOUT[39] ); - BLOCK0 U139 (A[39] , B[39] , POUT[39] , GOUT[40] ); - BLOCK0 U140 (A[40] , B[40] , POUT[40] , GOUT[41] ); - BLOCK0 U141 (A[41] , B[41] , POUT[41] , GOUT[42] ); - BLOCK0 U142 (A[42] , B[42] , POUT[42] , GOUT[43] ); - BLOCK0 U143 (A[43] , B[43] , POUT[43] , GOUT[44] ); - BLOCK0 U144 (A[44] , B[44] , POUT[44] , GOUT[45] ); - BLOCK0 U145 (A[45] , B[45] , POUT[45] , GOUT[46] ); - BLOCK0 U146 (A[46] , B[46] , POUT[46] , GOUT[47] ); - BLOCK0 U147 (A[47] , B[47] , POUT[47] , GOUT[48] ); - BLOCK0 U148 (A[48] , B[48] , POUT[48] , GOUT[49] ); - BLOCK0 U149 (A[49] , B[49] , POUT[49] , GOUT[50] ); - BLOCK0 U150 (A[50] , B[50] , POUT[50] , GOUT[51] ); - BLOCK0 U151 (A[51] , B[51] , POUT[51] , GOUT[52] ); - BLOCK0 U152 (A[52] , B[52] , POUT[52] , GOUT[53] ); - BLOCK0 U153 (A[53] , B[53] , POUT[53] , GOUT[54] ); - BLOCK0 U154 (A[54] , B[54] , POUT[54] , GOUT[55] ); - BLOCK0 U155 (A[55] , B[55] , POUT[55] , GOUT[56] ); - BLOCK0 U156 (A[56] , B[56] , POUT[56] , GOUT[57] ); - BLOCK0 U157 (A[57] , B[57] , POUT[57] , GOUT[58] ); - BLOCK0 U158 (A[58] , B[58] , POUT[58] , GOUT[59] ); - BLOCK0 U159 (A[59] , B[59] , POUT[59] , GOUT[60] ); - BLOCK0 U160 (A[60] , B[60] , POUT[60] , GOUT[61] ); - BLOCK0 U161 (A[61] , B[61] , POUT[61] , GOUT[62] ); - BLOCK0 U162 (A[62] , B[62] , POUT[62] , GOUT[63] ); - BLOCK0 U163 (A[63] , B[63] , POUT[63] , GOUT[64] ); - INVBLOCK U2 (CIN , GOUT[0] ); - -endmodule // PRESTAGE_64 - - -module DBLC_0_64 ( PIN, GIN, POUT, GOUT ); - - input [0:63] PIN; - input [0:64] GIN; - - output [0:62] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , GOUT[1] ); - BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , POUT[0] , GOUT[2] ); - BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , POUT[1] , GOUT[3] ); - BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , POUT[2] , GOUT[4] ); - BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , POUT[3] , GOUT[5] ); - BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , POUT[4] , GOUT[6] ); - BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , POUT[5] , GOUT[7] ); - BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , POUT[6] , GOUT[8] ); - BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , POUT[7] , GOUT[9] ); - BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , POUT[8] , GOUT[10] ); - BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , POUT[9] , GOUT[11] ); - BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , POUT[10] , GOUT[12] ); - BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , POUT[11] , GOUT[13] ); - BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , POUT[12] , GOUT[14] ); - BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , POUT[13] , GOUT[15] ); - BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , POUT[14] , GOUT[16] ); - BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , POUT[15] , GOUT[17] ); - BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , POUT[16] , GOUT[18] ); - BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , POUT[17] , GOUT[19] ); - BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , POUT[18] , GOUT[20] ); - BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , POUT[19] , GOUT[21] ); - BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , POUT[20] , GOUT[22] ); - BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , POUT[21] , GOUT[23] ); - BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , POUT[22] , GOUT[24] ); - BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , POUT[23] , GOUT[25] ); - BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , POUT[24] , GOUT[26] ); - BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , POUT[25] , GOUT[27] ); - BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , POUT[26] , GOUT[28] ); - BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , POUT[27] , GOUT[29] ); - BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , POUT[28] , GOUT[30] ); - BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , POUT[29] , GOUT[31] ); - BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , POUT[30] , GOUT[32] ); - BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , POUT[31] , GOUT[33] ); - BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , POUT[32] , GOUT[34] ); - BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , POUT[33] , GOUT[35] ); - BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , POUT[34] , GOUT[36] ); - BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , POUT[35] , GOUT[37] ); - BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , POUT[36] , GOUT[38] ); - BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , POUT[37] , GOUT[39] ); - BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , POUT[38] , GOUT[40] ); - BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , POUT[39] , GOUT[41] ); - BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , POUT[40] , GOUT[42] ); - BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , POUT[41] , GOUT[43] ); - BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , POUT[42] , GOUT[44] ); - BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , POUT[43] , GOUT[45] ); - BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , POUT[44] , GOUT[46] ); - BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , POUT[45] , GOUT[47] ); - BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , POUT[46] , GOUT[48] ); - BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , POUT[47] , GOUT[49] ); - BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , POUT[48] , GOUT[50] ); - BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , POUT[49] , GOUT[51] ); - BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , POUT[50] , GOUT[52] ); - BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , POUT[51] , GOUT[53] ); - BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , POUT[52] , GOUT[54] ); - BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , POUT[53] , GOUT[55] ); - BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , POUT[54] , GOUT[56] ); - BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , POUT[55] , GOUT[57] ); - BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , POUT[56] , GOUT[58] ); - BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , POUT[57] , GOUT[59] ); - BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , POUT[58] , GOUT[60] ); - BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , POUT[59] , GOUT[61] ); - BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , POUT[60] , GOUT[62] ); - BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , POUT[61] , GOUT[63] ); - BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , POUT[62] , GOUT[64] ); - -endmodule // DBLC_0_64 - - -module DBLC_1_64 ( PIN, GIN, POUT, GOUT ); - - input [0:62] PIN; - input [0:64] GIN; - - output [0:60] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , GOUT[2] ); - BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , GOUT[3] ); - BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , POUT[0] , GOUT[4] ); - BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , POUT[1] , GOUT[5] ); - BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , POUT[2] , GOUT[6] ); - BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , POUT[3] , GOUT[7] ); - BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , POUT[4] , GOUT[8] ); - BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , POUT[5] , GOUT[9] ); - BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , POUT[6] , GOUT[10] ); - BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , POUT[7] , GOUT[11] ); - BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , POUT[8] , GOUT[12] ); - BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , POUT[9] , GOUT[13] ); - BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , POUT[10] , GOUT[14] ); - BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , POUT[11] , GOUT[15] ); - BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , POUT[12] , GOUT[16] ); - BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , POUT[13] , GOUT[17] ); - BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , POUT[14] , GOUT[18] ); - BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , POUT[15] , GOUT[19] ); - BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , POUT[16] , GOUT[20] ); - BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , POUT[17] , GOUT[21] ); - BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , POUT[18] , GOUT[22] ); - BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , POUT[19] , GOUT[23] ); - BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , POUT[20] , GOUT[24] ); - BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , POUT[21] , GOUT[25] ); - BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , POUT[22] , GOUT[26] ); - BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , POUT[23] , GOUT[27] ); - BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , POUT[24] , GOUT[28] ); - BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , POUT[25] , GOUT[29] ); - BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , POUT[26] , GOUT[30] ); - BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , POUT[27] , GOUT[31] ); - BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , POUT[28] , GOUT[32] ); - BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , POUT[29] , GOUT[33] ); - BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , POUT[30] , GOUT[34] ); - BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , POUT[31] , GOUT[35] ); - BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , POUT[32] , GOUT[36] ); - BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , POUT[33] , GOUT[37] ); - BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , POUT[34] , GOUT[38] ); - BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , POUT[35] , GOUT[39] ); - BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , POUT[36] , GOUT[40] ); - BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , POUT[37] , GOUT[41] ); - BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , POUT[38] , GOUT[42] ); - BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , POUT[39] , GOUT[43] ); - BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , POUT[40] , GOUT[44] ); - BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , POUT[41] , GOUT[45] ); - BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , POUT[42] , GOUT[46] ); - BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , POUT[43] , GOUT[47] ); - BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , POUT[44] , GOUT[48] ); - BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , POUT[45] , GOUT[49] ); - BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , POUT[46] , GOUT[50] ); - BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , POUT[47] , GOUT[51] ); - BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , POUT[48] , GOUT[52] ); - BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , POUT[49] , GOUT[53] ); - BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , POUT[50] , GOUT[54] ); - BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , POUT[51] , GOUT[55] ); - BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , POUT[52] , GOUT[56] ); - BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , POUT[53] , GOUT[57] ); - BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , POUT[54] , GOUT[58] ); - BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , POUT[55] , GOUT[59] ); - BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , POUT[56] , GOUT[60] ); - BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , POUT[57] , GOUT[61] ); - BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , POUT[58] , GOUT[62] ); - BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , POUT[59] , GOUT[63] ); - BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , POUT[60] , GOUT[64] ); - -endmodule // DBLC_1_64 - - -module DBLC_2_64 ( PIN, GIN, POUT, GOUT ); - - input [0:60] PIN; - input [0:64] GIN; - - output [0:56] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , GOUT[4] ); - BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , GOUT[5] ); - BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , GOUT[6] ); - BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , GOUT[7] ); - BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , POUT[0] , GOUT[8] ); - BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , POUT[1] , GOUT[9] ); - BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , POUT[2] , GOUT[10] ); - BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , POUT[3] , GOUT[11] ); - BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , POUT[4] , GOUT[12] ); - BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , POUT[5] , GOUT[13] ); - BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , POUT[6] , GOUT[14] ); - BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , POUT[7] , GOUT[15] ); - BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , POUT[8] , GOUT[16] ); - BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , POUT[9] , GOUT[17] ); - BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , POUT[10] , GOUT[18] ); - BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , POUT[11] , GOUT[19] ); - BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , POUT[12] , GOUT[20] ); - BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , POUT[13] , GOUT[21] ); - BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , POUT[14] , GOUT[22] ); - BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , POUT[15] , GOUT[23] ); - BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , POUT[16] , GOUT[24] ); - BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , POUT[17] , GOUT[25] ); - BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , POUT[18] , GOUT[26] ); - BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , POUT[19] , GOUT[27] ); - BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , POUT[20] , GOUT[28] ); - BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , POUT[21] , GOUT[29] ); - BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , POUT[22] , GOUT[30] ); - BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , POUT[23] , GOUT[31] ); - BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , POUT[24] , GOUT[32] ); - BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , POUT[25] , GOUT[33] ); - BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , POUT[26] , GOUT[34] ); - BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , POUT[27] , GOUT[35] ); - BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , POUT[28] , GOUT[36] ); - BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , POUT[29] , GOUT[37] ); - BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , POUT[30] , GOUT[38] ); - BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , POUT[31] , GOUT[39] ); - BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , POUT[32] , GOUT[40] ); - BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , POUT[33] , GOUT[41] ); - BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , POUT[34] , GOUT[42] ); - BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , POUT[35] , GOUT[43] ); - BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , POUT[36] , GOUT[44] ); - BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , POUT[37] , GOUT[45] ); - BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , POUT[38] , GOUT[46] ); - BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , POUT[39] , GOUT[47] ); - BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , POUT[40] , GOUT[48] ); - BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , POUT[41] , GOUT[49] ); - BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , POUT[42] , GOUT[50] ); - BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , POUT[43] , GOUT[51] ); - BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , POUT[44] , GOUT[52] ); - BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , POUT[45] , GOUT[53] ); - BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , POUT[46] , GOUT[54] ); - BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , POUT[47] , GOUT[55] ); - BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , POUT[48] , GOUT[56] ); - BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , POUT[49] , GOUT[57] ); - BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , POUT[50] , GOUT[58] ); - BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , POUT[51] , GOUT[59] ); - BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , POUT[52] , GOUT[60] ); - BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , POUT[53] , GOUT[61] ); - BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , POUT[54] , GOUT[62] ); - BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , POUT[55] , GOUT[63] ); - BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , POUT[56] , GOUT[64] ); - -endmodule // DBLC_2_64 - - -module DBLC_3_64 ( PIN, GIN, POUT, GOUT ); - - input [0:56] PIN; - input [0:64] GIN; - - output [0:48] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , GOUT[8] ); - BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , GOUT[9] ); - BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , GOUT[10] ); - BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , GOUT[11] ); - BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , GOUT[12] ); - BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , GOUT[13] ); - BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , GOUT[14] ); - BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , GOUT[15] ); - BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , POUT[0] , GOUT[16] ); - BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , POUT[1] , GOUT[17] ); - BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , POUT[2] , GOUT[18] ); - BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , POUT[3] , GOUT[19] ); - BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , POUT[4] , GOUT[20] ); - BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , POUT[5] , GOUT[21] ); - BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , POUT[6] , GOUT[22] ); - BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , POUT[7] , GOUT[23] ); - BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , POUT[8] , GOUT[24] ); - BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , POUT[9] , GOUT[25] ); - BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , POUT[10] , GOUT[26] ); - BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , POUT[11] , GOUT[27] ); - BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , POUT[12] , GOUT[28] ); - BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , POUT[13] , GOUT[29] ); - BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , POUT[14] , GOUT[30] ); - BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , POUT[15] , GOUT[31] ); - BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , POUT[16] , GOUT[32] ); - BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , POUT[17] , GOUT[33] ); - BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , POUT[18] , GOUT[34] ); - BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , POUT[19] , GOUT[35] ); - BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , POUT[20] , GOUT[36] ); - BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , POUT[21] , GOUT[37] ); - BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , POUT[22] , GOUT[38] ); - BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , POUT[23] , GOUT[39] ); - BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , POUT[24] , GOUT[40] ); - BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , POUT[25] , GOUT[41] ); - BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , POUT[26] , GOUT[42] ); - BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , POUT[27] , GOUT[43] ); - BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , POUT[28] , GOUT[44] ); - BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , POUT[29] , GOUT[45] ); - BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , POUT[30] , GOUT[46] ); - BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , POUT[31] , GOUT[47] ); - BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , POUT[32] , GOUT[48] ); - BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , POUT[33] , GOUT[49] ); - BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , POUT[34] , GOUT[50] ); - BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , POUT[35] , GOUT[51] ); - BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , POUT[36] , GOUT[52] ); - BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , POUT[37] , GOUT[53] ); - BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , POUT[38] , GOUT[54] ); - BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , POUT[39] , GOUT[55] ); - BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , POUT[40] , GOUT[56] ); - BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , POUT[41] , GOUT[57] ); - BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , POUT[42] , GOUT[58] ); - BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , POUT[43] , GOUT[59] ); - BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , POUT[44] , GOUT[60] ); - BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , POUT[45] , GOUT[61] ); - BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , POUT[46] , GOUT[62] ); - BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , POUT[47] , GOUT[63] ); - BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , POUT[48] , GOUT[64] ); - -endmodule // DBLC_3_64 - - -module DBLC_4_64 ( PIN, GIN, POUT, GOUT ); - - input [0:48] PIN; - input [0:64] GIN; - - output [0:32] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , GOUT[16] ); - BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , GOUT[17] ); - BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , GOUT[18] ); - BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , GOUT[19] ); - BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , GOUT[20] ); - BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , GOUT[21] ); - BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , GOUT[22] ); - BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , GOUT[23] ); - BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , GOUT[24] ); - BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , GOUT[25] ); - BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , GOUT[26] ); - BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , GOUT[27] ); - BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , GOUT[28] ); - BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , GOUT[29] ); - BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , GOUT[30] ); - BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , GOUT[31] ); - BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , POUT[0] , GOUT[32] ); - BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , POUT[1] , GOUT[33] ); - BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , POUT[2] , GOUT[34] ); - BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , POUT[3] , GOUT[35] ); - BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , POUT[4] , GOUT[36] ); - BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , POUT[5] , GOUT[37] ); - BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , POUT[6] , GOUT[38] ); - BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , POUT[7] , GOUT[39] ); - BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , POUT[8] , GOUT[40] ); - BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , POUT[9] , GOUT[41] ); - BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , POUT[10] , GOUT[42] ); - BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , POUT[11] , GOUT[43] ); - BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , POUT[12] , GOUT[44] ); - BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , POUT[13] , GOUT[45] ); - BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , POUT[14] , GOUT[46] ); - BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , POUT[15] , GOUT[47] ); - BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , POUT[16] , GOUT[48] ); - BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , POUT[17] , GOUT[49] ); - BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , POUT[18] , GOUT[50] ); - BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , POUT[19] , GOUT[51] ); - BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , POUT[20] , GOUT[52] ); - BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , POUT[21] , GOUT[53] ); - BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , POUT[22] , GOUT[54] ); - BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , POUT[23] , GOUT[55] ); - BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , POUT[24] , GOUT[56] ); - BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , POUT[25] , GOUT[57] ); - BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , POUT[26] , GOUT[58] ); - BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , POUT[27] , GOUT[59] ); - BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , POUT[28] , GOUT[60] ); - BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , POUT[29] , GOUT[61] ); - BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , POUT[30] , GOUT[62] ); - BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , POUT[31] , GOUT[63] ); - BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , POUT[32] , GOUT[64] ); - -endmodule // DBLC_4_64 - - -module DBLC_5_64 ( PIN, GIN, POUT, GOUT ); - - input [0:32] PIN; - input [0:64] GIN; - - output [0:0] POUT; - output [0:64] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - INVBLOCK U116 (GIN[16] , GOUT[16] ); - INVBLOCK U117 (GIN[17] , GOUT[17] ); - INVBLOCK U118 (GIN[18] , GOUT[18] ); - INVBLOCK U119 (GIN[19] , GOUT[19] ); - INVBLOCK U120 (GIN[20] , GOUT[20] ); - INVBLOCK U121 (GIN[21] , GOUT[21] ); - INVBLOCK U122 (GIN[22] , GOUT[22] ); - INVBLOCK U123 (GIN[23] , GOUT[23] ); - INVBLOCK U124 (GIN[24] , GOUT[24] ); - INVBLOCK U125 (GIN[25] , GOUT[25] ); - INVBLOCK U126 (GIN[26] , GOUT[26] ); - INVBLOCK U127 (GIN[27] , GOUT[27] ); - INVBLOCK U128 (GIN[28] , GOUT[28] ); - INVBLOCK U129 (GIN[29] , GOUT[29] ); - INVBLOCK U130 (GIN[30] , GOUT[30] ); - INVBLOCK U131 (GIN[31] , GOUT[31] ); - BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , GOUT[32] ); - BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , GOUT[33] ); - BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , GOUT[34] ); - BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , GOUT[35] ); - BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , GOUT[36] ); - BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , GOUT[37] ); - BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , GOUT[38] ); - BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , GOUT[39] ); - BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , GOUT[40] ); - BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , GOUT[41] ); - BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , GOUT[42] ); - BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , GOUT[43] ); - BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , GOUT[44] ); - BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , GOUT[45] ); - BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , GOUT[46] ); - BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , GOUT[47] ); - BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , GOUT[48] ); - BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , GOUT[49] ); - BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , GOUT[50] ); - BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , GOUT[51] ); - BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , GOUT[52] ); - BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , GOUT[53] ); - BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , GOUT[54] ); - BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , GOUT[55] ); - BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , GOUT[56] ); - BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , GOUT[57] ); - BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , GOUT[58] ); - BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , GOUT[59] ); - BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , GOUT[60] ); - BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , GOUT[61] ); - BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , GOUT[62] ); - BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , GOUT[63] ); - BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , POUT[0] , GOUT[64] ); - -endmodule // DBLC_5_64 - - -module XORSTAGE_64 ( A, B, PBIT, CARRY, SUM, COUT ); - - input [0:63] A; - input [0:63] B; - input PBIT; - input [0:64] CARRY; - - output [0:63] SUM; - output COUT; - - XXOR1 U20 (A[0] , B[0] , CARRY[0] , SUM[0] ); - XXOR1 U21 (A[1] , B[1] , CARRY[1] , SUM[1] ); - XXOR1 U22 (A[2] , B[2] , CARRY[2] , SUM[2] ); - XXOR1 U23 (A[3] , B[3] , CARRY[3] , SUM[3] ); - XXOR1 U24 (A[4] , B[4] , CARRY[4] , SUM[4] ); - XXOR1 U25 (A[5] , B[5] , CARRY[5] , SUM[5] ); - XXOR1 U26 (A[6] , B[6] , CARRY[6] , SUM[6] ); - XXOR1 U27 (A[7] , B[7] , CARRY[7] , SUM[7] ); - XXOR1 U28 (A[8] , B[8] , CARRY[8] , SUM[8] ); - XXOR1 U29 (A[9] , B[9] , CARRY[9] , SUM[9] ); - XXOR1 U210 (A[10] , B[10] , CARRY[10] , SUM[10] ); - XXOR1 U211 (A[11] , B[11] , CARRY[11] , SUM[11] ); - XXOR1 U212 (A[12] , B[12] , CARRY[12] , SUM[12] ); - XXOR1 U213 (A[13] , B[13] , CARRY[13] , SUM[13] ); - XXOR1 U214 (A[14] , B[14] , CARRY[14] , SUM[14] ); - XXOR1 U215 (A[15] , B[15] , CARRY[15] , SUM[15] ); - XXOR1 U216 (A[16] , B[16] , CARRY[16] , SUM[16] ); - XXOR1 U217 (A[17] , B[17] , CARRY[17] , SUM[17] ); - XXOR1 U218 (A[18] , B[18] , CARRY[18] , SUM[18] ); - XXOR1 U219 (A[19] , B[19] , CARRY[19] , SUM[19] ); - XXOR1 U220 (A[20] , B[20] , CARRY[20] , SUM[20] ); - XXOR1 U221 (A[21] , B[21] , CARRY[21] , SUM[21] ); - XXOR1 U222 (A[22] , B[22] , CARRY[22] , SUM[22] ); - XXOR1 U223 (A[23] , B[23] , CARRY[23] , SUM[23] ); - XXOR1 U224 (A[24] , B[24] , CARRY[24] , SUM[24] ); - XXOR1 U225 (A[25] , B[25] , CARRY[25] , SUM[25] ); - XXOR1 U226 (A[26] , B[26] , CARRY[26] , SUM[26] ); - XXOR1 U227 (A[27] , B[27] , CARRY[27] , SUM[27] ); - XXOR1 U228 (A[28] , B[28] , CARRY[28] , SUM[28] ); - XXOR1 U229 (A[29] , B[29] , CARRY[29] , SUM[29] ); - XXOR1 U230 (A[30] , B[30] , CARRY[30] , SUM[30] ); - XXOR1 U231 (A[31] , B[31] , CARRY[31] , SUM[31] ); - XXOR1 U232 (A[32] , B[32] , CARRY[32] , SUM[32] ); - XXOR1 U233 (A[33] , B[33] , CARRY[33] , SUM[33] ); - XXOR1 U234 (A[34] , B[34] , CARRY[34] , SUM[34] ); - XXOR1 U235 (A[35] , B[35] , CARRY[35] , SUM[35] ); - XXOR1 U236 (A[36] , B[36] , CARRY[36] , SUM[36] ); - XXOR1 U237 (A[37] , B[37] , CARRY[37] , SUM[37] ); - XXOR1 U238 (A[38] , B[38] , CARRY[38] , SUM[38] ); - XXOR1 U239 (A[39] , B[39] , CARRY[39] , SUM[39] ); - XXOR1 U240 (A[40] , B[40] , CARRY[40] , SUM[40] ); - XXOR1 U241 (A[41] , B[41] , CARRY[41] , SUM[41] ); - XXOR1 U242 (A[42] , B[42] , CARRY[42] , SUM[42] ); - XXOR1 U243 (A[43] , B[43] , CARRY[43] , SUM[43] ); - XXOR1 U244 (A[44] , B[44] , CARRY[44] , SUM[44] ); - XXOR1 U245 (A[45] , B[45] , CARRY[45] , SUM[45] ); - XXOR1 U246 (A[46] , B[46] , CARRY[46] , SUM[46] ); - XXOR1 U247 (A[47] , B[47] , CARRY[47] , SUM[47] ); - XXOR1 U248 (A[48] , B[48] , CARRY[48] , SUM[48] ); - XXOR1 U249 (A[49] , B[49] , CARRY[49] , SUM[49] ); - XXOR1 U250 (A[50] , B[50] , CARRY[50] , SUM[50] ); - XXOR1 U251 (A[51] , B[51] , CARRY[51] , SUM[51] ); - XXOR1 U252 (A[52] , B[52] , CARRY[52] , SUM[52] ); - XXOR1 U253 (A[53] , B[53] , CARRY[53] , SUM[53] ); - XXOR1 U254 (A[54] , B[54] , CARRY[54] , SUM[54] ); - XXOR1 U255 (A[55] , B[55] , CARRY[55] , SUM[55] ); - XXOR1 U256 (A[56] , B[56] , CARRY[56] , SUM[56] ); - XXOR1 U257 (A[57] , B[57] , CARRY[57] , SUM[57] ); - XXOR1 U258 (A[58] , B[58] , CARRY[58] , SUM[58] ); - XXOR1 U259 (A[59] , B[59] , CARRY[59] , SUM[59] ); - XXOR1 U260 (A[60] , B[60] , CARRY[60] , SUM[60] ); - XXOR1 U261 (A[61] , B[61] , CARRY[61] , SUM[61] ); - XXOR1 U262 (A[62] , B[62] , CARRY[62] , SUM[62] ); - XXOR1 U263 (A[63] , B[63] , CARRY[63] , SUM[63] ); - BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , COUT ); - -endmodule // XORSTAGE_64 - - -module DBLCTREE_64 ( PIN, GIN, GOUT, POUT ); - - input [0:63] PIN; - input [0:64] GIN; - - output [0:64] GOUT; - output [0:0] POUT; - - wire [0:62] INTPROP_0; - wire [0:64] INTGEN_0; - wire [0:60] INTPROP_1; - wire [0:64] INTGEN_1; - wire [0:56] INTPROP_2; - wire [0:64] INTGEN_2; - wire [0:48] INTPROP_3; - wire [0:64] INTGEN_3; - wire [0:32] INTPROP_4; - wire [0:64] INTGEN_4; - - DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) ); - DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) ); - DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) ); - DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) ); - DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) ); - DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .POUT(POUT) , .GOUT(GOUT) ); - -endmodule // DBLCTREE_64 - - -module DBLCADDER_64_64 ( OPA, OPB, CIN, SUM, COUT ); - - input [0:63] OPA; - input [0:63] OPB; - input CIN; - - output [0:63] SUM; - output COUT; - - wire [0:63] INTPROP; - wire [0:64] INTGEN; - wire [0:0] PBIT; - wire [0:64] CARRY; - - PRESTAGE_64 U1 (OPA , OPB , CIN , INTPROP , INTGEN ); - DBLCTREE_64 U2 (INTPROP , INTGEN , CARRY , PBIT ); - XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , CARRY[0:64] , SUM , COUT ); - -endmodule diff --git a/wally-pipelined/src/fpu/fpadd/cla52.v b/wally-pipelined/src/fpu/fpadd/cla52.v deleted file mode 100755 index 00fca299f..000000000 --- a/wally-pipelined/src/fpu/fpadd/cla52.v +++ /dev/null @@ -1,202 +0,0 @@ -// This module implements a 52-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla52 (S, CO, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - output CO; - - wire [0:63] A,B,Q; - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO = Q[52]; - -endmodule //cla52 diff --git a/wally-pipelined/src/fpu/fpadd/cla64.v b/wally-pipelined/src/fpu/fpadd/cla64.v deleted file mode 100755 index a0809e9d1..000000000 --- a/wally-pipelined/src/fpu/fpadd/cla64.v +++ /dev/null @@ -1,420 +0,0 @@ -// This module implements a 64-bit carry lookehead adder/subtractor. -// It is used to perform the primary addition in the floating point -// adder - -module cla64 (S, X, Y, Sub); - - input [63:0] X; - input [63:0] Y; - input Sub; - output [63:0] S; - wire CO; - wire [0:63] A,B,Q, Bbar; - - DBLCADDER_64_64 U1 (A , Bbar , Sub , Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = B ^ {64{Sub}}; - -endmodule // cla64 - -// This module performs 64-bit subtraction. It is used to get the two's complement -// of main addition or subtraction in the floating point adder. - -module cla_sub64 (S, X, Y); - - input [63:0] X; - input [63:0] Y; - - output [63:0] S; - - wire CO; - wire VDD = 1'b1; - wire [0:63] A,B,Q, Bbar; - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = ~B; - -endmodule // cla_sub64 \ No newline at end of file diff --git a/wally-pipelined/src/fpu/fpadd/convert_inputs.v b/wally-pipelined/src/fpu/fpadd/convert_inputs.v deleted file mode 100755 index 7ad934530..000000000 --- a/wally-pipelined/src/fpu/fpadd/convert_inputs.v +++ /dev/null @@ -1,61 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// the operation type (op_type) and the result precision (P). -// Based on the operation and precision , it conditionally -// converts single precision values to double precision values -// and modifies the sign of op1. The converted operands are Float1 -// and Float2. - -module convert_inputs(Float1, Float2, op1, op2, op_type, P); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [2:0] op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - - output [63:0] Float1; // Converted 1st input operand - output [63:0] Float2; // Converted 2nd input operand - - wire conv_SP; // Convert from SP to DP - wire negate; // Operation is negation - wire abs_val; // Operation is absolute value - wire Zexp1; // One if the exponent of op1 is zero - wire Zexp2; // One if the exponent of op2 is zero - wire Oexp1; // One if the exponent of op1 is all ones - wire Oexp2; // One if the exponent of op2 is all ones - - // Convert from single precision to double precision if (op_type is 11X - // and P is 0) or (op_type is not 11X and P is one). - assign conv_SP = (op_type[2]&op_type[1]) ^ P; - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] | - op1[58] | op1[57] | op1[56] | op1[55]); - assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] | - op2[58] | op2[57] | op2[56] | op2[55]); - assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] & - op1[58] & op1[57] & op1[56] & op1[55]); - assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] & - op2[58] & op2[57] & op2[56] &op2[55]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = conv_SP ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~conv_SP}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = conv_SP ? {op2[62], - {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~conv_SP}}; - - // Set the sign of Float1 based on its original sign and if the operation - // is negation (op_type = 101) or absolute value (op_type = 100) - - assign negate = op_type[2] & ~op_type[1] & op_type[0]; - assign abs_val = op_type[2] & ~op_type[1] & ~op_type[0]; - assign Float1[63] = (op1[63] ^ negate) & ~abs_val; - assign Float2[63] = op2[63]; - -endmodule // convert_inputs - diff --git a/wally-pipelined/src/fpu/fpadd/exception.v b/wally-pipelined/src/fpu/fpadd/exception.v deleted file mode 100755 index 8f5b1cd4b..000000000 --- a/wally-pipelined/src/fpu/fpadd/exception.v +++ /dev/null @@ -1,120 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. - -module exception (Ztype, Invalid, Denorm, ANorm, BNorm, Sub, A, B, op_type); - - input [63:0] A; // 1st input operand (op1) - input [63:0] B; // 2nd input operand (op2) - input [2:0] op_type; // Function opcode - output [3:0] Ztype; // Indicates type of result (Z) - output Invalid; // Invalid operation exception - output Denorm; // Denormalized input - output ANorm; // A is not zero or Denorm - output BNorm; // B is not zero or Denorm - output Sub; // The effective operation is subtraction - wire AzeroM; // '1' if the mantissa of A is zero - wire BzeroM; // '1' if the mantissa of B is zero - wire AzeroE; // '1' if the exponent of A is zero - wire BzeroE; // '1' if the exponent of B is zero - wire AonesE; // '1' if the exponent of A is all ones - wire BonesE; // '1' if the exponent of B is all ones - wire ADenorm; // '1' if A is a denomalized number - wire BDenorm; // '1' if B is a denomalized number - wire AInf; // '1' if A is infinite - wire BInf; // '1' if B is infinite - wire AZero; // '1' if A is 0 - wire BZero; // '1' if B is 0 - wire ANaN; // '1' if A is a not-a-number - wire BNaN; // '1' if B is a not-a-number - wire ASNaN; // '1' if A is a signalling not-a-number - wire BSNaN; // '1' if B is a signalling not-a-number - wire ZQNaN; // '1' if result Z is a quiet NaN - wire ZPInf; // '1' if result Z positive infnity - wire ZNInf; // '1' if result Z negative infnity - wire add_sub; // '1' if operation is add or subtract - wire converts; // See if there are any converts - - parameter [51:0] fifty_two_zeros = 52'h0000000000000; // Use parameter? - - - // Is this instruction a convert - assign converts = ~(~op_type[1] & ~op_type[2]); - - // Determine if mantissas are all zeros - assign AzeroM = (A[51:0] == fifty_two_zeros); - assign BzeroM = (B[51:0] == fifty_two_zeros); - - // Determine if exponents are all ones or all zeros - assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]; - assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]; - assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]); - assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]); - - // Determine special cases. Note: Zero is not really a special case. - assign ADenorm = AzeroE & ~AzeroM; - assign BDenorm = BzeroE & ~BzeroM; - assign AInf = AonesE & AzeroM; - assign BInf = BonesE & BzeroM; - assign ANaN = AonesE & ~AzeroM; - assign BNaN = BonesE & ~BzeroM; - assign ASNaN = ANaN & ~A[51]; - assign BSNaN = BNaN & ~B[51]; - assign AZero = AzeroE & AzeroM; - assign BZero = BzeroE & BzeroE; - - // A and B are normalized if their exponents are not zero. - assign ANorm = ~AzeroE; - assign BNorm = ~BzeroE; - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite and the "effective operation" is - // subtraction). - assign add_sub = ~op_type[2] & ~op_type[1]; - assign Invalid = (ASNaN | BSNaN | - (add_sub & AInf & BInf & (A[63]^B[63]^op_type[0]))) & ~converts; - - // The Denorm flag is set if (A is denormlized and the operation is not integer - // conversion ) or (if B is normalized and the operation is addition or subtraction). - assign Denorm = ADenorm&(op_type[2]|~op_type[1]) | BDenorm & add_sub; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN and the operation uses B). - assign ZQNaN = Invalid | ANaN | (BNaN & add_sub); - - // The result is +Inf if ((A is +Inf) or (B is -Inf and the operation is - // subtraction) or (B is +Inf and the operation is addition)) and (the - // result is not a quiet NaN). - assign ZPInf = (AInf&A[63] | add_sub&BInf&(~B[63]^op_type[0]))&~ZQNaN; - - // The result is -Inf if ((A is -Inf) or (B is +Inf and the operation is - // subtraction) or (B is -Inf and the operation is addition)) and the - // result is not a quiet NaN. - assign ZNInf = (AInf&~A[63] | add_sub&BInf&(B[63]^op_type[0]))&~ZQNaN; - - // Set the type of the result as follows: - // (needs optimization - got lazy or was late) - // Ztype Result - // 0000 Normal - // 0001 Quiet NaN - // 0010 Negative Infinity - // 0011 Positive Infinity - // 0100 +Bzero and +Azero (and vice-versa) - // 0101 +Bzero and -Azero (and vice-versa) - // 1000 Convert SP to DP (and vice-versa) - - assign Ztype[0] = ((ZQNaN | ZPInf) & ~(~op_type[2] & op_type[1])) | - ((AZero & BZero & (A[63]^B[63]^op_type[0])) - & ~converts); - assign Ztype[1] = ((ZNInf | ZPInf) & ~(~op_type[2] & op_type[1])) | - (((AZero & BZero & A[63] & B[63] & ~op_type[0]) | - (AZero & BZero & A[63] & ~B[63] & op_type[0])) - & ~converts); - assign Ztype[2] = ((AZero & BZero & ~op_type[1] & ~op_type[2]) - & ~converts); - assign Ztype[3] = (op_type[1] & op_type[2] & ~op_type[0]); - - // Determine if the effective operation is subtraction - assign Sub = add_sub & (A[63]^B[63]^op_type[0]); - -endmodule // exception - diff --git a/wally-pipelined/src/fpu/fpadd/f32_add_rd.do b/wally-pipelined/src/fpu/fpadd/f32_add_rd.do deleted file mode 100755 index 607fda622..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_add_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_add_rd.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,932 vectors, 389,365ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_add_rne.do b/wally-pipelined/src/fpu/fpadd/f32_add_rne.do deleted file mode 100755 index bc5ede611..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_add_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_add_rne.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_add_ru.do b/wally-pipelined/src/fpu/fpadd/f32_add_ru.do deleted file mode 100755 index faf652d87..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_add_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_add_ru.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,946 vectors, 389,500ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_add_rz.do b/wally-pipelined/src/fpu/fpadd/f32_add_rz.do deleted file mode 100755 index f24385dbf..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_add_rz.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_add_rz.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,111 vectors, 391,150ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_f64_rne.do b/wally-pipelined/src/fpu/fpadd/f32_f64_rne.do deleted file mode 100755 index 4f5cc2841..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_f64_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_f64_rne.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 544 vectors, 390,565ns -run 5480ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_sub_rd.do b/wally-pipelined/src/fpu/fpadd/f32_sub_rd.do deleted file mode 100755 index f4e8f6f7b..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_sub_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_sub_rd.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,932 vectors, 389,365ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_sub_rne.do b/wally-pipelined/src/fpu/fpadd/f32_sub_rne.do deleted file mode 100755 index e8efd2a22..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_sub_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_sub_rne.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_sub_ru.do b/wally-pipelined/src/fpu/fpadd/f32_sub_ru.do deleted file mode 100755 index 677584f16..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_sub_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_sub_ru.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,946 vectors, 389,500ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f32_sub_rz.do b/wally-pipelined/src/fpu/fpadd/f32_sub_rz.do deleted file mode 100755 index 031da39bf..000000000 --- a/wally-pipelined/src/fpu/fpadd/f32_sub_rz.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f32_sub_rz.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,111 vectors, 391,150ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_add_rd.do b/wally-pipelined/src/fpu/fpadd/f64_add_rd.do deleted file mode 100755 index cb6005b06..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_add_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_add_rd.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,932 vectors, 389,365ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_add_rne.do b/wally-pipelined/src/fpu/fpadd/f64_add_rne.do deleted file mode 100755 index c22ba1686..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_add_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_add_rne.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_add_ru.do b/wally-pipelined/src/fpu/fpadd/f64_add_ru.do deleted file mode 100755 index 18f340a01..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_add_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_add_ru.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,946 vectors, 389,500ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_add_rz.do b/wally-pipelined/src/fpu/fpadd/f64_add_rz.do deleted file mode 100755 index b527719e7..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_add_rz.do +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_add_rz.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,111 vectors, 391,150ns -# run 405000ns -run 100ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_f32_rne.do b/wally-pipelined/src/fpu/fpadd/f64_f32_rne.do deleted file mode 100755 index 9376da172..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_f32_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_f32_rne.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 565 vectors, 390,565ns -run 5750ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_sub_rd.do b/wally-pipelined/src/fpu/fpadd/f64_sub_rd.do deleted file mode 100755 index fcbbbfcd0..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_sub_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_sub_rd.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,927 vectors, 389,315ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_sub_rne.do b/wally-pipelined/src/fpu/fpadd/f64_sub_rne.do deleted file mode 100755 index 007c92e77..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_sub_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_sub_rne.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,059 vectors, 390,635ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_sub_ru.do b/wally-pipelined/src/fpu/fpadd/f64_sub_ru.do deleted file mode 100755 index e5afa4159..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_sub_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_sub_ru.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 38,937 vectors, 389,415ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/f64_sub_rz.do b/wally-pipelined/src/fpu/fpadd/f64_sub_rz.do deleted file mode 100755 index cc807b080..000000000 --- a/wally-pipelined/src/fpu/fpadd/f64_sub_rz.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog convert_inputs.v exception.v lzd.v shifter.v adder.v cla52.v cla64.v rounder.v fpadd.v tb_f64_sub_rz.sv - -# start and run simulation -vsim -novopt work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /tb/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,113 vectors, 391,175ns -run 405000ns -quit diff --git a/wally-pipelined/src/fpu/fpadd/fpadd.v b/wally-pipelined/src/fpu/fpadd/fpadd.v deleted file mode 100755 index 7f5f05ebc..000000000 --- a/wally-pipelined/src/fpu/fpadd/fpadd.v +++ /dev/null @@ -1,216 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr. -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// -// Basic Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - - -module fpadd (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [2:0] rm; // Rounding mode - specify values - input [2:0] op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - - wire [63:0] Float1; - wire [63:0] Float2; - wire [63:0] IntValue; - wire [11:0] exp1, exp2; - wire [11:0] exp_diff1, exp_diff2; - wire [10:0] exponent, exp_pre; - wire [11:0] exp_shift; - wire [63:0] Result; - wire [51:0] mantissaA; - wire [56:0] mantissaA1; - wire [63:0] mantissaA3; - wire [51:0] mantissaB; - wire [56:0] mantissaB1, mantissaB2; - wire [63:0] mantissaB3; - wire [63:0] sum, sum_tc, sum_corr, sum_norm; - wire [5:0] align_shift; - wire [5:0] norm_shift; - wire [3:0] sel_inv; - wire op1_Norm, op2_Norm; - wire opA_Norm, opB_Norm; - wire Invalid; - wire DenormIn, DenormIO; - wire [4:0] FlagsIn; - wire exp_valid; - wire exp_gt63; - wire Sticky_out; - wire signA, sign_corr; - wire corr_sign; - wire zeroB; - wire convert; - wire swap; - wire sub; - - // Convert the input operands to their appropriate forms based on - // the orignal operands, the op_type , and their precision P. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - - convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P); - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if op1 and op2 are not zero or denormalized. - // sub is one if the effective operation is subtaction. - - exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, sub, - Float1, Float2, op_type); - - // Perform Exponent Subtraction (used for alignment). For performance - // both exponent subtractions are performed in parallel. This was - // changed to a behavior level to allow the tools to try to optimize - // the two parallel additions. The input values are zero-extended to 12 - // bits prior to performing the addition. - - assign exp1 = {1'b0, Float1[62:52]}; - assign exp2 = {1'b0, Float2[62:52]}; - assign exp_diff1 = exp1 - exp2; - assign exp_diff2 = exp2 - exp1; - - // The second operand (B) should be set to zero, if op_type does not - // specify addition or subtraction - assign zeroB = op_type[2] | op_type[1]; - - // Swapped operands if zeroB is not one and exp1 < exp2. - // Swapping causes exp2 to be used for the result exponent. - // Only the exponent of the larger operand is used to determine - // the final result. - assign swap = exp_diff1[11] & ~zeroB; - assign exponent = swap ? exp2[10:0] : exp1[10:0]; - assign mantissaA = swap ? Float2[51:0] : Float1[51:0]; - assign mantissaB = swap ? Float1[51:0] : Float2[51:0]; - assign signA = swap ? Float2[63] : Float1[63]; - - // Determine the alignment shift and limit it to 63. If any bit from - // exp_shift[6] to exp_shift[11] is one, then shift is set to all ones. - assign exp_shift = swap ? exp_diff2 : exp_diff1; - assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9] - | exp_shift[8] | exp_shift[7] | exp_shift[6]; - assign align_shift = exp_shift | {6{exp_gt63}}; - - // Unpack the 52-bit mantissas to 57-bit numbers of the form. - // 001.M[51]M[50] ... M[1]M[0]00 - // Unless the number has an exponent of zero, in which case it - // is unpacked as - // 000.00 ... 00 - // This effectively flushes denormalized values to zero. - // The three bits of to the left of the binary point prevent overflow - // and loss of sign information. The two bits to the right of the - // original mantissa form the "guard" and "round" bits that are used - // to round the result. - assign opA_Norm = swap ? op2_Norm : op1_Norm; - assign opB_Norm = swap ? op1_Norm : op2_Norm; - assign mantissaA1 = {2'h0, opA_Norm, mantissaA[51:0]&{52{opA_Norm}}, 2'h0}; - assign mantissaB1 = {2'h0, opB_Norm, mantissaB[51:0]&{52{opB_Norm}}, 2'h0}; - - // Perform mantissa alignment using a 57-bit barrel shifter - // If any of the bits shifted out are one, Sticky_out is set. - // The size of the barrel shifter could be reduced by two bits - // by not adding the leading two zeros until after the shift. - barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift); - - // Place either the sign-extened 32-bit value or the original 64-bit value - // into IntValue (to be used for integer to floating point conversion) - assign IntValue [31:0] = op1[31:0]; - assign IntValue [63:32] = op_type[0] ? {32{op1[31]}} : op1[63:32]; - - // If doing an integer to floating point conversion, mantissaA3 is set to - // IntVal and the prenomalized exponent is set to 1084. Otherwise, - // mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero, - // and the exponent value is left unchanged. - assign convert = ~op_type[2] & op_type[1]; - assign mantissaA3 = convert ? IntValue : {mantissaA1, 7'h0}; - assign exp_pre = convert ? 11'b10000111100 : exponent; - - // Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to - // 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six - // zeros. - assign mantissaB3[63:7] = mantissaB2 & {57{~zeroB}}; - assign mantissaB3[6] = Sticky_out & ~zeroB; - assign mantissaB3[5:0] = 6'h0; - - // The sign of the result needs to be corrected if the true - // operation is subtraction and the input operands were swapped. - assign corr_sign = ~op_type[2]&~op_type[1]&op_type[0]&swap; - - // 64-bit Mantissa Adder/Subtractor - cla64 add1 (sum, mantissaA3, mantissaB3, sub); - - // 64-bit Mantissa Subtractor - to get the two's complement of the - // result when the sign from the adder/subtractor is negative. - cla_sub64 sub1 (sum_tc, mantissaB3, mantissaA3); - - // Determine the correct sign of the result - assign sign_corr = ((corr_sign ^ signA) & ~convert) ^ sum[63]; - - // If the sum is negative, use its two complement instead. - // This value has to be 64-bits to correctly handle the - // case 10...00 - assign sum_corr = sum[63] ? sum_tc : sum; - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - lz64 lzd1 (norm_shift, exp_valid, sum_corr); - - // Barell shifter used for normalization. It takes as inputs the - // the corrected sum and the amount by which the sum should - // be right shifted. It outputs the normalized sum. - barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. If the result is a single precision number, the actual - // mantissa is in the upper 23 bits and the lower 29 bits are zero. - // At this point, normalization has already been performed, so we know - // exactly where the rounding point is. The rounding units also - // handles special cases and set the exception flags. - - // Changed DenormIO -> Denorm and FlagsIn -> Flags in order to - // help in processor reservation station detection of load/stores. In - // other words, the processor would like to know ahead of time that - // if the result is an exception then don't load or store. - rounder round1 (Result, DenormIO, FlagsIn, rm, P, OvEn, UnEn, exp_valid, - sel_inv, Invalid, DenormIn, convert, sign_corr, exp_pre, - norm_shift, sum_norm); - - // Store the final result and the exception flags in registers. - assign AS_Result = Result; - assign {Denorm, Flags} = {DenormIO, FlagsIn}; - -endmodule // fpadd - - diff --git a/wally-pipelined/src/fpu/fpadd/lzd.v b/wally-pipelined/src/fpu/fpadd/lzd.v deleted file mode 100755 index b3a141608..000000000 --- a/wally-pipelined/src/fpu/fpadd/lzd.v +++ /dev/null @@ -1,137 +0,0 @@ -// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular -// leading zero detector circuit," in Electronics Letters, vol. 29, -// no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193. - -module lz2 (P, V, B0, B1); - - input B0; - input B1; - - output P; - output V; - - assign V = B0 | B1; - assign P = B0 & ~B1; - -endmodule // lz2 - -// Note: This module is not made out of two lz2's - why not? (MJS) - -module lz4 (ZP, ZV, B0, B1, V0, V1); - - input B0; - input B1; - input V0; - input V1; - - output [1:0] ZP; - output ZV; - - assign ZP[0] = V0 ? B0 : B1; - assign ZP[1] = ~V0; - assign ZV = V0 | V1; - -endmodule // lz4 - -// Note: This module is not made out of two lz4's - why not? (MJS) - -module lz8 (ZP, ZV, B); - - input [7:0] B; - - wire s1p0; - wire s1v0; - wire s1p1; - wire s1v1; - wire s2p0; - wire s2v0; - wire s2p1; - wire s2v1; - wire [1:0] ZPa; - wire [1:0] ZPb; - wire ZVa; - wire ZVb; - - output [2:0] ZP; - output ZV; - - lz2 l1(s1p0, s1v0, B[2], B[3]); - lz2 l2(s1p1, s1v1, B[0], B[1]); - lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1); - - lz2 l4(s2p0, s2v0, B[6], B[7]); - lz2 l5(s2p1, s2v1, B[4], B[5]); - lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1); - - assign ZP[1:0] = ZVb ? ZPb : ZPa; - assign ZP[2] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz8 - -module lz16 (ZP, ZV, B); - - input [15:0] B; - - wire [2:0] ZPa; - wire [2:0] ZPb; - wire ZVa; - wire ZVb; - - output [3:0] ZP; - output ZV; - - lz8 l1(ZPa, ZVa, B[7:0]); - lz8 l2(ZPb, ZVb, B[15:8]); - - assign ZP[2:0] = ZVb ? ZPb : ZPa; - assign ZP[3] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz16 - -module lz32 (ZP, ZV, B); - - input [31:0] B; - - wire [3:0] ZPa; - wire [3:0] ZPb; - wire ZVa; - wire ZVb; - - output [4:0] ZP; - output ZV; - - lz16 l1(ZPa, ZVa, B[15:0]); - lz16 l2(ZPb, ZVb, B[31:16]); - - assign ZP[3:0] = ZVb ? ZPb : ZPa; - assign ZP[4] = ~ZVb; - assign ZV = ZVa | ZVb; - -endmodule // lz32 - -// This module returns the number of leading zeros ZP in the 64-bit -// number B. If there are no ones in B, then ZP and ZV are both 0. - -module lz64 (ZP, ZV, B); - - input [63:0] B; - - wire [4:0] ZPa; - wire [4:0] ZPb; - wire ZVa; - wire ZVb; - - output [5:0] ZP; - output ZV; - - lz32 l1(ZPa, ZVa, B[31:0]); - lz32 l2(ZPb, ZVb, B[63:32]); - - assign ZV = ZVa | ZVb; - assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}}; - assign ZP[5] = ~ZVb & ZV; - -endmodule // lz64 - diff --git a/wally-pipelined/src/fpu/fpadd/rounder.v b/wally-pipelined/src/fpu/fpadd/rounder.v deleted file mode 100755 index b994acb30..000000000 --- a/wally-pipelined/src/fpu/fpadd/rounder.v +++ /dev/null @@ -1,214 +0,0 @@ -// The rounder takes as inputs a 64-bit value to be rounded, A, the -// exponent of the value to be rounded, the sign of the final result, Sign, -// the precision of the results, P, and the two-bit rounding mode, rm. -// It produces a rounded 52-bit result, Z, the exponent of the rounded -// result, Z_exp, and a flag that indicates if the result was rounded, -// Inexact. The rounding mode has the following values. -// rm Modee -// 00 round-to-nearest-even -// 01 round-toward-zero -// 10 round-toward-plus infinity -// 11 round-toward-minus infinity -// The rounding algorithm determines if '1' should be added to the -// truncated signficant result, based on three significant bits -// (least (L), round (R) and sticky (S)), the rounding mode (rm) -// and the sign of the final result (Sign). Visually, L and R appear as -// xxxxxL,Rxxxxxxx -// where , denotes the rounding boundary. S is the logical OR of all the -// bits to the right of R. - -module rounder (Result, DenormIO, Flags, rm, P, OvEn, - UnEn, exp_valid, sel_inv, Invalid, DenormIn, convert, Asign, Aexp, - norm_shift, A); - - input [2:0] rm; - input P; - input OvEn; - input UnEn; - input exp_valid; - input [3:0] sel_inv; - input Invalid; - input DenormIn; - input convert; - input Asign; - input [10:0] Aexp; - input [5:0] norm_shift; - input [63:0] A; - - output [63:0] Result; - output DenormIO; - output [4:0] Flags; - - wire Rsign; - wire [10:0] Rexp; - wire [11:0] Texp; - wire [51:0] Rmant; - wire [51:0] Tmant; - wire Rzero; - wire VSS = 1'b0; - wire VDD = 1'b1; - wire [51:0] B; // Value used to add the "ones" - wire S_SP; // Single precision sticky bit - wire S_DP; // Double precision sticky bit - wire S; // Actual sticky bit - wire R; // Round bit - wire L; // Least significant bit - wire add_one; // '1' if one should be added - wire UnFlow_SP, UnFlow_DP, UnderFlow; - wire OvFlow_SP, OvFlow_DP, OverFlow; - wire Inexact; - wire Round_zero; - wire Infinite; - wire VeryLarge; - wire Largest; - wire Adj_exp; - wire Valid; - wire NaN; - wire Cout; - wire Texp_l7z; - wire Texp_l7o; - wire OvCon; - - // Determine the sticky bits for double and single precision - assign S_DP= A[9]|A[8]|A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]; - assign S_SP = S_DP |A[38]|A[37]|A[36]|A[35]|A[34]|A[33]|A[32]|A[31]|A[30]| - A[29]|A[28]|A[27]|A[26]|A[25]|A[24]|A[23]|A[22]|A[21]|A[20]| - A[19]|A[18]|A[17]|A[16]|A[15]|A[14]|A[13]|A[12]|A[11]|A[10]; - - // Set the least (L), round (R), and sticky (S) bits based on - // the precision. - assign {L, R, S} = P ? {A[40],A[39],S_SP} : {A[11],A[10],S_DP}; - - // Add one if ((the rounding mode is round-to-nearest) and (R is one) and - // (S or L is one)) or ((the rounding mode is towards plus or minus - // infinity (rm[1] = 1)) and (the sign and rm[0] are the same) and - // (R or S is one)). - - // Appended statement allows for roundTiesAway: if the rounding mode is round-towards-away, - // then if the sign of the result is 0 (i.e., positive), then add_one; otherwise, add zero. - - assign add_one = ~rm[2] & ((~rm[1]&~rm[0]&R&(L|S)) | (rm[1]&(Asign^~rm[0])&(R|S))) | (rm[2] & R); - - // Add one using a 52-bit adder. The one is added to the LSB B[0] for - // double precision or to B[29] for single precision. - // This could be simplified by using a specialized adder. - // The current adder is actually 64-bits. The leading one - // for normalized results in not included in the addition. - assign B = {{22{VSS}}, add_one&P, {28{VSS}}, add_one&~P}; - cla52 add1(Tmant, Cout, A[62:11], B); - - // Now that rounding is done, we compute the final exponent - // and test for special cases. - - // Compute the value of the exponent by subtracting the shift - // value from the previous exponent and then adding 2 + cout. - // If needed this could be optimized to used a specialized - // adder. - - assign Texp = {VSS, Aexp} - {{6{VSS}}, norm_shift} +{{10{VSS}}, VDD, Cout}; - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o; - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11] is one) or Texp[10] to - // Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = Texp[11] | ~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = (~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z)); - - // Set the overflow and underflow flags. They should not be set if - // the input was infinite or NaN or the output of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]); - assign NaN = ~sel_inv[2]&~sel_inv[1]& sel_inv[0]; - assign UnderFlow = ((P & UnFlow_SP | UnFlow_DP)&Valid&exp_valid) | - (~Aexp[10]&Aexp[9]&Aexp[8]&Aexp[7]&~Aexp[6] - &~Aexp[5]&~Aexp[4]&~Aexp[3]&~Aexp[2] - &~Aexp[1]&~Aexp[0]&sel_inv[3]); - assign OverFlow = (P & OvFlow_SP | OvFlow_DP)&Valid&~UnderFlow&exp_valid; - - // The DenormIO is set if underflow has occurred or if their was a - // denormalized input. - assign DenormIO = DenormIn | UnderFlow; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (R|S|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {UnderFlow, VSS, OverFlow, Invalid, Inexact}; - - // Determine the final result. - - // The sign of the final result is one if the result is not zero and - // the sign of A is one, or if the result is zero and the the rounding - // mode is round-to-minus infinity. The final result is zero, if exp_valid - // is zero. If underflow occurs, then the result is set to zero. - // - // For Zero (goes equally for subtraction although - // signs may alter operands sign): - // -0 + -0 = -0 (always) - // +0 + +0 = +0 (always) - // -0 + +0 = +0 (for RN, RZ, RU) - // -0 + +0 = -0 (for RD) - assign Rzero = ~exp_valid | UnderFlow; - assign Rsign = ((Asign&exp_valid | - (sel_inv[2]&~sel_inv[1]&sel_inv[0]&rm[1]&rm[0] | - sel_inv[2]&sel_inv[1]&~sel_inv[0] | - ~exp_valid&rm[1]&rm[0]&~sel_inv[2] | - UnderFlow&rm[1]&rm[0]) & ~convert) & ~sel_inv[3]) | - (Asign & sel_inv[3]); - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~Asign&rm[0] | Asign&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | (~sel_inv[2] & sel_inv[1]); - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn & ~convert; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - assign Rmant[51] = Largest | NaN | (Tmant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = {51{Largest}} | (Tmant[50:0]&{51{~Infinite&Valid&~Rzero}}); - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - assign OvCon = OverFlow & OvEn & convert; - assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{VSS}}} - : {Rsign, Rexp, Rmant}; - -endmodule // rounder - diff --git a/wally-pipelined/src/fpu/fpadd/shifter.v b/wally-pipelined/src/fpu/fpadd/shifter.v deleted file mode 100755 index 7a85fc6ac..000000000 --- a/wally-pipelined/src/fpu/fpadd/shifter.v +++ /dev/null @@ -1,119 +0,0 @@ - -// MJS - This module implements a 57-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand alignment. - -module mux21x57 (Z, A, B, Sel); - - input [56:0] A; - input [56:0] B; - input Sel; - - output [56:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x57 - -// MJS - This module implements a 64-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand normalization. - -module mux21x64 (Z, A, B, Sel); - - input [63:0] A; - input [63:0] B; - input Sel; - - output [63:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x64 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 64-bit 2-to-1 muxes. The -// barrel shifter takes a 64-bit input A and shifts it left by up to -// 63-bits, as specified by Shift, to produce a 63-bit output Z. -// Bits to the right are filled with zeros. -// The 64 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bit shifts. - -module barrel_shifter_l64 (Z, A, Shift); - - input [63:0] A; - input [5:0] Shift; - - wire [63:0] stage1; - wire [63:0] stage2; - wire [63:0] stage3; - wire [63:0] stage4; - wire [63:0] stage5; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - - output [63:0] Z; - - mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]); - mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]); - mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]); - mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]); - mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]); - mux21x64 mx06(Z , stage5, {stage5[62:0], onezero}, Shift[0]); - -endmodule // barrel_shifter_l63 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 57-bit 2-to-1 muxes. The -// barrel shifter takes a 57-bit input A and right shifts it by up to -// 63-bits, as specified by Shift, to produce a 57-bit output Z. -// It also computes a Sticky bit, which is set to -// one if any of the bits that were shifted out was one. -// Bits shifted into the left are filled with zeros. -// The 63 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bits. - -module barrel_shifter_r57 (Z, Sticky, A, Shift); - - input [56:0] A; - input [5:0] Shift; - - output Sticky; - output [56:0] Z; - - wire [56:0] stage1; - wire [56:0] stage2; - wire [56:0] stage3; - wire [56:0] stage4; - wire [56:0] stage5; - wire [62:0] sixtythreezeros = 63'h0; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - wire [62:0] S; - - // Shift operations - mux21x57 mx01(stage1, A, {thirtytwozeros, A[56:32]}, Shift[5]); - mux21x57 mx02(stage2, stage1, {sixteenzeros, stage1[56:16]}, Shift[4]); - mux21x57 mx03(stage3, stage2, {eightzeros, stage2[56:8]}, Shift[3]); - mux21x57 mx04(stage4, stage3, {fourzeros, stage3[56:4]}, Shift[2]); - mux21x57 mx05(stage5, stage4, {twozeros, stage4[56:2]}, Shift[1]); - mux21x57 mx06(Z , stage5, {onezero, stage5[56:1]}, Shift[0]); - - // Sticky bit calculation. The Sticky bit is set to one if any of the - // bits that were shifter out were one - - assign S[31:0] = {32{Shift[5]}} & A[31:0]; - assign S[47:32] = {16{Shift[4]}} & stage1[15:0]; - assign S[55:48] = { 8{Shift[3]}} & stage2[7:0]; - assign S[59:56] = { 4{Shift[2]}} & stage3[3:0]; - assign S[61:60] = { 2{Shift[1]}} & stage4[1:0]; - assign S[62] = Shift[0] & stage5[0]; - assign Sticky = (S != sixtythreezeros); - -endmodule // barrel_shifter_r57 \ No newline at end of file diff --git a/wally-pipelined/src/fpu/fpadd/tb.v b/wally-pipelined/src/fpu/fpadd/tb.v deleted file mode 100755 index e3c655592..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb.v +++ /dev/null @@ -1,86 +0,0 @@ -// -// File name : tb.v -// Title : stimulus -// project : mult -// Library : test -// Author(s) : James E. Stine, Jr. -// Purpose : definition of modules for testbench -// notes : -// -// Copyright Oklahoma State University -// - -// Top level stimulus module - -module stimulus; - - reg clk; // Always declared so can simulate based on clock - - // Declare variables for stimulating input - reg [63:0] op1; - reg [63:0] op2; - reg [1:0] rm; - reg [2:0] op_type; - reg P; - reg OvEn; - reg UnEn; - - wire [63:0] AS_Result; - wire [4:0] Flags; - wire Denorm; - - integer handle3; - integer desc3; - - // Instantiate the design block counter - fpadd dut (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P , OvEn, UnEn); - - // Setup the clock to toggle every 1 time units - initial - begin - clk = 1'b1; - forever #25 clk = ~clk; - end - - initial - begin - handle3 = $fopen("tb.out"); - end - - always @(posedge clk) - begin - desc3 = handle3; - #5 $display(desc3, "%h %h || %h", op1, op2, AS_Result); - end - - // Stimulate the Input Signals - initial - begin - // Add your test vectors here - $display("%h", AS_Result); - #0 rm = 2'b00; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #0 op1 = 64'h4031e147ae147ae1; - #0 op2 = 64'h4046e147ae147ae1; - $display("%h", AS_Result); - #200; - #0 rm = 2'b00; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #0 op1 = 64'h4031e147ae147ae1; - #0 op2 = 64'h4046e147ae147ae1; - $display("%h", AS_Result); - - end - -endmodule // stimulus - - - - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rd.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_add_rd.sv deleted file mode 100755 index 9b2060cbe..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rd.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_add_rd.out"); - $readmemh("f32_add_rd.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b1; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_add_rne.sv deleted file mode 100755 index 49e70bae2..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rne.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_add_rne.out"); - $readmemh("f32_add_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b1; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_add_ru.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_add_ru.sv deleted file mode 100755 index c6dabea33..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_add_ru.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_add_ru.out"); - $readmemh("f32_add_ru.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b1; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rz.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_add_rz.sv deleted file mode 100755 index 95ee92876..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_add_rz.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_add_rz.out"); - $readmemh("f32_add_rz.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b1; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_f64_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_f64_rne.sv deleted file mode 100755 index d0766c2b5..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_f64_rne.sv +++ /dev/null @@ -1,75 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_f64_rne.out"); - $readmemh("f32_f64_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b110; - #0 P = 1'b0; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #0 op2 = 64'h0; - #1; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rd.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rd.sv deleted file mode 100755 index 366e4d769..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rd.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_sub_rd.out"); - $readmemh("f32_sub_rd.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b1; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rne.sv deleted file mode 100755 index b8fca3597..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rne.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_sub_rne.out"); - $readmemh("f32_sub_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b1; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_ru.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_sub_ru.sv deleted file mode 100755 index 158ff474e..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_ru.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_sub_ru.out"); - $readmemh("f32_sub_ru.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b1; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h", op1, op2, result); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rz.sv b/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rz.sv deleted file mode 100755 index ef8eb65ef..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f32_sub_rz.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, - rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f32_sub_rz.out"); - $readmemh("f32_sub_rz.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b1; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rd.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_add_rd.sv deleted file mode 100755 index 0f37bca43..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rd.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_add_rd.out"); - $readmemh("f64_add_rd.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_add_rne.sv deleted file mode 100755 index 1e4733570..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rne.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [2:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_add_rne.out"); - $readmemh("f64_add_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 rm = 3'b000; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_add_ru.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_add_ru.sv deleted file mode 100755 index 191cca388..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_add_ru.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_add_ru.out"); - $readmemh("f64_add_ru.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rz.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_add_rz.sv deleted file mode 100755 index 6a4df7973..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_add_rz.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [2:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_add_rz.out"); - $readmemh("f64_add_rz.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b000; - #0 P = 1'b0; - #0 rm = 3'b001; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_f32_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_f32_rne.sv deleted file mode 100755 index 53eb25982..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_f32_rne.sv +++ /dev/null @@ -1,79 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [31:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_f32_rne.out"); - $readmemh("f64_f32_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b110; - #0 P = 1'b1; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #0 op2 = 64'h0; - #1; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result[63:32] !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rd.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rd.sv deleted file mode 100755 index a427ebf95..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rd.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_sub_rd.out"); - $readmemh("f64_sub_rd.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b0; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rne.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rne.sv deleted file mode 100755 index dd25bd037..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rne.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_sub_rne.out"); - $readmemh("f64_sub_rne.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b0; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_ru.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_sub_ru.sv deleted file mode 100755 index d16ea7c24..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_ru.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_sub_ru.out"); - $readmemh("f64_sub_ru.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b0; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rz.sv b/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rz.sv deleted file mode 100755 index e68ec215b..000000000 --- a/wally-pipelined/src/fpu/fpadd/tb_f64_sub_rz.sv +++ /dev/null @@ -1,78 +0,0 @@ -// testbench -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic [2:0] op_type; - logic P; - logic OvEn; - logic UnEn; - - logic [63:0] result; - logic [4:0] Flags; - logic Denorm; - - logic clk; - logic [63:0] yexpected; - logic reset; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpadd dut (result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn); - - always - begin - clk = 1; #5; clk = 0; #5; - end - - initial - begin - handle3 = $fopen("f64_sub_rz.out"); - $readmemh("f64_sub_rz.tv", testvectors); - vectornum = 0; errors = 0; - reset = 1; #27; reset = 0; - end - - always @(posedge clk) - begin - desc3 = handle3; - #0 op_type = 3'b001; - #0 P = 1'b0; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - #1; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #5 $fdisplay(desc3, "%h_%h_%h_%b", op1, op2, result, Flags); - end - - // check results on falling edge of clk - always @(negedge clk) - if (~reset) - begin // skip during reset - if (result !== yexpected) begin - $display("Error: inputs = %h %h", op1, op2); - $display(" outputs = %h (%h expected)", result, yexpected); - errors = errors + 1; - end - //else - //begin - //$display("Good"); - // end - - vectornum = vectornum + 1; - if (testvectors[vectornum] === 56'bx) - begin - $display("%d tests completed with %d errors", - vectornum, errors); - end - end // if (~reset) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpdiv.sv b/wally-pipelined/src/fpu/fpdiv.sv index 454896a1c..f31b7e573 100755 --- a/wally-pipelined/src/fpu/fpdiv.sv +++ b/wally-pipelined/src/fpu/fpdiv.sv @@ -23,24 +23,23 @@ // // `timescale 1ps/1ps -module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [1:0] rm; // Rounding mode - specify values - input op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - input start; - input reset; - input clk; - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - logic done; +module fpdiv ( + input logic [63:0] op1, // 1st input operand (A) + input logic [63:0] op2, // 2nd input operand (B) + input logic [1:0] rm, // Rounding mode - specify values + input logic op_type, // Function opcode + input logic P, // Result Precision (0 for double, 1 for single) + input logic OvEn, // Overflow trap enabled + input logic UnEn, // Underflow trap enabled + input logic start, + input logic reset, + input logic clk, + output logic done, + output logic FDivBusyE, + output logic HoldInputs, + output logic [63:0] AS_Result, // Result of operation + output logic [4:0] Flags); // IEEE exception flags + logic Denorm; // Denorm on input or output // output done; supply1 vdd; @@ -89,7 +88,9 @@ module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, wire donev, sel_muxrv, sel_muxsv; wire [1:0] sel_muxav, sel_muxbv; wire load_regav, load_regbv, load_regcv; - wire load_regrv, load_regsv; + wire load_regrv, load_regs; + logic exp_cout1, exp_cout2; + logic exp_odd, open; // Convert the input operands to their appropriate forms based on // the orignal operands, the op_type , and their precision P. @@ -107,7 +108,7 @@ module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, Float1, Float2, op_type); // Determine Sign/Mantissa - assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type; + assign signResult = (Float1[63]^Float2[63]); assign mantissaA = {vdd, Float1[51:0]}; assign mantissaB = {vdd, Float2[51:0]}; // Perform Exponent Subtraction - expA - expB + Bias @@ -117,11 +118,13 @@ module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, assign bias = {3'h0, 10'h3FF}; // Divide exponent csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c); - adder #(14) explogic1 ({vss, exp_s}, {vss, exp_c}, 1'b1, {open, exp_diff}, exp_cout1); + // adder #(14) explogic1 ({vss, exp_s}, {vss, exp_c}, 1'b1, {open, exp_diff}, exp_cout1); + assign {exp_cout1, open, exp_diff} = {vss, exp_s} + {vss, exp_c} + 1'b1; // Sqrt exponent (check if exponent is odd) assign exp_odd = Float1[52] ? vss : vdd; - adder #(14) explogic2 ({vss, exp1}, {4'h0, 10'h3ff}, exp_odd, exp_sqrt, exp_cout2); + // adder #(14) explogic2 ({vss, exp1}, {4'h0, 10'h3ff}, exp_odd, exp_sqrt, exp_cout2); + assign {exp_cout2, exp_sqrt} = {vss, exp1} + {4'h0, 10'h3ff} + exp_odd; // Choose correct exponent assign expF = op_type ? exp_sqrt[13:1] : exp_diff; @@ -132,9 +135,9 @@ module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, load_regr, load_regs, P, op_type, exp_odd); // FSM : control divider - fsm_div control (done, load_rega, load_regb, load_regc, load_regd, + fsm control (done, load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); + clk, reset, start, op_type, FDivBusyE, HoldInputs); // Round the mantissa to a 52-bit value, with the leading one // removed. The rounding units also handles special cases and @@ -150,3 +153,4 @@ module fpdiv (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, flopenr #(5) regc (clk, reset, done, FlagsIn, Flags); endmodule // fpadd + diff --git a/wally-pipelined/src/fpu/fpdivsqrt/convert_inputs_div.sv b/wally-pipelined/src/fpu/fpdivsqrt/convert_inputs_div.sv deleted file mode 100755 index 0d4d72949..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/convert_inputs_div.sv +++ /dev/null @@ -1,50 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// and the result precision (P). Based on the operation and precision, -// it conditionally converts single precision values to double -// precision values and modifies the sign of op1. -// The converted operands are Float1 and Float2. -module convert_inputs_div (Float1, Float2b, op1, op2, op_type, P); - - input logic [63:0] op1; // 1st input operand (A) - input logic [63:0] op2; // 2nd input operand (B) - input logic P; // Result Precision (0 for double, 1 for single) - input logic op_type; // Operation - - output logic [63:0] Float1; // Converted 1st input operand - output logic [63:0] Float2b; // Converted 2nd input operand - - logic [63:0] Float2; - logic Zexp1; // One if the exponent of op1 is zero - logic Zexp2; // One if the exponent of op2 is zero - logic Oexp1; // One if the exponent of op1 is all ones - logic Oexp2; // One if the exponent of op2 is all ones - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(op1[62] | op1[61] | op1[60] | op1[59] | - op1[58] | op1[57] | op1[56] | op1[55]); - assign Zexp2 = ~(op2[62] | op2[61] | op2[60] | op2[59] | - op2[58] | op2[57] | op2[56] | op2[55]); - assign Oexp1 = (op1[62] & op1[61] & op1[60] & op1[59] & - op1[58] & op1[57] & op1[56] & op1[55]); - assign Oexp2 = (op2[62] & op2[61] & op2[60] & op2[59] & - op2[58] & op2[57] & op2[56] &op2[55]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = P ? {op1[62], {3{(~op1[62]&~Zexp1)|Oexp1}}, op1[61:32]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~P}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = P ? {op2[62], {3{(~op2[62]&~Zexp2)|Oexp2}}, op2[61:32]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~P}}; - - // Set the sign of Float1 based on its original sign - assign Float1[63] = op1[63]; - assign Float2[63] = op2[63]; - - // For sqrt, assign Float2 same as Float1 for simplicity - assign Float2b = op_type ? Float1 : Float2; - -endmodule // convert_inputs diff --git a/wally-pipelined/src/fpu/fpdivsqrt/divconv.sv b/wally-pipelined/src/fpu/fpdivsqrt/divconv.sv deleted file mode 100755 index 8fdddaa48..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/divconv.sv +++ /dev/null @@ -1,256 +0,0 @@ -`timescale 1ps/1ps -module divconv (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, - regr_out, d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk, load_rega, load_regb, - load_regc, load_regd, load_regr, load_regs, P, op_type, exp_odd); - - input logic [52:0] d, n; - input logic [2:0] sel_muxa, sel_muxb; - input logic sel_muxr; - input logic load_rega, load_regb, load_regc, load_regd; - input logic load_regr, load_regs; - input logic P; - input logic op_type; - input logic exp_odd; - input logic reset; - input logic clk; - - output logic [63:0] q1, qp1, qm1; - output logic [63:0] q0, qp0, qm0; - output logic [63:0] rega_out, regb_out, regc_out, regd_out; - output logic [127:0] regr_out; - - supply1 vdd; - supply0 vss; - - logic [63:0] muxa_out, muxb_out; - logic [10:0] ia_div, ia_sqrt; - logic [63:0] ia_out; - logic [127:0] mul_out; - logic [63:0] q_out1, qm_out1, qp_out1; - logic [63:0] q_out0, qm_out0, qp_out0; - logic [63:0] mcand, mplier, mcand_q; - logic [63:0] twocmp_out; - logic [64:0] three; - logic [127:0] Carry, Carry2; - logic [127:0] Sum, Sum2; - logic [127:0] constant, constant2; - logic [63:0] q_const, qp_const, qm_const; - logic [63:0] d2, n2; - logic [11:0] d3; - - // Check if exponent is odd for sqrt - // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {vss,d,10'h0} : {d,11'h0}; - assign n2 = op_type ? d2 : {n,11'h0}; - - // IA div/sqrt - sbtm ia1 (d[52:41], ia_div); - sbtm2 ia2 (d2[63:52], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}}; - - // Choose IA or iteration - mux6 #(64) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(64) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); - - // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(128) mx3a ({~n, {75{1'b1}}}, {{1'b1}, ~n, {74{1'b1}}}, q1[63], constant2); - // Select Mcand, Remainder/Q'' - mux2 #(128) mx3 (128'h0, constant2, sel_muxr, constant); - // Select mcand - remainder should always choose q1 [1,2) because - // adjustment of N in the from XX.FFFFFFF - mux2 #(64) mx4 (q0, q1, q1[63], mcand_q); - mux2 #(64) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(64) mx6 (muxa_out, mcand_q, sel_muxr, mcand); - // TDM multiplier (carry/save) - multiplier mult1 (mcand, mplier, Sum, Carry); - // Q*D - N (reversed but changed in rounder.v to account for sign reversal) - csa #(128) csa1 (Sum, Carry, constant, Sum2, Carry2); - // Add ulp for subtraction in remainder - mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); - - // Constant for Q'' - mux2 #(64) mx8 ({64'h0000_0000_0000_0200}, {64'h0000_0040_0000_0000}, P, q_const); - mux2 #(64) mx9 ({64'h0000_0000_0000_0A00}, {64'h0000_0140_0000_0000}, P, qp_const); - mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const); - - // CPA (from CSA)/Remainder addition/subtraction - adder #(128) cpa1 (Sum2, Carry2, muxr_out, mul_out, cout1); - - // Assuming [1,2) - q1 - adder #(64) cpa2 (regb_out, q_const, 1'b0, q_out1, cout2); - adder #(64) cpa3 (regb_out, qp_const, 1'b0, qp_out1, cout3); - adder #(64) cpa4 (regb_out, qm_const, 1'b1, qm_out1, cout4); - // Assuming [0.5,1) - q0 - adder #(64) cpa5 ({regb_out[62:0], vss}, q_const, 1'b0, q_out0, cout5); - adder #(64) cpa6 ({regb_out[62:0], vss}, qp_const, 1'b0, qp_out0, cout6); - adder #(64) cpa7 ({regb_out[62:0], vss}, qm_const, 1'b1, qm_out0, cout7); - - // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[126], mul_out[126], ~mul_out[125:63]}; - mux2 #(64) mxTC (~mul_out[126:63], three[64:1], op_type, twocmp_out); - - // regs - flopenr #(64) regc (clk, reset, load_regc, twocmp_out, regc_out); - flopenr #(64) regb (clk, reset, load_regb, mul_out[126:63], regb_out); - flopenr #(64) rega (clk, reset, load_rega, mul_out[126:63], rega_out); - flopenr #(64) regd (clk, reset, load_regd, mul_out[126:63], regd_out); - flopenr #(128) regr (clk, reset, load_regr, mul_out, regr_out); - // Assuming [1,2) - flopenr #(64) rege (clk, reset, load_regs, {q_out1[63:39], (q_out1[38:10] & {29{~P}}), 10'h0}, q1); - flopenr #(64) regf (clk, reset, load_regs, {qm_out1[63:39], (qm_out1[38:10] & {29{~P}}), 10'h0}, qm1); - flopenr #(64) regg (clk, reset, load_regs, {qp_out1[63:39], (qp_out1[38:10] & {29{~P}}), 10'h0}, qp1); - // Assuming [0,1) - flopenr #(64) regh (clk, reset, load_regs, {q_out0[63:39], (q_out0[38:10] & {29{~P}}), 10'h0}, q0); - flopenr #(64) regj (clk, reset, load_regs, {qm_out0[63:39], (qm_out0[38:10] & {29{~P}}), 10'h0}, qm0); - flopenr #(64) regk (clk, reset, load_regs, {qp_out0[63:39], (qp_out0[38:10] & {29{~P}}), 10'h0}, qp0); - -endmodule // divconv - -module adder #(parameter WIDTH=8) - (input logic [WIDTH-1:0] a, b, - input logic cin, - output logic [WIDTH-1:0] y, - output logic cout); - - assign {cout, y} = a + b + cin; - -endmodule // adder - -module flopenr #(parameter WIDTH = 8) - (input logic clk, reset, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #10 0; - else if (en) q <= #10 d; - -endmodule // flopenr - -module flopr #(parameter WIDTH = 8) - (input logic clk, reset, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #10 0; - else q <= #10 d; - -endmodule // flopr - -module flopenrc #(parameter WIDTH = 8) - (input logic clk, reset, en, clear, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #10 0; - else if (en) - if (clear) q <= #10 0; - else q <= #10 d; - -endmodule // flopenrc - -module floprc #(parameter WIDTH = 8) - (input logic clk, reset, clear, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #10 0; - else - if (clear) q <= #10 0; - else q <= #10 d; - -endmodule // floprc - -module mux2 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, - input logic s, - output logic [WIDTH-1:0] y); - - assign y = s ? d1 : d0; - -endmodule // mux2 - -module mux3 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[1] ? d2 : (s[0] ? d1 : d0); - -endmodule // mux3 - -module mux4 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, d3, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); - -endmodule // mux4 - -module mux5 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, d3, d4, - input logic [2:0] s, - output logic [WIDTH-1:0] y); - - always_comb - casez (s) - 3'b000 : y = d0; - 3'b001 : y = d1; - 3'b010 : y = d2; - 3'b011 : y = d3; - 3'b1?? : y = d4; - endcase // casez (s) - -endmodule // mux5 - -module mux6 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, - input logic [2:0] s, - output logic [WIDTH-1:0] y); - - always_comb - casez (s) - 3'b000 : y = d0; - 3'b001 : y = d1; - 3'b010 : y = d2; - 3'b011 : y = d3; - 3'b10? : y = d4; - 3'b11? : y = d5; - endcase // casez (s) - -endmodule // mux6 - -module eqcmp #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] a, b, - output logic y); - - assign y = (a == b); - -endmodule // eqcmp - -module fa (input logic a, b, c, output logic sum, carry); - - assign sum = a^b^c; - assign carry = a&b|a&c|b&c; - -endmodule // fa - -module csa #(parameter WIDTH=8) - (input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); - - logic [WIDTH:0] carry_temp; - genvar i; - generate - for (i=0;i" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_div_rd.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 299690000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rne.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rne.do deleted file mode 100755 index 06381f471..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rne.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_div_rne.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 299690000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_ru.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_div_ru.do deleted file mode 100755 index c81756903..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_ru.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_div_ru.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 299690000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rz.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rz.do deleted file mode 100755 index 0da06d37d..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_div_rz.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_div_rz.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 299690000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rd.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rd.do deleted file mode 100755 index dada1d10d..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_sqrt_rd.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 294244000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rne.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rne.do deleted file mode 100755 index a56b1c989..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_sqrt_rne.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 294244000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_ru.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_ru.do deleted file mode 100755 index ebd0fd5fb..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_sqrt_ru.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 294244000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rz.do b/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rz.do deleted file mode 100755 index 6fb981c22..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f32_sqrt_rz.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f32_sqrt_rz.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 294244000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rd.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rd.do deleted file mode 100755 index 1a32a1566..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rd.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_div_rd.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 368600000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rne.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rne.do deleted file mode 100755 index b3b073c9f..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rne.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_div_rne.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 368600000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_ru.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_div_ru.do deleted file mode 100755 index aa017fff0..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_ru.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_div_ru.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 368600000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rz.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rz.do deleted file mode 100755 index 515644def..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_div_rz.do +++ /dev/null @@ -1,57 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_div_rz.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 368600000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rd.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rd.do deleted file mode 100755 index e3e3d8f22..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rd.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_sqrt_rd.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 4364000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rne.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rne.do deleted file mode 100755 index 27391afdf..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rne.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_sqrt_rne.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 4364000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_ru.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_ru.do deleted file mode 100755 index 5dc18cefd..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_ru.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_sqrt_ru.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 4364000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rz.do b/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rz.do deleted file mode 100755 index 06713052c..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/f64_sqrt_rz.do +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv tb_f64_sqrt_rz.sv - - -# start and run simulation -vsim -voptargs=+acc work.tb - -#view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation --- 39,052 vectors, 390,565ns -run 4364000 -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.do b/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.do deleted file mode 100755 index 950ee2d81..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.do +++ /dev/null @@ -1,94 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mult_R4_64_64_cs.v sbtm_a1.sv sbtm_a0.sv sbtm.sv sbtm_a4.sv sbtm_a5.sv sbtm3.sv fsm_div.v divconvDP.sv convert_inputs_div.sv exception_div.sv rounder_div.sv fpdiv.sv test_fpdiv.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -color gold /tb/dut/clk -add wave -hex -color gold /tb/dut/mantissaA -add wave -hex -color gold /tb/dut/mantissaB -add wave -hex -color gold /tb/dut/op1 -add wave -hex -color gold /tb/dut/op2 -add wave -hex -color gold /tb/dut/AS_Result -add wave -hex -color gold /tb/dut/Flags -add wave -hex -color gold /tb/dut/Denorm -#add wave -noupdate -divider -height 32 "exponent" -#add wave -hex /tb/dut/exp1 -#add wave -hex /tb/dut/exp2 -#add wave -hex /tb/dut/expF -#add wave -hex /tb/dut/bias -#add wave -hex /tb/dut/exp_diff -#add wave -hex /tb/dut/exp_odd -#add wave -hex -r /tb/dut/explogic2/* -#add wave -hex -r /tb/dut/explogic1/* -add wave -noupdate -divider -height 32 "FSM" -add wave -hex /tb/dut/control/CURRENT_STATE -add wave -hex /tb/dut/control/NEXT_STATE -add wave -hex -color #0080ff /tb/dut/control/start -add wave -hex -color #0080ff /tb/dut/control/reset -add wave -hex -color #0080ff /tb/dut/control/op_type -add wave -hex -color #0080ff /tb/dut/control/load_rega -add wave -hex -color #0080ff /tb/dut/control/load_regb -add wave -hex -color #0080ff /tb/dut/control/load_regc -add wave -hex -color #0080ff /tb/dut/control/load_regr -add wave -hex -color #0080ff /tb/dut/control/load_regs -add wave -hex -color #0080ff /tb/dut/control/sel_muxa -add wave -hex -color #0080ff /tb/dut/control/sel_muxb -add wave -hex -color #0080ff /tb/dut/control/sel_muxr -add wave -hex -color #0080ff /tb/dut/control/done -add wave -noupdate -divider -height 32 "Convert" -add wave -hex -r /tb/dut/conv1/* -add wave -noupdate -divider -height 32 "Exceptions" -add wave -hex -r /tb/dut/exc1/* -add wave -noupdate -divider -height 32 "Rounder" -add wave -hex -r /tb/dut/round1/* -add wave -noupdate -divider -height 32 "Goldschmidt" -add wave -hex -r /tb/dut/goldy/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 14ns -quit diff --git a/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.sv b/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.sv deleted file mode 100755 index 4051f6de9..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/fpdiv.sv +++ /dev/null @@ -1,151 +0,0 @@ -// -// File name : fpdiv -// Title : Floating-Point Divider/Square-Root -// project : FPU -// Library : fpdiv -// Author(s) : James E. Stine, Jr. -// Purpose : definition of main unit to floating-point div/sqrt -// notes : -// -// Copyright Oklahoma State University -// -// Basic Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Exponent Logic -// Step 4: Divide/Sqrt using Goldschmidt -// Step 5: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 6: Round the result.// -// Step 7: Put quotient/remainder onto output. -// - -`timescale 1ps/1ps -module fpdiv (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - input [63:0] op1; // 1st input operand (A) - input [63:0] op2; // 2nd input operand (B) - input [1:0] rm; // Rounding mode - specify values - input op_type; // Function opcode - input P; // Result Precision (0 for double, 1 for single) - input OvEn; // Overflow trap enabled - input UnEn; // Underflow trap enabled - input start; - input reset; - input clk; - - output [63:0] AS_Result; // Result of operation - output [4:0] Flags; // IEEE exception flags - output Denorm; // Denorm on input or output - output done; - - supply1 vdd; - supply0 vss; - - wire [63:0] Float1; - wire [63:0] Float2; - wire [63:0] IntValue; - - wire [12:0] exp1, exp2, expF; - wire [12:0] exp_diff, bias; - wire [13:0] exp_sqrt; - wire [12:0] exp_s; - wire [12:0] exp_c; - - wire [10:0] exponent, exp_pre; - wire [63:0] Result; - wire [52:0] mantissaA; - wire [52:0] mantissaB; - wire [63:0] sum, sum_tc, sum_corr, sum_norm; - - wire [5:0] align_shift; - wire [5:0] norm_shift; - wire [2:0] sel_inv; - wire op1_Norm, op2_Norm; - wire opA_Norm, opB_Norm; - wire Invalid; - wire DenormIn, DenormIO; - wire [4:0] FlagsIn; - wire exp_gt63; - wire Sticky_out; - wire signResult, sign_corr; - wire corr_sign; - wire zeroB; - wire convert; - wire swap; - wire sub; - - wire [63:0] q1, qm1, qp1, q0, qm0, qp0; - wire [63:0] rega_out, regb_out, regc_out, regd_out; - wire [127:0] regr_out; - wire [2:0] sel_muxa, sel_muxb; - wire sel_muxr; - wire load_rega, load_regb, load_regc, load_regd, load_regr; - - wire donev, sel_muxrv, sel_muxsv; - wire [1:0] sel_muxav, sel_muxbv; - wire load_regav, load_regbv, load_regcv; - wire load_regrv, load_regsv; - - // Convert the input operands to their appropriate forms based on - // the orignal operands, the op_type , and their precision P. - // Single precision inputs are converted to double precision - // and the sign of the first operand is set appropratiately based on - // if the operation is absolute value or negation. - convert_inputs_div conv1 (Float1, Float2, op1, op2, op_type, P); - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "sel_inv" is used in - // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if op1 and op2 are not zero or denormalized. - // sub is one if the effective operation is subtaction. - exception_div exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, - Float1, Float2, op_type); - - // Determine Sign/Mantissa - assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type; - assign mantissaA = {vdd, Float1[51:0]}; - assign mantissaB = {vdd, Float2[51:0]}; - // Perform Exponent Subtraction - expA - expB + Bias - assign exp1 = {2'b0, Float1[62:52]}; - assign exp2 = {2'b0, Float2[62:52]}; - // bias : DP = 2^{11-1}-1 = 1023 - assign bias = {3'h0, 10'h3FF}; - // Divide exponent - csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c); - adder #(14) explogic1 ({vss, exp_s}, {vss, exp_c}, 1'b1, {open, exp_diff}, exp_cout1); - - // Sqrt exponent (check if exponent is odd) - assign exp_odd = Float1[52] ? vss : vdd; - adder #(14) explogic2 ({vss, exp1}, {4'h0, 10'h3ff}, exp_odd, exp_sqrt, exp_cout2); - // Choose correct exponent - assign expF = op_type ? exp_sqrt[13:1] : exp_diff; - - // Main Goldschmidt/Division Routine - divconv goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, - regr_out, mantissaB, mantissaA, sel_muxa, sel_muxb, sel_muxr, - reset, clk, load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, P, op_type, exp_odd); - - // FSM : control divider - fsm_div control (done, load_rega, load_regb, load_regc, load_regd, - load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. The rounding units also handles special cases and - // set the exception flags. - rounder_div round1 (Result, DenormIO, FlagsIn, - rm, P, OvEn, UnEn, expF, - sel_inv, Invalid, DenormIn, signResult, - q1, qm1, qp1, q0, qm0, qp0, regr_out); - - // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, done, Result, AS_Result); - flopenr #(1) regb (clk, reset, done, DenormIO, Denorm); - flopenr #(5) regc (clk, reset, done, FlagsIn, Flags); - -endmodule // fpadd diff --git a/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v b/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v deleted file mode 100755 index 77f0dc9af..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v +++ /dev/null @@ -1,459 +0,0 @@ -module fsm_div (done, load_rega, load_regb, load_regc, - load_regd, load_regr, load_regs, - sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - input clk; - input reset; - input start; - input error; - input op_type; - - output done; - output load_rega; - output load_regb; - output load_regc; - output load_regd; - output load_regr; - output load_regs; - - output [2:0] sel_muxa; - output [2:0] sel_muxb; - output sel_muxr; - - reg done; // End of cycles - reg load_rega; // enable for regA - reg load_regb; // enable for regB - reg load_regc; // enable for regC - reg load_regd; // enable for regD - reg load_regr; // enable for rem - reg load_regs; // enable for q,qm,qp - reg [2:0] sel_muxa; // Select muxA - reg [2:0] sel_muxb; // Select muxB - reg sel_muxr; // Select rem mux - - reg [4:0] CURRENT_STATE; - reg [4:0] NEXT_STATE; - - parameter [4:0] - S0=5'd0, S1=5'd1, S2=5'd2, - S3=5'd3, S4=5'd4, S5=5'd5, - S6=5'd6, S7=5'd7, S8=5'd8, - S9=5'd9, S10=5'd10, - S13=5'd13, S14=5'd14, S15=5'd15, - S16=5'd16, S17=5'd17, S18=5'd18, - S19=5'd19, S20=5'd20, S21=5'd21, - S22=5'd22, S23=5'd23, S24=5'd24, - S25=5'd25, S26=5'd26, S27=5'd27, - S28=5'd28, S29=5'd29, S30=5'd30; - - always @(posedge clk) - begin - if(reset==1'b1) - CURRENT_STATE<=S0; - else - CURRENT_STATE<=NEXT_STATE; - end - - always @(*) - begin - case(CURRENT_STATE) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - else if (start==1'b1 && op_type==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S1; - end // if (start==1'b1 && op_type==1'b0) - else if (start==1'b1 && op_type==1'b1) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S13; - end - end // case: S0 - S1: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S2; - end - S2: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S3; - end - S3: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S4; - end - S4: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S5; - end - S5: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; // add - NEXT_STATE <= S6; - end - S6: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end - S7: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end // case: S7 - S8: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S9; - end - S9: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - NEXT_STATE <= S10; - end - S10: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - S13: // start of sqrt path - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S14; - end - S14: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - NEXT_STATE <= S15; - end - S15: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S16; - end - S16: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S17; - end - S17: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S18; - end - S18: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S19; - end - S19: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S20; - end - S20: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S21; - end - S21: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S22; - end - S22: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S23; - end - S23: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S24; - end - S24: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S25; - end - S25: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - NEXT_STATE <= S26; - end - S26: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - default: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - endcase // case(CURRENT_STATE) - end // always @ (CURRENT_STATE or X) - -endmodule // fsm diff --git a/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v~ b/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v~ deleted file mode 100755 index 208b129c3..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/fsm_div.v~ +++ /dev/null @@ -1,459 +0,0 @@ -module fsm (done, load_rega, load_regb, load_regc, - load_regd, load_regr, load_regs, - sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - input clk; - input reset; - input start; - input error; - input op_type; - - output done; - output load_rega; - output load_regb; - output load_regc; - output load_regd; - output load_regr; - output load_regs; - - output [2:0] sel_muxa; - output [2:0] sel_muxb; - output sel_muxr; - - reg done; // End of cycles - reg load_rega; // enable for regA - reg load_regb; // enable for regB - reg load_regc; // enable for regC - reg load_regd; // enable for regD - reg load_regr; // enable for rem - reg load_regs; // enable for q,qm,qp - reg [2:0] sel_muxa; // Select muxA - reg [2:0] sel_muxb; // Select muxB - reg sel_muxr; // Select rem mux - - reg [4:0] CURRENT_STATE; - reg [4:0] NEXT_STATE; - - parameter [4:0] - S0=5'd0, S1=5'd1, S2=5'd2, - S3=5'd3, S4=5'd4, S5=5'd5, - S6=5'd6, S7=5'd7, S8=5'd8, - S9=5'd9, S10=5'd10, - S13=5'd13, S14=5'd14, S15=5'd15, - S16=5'd16, S17=5'd17, S18=5'd18, - S19=5'd19, S20=5'd20, S21=5'd21, - S22=5'd22, S23=5'd23, S24=5'd24, - S25=5'd25, S26=5'd26, S27=5'd27, - S28=5'd28, S29=5'd29, S30=5'd30; - - always @(posedge clk) - begin - if(reset==1'b1) - CURRENT_STATE<=S0; - else - CURRENT_STATE<=NEXT_STATE; - end - - always @(*) - begin - case(CURRENT_STATE) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - else if (start==1'b1 && op_type==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S1; - end // if (start==1'b1 && op_type==1'b0) - else if (start==1'b1 && op_type==1'b1) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S13; - end - end // case: S0 - S1: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S2; - end - S2: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S3; - end - S3: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S4; - end - S4: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S5; - end - S5: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; // add - NEXT_STATE <= S6; - end - S6: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end - S7: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end // case: S7 - S8: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S9; - end - S9: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - NEXT_STATE <= S10; - end - S10: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - S13: // start of sqrt path - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S14; - end - S14: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - NEXT_STATE <= S15; - end - S15: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S16; - end - S16: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S17; - end - S17: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S18; - end - S18: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S19; - end - S19: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S20; - end - S20: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S21; - end - S21: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S22; - end - S22: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S23; - end - S23: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S24; - end - S24: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S25; - end - S25: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - NEXT_STATE <= S26; - end - S26: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - default: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - endcase // case(CURRENT_STATE) - end // always @ (CURRENT_STATE or X) - -endmodule // fsm diff --git a/wally-pipelined/src/fpu/fpdivsqrt/list.lst b/wally-pipelined/src/fpu/fpdivsqrt/list.lst deleted file mode 100755 index 11e527799..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/list.lst +++ /dev/null @@ -1,31 +0,0 @@ - ns /tb/dut/goldy/mult1/x /tb/dut/goldy/mult1/Sum /tb/dut/goldy/mult1/Carry /tb/dut/goldy/mult1/xx /tb/dut/goldy/mult1/single /tb/dut/goldy/mult1/neg /tb/dut/goldy/mult1/pp_1_2 /tb/dut/goldy/mult1/pp_2_4 /tb/dut/goldy/mult1/pp_1_6 /tb/dut/goldy/mult1/pp_2_7 /tb/dut/goldy/mult1/pp_3_8 /tb/dut/goldy/mult1/pp_3_9 /tb/dut/goldy/mult1/pp_3_10 /tb/dut/goldy/mult1/pp_2_11 /tb/dut/goldy/mult1/pp_1_12 /tb/dut/goldy/mult1/pp_6_12 /tb/dut/goldy/mult1/pp_4_13 /tb/dut/goldy/mult1/pp_2_14 /tb/dut/goldy/mult1/pp_7_14 /tb/dut/goldy/mult1/pp_4_15 /tb/dut/goldy/mult1/pp_1_16 /tb/dut/goldy/mult1/pp_6_16 /tb/dut/goldy/mult1/pp_2_17 /tb/dut/goldy/mult1/pp_7_17 /tb/dut/goldy/mult1/pp_3_18 /tb/dut/goldy/mult1/pp_8_18 /tb/dut/goldy/mult1/pp_3_19 /tb/dut/goldy/mult1/pp_8_19 /tb/dut/goldy/mult1/pp_3_20 /tb/dut/goldy/mult1/pp_8_20 /tb/dut/goldy/mult1/pp_2_21 /tb/dut/goldy/mult1/pp_7_21 /tb/dut/goldy/mult1/pp_1_22 /tb/dut/goldy/mult1/pp_6_22 /tb/dut/goldy/mult1/pp_11_22 /tb/dut/goldy/mult1/pp_4_23 /tb/dut/goldy/mult1/pp_9_23 /tb/dut/goldy/mult1/pp_2_24 /tb/dut/goldy/mult1/pp_7_24 /tb/dut/goldy/mult1/pp_12_24 /tb/dut/goldy/mult1/pp_4_25 /tb/dut/goldy/mult1/pp_9_25 /tb/dut/goldy/mult1/pp_1_26 /tb/dut/goldy/mult1/pp_6_26 /tb/dut/goldy/mult1/pp_11_26 /tb/dut/goldy/mult1/pp_2_27 /tb/dut/goldy/mult1/pp_7_27 /tb/dut/goldy/mult1/pp_12_27 /tb/dut/goldy/mult1/pp_3_28 /tb/dut/goldy/mult1/pp_8_28 /tb/dut/goldy/mult1/pp_13_28 /tb/dut/goldy/mult1/pp_3_29 /tb/dut/goldy/mult1/pp_8_29 /tb/dut/goldy/mult1/pp_13_29 /tb/dut/goldy/mult1/pp_3_30 /tb/dut/goldy/mult1/pp_8_30 /tb/dut/goldy/mult1/pp_13_30 /tb/dut/goldy/mult1/pp_2_31 /tb/dut/goldy/mult1/pp_7_31 /tb/dut/goldy/mult1/pp_12_31 /tb/dut/goldy/mult1/pp_1_32 /tb/dut/goldy/mult1/pp_6_32 /tb/dut/goldy/mult1/pp_11_32 /tb/dut/goldy/mult1/pp_16_32 /tb/dut/goldy/mult1/pp_4_33 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1'h0 1'h1 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h1 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h1 1'h1 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h0 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h0 1'h1 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h0 1'h1 1'h1 1'h0 1'h1 1'h0 1'h0 1'h1 1'h1 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'hz 1'h0 diff --git a/wally-pipelined/src/fpu/fpdivsqrt/mult_R4_64_64_cs.v b/wally-pipelined/src/fpu/fpdivsqrt/mult_R4_64_64_cs.v deleted file mode 100755 index 7ad230df8..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/mult_R4_64_64_cs.v +++ /dev/null @@ -1,11995 +0,0 @@ -// This module is a 64 by 64 TDM multiplier. -// It is unsigned and uses Radix-4 Booth encoding. -// This file was automatically generated by tdm.pl. - -module mult64 (x, y, P); - - input [63:0] x; - input [63:0] y; - - output [127:0] P; - - wire [127:0] Sum; - wire [127:0] Carry; - wire [128:0] Pt; - - multiplier p1 (y, x, Sum, Carry); - //assign Pt = Sum + Carry; - //assign P = Pt[127:0]; - ldf128 cpa (cout, P, Sum, Carry, 1'b0); - -endmodule // mult64 - -module multiplier( y, x, Sum, Carry ); - - input [63:0] x; - input [63:0] y; - - output [127:0] Sum; - output [127:0] Carry; - - supply0 gnd; - - //Buffers and their nets. - - wire [63:0] xx; - wire [63:0] yy; - - buffer buffer_0_0( xx[0], x[0]); - buffer buffer_0_32( yy[0], y[0]); - buffer buffer_80_0( xx[1], x[1]); - buffer buffer_80_32( yy[1], y[1]); - buffer buffer_160_0( xx[2], x[2]); - buffer buffer_160_32( yy[2], y[2]); - buffer buffer_240_0( xx[3], x[3]); - buffer buffer_240_32( yy[3], y[3]); - buffer buffer_320_0( xx[4], x[4]); - buffer buffer_320_32( yy[4], y[4]); - buffer buffer_400_0( xx[5], x[5]); - buffer buffer_400_32( yy[5], y[5]); - buffer buffer_480_0( xx[6], x[6]); - buffer buffer_480_32( yy[6], y[6]); - buffer buffer_560_0( xx[7], x[7]); - buffer buffer_560_32( yy[7], y[7]); - buffer buffer_640_0( xx[8], x[8]); - buffer buffer_640_32( yy[8], y[8]); - buffer buffer_720_0( xx[9], x[9]); - buffer buffer_720_32( yy[9], y[9]); - buffer buffer_800_0( xx[10], x[10]); - buffer buffer_800_32( yy[10], y[10]); - buffer buffer_880_0( xx[11], x[11]); - buffer buffer_880_32( yy[11], y[11]); - buffer buffer_960_0( xx[12], x[12]); - buffer buffer_960_32( yy[12], y[12]); - buffer buffer_1040_0( xx[13], x[13]); - buffer buffer_1040_32( yy[13], y[13]); - buffer buffer_1120_0( xx[14], x[14]); - buffer buffer_1120_32( yy[14], y[14]); - buffer buffer_1200_0( xx[15], x[15]); - buffer buffer_1200_32( yy[15], y[15]); - buffer buffer_1280_0( xx[16], x[16]); - buffer buffer_1280_32( yy[16], y[16]); - buffer buffer_1360_0( xx[17], x[17]); - buffer buffer_1360_32( yy[17], y[17]); - buffer buffer_1440_0( xx[18], x[18]); - buffer buffer_1440_32( yy[18], y[18]); - buffer buffer_1520_0( xx[19], x[19]); - buffer buffer_1520_32( yy[19], y[19]); - buffer buffer_1600_0( xx[20], x[20]); - buffer buffer_1600_32( yy[20], y[20]); - buffer buffer_1680_0( xx[21], x[21]); - buffer buffer_1680_32( yy[21], y[21]); - buffer buffer_1760_0( xx[22], x[22]); - buffer buffer_1760_32( yy[22], y[22]); - buffer buffer_1840_0( xx[23], x[23]); - buffer buffer_1840_32( yy[23], y[23]); - buffer buffer_1920_0( xx[24], x[24]); - buffer buffer_1920_32( yy[24], y[24]); - buffer buffer_2000_0( xx[25], x[25]); - buffer buffer_2000_32( yy[25], y[25]); - buffer buffer_2080_0( xx[26], x[26]); - buffer buffer_2080_32( yy[26], y[26]); - buffer buffer_2160_0( xx[27], x[27]); - buffer buffer_2160_32( yy[27], y[27]); - buffer buffer_2240_0( xx[28], x[28]); - buffer buffer_2240_32( yy[28], y[28]); - buffer buffer_2320_0( xx[29], x[29]); - buffer buffer_2320_32( yy[29], y[29]); - buffer buffer_2400_0( xx[30], x[30]); - buffer buffer_2400_32( yy[30], y[30]); - buffer buffer_2480_0( xx[31], x[31]); - buffer buffer_2480_32( yy[31], y[31]); - buffer buffer_2560_0( xx[32], x[32]); - buffer buffer_2560_32( yy[32], y[32]); - buffer buffer_2640_0( xx[33], x[33]); - buffer buffer_2640_32( yy[33], y[33]); - buffer buffer_2720_0( xx[34], x[34]); - buffer buffer_2720_32( yy[34], y[34]); - buffer buffer_2800_0( xx[35], x[35]); - buffer buffer_2800_32( yy[35], y[35]); - buffer buffer_2880_0( xx[36], x[36]); - buffer buffer_2880_32( yy[36], y[36]); - buffer buffer_2960_0( xx[37], x[37]); - buffer buffer_2960_32( yy[37], y[37]); - buffer buffer_3040_0( xx[38], x[38]); - buffer buffer_3040_32( yy[38], y[38]); - buffer buffer_3120_0( xx[39], x[39]); - buffer buffer_3120_32( yy[39], y[39]); - buffer buffer_3200_0( xx[40], x[40]); - buffer buffer_3200_32( yy[40], y[40]); - buffer buffer_3280_0( xx[41], x[41]); - buffer buffer_3280_32( yy[41], y[41]); - buffer buffer_3360_0( xx[42], x[42]); - buffer buffer_3360_32( yy[42], y[42]); - buffer buffer_3440_0( xx[43], x[43]); - buffer buffer_3440_32( yy[43], y[43]); - buffer buffer_3520_0( xx[44], x[44]); - buffer buffer_3520_32( yy[44], y[44]); - buffer buffer_3600_0( xx[45], x[45]); - buffer buffer_3600_32( yy[45], y[45]); - buffer buffer_3680_0( xx[46], x[46]); - buffer buffer_3680_32( yy[46], y[46]); - buffer buffer_3760_0( xx[47], x[47]); - buffer buffer_3760_32( yy[47], y[47]); - buffer buffer_3840_0( xx[48], x[48]); - buffer buffer_3840_32( yy[48], y[48]); - buffer buffer_3920_0( xx[49], x[49]); - buffer buffer_3920_32( yy[49], y[49]); - buffer buffer_4000_0( xx[50], x[50]); - buffer buffer_4000_32( yy[50], y[50]); - buffer buffer_4080_0( xx[51], x[51]); - buffer buffer_4080_32( yy[51], y[51]); - buffer buffer_4160_0( xx[52], x[52]); - buffer buffer_4160_32( yy[52], y[52]); - buffer buffer_4240_0( xx[53], x[53]); - buffer buffer_4240_32( yy[53], y[53]); - buffer buffer_4320_0( xx[54], x[54]); - buffer buffer_4320_32( yy[54], y[54]); - buffer buffer_4400_0( xx[55], x[55]); - buffer buffer_4400_32( yy[55], y[55]); - buffer buffer_4480_0( xx[56], x[56]); - buffer buffer_4480_32( yy[56], y[56]); - buffer buffer_4560_0( xx[57], x[57]); - buffer buffer_4560_32( yy[57], y[57]); - buffer buffer_4640_0( xx[58], x[58]); - buffer buffer_4640_32( yy[58], y[58]); - buffer buffer_4720_0( xx[59], x[59]); - buffer buffer_4720_32( yy[59], y[59]); - buffer buffer_4800_0( xx[60], x[60]); - buffer buffer_4800_32( yy[60], y[60]); - buffer buffer_4880_0( xx[61], x[61]); - buffer buffer_4880_32( yy[61], y[61]); - buffer buffer_4960_0( xx[62], x[62]); - buffer buffer_4960_32( yy[62], y[62]); - buffer buffer_5040_0( xx[63], x[63]); - buffer buffer_5040_32( yy[63], y[63]); - - - //Booth encoders and related wiring - - wire [32:0] single; - wire [32:0] double; - wire [32:0] neg; - wire [31:0] negbar; - - r4be r4be_10240_0(gnd, xx[0], xx[1], single[0], double[0], neg[0]); - inverter inverter_10240_168(negbar[0], neg[0]); - r4be r4be_10240_184(xx[1], xx[2], xx[3], single[1], double[1], neg[1]); - inverter inverter_10240_352(negbar[1], neg[1]); - r4be r4be_10240_368(xx[3], xx[4], xx[5], single[2], double[2], neg[2]); - inverter inverter_10240_536(negbar[2], neg[2]); - r4be r4be_10240_552(xx[5], xx[6], xx[7], single[3], double[3], neg[3]); - inverter inverter_10240_720(negbar[3], neg[3]); - r4be r4be_10240_736(xx[7], xx[8], xx[9], single[4], double[4], neg[4]); - inverter inverter_10240_904(negbar[4], neg[4]); - r4be r4be_10240_920(xx[9], xx[10], xx[11], single[5], double[5], neg[5]); - inverter inverter_10240_1088(negbar[5], neg[5]); - r4be r4be_10240_1104(xx[11], xx[12], xx[13], single[6], double[6], neg[6]); - inverter inverter_10240_1272(negbar[6], neg[6]); - r4be r4be_10240_1288(xx[13], xx[14], xx[15], single[7], double[7], neg[7]); - inverter inverter_10240_1456(negbar[7], neg[7]); - r4be r4be_10240_1472(xx[15], xx[16], xx[17], single[8], double[8], neg[8]); - inverter inverter_10240_1640(negbar[8], neg[8]); - r4be r4be_10240_1656(xx[17], xx[18], xx[19], single[9], double[9], neg[9]); - inverter inverter_10240_1824(negbar[9], neg[9]); - r4be r4be_10240_1840(xx[19], xx[20], xx[21], single[10], double[10], neg[10]); - inverter inverter_10240_2008(negbar[10], neg[10]); - r4be r4be_10240_2024(xx[21], xx[22], xx[23], single[11], double[11], neg[11]); - inverter inverter_10240_2192(negbar[11], neg[11]); - r4be r4be_10240_2208(xx[23], xx[24], xx[25], single[12], double[12], neg[12]); - inverter inverter_10240_2376(negbar[12], neg[12]); - r4be r4be_10240_2392(xx[25], xx[26], xx[27], single[13], double[13], neg[13]); - inverter inverter_10240_2560(negbar[13], neg[13]); - r4be r4be_10240_2576(xx[27], xx[28], xx[29], single[14], double[14], neg[14]); - inverter inverter_10240_2744(negbar[14], neg[14]); - r4be r4be_10240_2760(xx[29], xx[30], xx[31], single[15], double[15], neg[15]); - inverter inverter_10240_2928(negbar[15], neg[15]); - r4be r4be_10240_2944(xx[31], xx[32], xx[33], single[16], double[16], neg[16]); - inverter inverter_10240_3112(negbar[16], neg[16]); - r4be r4be_10240_3128(xx[33], xx[34], xx[35], single[17], double[17], neg[17]); - inverter inverter_10240_3296(negbar[17], neg[17]); - r4be r4be_10240_3312(xx[35], xx[36], xx[37], single[18], double[18], neg[18]); - inverter inverter_10240_3480(negbar[18], neg[18]); - r4be r4be_10240_3496(xx[37], xx[38], xx[39], single[19], double[19], neg[19]); - inverter inverter_10240_3664(negbar[19], neg[19]); - r4be r4be_10240_3680(xx[39], xx[40], xx[41], single[20], double[20], neg[20]); - inverter inverter_10240_3848(negbar[20], neg[20]); - r4be r4be_10240_3864(xx[41], xx[42], xx[43], single[21], double[21], neg[21]); - inverter inverter_10240_4032(negbar[21], neg[21]); - r4be r4be_10240_4048(xx[43], xx[44], xx[45], single[22], double[22], neg[22]); - inverter inverter_10240_4216(negbar[22], neg[22]); - r4be r4be_10240_4232(xx[45], xx[46], xx[47], single[23], double[23], neg[23]); - inverter inverter_10240_4400(negbar[23], neg[23]); - r4be r4be_10240_4416(xx[47], xx[48], xx[49], single[24], double[24], neg[24]); - inverter inverter_10240_4584(negbar[24], neg[24]); - r4be r4be_10240_4600(xx[49], xx[50], xx[51], single[25], double[25], neg[25]); - inverter inverter_10240_4768(negbar[25], neg[25]); - r4be r4be_10240_4784(xx[51], xx[52], xx[53], single[26], double[26], neg[26]); - inverter inverter_10240_4952(negbar[26], neg[26]); - r4be r4be_10240_4968(xx[53], xx[54], xx[55], single[27], double[27], neg[27]); - inverter inverter_10240_5136(negbar[27], neg[27]); - r4be r4be_10240_5152(xx[55], xx[56], xx[57], single[28], double[28], neg[28]); - inverter inverter_10240_5320(negbar[28], neg[28]); - r4be r4be_10240_5336(xx[57], xx[58], xx[59], single[29], double[29], neg[29]); - inverter inverter_10240_5504(negbar[29], neg[29]); - r4be r4be_10240_5520(xx[59], xx[60], xx[61], single[30], double[30], neg[30]); - inverter inverter_10240_5688(negbar[30], neg[30]); - r4be r4be_10240_5704(xx[61], xx[62], xx[63], single[31], double[31], neg[31]); - inverter inverter_10240_5872(negbar[31], neg[31]); - r4be r4be_10240_5888(xx[63], gnd, gnd, single[32], double[32], neg[32]); - - // Below are the nets for the partial products (booth) - wire pp_0_0; - wire pp_0_2; - wire pp_1_2; - wire pp_0_3; - wire pp_1_3; - wire pp_0_4; - wire pp_1_4; - wire pp_2_4; - wire pp_0_5; - wire pp_1_5; - wire pp_2_5; - wire pp_0_6; - wire pp_1_6; - wire pp_2_6; - wire pp_3_6; - wire pp_0_7; - wire pp_1_7; - wire pp_2_7; - wire pp_3_7; - wire pp_0_8; - wire pp_1_8; - wire pp_2_8; - wire pp_3_8; - wire pp_4_8; - wire pp_0_9; - wire pp_1_9; - wire pp_2_9; - wire pp_3_9; - wire pp_4_9; - wire pp_0_10; - wire pp_1_10; - wire pp_2_10; - wire pp_3_10; - wire pp_4_10; - wire pp_5_10; - wire pp_0_11; - wire pp_1_11; - wire pp_2_11; - wire pp_3_11; - wire pp_4_11; - wire pp_5_11; - wire pp_0_12; - wire pp_1_12; - wire pp_2_12; - wire pp_3_12; - wire pp_4_12; - wire pp_5_12; - wire pp_6_12; - wire pp_0_13; - wire pp_1_13; - wire pp_2_13; - wire pp_3_13; - wire pp_4_13; - wire pp_5_13; - wire pp_6_13; - wire pp_0_14; - wire pp_1_14; - wire pp_2_14; - wire pp_3_14; - wire pp_4_14; - wire pp_5_14; - wire pp_6_14; - wire pp_7_14; - wire pp_0_15; - wire pp_1_15; - wire pp_2_15; - wire pp_3_15; - wire pp_4_15; - wire pp_5_15; - wire pp_6_15; - wire pp_7_15; - wire pp_0_16; - wire pp_1_16; - wire pp_2_16; - wire pp_3_16; - wire pp_4_16; - wire pp_5_16; - wire pp_6_16; - wire pp_7_16; - wire pp_8_16; - wire pp_0_17; - wire pp_1_17; - wire pp_2_17; - wire pp_3_17; - wire pp_4_17; - wire pp_5_17; - wire pp_6_17; - wire pp_7_17; - wire pp_8_17; - wire pp_0_18; - wire pp_1_18; - wire pp_2_18; - wire pp_3_18; - wire pp_4_18; - wire pp_5_18; - wire pp_6_18; - wire pp_7_18; - wire pp_8_18; - wire pp_9_18; - wire pp_0_19; - wire pp_1_19; - wire pp_2_19; - wire pp_3_19; - wire pp_4_19; - wire pp_5_19; - wire pp_6_19; - wire pp_7_19; - wire pp_8_19; - wire pp_9_19; - wire pp_0_20; - wire pp_1_20; - wire pp_2_20; - wire pp_3_20; - wire pp_4_20; - wire pp_5_20; - wire pp_6_20; - wire pp_7_20; - wire pp_8_20; - wire pp_9_20; - wire pp_10_20; - wire pp_0_21; - wire pp_1_21; - wire pp_2_21; - wire pp_3_21; - wire pp_4_21; - wire pp_5_21; - wire pp_6_21; - wire pp_7_21; - wire pp_8_21; - wire pp_9_21; - wire pp_10_21; - wire pp_0_22; - wire pp_1_22; - wire pp_2_22; - wire pp_3_22; - wire pp_4_22; - wire pp_5_22; - wire pp_6_22; - wire pp_7_22; - wire pp_8_22; - wire pp_9_22; - wire pp_10_22; - wire pp_11_22; - wire pp_0_23; - wire pp_1_23; - wire pp_2_23; - wire pp_3_23; - wire pp_4_23; - wire pp_5_23; - wire pp_6_23; - wire pp_7_23; - wire pp_8_23; - wire pp_9_23; - wire pp_10_23; - wire pp_11_23; - wire pp_0_24; - wire pp_1_24; - wire pp_2_24; - wire pp_3_24; - wire pp_4_24; - wire pp_5_24; - wire pp_6_24; - wire pp_7_24; - wire pp_8_24; - wire pp_9_24; - wire pp_10_24; - wire pp_11_24; - wire pp_12_24; - wire pp_0_25; - wire pp_1_25; - wire pp_2_25; - wire pp_3_25; - wire pp_4_25; - wire pp_5_25; - wire pp_6_25; - wire pp_7_25; - wire pp_8_25; - wire pp_9_25; - wire pp_10_25; - wire pp_11_25; - wire pp_12_25; - wire pp_0_26; - wire pp_1_26; - wire pp_2_26; - wire pp_3_26; - wire pp_4_26; - wire pp_5_26; - wire pp_6_26; - wire pp_7_26; - wire pp_8_26; - wire pp_9_26; - wire pp_10_26; - wire pp_11_26; - wire pp_12_26; - wire pp_13_26; - wire pp_0_27; - wire pp_1_27; - wire pp_2_27; - wire pp_3_27; - wire pp_4_27; - wire pp_5_27; - wire pp_6_27; - wire pp_7_27; - wire pp_8_27; - wire pp_9_27; - wire pp_10_27; - wire pp_11_27; - wire pp_12_27; - wire pp_13_27; - wire pp_0_28; - wire pp_1_28; - wire pp_2_28; - wire pp_3_28; - wire pp_4_28; - wire pp_5_28; - wire pp_6_28; - wire pp_7_28; - wire pp_8_28; - wire pp_9_28; - wire pp_10_28; - wire pp_11_28; - wire pp_12_28; - wire pp_13_28; - wire pp_14_28; - wire pp_0_29; - wire pp_1_29; - wire pp_2_29; - wire pp_3_29; - wire pp_4_29; - wire pp_5_29; - wire pp_6_29; - wire pp_7_29; - wire pp_8_29; - wire pp_9_29; - wire pp_10_29; - wire pp_11_29; - wire pp_12_29; - wire pp_13_29; - wire pp_14_29; - wire pp_0_30; - wire pp_1_30; - wire pp_2_30; - wire pp_3_30; - wire pp_4_30; - wire pp_5_30; - wire pp_6_30; - wire pp_7_30; - wire pp_8_30; - wire pp_9_30; - wire pp_10_30; - wire pp_11_30; - wire pp_12_30; - wire pp_13_30; - wire pp_14_30; - wire pp_15_30; - wire pp_0_31; - wire pp_1_31; - wire pp_2_31; - wire pp_3_31; - wire pp_4_31; - wire pp_5_31; - wire pp_6_31; - wire pp_7_31; - wire pp_8_31; - wire pp_9_31; - wire pp_10_31; - wire pp_11_31; - wire pp_12_31; - wire pp_13_31; - wire pp_14_31; - wire pp_15_31; - wire pp_0_32; - wire pp_1_32; - wire pp_2_32; - wire pp_3_32; - wire pp_4_32; - wire pp_5_32; - wire pp_6_32; - wire pp_7_32; - wire pp_8_32; - wire pp_9_32; - wire pp_10_32; - wire pp_11_32; - wire pp_12_32; - wire pp_13_32; - wire pp_14_32; - wire pp_15_32; - wire pp_16_32; - wire pp_0_33; - wire pp_1_33; - wire pp_2_33; - wire pp_3_33; - wire pp_4_33; - wire pp_5_33; - wire pp_6_33; - wire pp_7_33; - wire pp_8_33; - wire pp_9_33; - wire pp_10_33; - wire pp_11_33; - wire pp_12_33; - wire pp_13_33; - wire pp_14_33; - wire pp_15_33; - wire pp_16_33; - wire pp_0_34; - wire pp_1_34; - wire pp_2_34; - wire pp_3_34; - wire pp_4_34; - wire pp_5_34; - wire pp_6_34; - wire pp_7_34; - wire pp_8_34; - wire pp_9_34; - wire pp_10_34; - wire pp_11_34; - wire pp_12_34; - wire pp_13_34; - wire pp_14_34; - wire pp_15_34; - wire pp_16_34; - wire pp_17_34; - wire pp_0_35; - wire pp_1_35; - wire pp_2_35; - wire pp_3_35; - wire pp_4_35; - wire pp_5_35; - wire pp_6_35; - wire pp_7_35; - wire pp_8_35; - wire pp_9_35; - wire pp_10_35; - wire pp_11_35; - wire pp_12_35; - wire pp_13_35; - wire pp_14_35; - wire pp_15_35; - wire pp_16_35; - wire pp_17_35; - wire pp_0_36; - wire pp_1_36; - wire pp_2_36; - wire pp_3_36; - wire pp_4_36; - wire pp_5_36; - wire pp_6_36; - wire pp_7_36; - wire pp_8_36; - wire pp_9_36; - wire pp_10_36; - wire pp_11_36; - wire pp_12_36; - wire pp_13_36; - wire pp_14_36; - wire pp_15_36; - wire pp_16_36; - wire pp_17_36; - wire pp_18_36; - wire pp_0_37; - wire pp_1_37; - wire pp_2_37; - wire pp_3_37; - wire pp_4_37; - wire pp_5_37; - wire pp_6_37; - wire pp_7_37; - wire pp_8_37; - wire pp_9_37; - wire pp_10_37; - wire pp_11_37; - wire pp_12_37; - wire pp_13_37; - wire pp_14_37; - wire pp_15_37; - wire pp_16_37; - wire pp_17_37; - wire pp_18_37; - wire pp_0_38; - wire pp_1_38; - wire pp_2_38; - wire pp_3_38; - wire pp_4_38; - wire pp_5_38; - wire pp_6_38; - wire pp_7_38; - wire pp_8_38; - wire pp_9_38; - wire pp_10_38; - wire pp_11_38; - wire pp_12_38; - wire pp_13_38; - wire pp_14_38; - wire pp_15_38; - wire pp_16_38; - wire pp_17_38; - wire pp_18_38; - wire pp_19_38; - wire pp_0_39; - wire pp_1_39; - wire pp_2_39; - wire pp_3_39; - wire pp_4_39; - wire pp_5_39; - wire pp_6_39; - wire pp_7_39; - wire pp_8_39; - wire pp_9_39; - wire pp_10_39; - wire pp_11_39; - wire pp_12_39; - wire pp_13_39; - wire pp_14_39; - wire pp_15_39; - wire pp_16_39; - wire pp_17_39; - wire pp_18_39; - wire pp_19_39; - wire pp_0_40; - wire pp_1_40; - wire pp_2_40; - wire pp_3_40; - wire pp_4_40; - wire pp_5_40; - wire pp_6_40; - wire pp_7_40; - wire pp_8_40; - wire pp_9_40; - wire pp_10_40; - wire pp_11_40; - wire pp_12_40; - wire pp_13_40; - wire pp_14_40; - wire pp_15_40; - wire pp_16_40; - wire pp_17_40; - wire pp_18_40; - wire pp_19_40; - wire pp_20_40; - wire pp_0_41; - wire pp_1_41; - wire pp_2_41; - wire pp_3_41; - wire pp_4_41; - wire pp_5_41; - wire pp_6_41; - wire pp_7_41; - wire pp_8_41; - wire pp_9_41; - wire pp_10_41; - wire pp_11_41; - wire pp_12_41; - wire pp_13_41; - wire pp_14_41; - wire pp_15_41; - wire pp_16_41; - wire pp_17_41; - wire pp_18_41; - wire pp_19_41; - wire pp_20_41; - wire pp_0_42; - wire pp_1_42; - wire pp_2_42; - wire pp_3_42; - wire pp_4_42; - wire pp_5_42; - wire pp_6_42; - wire pp_7_42; - wire pp_8_42; - wire pp_9_42; - wire pp_10_42; - wire pp_11_42; - wire pp_12_42; - wire pp_13_42; - wire pp_14_42; - wire pp_15_42; - wire pp_16_42; - wire pp_17_42; - wire pp_18_42; - wire pp_19_42; - wire pp_20_42; - wire pp_21_42; - wire pp_0_43; - wire pp_1_43; - wire pp_2_43; - wire pp_3_43; - wire pp_4_43; - wire pp_5_43; - wire pp_6_43; - wire pp_7_43; - wire pp_8_43; - wire pp_9_43; - wire pp_10_43; - wire pp_11_43; - wire pp_12_43; - wire pp_13_43; - wire pp_14_43; - wire pp_15_43; - wire pp_16_43; - wire pp_17_43; - wire pp_18_43; - wire pp_19_43; - wire pp_20_43; - wire pp_21_43; - wire pp_0_44; - wire pp_1_44; - wire pp_2_44; - wire pp_3_44; - wire pp_4_44; - wire pp_5_44; - wire pp_6_44; - wire pp_7_44; - wire pp_8_44; - wire pp_9_44; - wire pp_10_44; - wire pp_11_44; - wire pp_12_44; - wire pp_13_44; - wire pp_14_44; - wire pp_15_44; - wire pp_16_44; - wire pp_17_44; - wire pp_18_44; - wire pp_19_44; - wire pp_20_44; - wire pp_21_44; - wire pp_22_44; - wire pp_0_45; - wire pp_1_45; - wire pp_2_45; - wire pp_3_45; - wire pp_4_45; - wire pp_5_45; - wire pp_6_45; - wire pp_7_45; - wire pp_8_45; - wire pp_9_45; - wire pp_10_45; - wire pp_11_45; - wire pp_12_45; - wire pp_13_45; - wire pp_14_45; - wire pp_15_45; - wire pp_16_45; - wire pp_17_45; - wire pp_18_45; - wire pp_19_45; - wire pp_20_45; - wire pp_21_45; - wire pp_22_45; - wire pp_0_46; - wire pp_1_46; - wire pp_2_46; - wire pp_3_46; - wire pp_4_46; - wire pp_5_46; - wire pp_6_46; - wire pp_7_46; - wire pp_8_46; - wire pp_9_46; - wire pp_10_46; - wire pp_11_46; - wire pp_12_46; - wire pp_13_46; - wire pp_14_46; - wire pp_15_46; - wire pp_16_46; - wire pp_17_46; - wire pp_18_46; - wire pp_19_46; - wire pp_20_46; - wire pp_21_46; - wire pp_22_46; - wire pp_23_46; - wire pp_0_47; - wire pp_1_47; - wire pp_2_47; - wire pp_3_47; - wire pp_4_47; - wire pp_5_47; - wire pp_6_47; - wire pp_7_47; - wire pp_8_47; - wire pp_9_47; - wire pp_10_47; - wire pp_11_47; - wire pp_12_47; - wire pp_13_47; - wire pp_14_47; - wire pp_15_47; - wire pp_16_47; - wire pp_17_47; - wire pp_18_47; - wire pp_19_47; - wire pp_20_47; - wire pp_21_47; - wire pp_22_47; - wire pp_23_47; - wire pp_0_48; - wire pp_1_48; - wire pp_2_48; - wire pp_3_48; - wire pp_4_48; - wire pp_5_48; - wire pp_6_48; - wire pp_7_48; - wire pp_8_48; - wire pp_9_48; - wire pp_10_48; - wire pp_11_48; - wire pp_12_48; - wire pp_13_48; - wire pp_14_48; - wire pp_15_48; - wire pp_16_48; - wire pp_17_48; - wire pp_18_48; - wire pp_19_48; - wire pp_20_48; - wire pp_21_48; - wire pp_22_48; - wire pp_23_48; - wire pp_24_48; - wire pp_0_49; - wire pp_1_49; - wire pp_2_49; - wire pp_3_49; - wire pp_4_49; - wire pp_5_49; - wire pp_6_49; - wire pp_7_49; - wire pp_8_49; - wire pp_9_49; - wire pp_10_49; - wire pp_11_49; - wire pp_12_49; - wire pp_13_49; - wire pp_14_49; - wire pp_15_49; - wire pp_16_49; - wire pp_17_49; - wire pp_18_49; - wire pp_19_49; - wire pp_20_49; - wire pp_21_49; - wire pp_22_49; - wire pp_23_49; - wire pp_24_49; - wire pp_0_50; - wire pp_1_50; - wire pp_2_50; - wire pp_3_50; - wire pp_4_50; - wire pp_5_50; - wire pp_6_50; - wire pp_7_50; - wire pp_8_50; - wire pp_9_50; - wire pp_10_50; - wire pp_11_50; - wire pp_12_50; - wire pp_13_50; - wire pp_14_50; - wire pp_15_50; - wire pp_16_50; - wire pp_17_50; - wire pp_18_50; - wire pp_19_50; - wire pp_20_50; - wire pp_21_50; - wire pp_22_50; - wire pp_23_50; - wire pp_24_50; - wire pp_25_50; - wire pp_0_51; - wire pp_1_51; - wire pp_2_51; - wire pp_3_51; - wire pp_4_51; - wire pp_5_51; - wire pp_6_51; - wire pp_7_51; - wire pp_8_51; - wire pp_9_51; - wire pp_10_51; - wire pp_11_51; - wire pp_12_51; - wire pp_13_51; - wire pp_14_51; - wire pp_15_51; - wire pp_16_51; - wire pp_17_51; - wire pp_18_51; - wire pp_19_51; - wire pp_20_51; - wire pp_21_51; - wire pp_22_51; - wire pp_23_51; - wire pp_24_51; - wire pp_25_51; - wire pp_0_52; - wire pp_1_52; - wire pp_2_52; - wire pp_3_52; - wire pp_4_52; - wire pp_5_52; - wire pp_6_52; - wire pp_7_52; - wire pp_8_52; - wire pp_9_52; - wire pp_10_52; - wire pp_11_52; - wire pp_12_52; - wire pp_13_52; - wire pp_14_52; - wire pp_15_52; - wire pp_16_52; - wire pp_17_52; - wire pp_18_52; - wire pp_19_52; - wire pp_20_52; - wire pp_21_52; - wire pp_22_52; - wire pp_23_52; - wire pp_24_52; - wire pp_25_52; - wire pp_26_52; - wire pp_0_53; - wire pp_1_53; - wire pp_2_53; - wire pp_3_53; - wire pp_4_53; - wire pp_5_53; - wire pp_6_53; - wire pp_7_53; - wire pp_8_53; - wire pp_9_53; - wire pp_10_53; - wire pp_11_53; - wire pp_12_53; - wire pp_13_53; - wire pp_14_53; - wire pp_15_53; - wire pp_16_53; - wire pp_17_53; - wire pp_18_53; - wire pp_19_53; - wire pp_20_53; - wire pp_21_53; - wire pp_22_53; - wire pp_23_53; - wire pp_24_53; - wire pp_25_53; - wire pp_26_53; - wire pp_0_54; - wire pp_1_54; - wire pp_2_54; - wire pp_3_54; - wire pp_4_54; - wire pp_5_54; - wire pp_6_54; - wire pp_7_54; - wire pp_8_54; - wire pp_9_54; - wire pp_10_54; - wire pp_11_54; - wire pp_12_54; - wire pp_13_54; - wire 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pp_29_88; - wire pp_30_88; - wire pp_31_88; - wire pp_32_88; - wire pp_13_89; - wire pp_14_89; - wire pp_15_89; - wire pp_16_89; - wire pp_17_89; - wire pp_18_89; - wire pp_19_89; - wire pp_20_89; - wire pp_21_89; - wire pp_22_89; - wire pp_23_89; - wire pp_24_89; - wire pp_25_89; - wire pp_26_89; - wire pp_27_89; - wire pp_28_89; - wire pp_29_89; - wire pp_30_89; - wire pp_31_89; - wire pp_32_89; - wire pp_13_90; - wire pp_14_90; - wire pp_15_90; - wire pp_16_90; - wire pp_17_90; - wire pp_18_90; - wire pp_19_90; - wire pp_20_90; - wire pp_21_90; - wire pp_22_90; - wire pp_23_90; - wire pp_24_90; - wire pp_25_90; - wire pp_26_90; - wire pp_27_90; - wire pp_28_90; - wire pp_29_90; - wire pp_30_90; - wire pp_31_90; - wire pp_32_90; - wire pp_14_91; - wire pp_15_91; - wire pp_16_91; - wire pp_17_91; - wire pp_18_91; - wire pp_19_91; - wire pp_20_91; - wire pp_21_91; - wire pp_22_91; - wire pp_23_91; - wire pp_24_91; - wire pp_25_91; - wire pp_26_91; - wire pp_27_91; - wire pp_28_91; - wire pp_29_91; - wire pp_30_91; - wire pp_31_91; - wire pp_32_91; - wire pp_14_92; - wire pp_15_92; - wire pp_16_92; - wire pp_17_92; - wire pp_18_92; - wire pp_19_92; - wire pp_20_92; - wire pp_21_92; - wire pp_22_92; - wire pp_23_92; - wire pp_24_92; - wire pp_25_92; - wire pp_26_92; - wire pp_27_92; - wire pp_28_92; - wire pp_29_92; - wire pp_30_92; - wire pp_31_92; - wire pp_32_92; - wire pp_15_93; - wire pp_16_93; - wire pp_17_93; - wire pp_18_93; - wire pp_19_93; - wire pp_20_93; - wire pp_21_93; - wire pp_22_93; - wire pp_23_93; - wire pp_24_93; - wire pp_25_93; - wire pp_26_93; - wire pp_27_93; - wire pp_28_93; - wire pp_29_93; - wire pp_30_93; - wire pp_31_93; - wire pp_32_93; - wire pp_15_94; - wire pp_16_94; - wire pp_17_94; - wire pp_18_94; - wire pp_19_94; - wire pp_20_94; - wire pp_21_94; - wire pp_22_94; - wire pp_23_94; - wire pp_24_94; - wire pp_25_94; - wire pp_26_94; - wire pp_27_94; - wire pp_28_94; - wire pp_29_94; - wire pp_30_94; - wire pp_31_94; - wire pp_32_94; - wire pp_16_95; - wire pp_17_95; - wire pp_18_95; - wire pp_19_95; - wire pp_20_95; - wire pp_21_95; - wire pp_22_95; - wire pp_23_95; - wire pp_24_95; - wire pp_25_95; - wire pp_26_95; - wire pp_27_95; - wire pp_28_95; - wire pp_29_95; - wire pp_30_95; - wire pp_31_95; - wire pp_32_95; - wire pp_16_96; - wire pp_17_96; - wire pp_18_96; - wire pp_19_96; - wire pp_20_96; - wire pp_21_96; - wire pp_22_96; - wire pp_23_96; - wire pp_24_96; - wire pp_25_96; - wire pp_26_96; - wire pp_27_96; - wire pp_28_96; - wire pp_29_96; - wire pp_30_96; - wire pp_31_96; - wire pp_32_96; - wire pp_17_97; - wire pp_18_97; - wire pp_19_97; - wire pp_20_97; - wire pp_21_97; - wire pp_22_97; - wire pp_23_97; - wire pp_24_97; - wire pp_25_97; - wire pp_26_97; - wire pp_27_97; - wire pp_28_97; - wire pp_29_97; - wire pp_30_97; - wire pp_31_97; - wire pp_32_97; - wire pp_17_98; - wire pp_18_98; - wire pp_19_98; - wire pp_20_98; - wire pp_21_98; - wire pp_22_98; - wire pp_23_98; - wire pp_24_98; - wire pp_25_98; - wire pp_26_98; - wire pp_27_98; - wire pp_28_98; - wire pp_29_98; - wire pp_30_98; - wire pp_31_98; - wire pp_32_98; - wire pp_18_99; - wire pp_19_99; - wire pp_20_99; - wire pp_21_99; - wire pp_22_99; - wire pp_23_99; - wire pp_24_99; - wire pp_25_99; - wire pp_26_99; - wire pp_27_99; - wire pp_28_99; - wire pp_29_99; - wire pp_30_99; - wire pp_31_99; - wire pp_32_99; - wire pp_18_100; - wire pp_19_100; - wire pp_20_100; - wire pp_21_100; - wire pp_22_100; - wire pp_23_100; - wire pp_24_100; - wire pp_25_100; - wire pp_26_100; - wire pp_27_100; - wire pp_28_100; - wire pp_29_100; - wire pp_30_100; - wire pp_31_100; - wire pp_32_100; - wire pp_19_101; - wire pp_20_101; - wire pp_21_101; - wire pp_22_101; - wire pp_23_101; - wire pp_24_101; - wire pp_25_101; - wire pp_26_101; - wire pp_27_101; - wire pp_28_101; - wire pp_29_101; - wire pp_30_101; - wire pp_31_101; - wire pp_32_101; - wire pp_19_102; - wire pp_20_102; - wire pp_21_102; - wire pp_22_102; - wire pp_23_102; - wire pp_24_102; - wire pp_25_102; - wire pp_26_102; - wire pp_27_102; - wire pp_28_102; - wire pp_29_102; - wire pp_30_102; - wire pp_31_102; - wire pp_32_102; - wire pp_20_103; - wire pp_21_103; - wire pp_22_103; - wire pp_23_103; - wire pp_24_103; - wire pp_25_103; - wire pp_26_103; - wire pp_27_103; - wire pp_28_103; - wire pp_29_103; - wire pp_30_103; - wire pp_31_103; - wire pp_32_103; - wire pp_20_104; - wire pp_21_104; - wire pp_22_104; - wire pp_23_104; - wire pp_24_104; - wire pp_25_104; - wire pp_26_104; - wire pp_27_104; - wire pp_28_104; - wire pp_29_104; - wire pp_30_104; - wire pp_31_104; - wire pp_32_104; - wire pp_21_105; - wire pp_22_105; - wire pp_23_105; - wire pp_24_105; - wire pp_25_105; - wire pp_26_105; - wire pp_27_105; - wire pp_28_105; - wire pp_29_105; - wire pp_30_105; - wire pp_31_105; - wire pp_32_105; - wire pp_21_106; - wire pp_22_106; - wire pp_23_106; - wire pp_24_106; - wire pp_25_106; - wire pp_26_106; - wire pp_27_106; - wire pp_28_106; - wire pp_29_106; - wire pp_30_106; - wire pp_31_106; - wire pp_32_106; - wire pp_22_107; - wire pp_23_107; - wire pp_24_107; - wire pp_25_107; - wire pp_26_107; - wire pp_27_107; - wire pp_28_107; - wire pp_29_107; - wire pp_30_107; - wire pp_31_107; - wire pp_32_107; - wire pp_22_108; - wire pp_23_108; - wire pp_24_108; - wire pp_25_108; - wire pp_26_108; - wire pp_27_108; - wire pp_28_108; - wire pp_29_108; - wire pp_30_108; - wire pp_31_108; - wire pp_32_108; - wire pp_23_109; - wire pp_24_109; - wire pp_25_109; - wire pp_26_109; - wire pp_27_109; - wire pp_28_109; - wire pp_29_109; - wire pp_30_109; - wire pp_31_109; - wire pp_32_109; - wire pp_23_110; - wire pp_24_110; - wire pp_25_110; - wire pp_26_110; - wire pp_27_110; - wire pp_28_110; - wire pp_29_110; - wire pp_30_110; - wire pp_31_110; - wire pp_32_110; - wire pp_24_111; - wire pp_25_111; - wire pp_26_111; - wire pp_27_111; - wire pp_28_111; - wire pp_29_111; - wire pp_30_111; - wire pp_31_111; - wire pp_32_111; - wire pp_24_112; - wire pp_25_112; - wire pp_26_112; - wire pp_27_112; - wire pp_28_112; - wire pp_29_112; - wire pp_30_112; - wire pp_31_112; - wire pp_32_112; - wire pp_25_113; - wire pp_26_113; - wire pp_27_113; - wire pp_28_113; - wire pp_29_113; - wire pp_30_113; - wire pp_31_113; - wire pp_32_113; - wire pp_25_114; - wire pp_26_114; - wire pp_27_114; - wire pp_28_114; - wire pp_29_114; - wire pp_30_114; - wire pp_31_114; - wire pp_32_114; - wire pp_26_115; - wire pp_27_115; - wire pp_28_115; - wire pp_29_115; - wire pp_30_115; - wire pp_31_115; - wire pp_32_115; - wire pp_26_116; - wire pp_27_116; - wire pp_28_116; - wire pp_29_116; - wire pp_30_116; - wire pp_31_116; - wire pp_32_116; - wire pp_27_117; - wire pp_28_117; - wire pp_29_117; - wire pp_30_117; - wire pp_31_117; - wire pp_32_117; - wire pp_27_118; - wire pp_28_118; - wire pp_29_118; - wire pp_30_118; - wire pp_31_118; - wire pp_32_118; - wire pp_28_119; - wire pp_29_119; - wire pp_30_119; - wire pp_31_119; - wire pp_32_119; - wire pp_28_120; - wire pp_29_120; - wire pp_30_120; - wire pp_31_120; - wire pp_32_120; - wire pp_29_121; - wire pp_30_121; - wire pp_31_121; - wire pp_32_121; - wire pp_29_122; - wire pp_30_122; - wire pp_31_122; - wire pp_32_122; - wire pp_30_123; - wire pp_31_123; - wire pp_32_123; - wire pp_30_124; - wire pp_31_124; - wire pp_32_124; - wire pp_31_125; - wire pp_32_125; - wire pp_31_126; - wire pp_32_126; - wire pp_32_127; - - // Below are the intermediate nets generated by the tree adders - wire int_0_2; - wire int_1_2; - wire int_0_3; - wire int_1_3; - wire int_0_4; - wire int_1_4; - wire int_2_4; - wire int_3_4; - wire int_0_5; - wire int_1_5; - wire int_2_5; - wire int_3_5; - wire int_0_6; - wire int_1_6; - wire int_2_6; - wire int_3_6; - wire int_4_6; - wire int_5_6; - wire int_0_7; - wire int_1_7; - wire int_2_7; - wire int_3_7; - wire int_4_7; - wire int_5_7; - wire int_0_8; - wire int_1_8; - wire int_2_8; - wire int_3_8; - wire int_4_8; - wire int_5_8; - wire int_6_8; - wire int_7_8; - wire int_0_9; - wire int_1_9; - wire int_2_9; - wire int_3_9; - wire int_4_9; - wire int_5_9; - wire int_6_9; - wire int_7_9; - wire int_0_10; - wire int_1_10; - wire int_2_10; - wire int_3_10; - wire int_4_10; - wire int_5_10; - wire int_6_10; - wire int_7_10; - wire int_8_10; - wire int_9_10; - wire int_0_11; - wire int_1_11; - wire int_2_11; - wire int_3_11; - wire int_4_11; - wire int_5_11; - wire int_6_11; - wire int_7_11; - wire int_8_11; - wire int_9_11; - wire int_0_12; - wire int_1_12; - wire int_2_12; - wire int_3_12; - wire int_4_12; - wire int_5_12; - wire int_6_12; - wire int_7_12; - wire int_8_12; - wire int_9_12; - wire int_10_12; - wire int_11_12; - wire int_0_13; - wire int_1_13; - wire int_2_13; - wire int_3_13; - wire int_4_13; - wire int_5_13; - wire int_6_13; - wire int_7_13; - wire int_8_13; - wire int_9_13; - wire int_10_13; - wire int_11_13; - wire int_0_14; - wire int_1_14; - wire int_2_14; - wire int_3_14; - wire int_4_14; - wire int_5_14; - wire int_6_14; - wire int_7_14; - wire int_8_14; - wire int_9_14; - wire int_10_14; - wire int_11_14; - wire int_12_14; - wire int_13_14; - wire int_0_15; - wire int_1_15; - wire int_2_15; - wire int_3_15; - wire int_4_15; - wire int_5_15; - wire int_6_15; - wire int_7_15; - wire int_8_15; - wire int_9_15; - wire int_10_15; - wire int_11_15; - wire int_12_15; - wire int_13_15; - wire int_0_16; - wire int_1_16; - wire int_2_16; - wire int_3_16; - wire int_4_16; - wire int_5_16; - wire int_6_16; - wire int_7_16; - wire int_8_16; - wire int_9_16; - wire int_10_16; - wire int_11_16; - wire int_12_16; - wire int_13_16; - wire int_14_16; - wire int_15_16; - wire int_0_17; - wire int_1_17; - wire int_2_17; - wire int_3_17; - wire int_4_17; - wire int_5_17; - wire int_6_17; - wire int_7_17; - wire int_8_17; - wire int_9_17; - wire int_10_17; - wire int_11_17; - wire int_12_17; - wire int_13_17; - wire int_14_17; - wire int_15_17; - wire int_0_18; - wire int_1_18; - wire int_2_18; - wire int_3_18; - wire int_4_18; - wire int_5_18; - wire int_6_18; - wire int_7_18; - wire int_8_18; - wire int_9_18; - wire int_10_18; - wire int_11_18; - wire int_12_18; - wire int_13_18; - wire int_14_18; - wire int_15_18; - wire int_16_18; - wire int_17_18; - wire int_0_19; - wire int_1_19; - wire int_2_19; - wire int_3_19; - wire int_4_19; - wire int_5_19; - wire int_6_19; - wire int_7_19; - wire int_8_19; - wire int_9_19; - wire int_10_19; - wire int_11_19; - wire int_12_19; - wire int_13_19; - wire int_14_19; - wire int_15_19; - wire int_16_19; - wire int_17_19; - wire int_0_20; - wire int_1_20; - wire int_2_20; - wire int_3_20; - wire int_4_20; - wire int_5_20; - wire int_6_20; - wire int_7_20; - wire int_8_20; - wire int_9_20; - wire int_10_20; - wire int_11_20; - wire int_12_20; - wire int_13_20; - wire int_14_20; - wire int_15_20; - wire int_16_20; - wire int_17_20; - wire int_18_20; - wire int_19_20; - wire int_0_21; - wire int_1_21; - wire int_2_21; - wire int_3_21; - wire int_4_21; - wire int_5_21; - wire int_6_21; - wire int_7_21; - wire int_8_21; - wire int_9_21; - wire int_10_21; - wire int_11_21; - wire int_12_21; - wire int_13_21; - wire int_14_21; - wire int_15_21; - wire int_16_21; - wire int_17_21; - wire int_18_21; - wire int_19_21; - wire int_0_22; - wire int_1_22; - wire int_2_22; - wire int_3_22; - wire int_4_22; - wire int_5_22; - wire int_6_22; - wire int_7_22; - wire int_8_22; - wire int_9_22; - wire int_10_22; - wire int_11_22; - wire int_12_22; - wire int_13_22; - wire int_14_22; - wire int_15_22; - wire int_16_22; - wire int_17_22; - wire int_18_22; - wire int_19_22; - wire int_20_22; - wire int_21_22; - wire int_0_23; - wire int_1_23; - wire int_2_23; - wire int_3_23; - wire int_4_23; - wire int_5_23; - wire int_6_23; - wire int_7_23; - wire int_8_23; - wire int_9_23; - wire int_10_23; - wire int_11_23; - wire int_12_23; - wire int_13_23; - wire int_14_23; - wire int_15_23; - wire int_16_23; - wire int_17_23; - wire int_18_23; - wire int_19_23; - wire int_20_23; - wire int_21_23; - wire int_0_24; - wire int_1_24; - wire int_2_24; - wire int_3_24; - wire int_4_24; - wire int_5_24; - wire int_6_24; - wire int_7_24; - wire int_8_24; - wire int_9_24; - wire int_10_24; - wire int_11_24; - wire int_12_24; - wire int_13_24; - wire int_14_24; - wire int_15_24; - wire int_16_24; - wire int_17_24; - wire int_18_24; - wire int_19_24; - wire int_20_24; - wire int_21_24; - wire int_22_24; - wire int_23_24; - wire int_0_25; - wire int_1_25; - wire int_2_25; - wire int_3_25; - wire int_4_25; - wire int_5_25; - wire int_6_25; - wire int_7_25; - wire int_8_25; - wire int_9_25; - wire int_10_25; - wire int_11_25; - wire int_12_25; - wire int_13_25; - wire int_14_25; - wire int_15_25; - wire int_16_25; - wire int_17_25; - wire int_18_25; - wire int_19_25; - wire int_20_25; - wire int_21_25; - wire int_22_25; - wire int_23_25; - wire int_0_26; - wire int_1_26; - wire int_2_26; - wire int_3_26; - wire int_4_26; - wire int_5_26; - wire int_6_26; - wire int_7_26; - wire int_8_26; - wire int_9_26; - wire int_10_26; - wire int_11_26; - wire int_12_26; - wire int_13_26; - wire int_14_26; - wire int_15_26; - wire int_16_26; - wire int_17_26; - wire int_18_26; - wire int_19_26; - wire int_20_26; - wire int_21_26; - wire int_22_26; - wire int_23_26; - wire int_24_26; - wire int_25_26; - wire int_0_27; - wire int_1_27; - wire int_2_27; - wire int_3_27; - wire int_4_27; - wire int_5_27; - wire int_6_27; - wire int_7_27; - wire int_8_27; - wire int_9_27; - wire int_10_27; - wire int_11_27; - wire int_12_27; - wire int_13_27; - wire int_14_27; - wire int_15_27; - wire int_16_27; - wire int_17_27; - wire int_18_27; - wire int_19_27; - wire int_20_27; - wire int_21_27; - wire int_22_27; - wire int_23_27; - wire int_24_27; - wire int_25_27; - wire int_0_28; - wire int_1_28; - wire int_2_28; - wire int_3_28; - wire int_4_28; - wire int_5_28; - wire int_6_28; - wire int_7_28; - wire int_8_28; - wire int_9_28; - wire int_10_28; - wire int_11_28; - wire int_12_28; - wire int_13_28; - wire int_14_28; - wire int_15_28; - wire int_16_28; - wire int_17_28; - wire int_18_28; - wire int_19_28; - wire int_20_28; - wire int_21_28; - wire int_22_28; - wire int_23_28; - wire int_24_28; - wire int_25_28; - wire int_26_28; - wire int_27_28; - wire int_0_29; - wire int_1_29; - wire int_2_29; - wire int_3_29; - wire int_4_29; - wire int_5_29; - wire int_6_29; - wire int_7_29; - wire int_8_29; - wire int_9_29; - wire int_10_29; - wire int_11_29; - wire int_12_29; - wire int_13_29; - wire int_14_29; - wire int_15_29; - wire int_16_29; - wire int_17_29; - wire int_18_29; - wire int_19_29; - wire int_20_29; - wire int_21_29; - wire int_22_29; - wire int_23_29; - wire int_24_29; - wire int_25_29; - wire int_26_29; - wire int_27_29; - wire int_0_30; - wire int_1_30; - wire int_2_30; - wire int_3_30; - wire int_4_30; - wire int_5_30; - wire int_6_30; - wire int_7_30; - wire int_8_30; - wire int_9_30; - wire int_10_30; - wire int_11_30; - wire int_12_30; - wire int_13_30; - wire int_14_30; - wire int_15_30; - wire int_16_30; - wire int_17_30; - wire int_18_30; - wire int_19_30; - wire int_20_30; - wire int_21_30; - wire int_22_30; - wire int_23_30; - wire int_24_30; - wire int_25_30; - wire int_26_30; - wire int_27_30; - wire int_28_30; - wire int_29_30; - wire int_0_31; - wire int_1_31; - wire int_2_31; - wire int_3_31; - wire int_4_31; - wire int_5_31; - wire int_6_31; - wire int_7_31; - wire int_8_31; - wire int_9_31; - wire int_10_31; - wire int_11_31; - wire int_12_31; - wire int_13_31; - wire int_14_31; - wire int_15_31; - wire int_16_31; - wire int_17_31; - wire int_18_31; - wire int_19_31; - wire int_20_31; - wire int_21_31; - wire int_22_31; - wire int_23_31; - wire int_24_31; - wire int_25_31; - wire int_26_31; - wire int_27_31; - wire int_28_31; - wire int_29_31; - wire int_0_32; - wire int_1_32; - wire int_2_32; - wire int_3_32; - wire int_4_32; - wire int_5_32; - wire int_6_32; - wire int_7_32; - wire int_8_32; - wire int_9_32; - wire int_10_32; - wire int_11_32; - wire int_12_32; - wire int_13_32; - wire int_14_32; - wire int_15_32; - wire int_16_32; - wire int_17_32; - wire int_18_32; - wire int_19_32; - wire int_20_32; - wire int_21_32; - wire int_22_32; - wire int_23_32; - wire int_24_32; - wire int_25_32; - wire int_26_32; - wire int_27_32; - wire int_28_32; - wire int_29_32; - wire int_30_32; - wire int_31_32; - wire int_0_33; - wire int_1_33; - wire int_2_33; - wire int_3_33; - wire int_4_33; - wire int_5_33; - wire int_6_33; - wire int_7_33; - wire int_8_33; - wire int_9_33; - wire int_10_33; - wire int_11_33; - wire int_12_33; - wire int_13_33; - wire int_14_33; - wire int_15_33; - wire int_16_33; - wire int_17_33; - wire int_18_33; - wire int_19_33; - wire int_20_33; - wire int_21_33; - wire int_22_33; - wire int_23_33; - wire int_24_33; - wire int_25_33; - wire int_26_33; - wire int_27_33; - wire int_28_33; - wire int_29_33; - wire int_30_33; - wire int_31_33; - wire int_0_34; - wire int_1_34; - wire int_2_34; - wire int_3_34; - wire int_4_34; - wire int_5_34; - wire int_6_34; - wire int_7_34; - wire int_8_34; - wire int_9_34; - wire int_10_34; - wire int_11_34; - wire int_12_34; - wire int_13_34; - wire int_14_34; - wire int_15_34; - wire int_16_34; - wire int_17_34; - wire int_18_34; - wire int_19_34; - wire int_20_34; - wire int_21_34; - wire int_22_34; - wire int_23_34; - wire int_24_34; - wire int_25_34; - wire int_26_34; - wire int_27_34; - wire int_28_34; - wire int_29_34; - wire int_30_34; - wire int_31_34; - wire int_32_34; - wire int_33_34; - wire int_0_35; - wire int_1_35; - wire int_2_35; - wire int_3_35; - wire int_4_35; - wire int_5_35; - wire int_6_35; - wire int_7_35; - wire int_8_35; - wire int_9_35; - wire int_10_35; - wire int_11_35; - wire int_12_35; - wire int_13_35; - wire int_14_35; - wire int_15_35; - wire int_16_35; - wire int_17_35; - wire int_18_35; - wire int_19_35; - wire int_20_35; - wire int_21_35; - wire int_22_35; - wire int_23_35; - wire int_24_35; - wire int_25_35; - wire int_26_35; - wire int_27_35; - wire int_28_35; - wire int_29_35; - wire int_30_35; - wire int_31_35; - wire int_32_35; - wire int_33_35; - wire int_0_36; - wire int_1_36; - wire int_2_36; - wire int_3_36; - wire int_4_36; - wire int_5_36; - wire int_6_36; - wire int_7_36; - wire int_8_36; - wire int_9_36; - wire int_10_36; - wire int_11_36; - wire int_12_36; - wire int_13_36; - wire int_14_36; - wire int_15_36; - wire int_16_36; - wire int_17_36; - wire int_18_36; - wire int_19_36; - wire int_20_36; - wire int_21_36; - wire int_22_36; - wire int_23_36; - wire int_24_36; - wire int_25_36; - wire int_26_36; - wire int_27_36; - wire int_28_36; - wire int_29_36; - wire int_30_36; - wire int_31_36; - wire int_32_36; - wire int_33_36; - wire int_34_36; - wire int_35_36; - wire int_0_37; - wire int_1_37; - wire int_2_37; - wire int_3_37; - wire int_4_37; - wire int_5_37; - wire int_6_37; - wire int_7_37; - wire int_8_37; - wire int_9_37; - wire int_10_37; - wire int_11_37; - wire int_12_37; - wire int_13_37; - wire int_14_37; - wire int_15_37; - wire int_16_37; - wire int_17_37; - wire int_18_37; - wire int_19_37; - wire int_20_37; - wire int_21_37; - wire int_22_37; - wire int_23_37; - wire int_24_37; - wire int_25_37; - wire int_26_37; - wire int_27_37; - wire int_28_37; - wire int_29_37; - wire int_30_37; - wire int_31_37; - wire int_32_37; - wire int_33_37; - wire int_34_37; - wire int_35_37; - wire int_0_38; - wire int_1_38; - wire int_2_38; - wire int_3_38; - wire int_4_38; - wire int_5_38; - wire int_6_38; - wire int_7_38; - wire int_8_38; - wire int_9_38; - wire int_10_38; - wire int_11_38; - wire int_12_38; - wire int_13_38; - wire int_14_38; - wire int_15_38; - wire int_16_38; - wire int_17_38; - wire int_18_38; - wire int_19_38; - wire int_20_38; - wire int_21_38; - wire int_22_38; - wire int_23_38; - wire int_24_38; - wire int_25_38; - wire int_26_38; - wire int_27_38; - wire int_28_38; - wire int_29_38; - wire int_30_38; - wire int_31_38; - wire int_32_38; - wire int_33_38; - wire int_34_38; - wire int_35_38; - wire int_36_38; - wire int_37_38; - wire int_0_39; - wire int_1_39; - wire int_2_39; - wire int_3_39; - wire int_4_39; - wire int_5_39; - wire int_6_39; - wire int_7_39; - wire int_8_39; - wire int_9_39; - wire int_10_39; - wire int_11_39; - wire int_12_39; - wire int_13_39; - wire int_14_39; - wire int_15_39; - wire int_16_39; - wire int_17_39; - wire int_18_39; - wire int_19_39; - wire int_20_39; - wire int_21_39; - wire int_22_39; - wire int_23_39; - wire int_24_39; - wire int_25_39; - wire int_26_39; - wire int_27_39; - wire int_28_39; - wire int_29_39; - wire int_30_39; - wire int_31_39; - wire int_32_39; - wire int_33_39; - wire int_34_39; - wire int_35_39; - wire int_36_39; - wire int_37_39; - wire int_0_40; - wire int_1_40; - wire int_2_40; - wire int_3_40; - wire int_4_40; - wire int_5_40; - wire int_6_40; - wire int_7_40; - wire int_8_40; - wire int_9_40; - wire int_10_40; - wire int_11_40; - wire int_12_40; - wire int_13_40; - wire int_14_40; - wire int_15_40; - wire int_16_40; - wire int_17_40; - wire int_18_40; - wire int_19_40; - wire int_20_40; - wire int_21_40; - wire int_22_40; - wire int_23_40; - wire int_24_40; - wire int_25_40; - wire int_26_40; - wire int_27_40; - wire int_28_40; - wire int_29_40; - wire int_30_40; - wire int_31_40; - wire int_32_40; - wire int_33_40; - wire int_34_40; - wire int_35_40; - wire int_36_40; - wire int_37_40; - wire int_38_40; - wire int_39_40; - wire int_0_41; - wire int_1_41; - wire int_2_41; - wire int_3_41; - wire int_4_41; - wire int_5_41; - wire int_6_41; - wire int_7_41; - wire int_8_41; - wire int_9_41; - wire int_10_41; - wire int_11_41; - wire int_12_41; - wire int_13_41; - wire int_14_41; - wire int_15_41; - wire int_16_41; - wire int_17_41; - wire int_18_41; - wire int_19_41; - wire int_20_41; - wire int_21_41; - wire int_22_41; - wire int_23_41; - wire int_24_41; - wire int_25_41; - wire int_26_41; - wire int_27_41; - wire int_28_41; - wire int_29_41; - wire int_30_41; - wire int_31_41; - wire int_32_41; - wire int_33_41; - wire int_34_41; - wire int_35_41; - wire int_36_41; - wire int_37_41; - wire int_38_41; - wire int_39_41; - wire int_0_42; - wire int_1_42; - wire int_2_42; - wire int_3_42; - wire int_4_42; - wire int_5_42; - wire int_6_42; - wire int_7_42; - wire int_8_42; - wire int_9_42; - wire int_10_42; - wire int_11_42; - wire int_12_42; - wire int_13_42; - wire int_14_42; - wire int_15_42; - wire int_16_42; - wire int_17_42; - wire int_18_42; - wire int_19_42; - wire int_20_42; - wire int_21_42; - wire int_22_42; - wire int_23_42; - wire int_24_42; - wire int_25_42; - wire int_26_42; - wire int_27_42; - wire int_28_42; - wire int_29_42; - wire int_30_42; - wire int_31_42; - wire int_32_42; - wire int_33_42; - wire int_34_42; - wire int_35_42; - wire int_36_42; - wire int_37_42; - wire int_38_42; - wire int_39_42; - wire int_40_42; - wire int_41_42; - wire int_0_43; - wire int_1_43; - wire int_2_43; - wire int_3_43; - wire int_4_43; - wire int_5_43; - wire int_6_43; - wire int_7_43; - wire int_8_43; - wire int_9_43; - wire int_10_43; - wire int_11_43; - wire int_12_43; - wire int_13_43; - wire int_14_43; - wire int_15_43; - wire int_16_43; - wire int_17_43; - wire int_18_43; - wire int_19_43; - wire int_20_43; - wire int_21_43; - wire int_22_43; - wire int_23_43; - wire int_24_43; - wire int_25_43; - wire int_26_43; - wire int_27_43; - wire int_28_43; - wire int_29_43; - wire int_30_43; - wire int_31_43; - wire int_32_43; - wire int_33_43; - wire int_34_43; - wire int_35_43; - wire int_36_43; - wire int_37_43; - wire int_38_43; - wire int_39_43; - wire int_40_43; - wire int_41_43; - wire int_0_44; - wire int_1_44; - wire int_2_44; - wire int_3_44; - wire int_4_44; - wire int_5_44; - wire int_6_44; - wire int_7_44; - wire int_8_44; - wire int_9_44; - wire int_10_44; - wire int_11_44; - wire int_12_44; - wire int_13_44; - wire int_14_44; - wire int_15_44; - wire int_16_44; - wire int_17_44; - wire int_18_44; - wire int_19_44; - wire int_20_44; - wire int_21_44; - wire int_22_44; - wire int_23_44; - wire int_24_44; - wire int_25_44; - wire int_26_44; - wire int_27_44; - wire int_28_44; - wire int_29_44; - wire int_30_44; - wire int_31_44; - wire int_32_44; - wire int_33_44; - wire int_34_44; - wire int_35_44; - wire int_36_44; - wire int_37_44; - wire int_38_44; - wire int_39_44; - wire int_40_44; - wire int_41_44; - wire int_42_44; - wire int_43_44; - wire int_0_45; - wire int_1_45; - wire int_2_45; - wire int_3_45; - wire int_4_45; - wire int_5_45; - wire int_6_45; - wire int_7_45; - wire int_8_45; - wire int_9_45; - wire int_10_45; - wire int_11_45; - wire int_12_45; - wire int_13_45; - wire int_14_45; - wire int_15_45; - wire int_16_45; - wire int_17_45; - wire int_18_45; - wire int_19_45; - wire int_20_45; - wire int_21_45; - wire int_22_45; - wire int_23_45; - wire int_24_45; - wire int_25_45; - wire int_26_45; - wire int_27_45; - wire int_28_45; - wire int_29_45; - wire int_30_45; - wire int_31_45; - wire int_32_45; - wire int_33_45; - wire int_34_45; - wire int_35_45; - wire int_36_45; - wire int_37_45; - wire int_38_45; - wire int_39_45; - wire int_40_45; - wire int_41_45; - wire int_42_45; - wire int_43_45; - wire int_0_46; - wire int_1_46; - wire int_2_46; - wire int_3_46; - wire int_4_46; - wire int_5_46; - wire int_6_46; - wire int_7_46; - wire int_8_46; - wire int_9_46; - wire int_10_46; - wire int_11_46; - wire int_12_46; - wire int_13_46; - wire int_14_46; - wire int_15_46; - wire int_16_46; - wire int_17_46; - wire int_18_46; - wire int_19_46; - wire int_20_46; - wire int_21_46; - wire int_22_46; - wire int_23_46; - wire int_24_46; - wire int_25_46; - wire int_26_46; - wire int_27_46; - wire int_28_46; - wire int_29_46; - wire int_30_46; - wire int_31_46; - wire int_32_46; - wire int_33_46; - wire int_34_46; - wire int_35_46; - wire int_36_46; - wire int_37_46; - wire int_38_46; - wire int_39_46; - wire int_40_46; - wire int_41_46; - wire int_42_46; - wire int_43_46; - wire int_44_46; - wire int_45_46; - wire int_0_47; - wire int_1_47; - wire int_2_47; - wire int_3_47; - wire int_4_47; - wire int_5_47; - wire int_6_47; - wire int_7_47; - wire int_8_47; - wire int_9_47; - wire int_10_47; - wire int_11_47; - wire int_12_47; - wire int_13_47; - wire int_14_47; - wire int_15_47; - wire int_16_47; - wire int_17_47; - wire int_18_47; - wire int_19_47; - wire int_20_47; - wire int_21_47; - wire int_22_47; - wire int_23_47; - wire int_24_47; - wire int_25_47; - wire int_26_47; - wire int_27_47; - wire int_28_47; - wire int_29_47; - wire int_30_47; - wire int_31_47; - wire int_32_47; - wire int_33_47; - wire int_34_47; - wire int_35_47; - wire int_36_47; - wire int_37_47; - wire int_38_47; - wire int_39_47; - wire int_40_47; - wire int_41_47; - wire int_42_47; - wire int_43_47; - wire int_44_47; - wire int_45_47; - wire int_0_48; - wire int_1_48; - wire int_2_48; - wire int_3_48; - wire int_4_48; - wire int_5_48; - wire int_6_48; - wire int_7_48; - wire int_8_48; - wire int_9_48; - wire int_10_48; - wire int_11_48; - wire int_12_48; - wire int_13_48; - wire int_14_48; - wire int_15_48; - wire int_16_48; - wire int_17_48; - wire int_18_48; - wire int_19_48; - wire int_20_48; - wire int_21_48; - wire int_22_48; - wire int_23_48; - wire int_24_48; - wire int_25_48; - wire int_26_48; - wire int_27_48; - wire int_28_48; - wire int_29_48; - wire int_30_48; - wire int_31_48; - wire int_32_48; - wire int_33_48; - wire int_34_48; - wire int_35_48; - wire int_36_48; - wire int_37_48; - wire int_38_48; - wire int_39_48; - wire int_40_48; - wire int_41_48; - wire int_42_48; - wire int_43_48; - wire int_44_48; - wire int_45_48; - wire int_46_48; - wire int_47_48; - wire int_0_49; - wire int_1_49; - wire int_2_49; - wire int_3_49; - wire int_4_49; - wire int_5_49; - wire int_6_49; - wire int_7_49; - wire int_8_49; - wire int_9_49; - wire int_10_49; - wire int_11_49; - wire int_12_49; - wire int_13_49; - wire int_14_49; - wire int_15_49; - wire int_16_49; - wire int_17_49; - wire int_18_49; - wire int_19_49; - wire int_20_49; - wire int_21_49; - wire int_22_49; - wire int_23_49; - wire int_24_49; - wire int_25_49; - wire int_26_49; - wire int_27_49; - wire int_28_49; - wire int_29_49; - wire int_30_49; - wire int_31_49; - wire int_32_49; - wire int_33_49; - wire int_34_49; - wire int_35_49; - wire int_36_49; - wire int_37_49; - wire int_38_49; - wire int_39_49; - wire int_40_49; - wire int_41_49; - wire int_42_49; - wire int_43_49; - wire int_44_49; - wire int_45_49; - wire int_46_49; - wire int_47_49; - wire int_0_50; - wire int_1_50; - wire int_2_50; - wire int_3_50; - wire int_4_50; - wire int_5_50; - wire int_6_50; - wire int_7_50; - wire int_8_50; - wire int_9_50; - wire int_10_50; - wire int_11_50; - wire int_12_50; - wire int_13_50; - wire int_14_50; - wire int_15_50; - wire int_16_50; - wire int_17_50; - wire int_18_50; - wire int_19_50; - wire int_20_50; - wire int_21_50; - wire int_22_50; - wire int_23_50; - wire int_24_50; - wire int_25_50; - wire int_26_50; - wire int_27_50; - wire int_28_50; - wire int_29_50; - wire int_30_50; - wire int_31_50; - wire int_32_50; - wire int_33_50; - wire int_34_50; - wire int_35_50; - wire int_36_50; - wire int_37_50; - wire int_38_50; - wire int_39_50; - wire int_40_50; - wire int_41_50; - wire int_42_50; - wire int_43_50; - wire int_44_50; - wire int_45_50; - wire int_46_50; - wire int_47_50; - wire int_48_50; - wire int_49_50; - wire int_0_51; - wire int_1_51; - wire int_2_51; - wire int_3_51; - wire int_4_51; - wire int_5_51; - wire int_6_51; - wire int_7_51; - wire int_8_51; - wire int_9_51; - wire int_10_51; - wire int_11_51; - wire int_12_51; - wire int_13_51; - wire int_14_51; - wire int_15_51; - wire int_16_51; - wire int_17_51; - wire int_18_51; - wire int_19_51; - wire int_20_51; - wire int_21_51; - wire int_22_51; - wire int_23_51; - wire int_24_51; - wire int_25_51; - wire int_26_51; - wire int_27_51; - wire int_28_51; - wire int_29_51; - wire int_30_51; - wire int_31_51; - wire int_32_51; - wire int_33_51; - wire int_34_51; - wire int_35_51; - wire int_36_51; - wire int_37_51; - wire int_38_51; - wire int_39_51; - wire int_40_51; - wire int_41_51; - wire int_42_51; - wire int_43_51; - wire int_44_51; - wire int_45_51; - wire int_46_51; - wire int_47_51; - wire int_48_51; - wire int_49_51; - wire int_0_52; - wire int_1_52; - wire int_2_52; - wire int_3_52; - wire int_4_52; - wire int_5_52; - wire int_6_52; - wire int_7_52; - wire int_8_52; - wire int_9_52; - wire int_10_52; - wire int_11_52; - wire int_12_52; - wire int_13_52; - wire int_14_52; - wire int_15_52; - wire int_16_52; - wire int_17_52; - wire int_18_52; - wire int_19_52; - wire int_20_52; - wire int_21_52; - wire int_22_52; - wire int_23_52; - wire int_24_52; - wire int_25_52; - wire int_26_52; - wire int_27_52; - wire int_28_52; - wire int_29_52; - wire int_30_52; - wire int_31_52; - wire int_32_52; - wire int_33_52; - wire int_34_52; - wire int_35_52; - wire int_36_52; - wire int_37_52; - wire int_38_52; - wire int_39_52; - wire int_40_52; - wire int_41_52; - wire int_42_52; - wire int_43_52; - wire int_44_52; - wire int_45_52; - wire int_46_52; - wire int_47_52; - wire int_48_52; - wire int_49_52; - wire int_50_52; - wire int_51_52; - wire int_0_53; - wire int_1_53; - wire int_2_53; - wire int_3_53; - wire int_4_53; - wire int_5_53; - wire int_6_53; - wire int_7_53; - wire int_8_53; - wire int_9_53; - wire int_10_53; - wire int_11_53; - wire int_12_53; - wire int_13_53; - wire int_14_53; - wire int_15_53; - wire int_16_53; - wire int_17_53; - wire int_18_53; - wire int_19_53; - wire int_20_53; - wire int_21_53; - wire int_22_53; - wire int_23_53; - wire int_24_53; - wire int_25_53; - wire int_26_53; - wire int_27_53; - wire int_28_53; - wire int_29_53; - wire int_30_53; - wire int_31_53; - wire int_32_53; - wire int_33_53; - wire int_34_53; - wire int_35_53; - wire int_36_53; - wire int_37_53; - wire int_38_53; - wire int_39_53; - wire int_40_53; - wire int_41_53; - wire int_42_53; - wire int_43_53; - wire int_44_53; - wire int_45_53; - wire int_46_53; - wire int_47_53; - wire int_48_53; - wire int_49_53; - wire int_50_53; - wire int_51_53; - wire int_0_54; - wire int_1_54; - wire int_2_54; - wire int_3_54; - wire int_4_54; - wire int_5_54; - wire int_6_54; - wire int_7_54; - wire int_8_54; - wire int_9_54; - wire int_10_54; - wire int_11_54; - wire int_12_54; - wire int_13_54; - wire int_14_54; - wire int_15_54; - wire int_16_54; - wire int_17_54; - wire int_18_54; - wire int_19_54; - wire int_20_54; - wire int_21_54; - wire int_22_54; - wire int_23_54; - wire int_24_54; - wire int_25_54; - wire int_26_54; - wire int_27_54; - wire int_28_54; - wire int_29_54; - wire int_30_54; - wire int_31_54; - wire int_32_54; - wire int_33_54; - wire int_34_54; - wire int_35_54; - wire int_36_54; - wire int_37_54; - wire int_38_54; - wire int_39_54; - wire int_40_54; - wire int_41_54; - wire int_42_54; - wire int_43_54; - wire int_44_54; - wire int_45_54; - wire int_46_54; - wire int_47_54; - wire int_48_54; - wire int_49_54; - wire int_50_54; - wire int_51_54; - wire int_52_54; - wire int_53_54; - wire int_0_55; - wire int_1_55; - wire int_2_55; - wire int_3_55; - wire int_4_55; - wire int_5_55; - wire int_6_55; - wire int_7_55; - wire int_8_55; - wire int_9_55; - wire int_10_55; - wire int_11_55; - wire int_12_55; - wire int_13_55; - wire int_14_55; - wire int_15_55; - wire int_16_55; - wire int_17_55; - wire int_18_55; - wire int_19_55; - wire int_20_55; - wire int_21_55; - wire int_22_55; - wire int_23_55; - wire int_24_55; - wire int_25_55; - wire int_26_55; - wire int_27_55; - wire int_28_55; - wire int_29_55; - wire int_30_55; - wire int_31_55; - wire int_32_55; - wire int_33_55; - wire int_34_55; - wire int_35_55; - wire int_36_55; - wire int_37_55; - wire int_38_55; - wire int_39_55; - wire int_40_55; - wire int_41_55; - wire int_42_55; - wire int_43_55; - wire int_44_55; - wire int_45_55; - wire int_46_55; - wire int_47_55; - wire int_48_55; - wire int_49_55; - wire int_50_55; - wire int_51_55; - wire int_52_55; - wire int_53_55; - wire int_0_56; - wire int_1_56; - wire int_2_56; - wire int_3_56; - wire int_4_56; - wire int_5_56; - wire int_6_56; - wire int_7_56; - wire int_8_56; - wire int_9_56; - wire int_10_56; - wire int_11_56; - wire int_12_56; - wire int_13_56; - wire int_14_56; - wire int_15_56; - wire int_16_56; - wire int_17_56; - wire int_18_56; - wire int_19_56; - wire int_20_56; - wire int_21_56; - wire int_22_56; - wire int_23_56; - wire int_24_56; - wire int_25_56; - wire int_26_56; - wire int_27_56; - wire int_28_56; - wire int_29_56; - wire int_30_56; - wire int_31_56; - wire int_32_56; - wire int_33_56; - wire int_34_56; - wire int_35_56; - wire int_36_56; - wire int_37_56; - wire int_38_56; - wire int_39_56; - wire int_40_56; - wire int_41_56; - wire int_42_56; - wire int_43_56; - wire int_44_56; - wire int_45_56; - wire int_46_56; - wire int_47_56; - wire int_48_56; - wire int_49_56; - wire int_50_56; - wire int_51_56; - wire int_52_56; - wire int_53_56; - wire int_54_56; - wire int_55_56; - wire int_0_57; - wire int_1_57; - wire int_2_57; - wire int_3_57; - wire int_4_57; - wire int_5_57; - wire int_6_57; - wire int_7_57; - wire int_8_57; - wire int_9_57; - wire int_10_57; - wire int_11_57; - wire int_12_57; - wire int_13_57; - wire int_14_57; - wire int_15_57; - wire int_16_57; - wire int_17_57; - wire int_18_57; - wire int_19_57; - wire int_20_57; - wire int_21_57; - wire int_22_57; - wire int_23_57; - wire int_24_57; - wire int_25_57; - wire int_26_57; - wire int_27_57; - wire int_28_57; - wire int_29_57; - wire int_30_57; - wire int_31_57; - wire int_32_57; - wire int_33_57; - wire int_34_57; - wire int_35_57; - wire int_36_57; - wire int_37_57; - wire int_38_57; - wire int_39_57; - wire int_40_57; - wire int_41_57; - wire int_42_57; - wire int_43_57; - wire int_44_57; - wire int_45_57; - wire int_46_57; - wire int_47_57; - wire int_48_57; - wire int_49_57; - wire int_50_57; - wire int_51_57; - wire int_52_57; - wire int_53_57; - wire int_54_57; - wire int_55_57; - wire int_0_58; - wire int_1_58; - wire int_2_58; - wire int_3_58; - wire int_4_58; - wire int_5_58; - wire int_6_58; - wire int_7_58; - wire int_8_58; - wire int_9_58; - wire int_10_58; - wire int_11_58; - wire int_12_58; - wire int_13_58; - wire int_14_58; - wire int_15_58; - wire int_16_58; - wire int_17_58; - wire int_18_58; - wire int_19_58; - wire int_20_58; - wire int_21_58; - wire int_22_58; - wire int_23_58; - wire int_24_58; - wire int_25_58; - wire int_26_58; - wire int_27_58; - wire int_28_58; - wire int_29_58; - wire int_30_58; - wire int_31_58; - wire int_32_58; - wire int_33_58; - wire int_34_58; - wire int_35_58; - wire int_36_58; - wire int_37_58; - wire int_38_58; - wire int_39_58; - wire int_40_58; - wire int_41_58; - wire int_42_58; - wire int_43_58; - wire int_44_58; - wire int_45_58; - wire int_46_58; - wire int_47_58; - wire int_48_58; - wire int_49_58; - wire int_50_58; - wire int_51_58; - wire int_52_58; - wire int_53_58; - wire int_54_58; - wire int_55_58; - wire int_56_58; - wire int_57_58; - wire int_0_59; - wire int_1_59; - wire int_2_59; - wire int_3_59; - wire int_4_59; - wire int_5_59; - wire int_6_59; - wire int_7_59; - wire int_8_59; - wire int_9_59; - wire int_10_59; - wire int_11_59; - wire int_12_59; - wire int_13_59; - wire int_14_59; - wire int_15_59; - wire int_16_59; - wire int_17_59; - wire int_18_59; - wire int_19_59; - wire int_20_59; - wire int_21_59; - wire int_22_59; - wire int_23_59; - wire int_24_59; - wire int_25_59; - wire int_26_59; - wire int_27_59; - wire int_28_59; - wire int_29_59; - wire int_30_59; - wire int_31_59; - wire int_32_59; - wire int_33_59; - wire int_34_59; - wire int_35_59; - wire int_36_59; - wire int_37_59; - wire int_38_59; - wire int_39_59; - wire int_40_59; - wire int_41_59; - wire int_42_59; - wire int_43_59; - wire int_44_59; - wire int_45_59; - wire int_46_59; - wire int_47_59; - wire int_48_59; - wire int_49_59; - wire int_50_59; - wire int_51_59; - wire int_52_59; - wire int_53_59; - wire int_54_59; - wire int_55_59; - wire int_56_59; - wire int_57_59; - wire int_0_60; - wire int_1_60; - wire int_2_60; - wire int_3_60; - wire int_4_60; - wire int_5_60; - wire int_6_60; - wire int_7_60; - wire int_8_60; - wire int_9_60; - wire int_10_60; - wire int_11_60; - wire int_12_60; - wire int_13_60; - wire int_14_60; - wire int_15_60; - wire int_16_60; - wire int_17_60; - wire int_18_60; - wire int_19_60; - wire int_20_60; - wire int_21_60; - wire int_22_60; - wire int_23_60; - wire int_24_60; - wire int_25_60; - wire int_26_60; - wire int_27_60; - wire int_28_60; - wire int_29_60; - wire int_30_60; - wire int_31_60; - wire int_32_60; - wire int_33_60; - wire int_34_60; - wire int_35_60; - wire int_36_60; - wire int_37_60; - wire int_38_60; - wire int_39_60; - wire int_40_60; - wire int_41_60; - wire int_42_60; - wire int_43_60; - wire int_44_60; - wire int_45_60; - wire int_46_60; - wire int_47_60; - wire int_48_60; - wire int_49_60; - wire int_50_60; - wire int_51_60; - wire int_52_60; - wire int_53_60; - wire int_54_60; - wire int_55_60; - wire int_56_60; - wire int_57_60; - wire int_58_60; - wire int_59_60; - wire int_0_61; - wire int_1_61; - wire int_2_61; - wire int_3_61; - wire int_4_61; - wire int_5_61; - wire int_6_61; - wire int_7_61; - wire int_8_61; - wire int_9_61; - wire int_10_61; - wire int_11_61; - wire int_12_61; - wire int_13_61; - wire int_14_61; - wire int_15_61; - wire int_16_61; - wire int_17_61; - wire int_18_61; - wire int_19_61; - wire int_20_61; - wire int_21_61; - wire int_22_61; - wire int_23_61; - wire int_24_61; - wire int_25_61; - wire int_26_61; - wire int_27_61; - wire int_28_61; - wire int_29_61; - wire int_30_61; - wire int_31_61; - wire int_32_61; - wire int_33_61; - wire int_34_61; - wire int_35_61; - wire int_36_61; - wire int_37_61; - wire int_38_61; - wire int_39_61; - wire int_40_61; - wire int_41_61; - wire int_42_61; - wire int_43_61; - wire int_44_61; - wire int_45_61; - wire int_46_61; - wire int_47_61; - wire int_48_61; - wire int_49_61; - wire int_50_61; - wire int_51_61; - wire int_52_61; - wire int_53_61; - wire int_54_61; - wire int_55_61; - wire int_56_61; - wire int_57_61; - wire int_58_61; - wire int_59_61; - wire int_0_62; - wire int_1_62; - wire int_2_62; - wire int_3_62; - wire int_4_62; - wire int_5_62; - wire int_6_62; - wire int_7_62; - wire int_8_62; - wire int_9_62; - wire int_10_62; - wire int_11_62; - wire int_12_62; - wire int_13_62; - wire int_14_62; - wire int_15_62; - wire int_16_62; - wire int_17_62; - wire int_18_62; - wire int_19_62; - wire int_20_62; - wire int_21_62; - wire int_22_62; - wire int_23_62; - wire int_24_62; - wire int_25_62; - wire int_26_62; - wire int_27_62; - wire int_28_62; - wire int_29_62; - wire int_30_62; - wire int_31_62; - wire int_32_62; - wire int_33_62; - wire int_34_62; - wire int_35_62; - wire int_36_62; - wire int_37_62; - wire int_38_62; - wire int_39_62; - wire int_40_62; - wire int_41_62; - wire int_42_62; - wire int_43_62; - wire int_44_62; - wire int_45_62; - wire int_46_62; - wire int_47_62; - wire int_48_62; - wire int_49_62; - wire int_50_62; - wire int_51_62; - wire int_52_62; - wire int_53_62; - wire int_54_62; - wire int_55_62; - wire int_56_62; - wire int_57_62; - wire int_58_62; - wire int_59_62; - wire int_60_62; - wire int_61_62; - wire int_0_63; - wire int_1_63; - wire int_2_63; - wire int_3_63; - wire int_4_63; - wire int_5_63; - wire int_6_63; - wire int_7_63; - wire int_8_63; - wire int_9_63; - wire int_10_63; - wire int_11_63; - wire int_12_63; - wire int_13_63; - wire int_14_63; - wire int_15_63; - wire int_16_63; - wire int_17_63; - wire int_18_63; - wire int_19_63; - wire int_20_63; - wire int_21_63; - wire int_22_63; - wire int_23_63; - wire int_24_63; - wire int_25_63; - wire int_26_63; - wire int_27_63; - wire int_28_63; - wire int_29_63; - wire int_30_63; - wire int_31_63; - wire int_32_63; - wire int_33_63; - wire int_34_63; - wire int_35_63; - wire int_36_63; - wire int_37_63; - wire int_38_63; - wire int_39_63; - wire int_40_63; - wire int_41_63; - wire int_42_63; - wire int_43_63; - wire int_44_63; - wire int_45_63; - wire int_46_63; - wire int_47_63; - wire int_48_63; - wire int_49_63; - wire int_50_63; - wire int_51_63; - wire int_52_63; - wire int_53_63; - wire int_54_63; - wire int_55_63; - wire int_56_63; - wire int_57_63; - wire int_58_63; - wire int_59_63; - wire int_60_63; - wire int_61_63; - wire int_0_64; - wire int_1_64; - wire int_2_64; - wire int_3_64; - wire int_4_64; - wire int_5_64; - wire int_6_64; - wire int_7_64; - wire int_8_64; - wire int_9_64; - wire int_10_64; - wire int_11_64; - wire int_12_64; - wire int_13_64; - wire int_14_64; - wire int_15_64; - wire int_16_64; - wire int_17_64; - wire int_18_64; - wire int_19_64; - wire int_20_64; - wire int_21_64; - wire int_22_64; - wire int_23_64; - wire int_24_64; - wire int_25_64; - wire int_26_64; - wire int_27_64; - wire int_28_64; - wire int_29_64; - wire int_30_64; - wire int_31_64; - wire int_32_64; - wire int_33_64; - wire int_34_64; - wire int_35_64; - wire int_36_64; - wire int_37_64; - wire int_38_64; - wire int_39_64; - wire int_40_64; - wire int_41_64; - wire int_42_64; - wire int_43_64; - wire int_44_64; - wire int_45_64; - wire int_46_64; - wire int_47_64; - wire int_48_64; - wire int_49_64; - wire int_50_64; - wire int_51_64; - wire int_52_64; - wire int_53_64; - wire int_54_64; - wire int_55_64; - wire int_56_64; - wire int_57_64; - wire int_58_64; - wire int_59_64; - wire int_60_64; - wire int_61_64; - wire int_0_65; - wire int_1_65; - wire int_2_65; - wire int_3_65; - wire int_4_65; - wire int_5_65; - wire int_6_65; - wire int_7_65; - wire int_8_65; - wire int_9_65; - wire int_10_65; - wire int_11_65; - wire int_12_65; - wire int_13_65; - wire int_14_65; - wire int_15_65; - wire int_16_65; - wire int_17_65; - wire int_18_65; - wire int_19_65; - wire int_20_65; - wire int_21_65; - wire int_22_65; - wire int_23_65; - wire int_24_65; - wire int_25_65; - wire int_26_65; - wire int_27_65; - wire int_28_65; - wire int_29_65; - wire int_30_65; - wire int_31_65; - wire int_32_65; - wire int_33_65; - wire int_34_65; - wire int_35_65; - wire int_36_65; - wire int_37_65; - wire int_38_65; - wire int_39_65; - wire int_40_65; - wire int_41_65; - wire int_42_65; - wire int_43_65; - wire int_44_65; - wire int_45_65; - wire int_46_65; - wire int_47_65; - wire int_48_65; - wire int_49_65; - wire int_50_65; - wire int_51_65; - wire int_52_65; - wire int_53_65; - wire int_54_65; - wire int_55_65; - wire int_56_65; - wire int_57_65; - wire int_58_65; - wire int_59_65; - wire int_60_65; - wire int_61_65; - wire int_0_66; - wire int_1_66; - wire int_2_66; - wire int_3_66; - wire int_4_66; - wire int_5_66; - wire int_6_66; - wire int_7_66; - wire int_8_66; - wire int_9_66; - wire int_10_66; - wire int_11_66; - wire int_12_66; - wire int_13_66; - wire int_14_66; - wire int_15_66; - wire int_16_66; - wire int_17_66; - wire int_18_66; - wire int_19_66; - wire int_20_66; - wire int_21_66; - wire int_22_66; - wire int_23_66; - wire int_24_66; - wire int_25_66; - wire int_26_66; - wire int_27_66; - wire int_28_66; - wire int_29_66; - wire int_30_66; - wire int_31_66; - wire int_32_66; - wire int_33_66; - wire int_34_66; - wire int_35_66; - wire int_36_66; - wire int_37_66; - wire int_38_66; - wire int_39_66; - wire int_40_66; - wire int_41_66; - wire int_42_66; - wire int_43_66; - wire int_44_66; - wire int_45_66; - wire int_46_66; - wire int_47_66; - wire int_48_66; - wire int_49_66; - wire int_50_66; - wire int_51_66; - wire int_52_66; - wire int_53_66; - wire int_54_66; - wire int_55_66; - wire int_56_66; - wire int_57_66; - wire int_58_66; - wire int_59_66; - wire int_60_66; - wire int_61_66; - wire int_0_67; - wire int_1_67; - wire int_2_67; - wire int_3_67; - wire int_4_67; - wire int_5_67; - wire int_6_67; - wire int_7_67; - wire int_8_67; - wire int_9_67; - wire int_10_67; - wire int_11_67; - wire int_12_67; - wire int_13_67; - wire int_14_67; - wire int_15_67; - wire int_16_67; - wire int_17_67; - wire int_18_67; - wire int_19_67; - wire int_20_67; - wire int_21_67; - wire int_22_67; - wire int_23_67; - wire int_24_67; - wire int_25_67; - wire int_26_67; - wire int_27_67; - wire int_28_67; - wire int_29_67; - wire int_30_67; - wire int_31_67; - wire int_32_67; - wire int_33_67; - wire int_34_67; - wire int_35_67; - wire int_36_67; - wire int_37_67; - wire int_38_67; - wire int_39_67; - wire int_40_67; - wire int_41_67; - wire int_42_67; - wire int_43_67; - wire int_44_67; - wire int_45_67; - wire int_46_67; - wire int_47_67; - wire int_48_67; - wire int_49_67; - wire int_50_67; - wire int_51_67; - wire int_52_67; - wire int_53_67; - wire int_54_67; - wire int_55_67; - wire int_56_67; - wire int_57_67; - wire int_58_67; - wire int_59_67; - wire int_60_67; - wire int_61_67; - wire int_0_68; - wire int_1_68; - wire int_2_68; - wire int_3_68; - wire int_4_68; - wire int_5_68; - wire int_6_68; - wire int_7_68; - wire int_8_68; - wire int_9_68; - wire int_10_68; - wire int_11_68; - wire int_12_68; - wire int_13_68; - wire int_14_68; - wire int_15_68; - wire int_16_68; - wire int_17_68; - wire int_18_68; - wire int_19_68; - wire int_20_68; - wire int_21_68; - wire int_22_68; - wire int_23_68; - wire int_24_68; - wire int_25_68; - wire int_26_68; - wire int_27_68; - wire int_28_68; - wire int_29_68; - wire int_30_68; - wire int_31_68; - wire int_32_68; - wire int_33_68; - wire int_34_68; - wire int_35_68; - wire int_36_68; - wire int_37_68; - wire int_38_68; - wire int_39_68; - wire int_40_68; - wire int_41_68; - wire int_42_68; - wire int_43_68; - wire int_44_68; - wire int_45_68; - wire int_46_68; - wire int_47_68; - wire int_48_68; - wire int_49_68; - wire int_50_68; - wire int_51_68; - wire int_52_68; - wire int_53_68; - wire int_54_68; - wire int_55_68; - wire int_56_68; - wire int_57_68; - wire int_58_68; - wire int_59_68; - wire int_60_68; - wire int_61_68; - wire int_0_69; - wire int_1_69; - wire int_2_69; - wire int_3_69; - wire int_4_69; - wire int_5_69; - wire int_6_69; - wire int_7_69; - wire int_8_69; - wire int_9_69; - wire int_10_69; - wire int_11_69; - wire int_12_69; - wire int_13_69; - wire int_14_69; - wire int_15_69; - wire int_16_69; - wire int_17_69; - wire int_18_69; - wire int_19_69; - wire int_20_69; - wire int_21_69; - wire int_22_69; - wire int_23_69; - wire int_24_69; - wire int_25_69; - wire int_26_69; - wire int_27_69; - wire int_28_69; - wire int_29_69; - wire int_30_69; - wire int_31_69; - wire int_32_69; - wire int_33_69; - wire int_34_69; - wire int_35_69; - wire int_36_69; - wire int_37_69; - wire int_38_69; - wire int_39_69; - wire int_40_69; - wire int_41_69; - wire int_42_69; - wire int_43_69; - wire int_44_69; - wire int_45_69; - wire int_46_69; - wire int_47_69; - wire int_48_69; - wire int_49_69; - wire int_50_69; - wire int_51_69; - wire int_52_69; - wire int_53_69; - wire int_54_69; - wire int_55_69; - wire int_56_69; - wire int_57_69; - wire int_58_69; - wire int_59_69; - wire int_0_70; - wire int_1_70; - wire int_2_70; - wire int_3_70; - wire int_4_70; - wire int_5_70; - wire int_6_70; - wire int_7_70; - wire int_8_70; - wire int_9_70; - wire int_10_70; - wire int_11_70; - wire int_12_70; - wire int_13_70; - wire int_14_70; - wire int_15_70; - wire int_16_70; - wire int_17_70; - wire int_18_70; - wire int_19_70; - wire int_20_70; - wire int_21_70; - wire int_22_70; - wire int_23_70; - wire int_24_70; - wire int_25_70; - wire int_26_70; - wire int_27_70; - wire int_28_70; - wire int_29_70; - wire int_30_70; - wire int_31_70; - wire int_32_70; - wire int_33_70; - wire int_34_70; - wire int_35_70; - wire int_36_70; - wire int_37_70; - wire int_38_70; - wire int_39_70; - wire int_40_70; - wire int_41_70; - wire int_42_70; - wire int_43_70; - wire int_44_70; - wire int_45_70; - wire int_46_70; - wire int_47_70; - wire int_48_70; - wire int_49_70; - wire int_50_70; - wire int_51_70; - wire int_52_70; - wire int_53_70; - wire int_54_70; - wire int_55_70; - wire int_56_70; - wire int_57_70; - wire int_58_70; - wire int_59_70; - wire int_0_71; - wire int_1_71; - wire int_2_71; - wire int_3_71; - wire int_4_71; - wire int_5_71; - wire int_6_71; - wire int_7_71; - wire int_8_71; - wire int_9_71; - wire int_10_71; - wire int_11_71; - wire int_12_71; - wire int_13_71; - wire int_14_71; - wire int_15_71; - wire int_16_71; - wire int_17_71; - wire int_18_71; - wire int_19_71; - wire int_20_71; - wire int_21_71; - wire int_22_71; - wire int_23_71; - wire int_24_71; - wire int_25_71; - wire int_26_71; - wire int_27_71; - wire int_28_71; - wire int_29_71; - wire int_30_71; - wire int_31_71; - wire int_32_71; - wire int_33_71; - wire int_34_71; - wire int_35_71; - wire int_36_71; - wire int_37_71; - wire int_38_71; - wire int_39_71; - wire int_40_71; - wire int_41_71; - wire int_42_71; - wire int_43_71; - wire int_44_71; - wire int_45_71; - wire int_46_71; - wire int_47_71; - wire int_48_71; - wire int_49_71; - wire int_50_71; - wire int_51_71; - wire int_52_71; - wire int_53_71; - wire int_54_71; - wire int_55_71; - wire int_56_71; - wire int_57_71; - wire int_0_72; - wire int_1_72; - wire int_2_72; - wire int_3_72; - wire int_4_72; - wire int_5_72; - wire int_6_72; - wire int_7_72; - wire int_8_72; - wire int_9_72; - wire int_10_72; - wire int_11_72; - wire int_12_72; - wire int_13_72; - wire int_14_72; - wire int_15_72; - wire int_16_72; - wire int_17_72; - wire int_18_72; - wire int_19_72; - wire int_20_72; - wire int_21_72; - wire int_22_72; - wire int_23_72; - wire int_24_72; - wire int_25_72; - wire int_26_72; - wire int_27_72; - wire int_28_72; - wire int_29_72; - wire int_30_72; - wire int_31_72; - wire int_32_72; - wire int_33_72; - wire int_34_72; - wire int_35_72; - wire int_36_72; - wire int_37_72; - wire int_38_72; - wire int_39_72; - wire int_40_72; - wire int_41_72; - wire int_42_72; - wire int_43_72; - wire int_44_72; - wire int_45_72; - wire int_46_72; - wire int_47_72; - wire int_48_72; - wire int_49_72; - wire int_50_72; - wire int_51_72; - wire int_52_72; - wire int_53_72; - wire int_54_72; - wire int_55_72; - wire int_56_72; - wire int_57_72; - wire int_0_73; - wire int_1_73; - wire int_2_73; - wire int_3_73; - wire int_4_73; - wire int_5_73; - wire int_6_73; - wire int_7_73; - wire int_8_73; - wire int_9_73; - wire int_10_73; - wire int_11_73; - wire int_12_73; - wire int_13_73; - wire int_14_73; - wire int_15_73; - wire int_16_73; - wire int_17_73; - wire int_18_73; - wire int_19_73; - wire int_20_73; - wire int_21_73; - wire int_22_73; - wire int_23_73; - wire int_24_73; - wire int_25_73; - wire int_26_73; - wire int_27_73; - wire int_28_73; - wire int_29_73; - wire int_30_73; - wire int_31_73; - wire int_32_73; - wire int_33_73; - wire int_34_73; - wire int_35_73; - wire int_36_73; - wire int_37_73; - wire int_38_73; - wire int_39_73; - wire int_40_73; - wire int_41_73; - wire int_42_73; - wire int_43_73; - wire int_44_73; - wire int_45_73; - wire int_46_73; - wire int_47_73; - wire int_48_73; - wire int_49_73; - wire int_50_73; - wire int_51_73; - wire int_52_73; - wire int_53_73; - wire int_54_73; - wire int_55_73; - wire int_0_74; - wire int_1_74; - wire int_2_74; - wire int_3_74; - wire int_4_74; - wire int_5_74; - wire int_6_74; - wire int_7_74; - wire int_8_74; - wire int_9_74; - wire int_10_74; - wire int_11_74; - wire int_12_74; - wire int_13_74; - wire int_14_74; - wire int_15_74; - wire int_16_74; - wire int_17_74; - wire int_18_74; - wire int_19_74; - wire int_20_74; - wire int_21_74; - wire int_22_74; - wire int_23_74; - wire int_24_74; - wire int_25_74; - wire int_26_74; - wire int_27_74; - wire int_28_74; - wire int_29_74; - wire int_30_74; - wire int_31_74; - wire int_32_74; - wire int_33_74; - wire int_34_74; - wire int_35_74; - wire int_36_74; - wire int_37_74; - wire int_38_74; - wire int_39_74; - wire int_40_74; - wire int_41_74; - wire int_42_74; - wire int_43_74; - wire int_44_74; - wire int_45_74; - wire int_46_74; - wire int_47_74; - wire int_48_74; - wire int_49_74; - wire int_50_74; - wire int_51_74; - wire int_52_74; - wire int_53_74; - wire int_54_74; - wire int_55_74; - wire int_0_75; - wire int_1_75; - wire int_2_75; - wire int_3_75; - wire int_4_75; - wire int_5_75; - wire int_6_75; - wire int_7_75; - wire int_8_75; - wire int_9_75; - wire int_10_75; - wire int_11_75; - wire int_12_75; - wire int_13_75; - wire int_14_75; - wire int_15_75; - wire int_16_75; - wire int_17_75; - wire int_18_75; - wire int_19_75; - wire int_20_75; - wire int_21_75; - wire int_22_75; - wire int_23_75; - wire int_24_75; - wire int_25_75; - wire int_26_75; - wire int_27_75; - wire int_28_75; - wire int_29_75; - wire int_30_75; - wire int_31_75; - wire int_32_75; - wire int_33_75; - wire int_34_75; - wire int_35_75; - wire int_36_75; - wire int_37_75; - wire int_38_75; - wire int_39_75; - wire int_40_75; - wire int_41_75; - wire int_42_75; - wire int_43_75; - wire int_44_75; - wire int_45_75; - wire int_46_75; - wire int_47_75; - wire int_48_75; - wire int_49_75; - wire int_50_75; - wire int_51_75; - wire int_52_75; - wire int_53_75; - wire int_0_76; - wire int_1_76; - wire int_2_76; - wire int_3_76; - wire int_4_76; - wire int_5_76; - wire int_6_76; - wire int_7_76; - wire int_8_76; - wire int_9_76; - wire int_10_76; - wire int_11_76; - wire int_12_76; - wire int_13_76; - wire int_14_76; - wire int_15_76; - wire int_16_76; - wire int_17_76; - wire int_18_76; - wire int_19_76; - wire int_20_76; - wire int_21_76; - wire int_22_76; - wire int_23_76; - wire int_24_76; - wire int_25_76; - wire int_26_76; - wire int_27_76; - wire int_28_76; - wire int_29_76; - wire int_30_76; - wire int_31_76; - wire int_32_76; - wire int_33_76; - wire int_34_76; - wire int_35_76; - wire int_36_76; - wire int_37_76; - wire int_38_76; - wire int_39_76; - wire int_40_76; - wire int_41_76; - wire int_42_76; - wire int_43_76; - wire int_44_76; - wire int_45_76; - wire int_46_76; - wire int_47_76; - wire int_48_76; - wire int_49_76; - wire int_50_76; - wire int_51_76; - wire int_52_76; - wire int_53_76; - wire int_0_77; - wire int_1_77; - wire int_2_77; - wire int_3_77; - wire int_4_77; - wire int_5_77; - wire int_6_77; - wire int_7_77; - wire int_8_77; - wire int_9_77; - wire int_10_77; - wire int_11_77; - wire int_12_77; - wire int_13_77; - wire int_14_77; - wire int_15_77; - wire int_16_77; - wire int_17_77; - wire int_18_77; - wire int_19_77; - wire int_20_77; - wire int_21_77; - wire int_22_77; - wire int_23_77; - wire int_24_77; - wire int_25_77; - wire int_26_77; - wire int_27_77; - wire int_28_77; - wire int_29_77; - wire int_30_77; - wire int_31_77; - wire int_32_77; - wire int_33_77; - wire int_34_77; - wire int_35_77; - wire int_36_77; - wire int_37_77; - wire int_38_77; - wire int_39_77; - wire int_40_77; - wire int_41_77; - wire int_42_77; - wire int_43_77; - wire int_44_77; - wire int_45_77; - wire int_46_77; - wire int_47_77; - wire int_48_77; - wire int_49_77; - wire int_50_77; - wire int_51_77; - wire int_0_78; - wire int_1_78; - wire int_2_78; - wire int_3_78; - wire int_4_78; - wire int_5_78; - wire int_6_78; - wire int_7_78; - wire int_8_78; - wire int_9_78; - wire int_10_78; - wire int_11_78; - wire int_12_78; - wire int_13_78; - wire int_14_78; - wire int_15_78; - wire int_16_78; - wire int_17_78; - wire int_18_78; - wire int_19_78; - wire int_20_78; - wire int_21_78; - wire int_22_78; - wire int_23_78; - wire int_24_78; - wire int_25_78; - wire int_26_78; - wire int_27_78; - wire int_28_78; - wire int_29_78; - wire int_30_78; - wire int_31_78; - wire int_32_78; - wire int_33_78; - wire int_34_78; - wire int_35_78; - wire int_36_78; - wire int_37_78; - wire int_38_78; - wire int_39_78; - wire int_40_78; - wire int_41_78; - wire int_42_78; - wire int_43_78; - wire int_44_78; - wire int_45_78; - wire int_46_78; - wire int_47_78; - wire int_48_78; - wire int_49_78; - wire int_50_78; - wire int_51_78; - wire int_0_79; - wire int_1_79; - wire int_2_79; - wire int_3_79; - wire int_4_79; - wire int_5_79; - wire int_6_79; - wire int_7_79; - wire int_8_79; - wire int_9_79; - wire int_10_79; - wire int_11_79; - wire int_12_79; - wire int_13_79; - wire int_14_79; - wire int_15_79; - wire int_16_79; - wire int_17_79; - wire int_18_79; - wire int_19_79; - wire int_20_79; - wire int_21_79; - wire int_22_79; - wire int_23_79; - wire int_24_79; - wire int_25_79; - wire int_26_79; - wire int_27_79; - wire int_28_79; - wire int_29_79; - wire int_30_79; - wire int_31_79; - wire int_32_79; - wire int_33_79; - wire int_34_79; - wire int_35_79; - wire int_36_79; - wire int_37_79; - wire int_38_79; - wire int_39_79; - wire int_40_79; - wire int_41_79; - wire int_42_79; - wire int_43_79; - wire int_44_79; - wire int_45_79; - wire int_46_79; - wire int_47_79; - wire int_48_79; - wire int_49_79; - wire int_0_80; - wire int_1_80; - wire int_2_80; - wire int_3_80; - wire int_4_80; - wire int_5_80; - wire int_6_80; - wire int_7_80; - wire int_8_80; - wire int_9_80; - wire int_10_80; - wire int_11_80; - wire int_12_80; - wire int_13_80; - wire int_14_80; - wire int_15_80; - wire int_16_80; - wire int_17_80; - wire int_18_80; - wire int_19_80; - wire int_20_80; - wire int_21_80; - wire int_22_80; - wire int_23_80; - wire int_24_80; - wire int_25_80; - wire int_26_80; - wire int_27_80; - wire int_28_80; - wire int_29_80; - wire int_30_80; - wire int_31_80; - wire int_32_80; - wire int_33_80; - wire int_34_80; - wire int_35_80; - wire int_36_80; - wire int_37_80; - wire int_38_80; - wire int_39_80; - wire int_40_80; - wire int_41_80; - wire int_42_80; - wire int_43_80; - wire int_44_80; - wire int_45_80; - wire int_46_80; - wire int_47_80; - wire int_48_80; - wire int_49_80; - wire int_0_81; - wire int_1_81; - wire int_2_81; - wire int_3_81; - wire int_4_81; - wire int_5_81; - wire int_6_81; - wire int_7_81; - wire int_8_81; - wire int_9_81; - wire int_10_81; - wire int_11_81; - wire int_12_81; - wire int_13_81; - wire int_14_81; - wire int_15_81; - wire int_16_81; - wire int_17_81; - wire int_18_81; - wire int_19_81; - wire int_20_81; - wire int_21_81; - wire int_22_81; - wire int_23_81; - wire int_24_81; - wire int_25_81; - wire int_26_81; - wire int_27_81; - wire int_28_81; - wire int_29_81; - wire int_30_81; - wire int_31_81; - wire int_32_81; - wire int_33_81; - wire int_34_81; - wire int_35_81; - wire int_36_81; - wire int_37_81; - wire int_38_81; - wire int_39_81; - wire int_40_81; - wire int_41_81; - wire int_42_81; - wire int_43_81; - wire int_44_81; - wire int_45_81; - wire int_46_81; - wire int_47_81; - wire int_0_82; - wire int_1_82; - wire int_2_82; - wire int_3_82; - wire int_4_82; - wire int_5_82; - wire int_6_82; - wire int_7_82; - wire int_8_82; - wire int_9_82; - wire int_10_82; - wire int_11_82; - wire int_12_82; - wire int_13_82; - wire int_14_82; - wire int_15_82; - wire int_16_82; - wire int_17_82; - wire int_18_82; - wire int_19_82; - wire int_20_82; - wire int_21_82; - wire int_22_82; - wire int_23_82; - wire int_24_82; - wire int_25_82; - wire int_26_82; - wire int_27_82; - wire int_28_82; - wire int_29_82; - wire int_30_82; - wire int_31_82; - wire int_32_82; - wire int_33_82; - wire int_34_82; - wire int_35_82; - wire int_36_82; - wire int_37_82; - wire int_38_82; - wire int_39_82; - wire int_40_82; - wire int_41_82; - wire int_42_82; - wire int_43_82; - wire int_44_82; - wire int_45_82; - wire int_46_82; - wire int_47_82; - wire int_0_83; - wire int_1_83; - wire int_2_83; - wire int_3_83; - wire int_4_83; - wire int_5_83; - wire int_6_83; - wire int_7_83; - wire int_8_83; - wire int_9_83; - wire int_10_83; - wire int_11_83; - wire int_12_83; - wire int_13_83; - wire int_14_83; - wire int_15_83; - wire int_16_83; - wire int_17_83; - wire int_18_83; - wire int_19_83; - wire int_20_83; - wire int_21_83; - wire int_22_83; - wire int_23_83; - wire int_24_83; - wire int_25_83; - wire int_26_83; - wire int_27_83; - wire int_28_83; - wire int_29_83; - wire int_30_83; - wire int_31_83; - wire int_32_83; - wire int_33_83; - wire int_34_83; - wire int_35_83; - wire int_36_83; - wire int_37_83; - wire int_38_83; - wire int_39_83; - wire int_40_83; - wire int_41_83; - wire int_42_83; - wire int_43_83; - wire int_44_83; - wire int_45_83; - wire int_0_84; - wire int_1_84; - wire int_2_84; - wire int_3_84; - wire int_4_84; - wire int_5_84; - wire int_6_84; - wire int_7_84; - wire int_8_84; - wire int_9_84; - wire int_10_84; - wire int_11_84; - wire int_12_84; - wire int_13_84; - wire int_14_84; - wire int_15_84; - wire int_16_84; - wire int_17_84; - wire int_18_84; - wire int_19_84; - wire int_20_84; - wire int_21_84; - wire int_22_84; - wire int_23_84; - wire int_24_84; - wire int_25_84; - wire int_26_84; - wire int_27_84; - wire int_28_84; - wire int_29_84; - wire int_30_84; - wire int_31_84; - wire int_32_84; - wire int_33_84; - wire int_34_84; - wire int_35_84; - wire int_36_84; - wire int_37_84; - wire int_38_84; - wire int_39_84; - wire int_40_84; - wire int_41_84; - wire int_42_84; - wire int_43_84; - wire int_44_84; - wire int_45_84; - wire int_0_85; - wire int_1_85; - wire int_2_85; - wire int_3_85; - wire int_4_85; - wire int_5_85; - wire int_6_85; - wire int_7_85; - wire int_8_85; - wire int_9_85; - wire int_10_85; - wire int_11_85; - wire int_12_85; - wire int_13_85; - wire int_14_85; - wire int_15_85; - wire int_16_85; - wire int_17_85; - wire int_18_85; - wire int_19_85; - wire int_20_85; - wire int_21_85; - wire int_22_85; - wire int_23_85; - wire int_24_85; - wire int_25_85; - wire int_26_85; - wire int_27_85; - wire int_28_85; - wire int_29_85; - wire int_30_85; - wire int_31_85; - wire int_32_85; - wire int_33_85; - wire int_34_85; - wire int_35_85; - wire int_36_85; - wire int_37_85; - wire int_38_85; - wire int_39_85; - wire int_40_85; - wire int_41_85; - wire int_42_85; - wire int_43_85; - wire int_0_86; - wire int_1_86; - wire int_2_86; - wire int_3_86; - wire int_4_86; - wire int_5_86; - wire int_6_86; - wire int_7_86; - wire int_8_86; - wire int_9_86; - wire int_10_86; - wire int_11_86; - wire int_12_86; - wire int_13_86; - wire int_14_86; - wire int_15_86; - wire int_16_86; - wire int_17_86; - wire int_18_86; - wire int_19_86; - wire int_20_86; - wire int_21_86; - wire int_22_86; - wire int_23_86; - wire int_24_86; - wire int_25_86; - wire int_26_86; - wire int_27_86; - wire int_28_86; - wire int_29_86; - wire int_30_86; - wire int_31_86; - wire int_32_86; - wire int_33_86; - wire int_34_86; - wire int_35_86; - wire int_36_86; - wire int_37_86; - wire int_38_86; - wire int_39_86; - wire int_40_86; - wire int_41_86; - wire int_42_86; - wire int_43_86; - wire int_0_87; - wire int_1_87; - wire int_2_87; - wire int_3_87; - wire int_4_87; - wire int_5_87; - wire int_6_87; - wire int_7_87; - wire int_8_87; - wire int_9_87; - wire int_10_87; - wire int_11_87; - wire int_12_87; - wire int_13_87; - wire int_14_87; - wire int_15_87; - wire int_16_87; - wire int_17_87; - wire int_18_87; - wire int_19_87; - wire int_20_87; - wire int_21_87; - wire int_22_87; - wire int_23_87; - wire int_24_87; - wire int_25_87; - wire int_26_87; - wire int_27_87; - wire int_28_87; - wire int_29_87; - wire int_30_87; - wire int_31_87; - wire int_32_87; - wire int_33_87; - wire int_34_87; - wire int_35_87; - wire int_36_87; - wire int_37_87; - wire int_38_87; - wire int_39_87; - wire int_40_87; - wire int_41_87; - wire int_0_88; - wire int_1_88; - wire int_2_88; - wire int_3_88; - wire int_4_88; - wire int_5_88; - wire int_6_88; - wire int_7_88; - wire int_8_88; - wire int_9_88; - wire int_10_88; - wire int_11_88; - wire int_12_88; - wire int_13_88; - wire int_14_88; - wire int_15_88; - wire int_16_88; - wire int_17_88; - wire int_18_88; - wire int_19_88; - wire int_20_88; - wire int_21_88; - wire int_22_88; - wire int_23_88; - wire int_24_88; - wire int_25_88; - wire int_26_88; - wire int_27_88; - wire int_28_88; - wire int_29_88; - wire int_30_88; - wire int_31_88; - wire int_32_88; - wire int_33_88; - wire int_34_88; - wire int_35_88; - wire int_36_88; - wire int_37_88; - wire int_38_88; - wire int_39_88; - wire int_40_88; - wire int_41_88; - wire int_0_89; - wire int_1_89; - wire int_2_89; - wire int_3_89; - wire int_4_89; - wire int_5_89; - wire int_6_89; - wire int_7_89; - wire int_8_89; - wire int_9_89; - wire int_10_89; - wire int_11_89; - wire int_12_89; - wire int_13_89; - wire int_14_89; - wire int_15_89; - wire int_16_89; - wire int_17_89; - wire int_18_89; - wire int_19_89; - wire int_20_89; - wire int_21_89; - wire int_22_89; - wire int_23_89; - wire int_24_89; - wire int_25_89; - wire int_26_89; - wire int_27_89; - wire int_28_89; - wire int_29_89; - wire int_30_89; - wire int_31_89; - wire int_32_89; - wire int_33_89; - wire int_34_89; - wire int_35_89; - wire int_36_89; - wire int_37_89; - wire int_38_89; - wire int_39_89; - wire int_0_90; - wire int_1_90; - wire int_2_90; - wire int_3_90; - wire int_4_90; - wire int_5_90; - wire int_6_90; - wire int_7_90; - wire int_8_90; - wire int_9_90; - wire int_10_90; - wire int_11_90; - wire int_12_90; - wire int_13_90; - wire int_14_90; - wire int_15_90; - wire int_16_90; - wire int_17_90; - wire int_18_90; - wire int_19_90; - wire int_20_90; - wire int_21_90; - wire int_22_90; - wire int_23_90; - wire int_24_90; - wire int_25_90; - wire int_26_90; - wire int_27_90; - wire int_28_90; - wire int_29_90; - wire int_30_90; - wire int_31_90; - wire int_32_90; - wire int_33_90; - wire int_34_90; - wire int_35_90; - wire int_36_90; - wire int_37_90; - wire int_38_90; - wire int_39_90; - wire int_0_91; - wire int_1_91; - wire int_2_91; - wire int_3_91; - wire int_4_91; - wire int_5_91; - wire int_6_91; - wire int_7_91; - wire int_8_91; - wire int_9_91; - wire int_10_91; - wire int_11_91; - wire int_12_91; - wire int_13_91; - wire int_14_91; - wire int_15_91; - wire int_16_91; - wire int_17_91; - wire int_18_91; - wire int_19_91; - wire int_20_91; - wire int_21_91; - wire int_22_91; - wire int_23_91; - wire int_24_91; - wire int_25_91; - wire int_26_91; - wire int_27_91; - wire int_28_91; - wire int_29_91; - wire int_30_91; - wire int_31_91; - wire int_32_91; - wire int_33_91; - wire int_34_91; - wire int_35_91; - wire int_36_91; - wire int_37_91; - wire int_0_92; - wire int_1_92; - wire int_2_92; - wire int_3_92; - wire int_4_92; - wire int_5_92; - wire int_6_92; - wire int_7_92; - wire int_8_92; - wire int_9_92; - wire int_10_92; - wire int_11_92; - wire int_12_92; - wire int_13_92; - wire int_14_92; - wire int_15_92; - wire int_16_92; - wire int_17_92; - wire int_18_92; - wire int_19_92; - wire int_20_92; - wire int_21_92; - wire int_22_92; - wire int_23_92; - wire int_24_92; - wire int_25_92; - wire int_26_92; - wire int_27_92; - wire int_28_92; - wire int_29_92; - wire int_30_92; - wire int_31_92; - wire int_32_92; - wire int_33_92; - wire int_34_92; - wire int_35_92; - wire int_36_92; - wire int_37_92; - wire int_0_93; - wire int_1_93; - wire int_2_93; - wire int_3_93; - wire int_4_93; - wire int_5_93; - wire int_6_93; - wire int_7_93; - wire int_8_93; - wire int_9_93; - wire int_10_93; - wire int_11_93; - wire int_12_93; - wire int_13_93; - wire int_14_93; - wire int_15_93; - wire int_16_93; - wire int_17_93; - wire int_18_93; - wire int_19_93; - wire int_20_93; - wire int_21_93; - wire int_22_93; - wire int_23_93; - wire int_24_93; - wire int_25_93; - wire int_26_93; - wire int_27_93; - wire int_28_93; - wire int_29_93; - wire int_30_93; - wire int_31_93; - wire int_32_93; - wire int_33_93; - wire int_34_93; - wire int_35_93; - wire int_0_94; - wire int_1_94; - wire int_2_94; - wire int_3_94; - wire int_4_94; - wire int_5_94; - wire int_6_94; - wire int_7_94; - wire int_8_94; - wire int_9_94; - wire int_10_94; - wire int_11_94; - wire int_12_94; - wire int_13_94; - wire int_14_94; - wire int_15_94; - wire int_16_94; - wire int_17_94; - wire int_18_94; - wire int_19_94; - wire int_20_94; - wire int_21_94; - wire int_22_94; - wire int_23_94; - wire int_24_94; - wire int_25_94; - wire int_26_94; - wire int_27_94; - wire int_28_94; - wire int_29_94; - wire int_30_94; - wire int_31_94; - wire int_32_94; - wire int_33_94; - wire int_34_94; - wire int_35_94; - wire int_0_95; - wire int_1_95; - wire int_2_95; - wire int_3_95; - wire int_4_95; - wire int_5_95; - wire int_6_95; - wire int_7_95; - wire int_8_95; - wire int_9_95; - wire int_10_95; - wire int_11_95; - wire int_12_95; - wire int_13_95; - wire int_14_95; - wire int_15_95; - wire int_16_95; - wire int_17_95; - wire int_18_95; - wire int_19_95; - wire int_20_95; - wire int_21_95; - wire int_22_95; - wire int_23_95; - wire int_24_95; - wire int_25_95; - wire int_26_95; - wire int_27_95; - wire int_28_95; - wire int_29_95; - wire int_30_95; - wire int_31_95; - wire int_32_95; - wire int_33_95; - wire int_0_96; - wire int_1_96; - wire int_2_96; - wire int_3_96; - wire int_4_96; - wire int_5_96; - wire int_6_96; - wire int_7_96; - wire int_8_96; - wire int_9_96; - wire int_10_96; - wire int_11_96; - wire int_12_96; - wire int_13_96; - wire int_14_96; - wire int_15_96; - wire int_16_96; - wire int_17_96; - wire int_18_96; - wire int_19_96; - wire int_20_96; - wire int_21_96; - wire int_22_96; - wire int_23_96; - wire int_24_96; - wire int_25_96; - wire int_26_96; - wire int_27_96; - wire int_28_96; - wire int_29_96; - wire int_30_96; - wire int_31_96; - wire int_32_96; - wire int_33_96; - wire int_0_97; - wire int_1_97; - wire int_2_97; - wire int_3_97; - wire int_4_97; - wire int_5_97; - wire int_6_97; - wire int_7_97; - wire int_8_97; - wire int_9_97; - wire int_10_97; - wire int_11_97; - wire int_12_97; - wire int_13_97; - wire int_14_97; - wire int_15_97; - wire int_16_97; - wire int_17_97; - wire int_18_97; - wire int_19_97; - wire int_20_97; - wire int_21_97; - wire int_22_97; - wire int_23_97; - wire int_24_97; - wire int_25_97; - wire int_26_97; - wire int_27_97; - wire int_28_97; - wire int_29_97; - wire int_30_97; - wire int_31_97; - wire int_0_98; - wire int_1_98; - wire int_2_98; - wire int_3_98; - wire int_4_98; - wire int_5_98; - wire int_6_98; - wire int_7_98; - wire int_8_98; - wire int_9_98; - wire int_10_98; - wire int_11_98; - wire int_12_98; - wire int_13_98; - wire int_14_98; - wire int_15_98; - wire int_16_98; - wire int_17_98; - wire int_18_98; - wire int_19_98; - wire int_20_98; - wire int_21_98; - wire int_22_98; - wire int_23_98; - wire int_24_98; - wire int_25_98; - wire int_26_98; - wire int_27_98; - wire int_28_98; - wire int_29_98; - wire int_30_98; - wire int_31_98; - wire int_0_99; - wire int_1_99; - wire int_2_99; - wire int_3_99; - wire int_4_99; - wire int_5_99; - wire int_6_99; - wire int_7_99; - wire int_8_99; - wire int_9_99; - wire int_10_99; - wire int_11_99; - wire int_12_99; - wire int_13_99; - wire int_14_99; - wire int_15_99; - wire int_16_99; - wire int_17_99; - wire int_18_99; - wire int_19_99; - wire int_20_99; - wire int_21_99; - wire int_22_99; - wire int_23_99; - wire int_24_99; - wire int_25_99; - wire int_26_99; - wire int_27_99; - wire int_28_99; - wire int_29_99; - wire int_0_100; - wire int_1_100; - wire int_2_100; - wire int_3_100; - wire int_4_100; - wire int_5_100; - wire int_6_100; - wire int_7_100; - wire int_8_100; - wire int_9_100; - wire int_10_100; - wire int_11_100; - wire int_12_100; - wire int_13_100; - wire int_14_100; - wire int_15_100; - wire int_16_100; - wire int_17_100; - wire int_18_100; - wire int_19_100; - wire int_20_100; - wire int_21_100; - wire int_22_100; - wire int_23_100; - wire int_24_100; - wire int_25_100; - wire int_26_100; - wire int_27_100; - wire int_28_100; - wire int_29_100; - wire int_0_101; - wire int_1_101; - wire int_2_101; - wire int_3_101; - wire int_4_101; - wire int_5_101; - wire int_6_101; - wire int_7_101; - wire int_8_101; - wire int_9_101; - wire int_10_101; - wire int_11_101; - wire int_12_101; - wire int_13_101; - wire int_14_101; - wire int_15_101; - wire int_16_101; - wire int_17_101; - wire int_18_101; - wire int_19_101; - wire int_20_101; - wire int_21_101; - wire int_22_101; - wire int_23_101; - wire int_24_101; - wire int_25_101; - wire int_26_101; - wire int_27_101; - wire int_0_102; - wire int_1_102; - wire int_2_102; - wire int_3_102; - wire int_4_102; - wire int_5_102; - wire int_6_102; - wire int_7_102; - wire int_8_102; - wire int_9_102; - wire int_10_102; - wire int_11_102; - wire int_12_102; - wire int_13_102; - wire int_14_102; - wire int_15_102; - wire int_16_102; - wire int_17_102; - wire int_18_102; - wire int_19_102; - wire int_20_102; - wire int_21_102; - wire int_22_102; - wire int_23_102; - wire int_24_102; - wire int_25_102; - wire int_26_102; - wire int_27_102; - wire int_0_103; - wire int_1_103; - wire int_2_103; - wire int_3_103; - wire int_4_103; - wire int_5_103; - wire int_6_103; - wire int_7_103; - wire int_8_103; - wire int_9_103; - wire int_10_103; - wire int_11_103; - wire int_12_103; - wire int_13_103; - wire int_14_103; - wire int_15_103; - wire int_16_103; - wire int_17_103; - wire int_18_103; - wire int_19_103; - wire int_20_103; - wire int_21_103; - wire int_22_103; - wire int_23_103; - wire int_24_103; - wire int_25_103; - wire int_0_104; - wire int_1_104; - wire int_2_104; - wire int_3_104; - wire int_4_104; - wire int_5_104; - wire int_6_104; - wire int_7_104; - wire int_8_104; - wire int_9_104; - wire int_10_104; - wire int_11_104; - wire int_12_104; - wire int_13_104; - wire int_14_104; - wire int_15_104; - wire int_16_104; - wire int_17_104; - wire int_18_104; - wire int_19_104; - wire int_20_104; - wire int_21_104; - wire int_22_104; - wire int_23_104; - wire int_24_104; - wire int_25_104; - wire int_0_105; - wire int_1_105; - wire int_2_105; - wire int_3_105; - wire int_4_105; - wire int_5_105; - wire int_6_105; - wire int_7_105; - wire int_8_105; - wire int_9_105; - wire int_10_105; - wire int_11_105; - wire int_12_105; - wire int_13_105; - wire int_14_105; - wire int_15_105; - wire int_16_105; - wire int_17_105; - wire int_18_105; - wire int_19_105; - wire int_20_105; - wire int_21_105; - wire int_22_105; - wire int_23_105; - wire int_0_106; - wire int_1_106; - wire int_2_106; - wire int_3_106; - wire int_4_106; - wire int_5_106; - wire int_6_106; - wire int_7_106; - wire int_8_106; - wire int_9_106; - wire int_10_106; - wire int_11_106; - wire int_12_106; - wire int_13_106; - wire int_14_106; - wire int_15_106; - wire int_16_106; - wire int_17_106; - wire int_18_106; - wire int_19_106; - wire int_20_106; - wire int_21_106; - wire int_22_106; - wire int_23_106; - wire int_0_107; - wire int_1_107; - wire int_2_107; - wire int_3_107; - wire int_4_107; - wire int_5_107; - wire int_6_107; - wire int_7_107; - wire int_8_107; - wire int_9_107; - wire int_10_107; - wire int_11_107; - wire int_12_107; - wire int_13_107; - wire int_14_107; - wire int_15_107; - wire int_16_107; - wire int_17_107; - wire int_18_107; - wire int_19_107; - wire int_20_107; - wire int_21_107; - wire int_0_108; - wire int_1_108; - wire int_2_108; - wire int_3_108; - wire int_4_108; - wire int_5_108; - wire int_6_108; - wire int_7_108; - wire int_8_108; - wire int_9_108; - wire int_10_108; - wire int_11_108; - wire int_12_108; - wire int_13_108; - wire int_14_108; - wire int_15_108; - wire int_16_108; - wire int_17_108; - wire int_18_108; - wire int_19_108; - wire int_20_108; - wire int_21_108; - wire int_0_109; - wire int_1_109; - wire int_2_109; - wire int_3_109; - wire int_4_109; - wire int_5_109; - wire int_6_109; - wire int_7_109; - wire int_8_109; - wire int_9_109; - wire int_10_109; - wire int_11_109; - wire int_12_109; - wire int_13_109; - wire int_14_109; - wire int_15_109; - wire int_16_109; - wire int_17_109; - wire int_18_109; - wire int_19_109; - wire int_0_110; - wire int_1_110; - wire int_2_110; - wire int_3_110; - wire int_4_110; - wire int_5_110; - wire int_6_110; - wire int_7_110; - wire int_8_110; - wire int_9_110; - wire int_10_110; - wire int_11_110; - wire int_12_110; - wire int_13_110; - wire int_14_110; - wire int_15_110; - wire int_16_110; - wire int_17_110; - wire int_18_110; - wire int_19_110; - wire int_0_111; - wire int_1_111; - wire int_2_111; - wire int_3_111; - wire int_4_111; - wire int_5_111; - wire int_6_111; - wire int_7_111; - wire int_8_111; - wire int_9_111; - wire int_10_111; - wire int_11_111; - wire int_12_111; - wire int_13_111; - wire int_14_111; - wire int_15_111; - wire int_16_111; - wire int_17_111; - wire int_0_112; - wire int_1_112; - wire int_2_112; - wire int_3_112; - wire int_4_112; - wire int_5_112; - wire int_6_112; - wire int_7_112; - wire int_8_112; - wire int_9_112; - wire int_10_112; - wire int_11_112; - wire int_12_112; - wire int_13_112; - wire int_14_112; - wire int_15_112; - wire int_16_112; - wire int_17_112; - wire int_0_113; - wire int_1_113; - wire int_2_113; - wire int_3_113; - wire int_4_113; - wire int_5_113; - wire int_6_113; - wire int_7_113; - wire int_8_113; - wire int_9_113; - wire int_10_113; - wire int_11_113; - wire int_12_113; - wire int_13_113; - wire int_14_113; - wire int_15_113; - wire int_0_114; - wire int_1_114; - wire int_2_114; - wire int_3_114; - wire int_4_114; - wire int_5_114; - wire int_6_114; - wire int_7_114; - wire int_8_114; - wire int_9_114; - wire int_10_114; - wire int_11_114; - wire int_12_114; - wire int_13_114; - wire int_14_114; - wire int_15_114; - wire int_0_115; - wire int_1_115; - wire int_2_115; - wire int_3_115; - wire int_4_115; - wire int_5_115; - wire int_6_115; - wire int_7_115; - wire int_8_115; - wire int_9_115; - wire int_10_115; - wire int_11_115; - wire int_12_115; - wire int_13_115; - wire int_0_116; - wire int_1_116; - wire int_2_116; - wire int_3_116; - wire int_4_116; - wire int_5_116; - wire int_6_116; - wire int_7_116; - wire int_8_116; - wire int_9_116; - wire int_10_116; - wire int_11_116; - wire int_12_116; - wire int_13_116; - wire int_0_117; - wire int_1_117; - wire int_2_117; - wire int_3_117; - wire int_4_117; - wire int_5_117; - wire int_6_117; - wire int_7_117; - wire int_8_117; - wire int_9_117; - wire int_10_117; - wire int_11_117; - wire int_0_118; - wire int_1_118; - wire int_2_118; - wire int_3_118; - wire int_4_118; - wire int_5_118; - wire int_6_118; - wire int_7_118; - wire int_8_118; - wire int_9_118; - wire int_10_118; - wire int_11_118; - wire int_0_119; - wire int_1_119; - wire int_2_119; - wire int_3_119; - wire int_4_119; - wire int_5_119; - wire int_6_119; - wire int_7_119; - wire int_8_119; - wire int_9_119; - wire int_0_120; - wire int_1_120; - wire int_2_120; - wire int_3_120; - wire int_4_120; - wire int_5_120; - wire int_6_120; - wire int_7_120; - wire int_8_120; - wire int_9_120; - wire int_0_121; - wire int_1_121; - wire int_2_121; - wire int_3_121; - wire int_4_121; - wire int_5_121; - wire int_6_121; - wire int_7_121; - wire int_0_122; - wire int_1_122; - wire int_2_122; - wire int_3_122; - wire int_4_122; - wire int_5_122; - wire int_6_122; - wire int_7_122; - wire int_0_123; - wire int_1_123; - wire int_2_123; - wire int_3_123; - wire int_4_123; - wire int_5_123; - wire int_0_124; - wire int_1_124; - wire int_2_124; - wire int_3_124; - wire int_4_124; - wire int_5_124; - wire int_0_125; - wire int_1_125; - wire int_2_125; - wire int_3_125; - wire int_0_126; - wire int_1_126; - wire int_2_126; - wire int_3_126; - wire int_0_127; - wire int_1_127; - - // Below are the intermediate nets for the final adders - wire final_0; - wire final_1; - wire final_2; - wire final_3; - wire final_4; - wire final_5; - wire final_6; - wire final_7; - wire final_8; - wire final_9; - wire final_10; - wire final_11; - wire final_12; - wire final_13; - wire final_14; - wire final_15; - wire final_16; - wire final_17; - wire final_18; - wire final_19; - wire final_20; - wire final_21; - wire final_22; - wire final_23; - wire final_24; - wire final_25; - wire final_26; - wire final_27; - wire final_28; - wire final_29; - wire final_30; - wire final_31; - wire final_32; - wire final_33; - wire final_34; - wire final_35; - wire final_36; - wire final_37; - wire final_38; - wire final_39; - wire final_40; - wire final_41; - wire final_42; - wire final_43; - wire final_44; - wire final_45; - wire final_46; - wire final_47; - wire final_48; - wire final_49; - wire final_50; - wire final_51; - wire final_52; - wire final_53; - wire final_54; - wire final_55; - wire final_56; - wire final_57; - wire final_58; - wire final_59; - wire final_60; - wire final_61; - wire final_62; - wire final_63; - wire final_64; - wire final_65; - wire final_66; - wire final_67; - wire final_68; - wire final_69; - wire final_70; - wire final_71; - wire final_72; - wire final_73; - wire final_74; - wire final_75; - wire final_76; - wire final_77; - wire final_78; - wire final_79; - wire final_80; - wire final_81; - wire final_82; - wire final_83; - wire final_84; - wire final_85; - wire final_86; - wire final_87; - wire final_88; - wire final_89; - wire final_90; - wire final_91; - wire final_92; - wire final_93; - wire final_94; - wire final_95; - wire final_96; - wire final_97; - wire final_98; - wire final_99; - wire final_100; - wire final_101; - wire final_102; - wire final_103; - wire final_104; - wire final_105; - wire final_106; - wire final_107; - wire final_108; - wire final_109; - wire final_110; - wire final_111; - wire final_112; - wire final_113; - wire final_114; - wire final_115; - wire final_116; - wire final_117; - wire final_118; - wire final_119; - wire final_120; - wire final_121; - wire final_122; - wire final_123; - wire final_124; - wire final_125; - wire final_126; - - // Below are the gates for the TDM trees. - - // Hardware for column 0 - - r4bs r4bs_0_64(gnd, yy[0], single[0], double[0], neg[0], pp_0_0); - assign Sum[0] = neg[0]; - assign Carry[0] = pp_0_0; - - // Hardware for column 1 - - r4bs r4bs_80_64(yy[0], yy[1], single[0], double[0], neg[0], pp_0_1); - assign Sum[1] = pp_0_1; - assign Carry[1] = gnd; - - // Hardware for column 2 - - r4bs r4bs_160_64(yy[1], yy[2], single[0], double[0], neg[0], pp_0_2); - halfAdd HA_160_192(int_1_2, int_0_2, neg[1], pp_0_2); - r4bs r4bs_160_272(gnd, yy[0], single[1], double[1], neg[1], pp_1_2); - assign Sum[2] = pp_1_2; - assign Carry[2] = int_0_2; - - // Hardware for column 3 - - r4bs r4bs_240_64(yy[2], yy[3], single[0], double[0], neg[0], pp_0_3); - r4bs r4bs_240_192(yy[0], yy[1], single[1], double[1], neg[1], pp_1_3); - halfAdd HA_240_320(int_1_3, int_0_3, pp_0_3, pp_1_3); - assign Sum[3] = int_1_2; - assign Carry[3] = int_0_3; - - // Hardware for column 4 - - r4bs r4bs_320_64(yy[3], yy[4], single[0], double[0], neg[0], pp_0_4); - halfAdd HA_320_192(int_1_4, int_0_4, neg[2], pp_0_4); - r4bs r4bs_320_272(yy[1], yy[2], single[1], double[1], neg[1], pp_1_4); - r4bs r4bs_320_400(gnd, yy[0], single[2], double[2], neg[2], pp_2_4); - fullAdd_x FA_320_528(int_3_4, int_2_4, pp_1_4, pp_2_4, int_1_3); - assign Sum[4] = int_0_4; - assign Carry[4] = int_2_4; - - // Hardware for column 5 - - r4bs r4bs_400_64(yy[4], yy[5], single[0], double[0], neg[0], pp_0_5); - r4bs r4bs_400_192(yy[2], yy[3], single[1], double[1], neg[1], pp_1_5); - halfAdd HA_400_320(int_1_5, int_0_5, pp_0_5, pp_1_5); - r4bs r4bs_400_400(yy[0], yy[1], single[2], double[2], neg[2], pp_2_5); - fullAdd_x FA_400_528(int_3_5, int_2_5, pp_2_5, int_1_4, int_0_5); - assign Sum[5] = int_3_4; - assign Carry[5] = int_2_5; - - // Hardware for column 6 - - r4bs r4bs_480_64(yy[5], yy[6], single[0], double[0], neg[0], pp_0_6); - halfAdd HA_480_192(int_1_6, int_0_6, neg[3], pp_0_6); - r4bs r4bs_480_272(yy[3], yy[4], single[1], double[1], neg[1], pp_1_6); - r4bs r4bs_480_400(yy[1], yy[2], single[2], double[2], neg[2], pp_2_6); - r4bs r4bs_480_528(gnd, yy[0], single[3], double[3], neg[3], pp_3_6); - fullAdd_x FA_480_656(int_3_6, int_2_6, pp_1_6, pp_2_6, pp_3_6); - fullAdd_x FA_480_872(int_5_6, int_4_6, int_1_5, int_0_6, int_3_5); - assign Sum[6] = int_2_6; - assign Carry[6] = int_4_6; - - // Hardware for column 7 - - r4bs r4bs_560_64(yy[6], yy[7], single[0], double[0], neg[0], pp_0_7); - r4bs r4bs_560_192(yy[4], yy[5], single[1], double[1], neg[1], pp_1_7); - halfAdd HA_560_320(int_1_7, int_0_7, pp_0_7, pp_1_7); - r4bs r4bs_560_400(yy[2], yy[3], single[2], double[2], neg[2], pp_2_7); - r4bs r4bs_560_528(yy[0], yy[1], single[3], double[3], neg[3], pp_3_7); - fullAdd_x FA_560_656(int_3_7, int_2_7, pp_2_7, pp_3_7, int_1_6); - fullAdd_x FA_560_872(int_5_7, int_4_7, int_3_6, int_0_7, int_2_7); - assign Sum[7] = int_5_6; - assign Carry[7] = int_4_7; - - // Hardware for column 8 - - r4bs r4bs_640_64(yy[7], yy[8], single[0], double[0], neg[0], pp_0_8); - halfAdd HA_640_192(int_1_8, int_0_8, neg[4], pp_0_8); - r4bs r4bs_640_272(yy[5], yy[6], single[1], double[1], neg[1], pp_1_8); - r4bs r4bs_640_400(yy[3], yy[4], single[2], double[2], neg[2], pp_2_8); - r4bs r4bs_640_528(yy[1], yy[2], single[3], double[3], neg[3], pp_3_8); - fullAdd_x FA_640_656(int_3_8, int_2_8, pp_1_8, pp_2_8, pp_3_8); - r4bs r4bs_640_872(gnd, yy[0], single[4], double[4], neg[4], pp_4_8); - fullAdd_x FA_640_1000(int_5_8, int_4_8, pp_4_8, int_1_7, int_0_8); - fullAdd_x FA_640_1216(int_7_8, int_6_8, int_3_7, int_2_8, int_4_8); - assign Sum[8] = int_5_7; - assign Carry[8] = int_6_8; - - // Hardware for column 9 - - r4bs r4bs_720_64(yy[8], yy[9], single[0], double[0], neg[0], pp_0_9); - r4bs r4bs_720_192(yy[6], yy[7], single[1], double[1], neg[1], pp_1_9); - halfAdd HA_720_320(int_1_9, int_0_9, pp_0_9, pp_1_9); - r4bs r4bs_720_400(yy[4], yy[5], single[2], double[2], neg[2], pp_2_9); - r4bs r4bs_720_528(yy[2], yy[3], single[3], double[3], neg[3], pp_3_9); - r4bs r4bs_720_656(yy[0], yy[1], single[4], double[4], neg[4], pp_4_9); - fullAdd_x FA_720_784(int_3_9, int_2_9, pp_2_9, pp_3_9, pp_4_9); - fullAdd_x FA_720_1000(int_5_9, int_4_9, int_1_8, int_3_8, int_0_9); - fullAdd_x FA_720_1216(int_7_9, int_6_9, int_5_8, int_2_9, int_4_9); - assign Sum[9] = int_7_8; - assign Carry[9] = int_6_9; - - // Hardware for column 10 - - r4bs r4bs_800_64(yy[9], yy[10], single[0], double[0], neg[0], pp_0_10); - halfAdd HA_800_192(int_1_10, int_0_10, neg[5], pp_0_10); - r4bs r4bs_800_272(yy[7], yy[8], single[1], double[1], neg[1], pp_1_10); - r4bs r4bs_800_400(yy[5], yy[6], single[2], double[2], neg[2], pp_2_10); - r4bs r4bs_800_528(yy[3], yy[4], single[3], double[3], neg[3], pp_3_10); - fullAdd_x FA_800_656(int_3_10, int_2_10, pp_1_10, pp_2_10, pp_3_10); - r4bs r4bs_800_872(yy[1], yy[2], single[4], double[4], neg[4], pp_4_10); - r4bs r4bs_800_1000(gnd, yy[0], single[5], double[5], neg[5], pp_5_10); - fullAdd_x FA_800_1128(int_5_10, int_4_10, pp_4_10, pp_5_10, int_1_9); - fullAdd_x FA_800_1344(int_7_10, int_6_10, int_3_9, int_0_10, int_5_9); - fullAdd_x FA_800_1560(int_9_10, int_8_10, int_2_10, int_4_10, int_6_10); - assign Sum[10] = int_7_9; - assign Carry[10] = int_8_10; - - // Hardware for column 11 - - r4bs r4bs_880_64(yy[10], yy[11], single[0], double[0], neg[0], pp_0_11); - r4bs r4bs_880_192(yy[8], yy[9], single[1], double[1], neg[1], pp_1_11); - halfAdd HA_880_320(int_1_11, int_0_11, pp_0_11, pp_1_11); - r4bs r4bs_880_400(yy[6], yy[7], single[2], double[2], neg[2], pp_2_11); - r4bs r4bs_880_528(yy[4], yy[5], single[3], double[3], neg[3], pp_3_11); - r4bs r4bs_880_656(yy[2], yy[3], single[4], double[4], neg[4], pp_4_11); - fullAdd_x FA_880_784(int_3_11, int_2_11, pp_2_11, pp_3_11, pp_4_11); - r4bs r4bs_880_1000(yy[0], yy[1], single[5], double[5], neg[5], pp_5_11); - fullAdd_x FA_880_1128(int_5_11, int_4_11, pp_5_11, int_1_10, int_3_10); - fullAdd_x FA_880_1344(int_7_11, int_6_11, int_0_11, int_5_10, int_2_11); - fullAdd_x FA_880_1560(int_9_11, int_8_11, int_4_11, int_7_10, int_6_11); - assign Sum[11] = int_9_10; - assign Carry[11] = int_8_11; - - // Hardware for column 12 - - r4bs r4bs_960_64(yy[11], yy[12], single[0], double[0], neg[0], pp_0_12); - halfAdd HA_960_192(int_1_12, int_0_12, neg[6], pp_0_12); - r4bs r4bs_960_272(yy[9], yy[10], single[1], double[1], neg[1], pp_1_12); - r4bs r4bs_960_400(yy[7], yy[8], single[2], double[2], neg[2], pp_2_12); - r4bs r4bs_960_528(yy[5], yy[6], single[3], double[3], neg[3], pp_3_12); - fullAdd_x FA_960_656(int_3_12, int_2_12, pp_1_12, pp_2_12, pp_3_12); - r4bs r4bs_960_872(yy[3], yy[4], single[4], double[4], neg[4], pp_4_12); - r4bs r4bs_960_1000(yy[1], yy[2], single[5], double[5], neg[5], pp_5_12); - r4bs r4bs_960_1128(gnd, yy[0], single[6], double[6], neg[6], pp_6_12); - fullAdd_x FA_960_1256(int_5_12, int_4_12, pp_4_12, pp_5_12, pp_6_12); - fullAdd_x FA_960_1472(int_7_12, int_6_12, int_1_11, int_3_11, int_0_12); - fullAdd_x FA_960_1688(int_9_12, int_8_12, int_5_11, int_2_12, int_4_12); - fullAdd_x FA_960_1904(int_11_12, int_10_12, int_7_11, int_6_12, int_8_12); - assign Sum[12] = int_9_11; - assign Carry[12] = int_10_12; - - // Hardware for column 13 - - r4bs r4bs_1040_64(yy[12], yy[13], single[0], double[0], neg[0], pp_0_13); - r4bs r4bs_1040_192(yy[10], yy[11], single[1], double[1], neg[1], pp_1_13); - halfAdd HA_1040_320(int_1_13, int_0_13, pp_0_13, pp_1_13); - r4bs r4bs_1040_400(yy[8], yy[9], single[2], double[2], neg[2], pp_2_13); - r4bs r4bs_1040_528(yy[6], yy[7], single[3], double[3], neg[3], pp_3_13); - r4bs r4bs_1040_656(yy[4], yy[5], single[4], double[4], neg[4], pp_4_13); - fullAdd_x FA_1040_784(int_3_13, int_2_13, pp_2_13, pp_3_13, pp_4_13); - r4bs r4bs_1040_1000(yy[2], yy[3], single[5], double[5], neg[5], pp_5_13); - r4bs r4bs_1040_1128(yy[0], yy[1], single[6], double[6], neg[6], pp_6_13); - fullAdd_x FA_1040_1256(int_5_13, int_4_13, pp_5_13, pp_6_13, int_1_12); - fullAdd_x FA_1040_1472(int_7_13, int_6_13, int_3_12, int_5_12, int_0_13); - fullAdd_x FA_1040_1688(int_9_13, int_8_13, int_7_12, int_2_13, int_4_13); - fullAdd_x FA_1040_1904(int_11_13, int_10_13, int_9_12, int_6_13, int_8_13); - assign Sum[13] = int_11_12; - assign Carry[13] = int_10_13; - - // Hardware for column 14 - - r4bs r4bs_1120_64(yy[13], yy[14], single[0], double[0], neg[0], pp_0_14); - halfAdd HA_1120_192(int_1_14, int_0_14, neg[7], pp_0_14); - r4bs r4bs_1120_272(yy[11], yy[12], single[1], double[1], neg[1], pp_1_14); - r4bs r4bs_1120_400(yy[9], yy[10], single[2], double[2], neg[2], pp_2_14); - r4bs r4bs_1120_528(yy[7], yy[8], single[3], double[3], neg[3], pp_3_14); - fullAdd_x FA_1120_656(int_3_14, int_2_14, pp_1_14, pp_2_14, pp_3_14); - r4bs r4bs_1120_872(yy[5], yy[6], single[4], double[4], neg[4], pp_4_14); - r4bs r4bs_1120_1000(yy[3], yy[4], single[5], double[5], neg[5], pp_5_14); - r4bs r4bs_1120_1128(yy[1], yy[2], single[6], double[6], neg[6], pp_6_14); - fullAdd_x FA_1120_1256(int_5_14, int_4_14, pp_4_14, pp_5_14, pp_6_14); - r4bs r4bs_1120_1472(gnd, yy[0], single[7], double[7], neg[7], pp_7_14); - fullAdd_x FA_1120_1600(int_7_14, int_6_14, pp_7_14, int_1_13, int_3_13); - fullAdd_x FA_1120_1816(int_9_14, int_8_14, int_0_14, int_5_13, int_7_13); - fullAdd_x FA_1120_2032(int_11_14, int_10_14, int_2_14, int_4_14, int_6_14); - fullAdd_x FA_1120_2248(int_13_14, int_12_14, int_9_13, int_8_14, int_10_14); - assign Sum[14] = int_11_13; - assign Carry[14] = int_12_14; - - // Hardware for column 15 - - r4bs r4bs_1200_64(yy[14], yy[15], single[0], double[0], neg[0], pp_0_15); - r4bs r4bs_1200_192(yy[12], yy[13], single[1], double[1], neg[1], pp_1_15); - halfAdd HA_1200_320(int_1_15, int_0_15, pp_0_15, pp_1_15); - r4bs r4bs_1200_400(yy[10], yy[11], single[2], double[2], neg[2], pp_2_15); - r4bs r4bs_1200_528(yy[8], yy[9], single[3], double[3], neg[3], pp_3_15); - r4bs r4bs_1200_656(yy[6], yy[7], single[4], double[4], neg[4], pp_4_15); - fullAdd_x FA_1200_784(int_3_15, int_2_15, pp_2_15, pp_3_15, pp_4_15); - r4bs r4bs_1200_1000(yy[4], yy[5], single[5], double[5], neg[5], pp_5_15); - r4bs r4bs_1200_1128(yy[2], yy[3], single[6], double[6], neg[6], pp_6_15); - r4bs r4bs_1200_1256(yy[0], yy[1], single[7], double[7], neg[7], pp_7_15); - fullAdd_x FA_1200_1384(int_5_15, int_4_15, pp_5_15, pp_6_15, pp_7_15); - fullAdd_x FA_1200_1600(int_7_15, int_6_15, int_1_14, int_3_14, int_5_14); - fullAdd_x FA_1200_1816(int_9_15, int_8_15, int_0_15, int_7_14, int_2_15); - fullAdd_x FA_1200_2032(int_11_15, int_10_15, int_4_15, int_9_14, int_6_15); - fullAdd_x FA_1200_2248(int_13_15, int_12_15, int_11_14, int_8_15, int_13_14); - assign Sum[15] = int_10_15; - assign Carry[15] = int_12_15; - - // Hardware for column 16 - - r4bs r4bs_1280_64(yy[15], yy[16], single[0], double[0], neg[0], pp_0_16); - halfAdd HA_1280_192(int_1_16, int_0_16, neg[8], pp_0_16); - r4bs r4bs_1280_272(yy[13], yy[14], single[1], double[1], neg[1], pp_1_16); - r4bs r4bs_1280_400(yy[11], yy[12], single[2], double[2], neg[2], pp_2_16); - r4bs r4bs_1280_528(yy[9], yy[10], single[3], double[3], neg[3], pp_3_16); - fullAdd_x FA_1280_656(int_3_16, int_2_16, pp_1_16, pp_2_16, pp_3_16); - r4bs r4bs_1280_872(yy[7], yy[8], single[4], double[4], neg[4], pp_4_16); - r4bs r4bs_1280_1000(yy[5], yy[6], single[5], double[5], neg[5], pp_5_16); - r4bs r4bs_1280_1128(yy[3], yy[4], single[6], double[6], neg[6], pp_6_16); - fullAdd_x FA_1280_1256(int_5_16, int_4_16, pp_4_16, pp_5_16, pp_6_16); - r4bs r4bs_1280_1472(yy[1], yy[2], single[7], double[7], neg[7], pp_7_16); - r4bs r4bs_1280_1600(gnd, yy[0], single[8], double[8], neg[8], pp_8_16); - fullAdd_x FA_1280_1728(int_7_16, int_6_16, pp_7_16, pp_8_16, int_1_15); - fullAdd_x FA_1280_1944(int_9_16, int_8_16, int_3_15, int_5_15, int_0_16); - fullAdd_x FA_1280_2160(int_11_16, int_10_16, int_7_15, int_2_16, int_4_16); - fullAdd_x FA_1280_2376(int_13_16, int_12_16, int_6_16, int_9_15, int_8_16); - fullAdd_x FA_1280_2592(int_15_16, int_14_16, int_11_15, int_10_16, int_12_16); - assign Sum[16] = int_13_15; - assign Carry[16] = int_14_16; - - // Hardware for column 17 - - r4bs r4bs_1360_64(yy[16], yy[17], single[0], double[0], neg[0], pp_0_17); - r4bs r4bs_1360_192(yy[14], yy[15], single[1], double[1], neg[1], pp_1_17); - halfAdd HA_1360_320(int_1_17, int_0_17, pp_0_17, pp_1_17); - r4bs r4bs_1360_400(yy[12], yy[13], single[2], double[2], neg[2], pp_2_17); - r4bs r4bs_1360_528(yy[10], yy[11], single[3], double[3], neg[3], pp_3_17); - r4bs r4bs_1360_656(yy[8], yy[9], single[4], double[4], neg[4], pp_4_17); - fullAdd_x FA_1360_784(int_3_17, int_2_17, pp_2_17, pp_3_17, pp_4_17); - r4bs r4bs_1360_1000(yy[6], yy[7], single[5], double[5], neg[5], pp_5_17); - r4bs r4bs_1360_1128(yy[4], yy[5], single[6], double[6], neg[6], pp_6_17); - r4bs r4bs_1360_1256(yy[2], yy[3], single[7], double[7], neg[7], pp_7_17); - fullAdd_x FA_1360_1384(int_5_17, int_4_17, pp_5_17, pp_6_17, pp_7_17); - r4bs r4bs_1360_1600(yy[0], yy[1], single[8], double[8], neg[8], pp_8_17); - fullAdd_x FA_1360_1728(int_7_17, int_6_17, pp_8_17, int_1_16, int_3_16); - fullAdd_x FA_1360_1944(int_9_17, int_8_17, int_5_16, int_0_17, int_7_16); - fullAdd_x FA_1360_2160(int_11_17, int_10_17, int_9_16, int_2_17, int_4_17); - fullAdd_x FA_1360_2376(int_13_17, int_12_17, int_6_17, int_11_16, int_8_17); - fullAdd_x FA_1360_2592(int_15_17, int_14_17, int_13_16, int_10_17, int_12_17); - assign Sum[17] = int_15_16; - assign Carry[17] = int_14_17; - - // Hardware for column 18 - - r4bs r4bs_1440_64(yy[17], yy[18], single[0], double[0], neg[0], pp_0_18); - halfAdd HA_1440_192(int_1_18, int_0_18, neg[9], pp_0_18); - r4bs r4bs_1440_272(yy[15], yy[16], single[1], double[1], neg[1], pp_1_18); - r4bs r4bs_1440_400(yy[13], yy[14], single[2], double[2], neg[2], pp_2_18); - r4bs r4bs_1440_528(yy[11], yy[12], single[3], double[3], neg[3], pp_3_18); - fullAdd_x FA_1440_656(int_3_18, int_2_18, pp_1_18, pp_2_18, pp_3_18); - r4bs r4bs_1440_872(yy[9], yy[10], single[4], double[4], neg[4], pp_4_18); - r4bs r4bs_1440_1000(yy[7], yy[8], single[5], double[5], neg[5], pp_5_18); - r4bs r4bs_1440_1128(yy[5], yy[6], single[6], double[6], neg[6], pp_6_18); - fullAdd_x FA_1440_1256(int_5_18, int_4_18, pp_4_18, pp_5_18, pp_6_18); - r4bs r4bs_1440_1472(yy[3], yy[4], single[7], double[7], neg[7], pp_7_18); - r4bs r4bs_1440_1600(yy[1], yy[2], single[8], double[8], neg[8], pp_8_18); - r4bs r4bs_1440_1728(gnd, yy[0], single[9], double[9], neg[9], pp_9_18); - fullAdd_x FA_1440_1856(int_7_18, int_6_18, pp_7_18, pp_8_18, pp_9_18); - fullAdd_x FA_1440_2072(int_9_18, int_8_18, int_1_17, int_3_17, int_5_17); - fullAdd_x FA_1440_2288(int_11_18, int_10_18, int_0_18, int_7_17, int_2_18); - fullAdd_x FA_1440_2504(int_13_18, int_12_18, int_4_18, int_6_18, int_9_17); - fullAdd_x FA_1440_2720(int_15_18, int_14_18, int_11_17, int_8_18, int_13_17); - fullAdd_x FA_1440_2936(int_17_18, int_16_18, int_10_18, int_12_18, int_14_18); - assign Sum[18] = int_15_17; - assign Carry[18] = int_16_18; - - // Hardware for column 19 - - r4bs r4bs_1520_64(yy[18], yy[19], single[0], double[0], neg[0], pp_0_19); - r4bs r4bs_1520_192(yy[16], yy[17], single[1], double[1], neg[1], pp_1_19); - halfAdd HA_1520_320(int_1_19, int_0_19, pp_0_19, pp_1_19); - r4bs r4bs_1520_400(yy[14], yy[15], single[2], double[2], neg[2], pp_2_19); - r4bs r4bs_1520_528(yy[12], yy[13], single[3], double[3], neg[3], pp_3_19); - r4bs r4bs_1520_656(yy[10], yy[11], single[4], double[4], neg[4], pp_4_19); - fullAdd_x FA_1520_784(int_3_19, int_2_19, pp_2_19, pp_3_19, pp_4_19); - r4bs r4bs_1520_1000(yy[8], yy[9], single[5], double[5], neg[5], pp_5_19); - r4bs r4bs_1520_1128(yy[6], yy[7], single[6], double[6], neg[6], pp_6_19); - r4bs r4bs_1520_1256(yy[4], yy[5], single[7], double[7], neg[7], pp_7_19); - fullAdd_x FA_1520_1384(int_5_19, int_4_19, pp_5_19, pp_6_19, pp_7_19); - r4bs r4bs_1520_1600(yy[2], yy[3], single[8], double[8], neg[8], pp_8_19); - r4bs r4bs_1520_1728(yy[0], yy[1], single[9], double[9], neg[9], pp_9_19); - fullAdd_x FA_1520_1856(int_7_19, int_6_19, pp_8_19, pp_9_19, int_1_18); - fullAdd_x FA_1520_2072(int_9_19, int_8_19, int_3_18, int_5_18, int_7_18); - fullAdd_x FA_1520_2288(int_11_19, int_10_19, int_0_19, int_9_18, int_2_19); - fullAdd_x FA_1520_2504(int_13_19, int_12_19, int_4_19, int_6_19, int_11_18); - fullAdd_x FA_1520_2720(int_15_19, int_14_19, int_8_19, int_13_18, int_10_19); - fullAdd_x FA_1520_2936(int_17_19, int_16_19, int_12_19, int_15_18, int_14_19); - assign Sum[19] = int_17_18; - assign Carry[19] = int_16_19; - - // Hardware for column 20 - - r4bs r4bs_1600_64(yy[19], yy[20], single[0], double[0], neg[0], pp_0_20); - halfAdd HA_1600_192(int_1_20, int_0_20, neg[10], pp_0_20); - r4bs r4bs_1600_272(yy[17], yy[18], single[1], double[1], neg[1], pp_1_20); - r4bs r4bs_1600_400(yy[15], yy[16], single[2], double[2], neg[2], pp_2_20); - r4bs r4bs_1600_528(yy[13], yy[14], single[3], double[3], neg[3], pp_3_20); - fullAdd_x FA_1600_656(int_3_20, int_2_20, pp_1_20, pp_2_20, pp_3_20); - r4bs r4bs_1600_872(yy[11], yy[12], single[4], double[4], neg[4], pp_4_20); - r4bs r4bs_1600_1000(yy[9], yy[10], single[5], double[5], neg[5], pp_5_20); - r4bs r4bs_1600_1128(yy[7], yy[8], single[6], double[6], neg[6], pp_6_20); - fullAdd_x FA_1600_1256(int_5_20, int_4_20, pp_4_20, pp_5_20, pp_6_20); - r4bs r4bs_1600_1472(yy[5], yy[6], single[7], double[7], neg[7], pp_7_20); - r4bs r4bs_1600_1600(yy[3], yy[4], single[8], double[8], neg[8], pp_8_20); - r4bs r4bs_1600_1728(yy[1], yy[2], single[9], double[9], neg[9], pp_9_20); - fullAdd_x FA_1600_1856(int_7_20, int_6_20, pp_7_20, pp_8_20, pp_9_20); - r4bs r4bs_1600_2072(gnd, yy[0], single[10], double[10], neg[10], pp_10_20); - fullAdd_x FA_1600_2200(int_9_20, int_8_20, pp_10_20, int_1_19, int_3_19); - fullAdd_x FA_1600_2416(int_11_20, int_10_20, int_5_19, int_0_20, int_7_19); - fullAdd_x FA_1600_2632(int_13_20, int_12_20, int_9_19, int_2_20, int_4_20); - fullAdd_x FA_1600_2848(int_15_20, int_14_20, int_6_20, int_8_20, int_11_19); - fullAdd_x FA_1600_3064(int_17_20, int_16_20, int_10_20, int_13_19, int_12_20); - fullAdd_x FA_1600_3280(int_19_20, int_18_20, int_14_20, int_15_19, int_16_20); - assign Sum[20] = int_17_19; - assign Carry[20] = int_18_20; - - // Hardware for column 21 - - r4bs r4bs_1680_64(yy[20], yy[21], single[0], double[0], neg[0], pp_0_21); - r4bs r4bs_1680_192(yy[18], yy[19], single[1], double[1], neg[1], pp_1_21); - halfAdd HA_1680_320(int_1_21, int_0_21, pp_0_21, pp_1_21); - r4bs r4bs_1680_400(yy[16], yy[17], single[2], double[2], neg[2], pp_2_21); - r4bs r4bs_1680_528(yy[14], yy[15], single[3], double[3], neg[3], pp_3_21); - r4bs r4bs_1680_656(yy[12], yy[13], single[4], double[4], neg[4], pp_4_21); - fullAdd_x FA_1680_784(int_3_21, int_2_21, pp_2_21, pp_3_21, pp_4_21); - r4bs r4bs_1680_1000(yy[10], yy[11], single[5], double[5], neg[5], pp_5_21); - r4bs r4bs_1680_1128(yy[8], yy[9], single[6], double[6], neg[6], pp_6_21); - r4bs r4bs_1680_1256(yy[6], yy[7], single[7], double[7], neg[7], pp_7_21); - fullAdd_x FA_1680_1384(int_5_21, int_4_21, pp_5_21, pp_6_21, pp_7_21); - r4bs r4bs_1680_1600(yy[4], yy[5], single[8], double[8], neg[8], pp_8_21); - r4bs r4bs_1680_1728(yy[2], yy[3], single[9], double[9], neg[9], pp_9_21); - r4bs r4bs_1680_1856(yy[0], yy[1], single[10], double[10], neg[10], pp_10_21); - fullAdd_x FA_1680_1984(int_7_21, int_6_21, pp_8_21, pp_9_21, pp_10_21); - fullAdd_x FA_1680_2200(int_9_21, int_8_21, int_1_20, int_3_20, int_5_20); - fullAdd_x FA_1680_2416(int_11_21, int_10_21, int_7_20, int_0_21, int_9_20); - fullAdd_x FA_1680_2632(int_13_21, int_12_21, int_2_21, int_4_21, int_6_21); - fullAdd_x FA_1680_2848(int_15_21, int_14_21, int_11_20, int_13_20, int_8_21); - fullAdd_x FA_1680_3064(int_17_21, int_16_21, int_10_21, int_15_20, int_12_21); - fullAdd_x FA_1680_3280(int_19_21, int_18_21, int_17_20, int_14_21, int_16_21); - assign Sum[21] = int_19_20; - assign Carry[21] = int_18_21; - - // Hardware for column 22 - - r4bs r4bs_1760_64(yy[21], yy[22], single[0], double[0], neg[0], pp_0_22); - halfAdd HA_1760_192(int_1_22, int_0_22, neg[11], pp_0_22); - r4bs r4bs_1760_272(yy[19], yy[20], single[1], double[1], neg[1], pp_1_22); - r4bs r4bs_1760_400(yy[17], yy[18], single[2], double[2], neg[2], pp_2_22); - r4bs r4bs_1760_528(yy[15], yy[16], single[3], double[3], neg[3], pp_3_22); - fullAdd_x FA_1760_656(int_3_22, int_2_22, pp_1_22, pp_2_22, pp_3_22); - r4bs r4bs_1760_872(yy[13], yy[14], single[4], double[4], neg[4], pp_4_22); - r4bs r4bs_1760_1000(yy[11], yy[12], single[5], double[5], neg[5], pp_5_22); - r4bs r4bs_1760_1128(yy[9], yy[10], single[6], double[6], neg[6], pp_6_22); - fullAdd_x FA_1760_1256(int_5_22, int_4_22, pp_4_22, pp_5_22, pp_6_22); - r4bs r4bs_1760_1472(yy[7], yy[8], single[7], double[7], neg[7], pp_7_22); - r4bs r4bs_1760_1600(yy[5], yy[6], single[8], double[8], neg[8], pp_8_22); - r4bs r4bs_1760_1728(yy[3], yy[4], single[9], double[9], neg[9], pp_9_22); - fullAdd_x FA_1760_1856(int_7_22, int_6_22, pp_7_22, pp_8_22, pp_9_22); - r4bs r4bs_1760_2072(yy[1], yy[2], single[10], double[10], neg[10], pp_10_22); - r4bs r4bs_1760_2200(gnd, yy[0], single[11], double[11], neg[11], pp_11_22); - fullAdd_x FA_1760_2328(int_9_22, int_8_22, pp_10_22, pp_11_22, int_1_21); - fullAdd_x FA_1760_2544(int_11_22, int_10_22, int_3_21, int_5_21, int_7_21); - fullAdd_x FA_1760_2760(int_13_22, int_12_22, int_0_22, int_9_21, int_2_22); - fullAdd_x FA_1760_2976(int_15_22, int_14_22, int_4_22, int_6_22, int_8_22); - fullAdd_x FA_1760_3192(int_17_22, int_16_22, int_11_21, int_13_21, int_10_22); - fullAdd_x FA_1760_3408(int_19_22, int_18_22, int_15_21, int_12_22, int_14_22); - fullAdd_x FA_1760_3624(int_21_22, int_20_22, int_17_21, int_16_22, int_18_22); - assign Sum[22] = int_19_21; - assign Carry[22] = int_20_22; - - // Hardware for column 23 - - r4bs r4bs_1840_64(yy[22], yy[23], single[0], double[0], neg[0], pp_0_23); - r4bs r4bs_1840_192(yy[20], yy[21], single[1], double[1], neg[1], pp_1_23); - halfAdd HA_1840_320(int_1_23, int_0_23, pp_0_23, pp_1_23); - r4bs r4bs_1840_400(yy[18], yy[19], single[2], double[2], neg[2], pp_2_23); - r4bs r4bs_1840_528(yy[16], yy[17], single[3], double[3], neg[3], pp_3_23); - r4bs r4bs_1840_656(yy[14], yy[15], single[4], double[4], neg[4], pp_4_23); - fullAdd_x FA_1840_784(int_3_23, int_2_23, pp_2_23, pp_3_23, pp_4_23); - r4bs r4bs_1840_1000(yy[12], yy[13], single[5], double[5], neg[5], pp_5_23); - r4bs r4bs_1840_1128(yy[10], yy[11], single[6], double[6], neg[6], pp_6_23); - r4bs r4bs_1840_1256(yy[8], yy[9], single[7], double[7], neg[7], pp_7_23); - fullAdd_x FA_1840_1384(int_5_23, int_4_23, pp_5_23, pp_6_23, pp_7_23); - r4bs r4bs_1840_1600(yy[6], yy[7], single[8], double[8], neg[8], pp_8_23); - r4bs r4bs_1840_1728(yy[4], yy[5], single[9], double[9], neg[9], pp_9_23); - r4bs r4bs_1840_1856(yy[2], yy[3], single[10], double[10], neg[10], pp_10_23); - fullAdd_x FA_1840_1984(int_7_23, int_6_23, pp_8_23, pp_9_23, pp_10_23); - r4bs r4bs_1840_2200(yy[0], yy[1], single[11], double[11], neg[11], pp_11_23); - fullAdd_x FA_1840_2328(int_9_23, int_8_23, pp_11_23, int_1_22, int_3_22); - fullAdd_x FA_1840_2544(int_11_23, int_10_23, int_5_22, int_7_22, int_0_23); - fullAdd_x FA_1840_2760(int_13_23, int_12_23, int_9_22, int_11_22, int_2_23); - fullAdd_x FA_1840_2976(int_15_23, int_14_23, int_4_23, int_6_23, int_8_23); - fullAdd_x FA_1840_3192(int_17_23, int_16_23, int_13_22, int_15_22, int_10_23); - fullAdd_x FA_1840_3408(int_19_23, int_18_23, int_17_22, int_12_23, int_14_23); - fullAdd_x FA_1840_3624(int_21_23, int_20_23, int_19_22, int_16_23, int_18_23); - assign Sum[23] = int_21_22; - assign Carry[23] = int_20_23; - - // Hardware for column 24 - - r4bs r4bs_1920_64(yy[23], yy[24], single[0], double[0], neg[0], pp_0_24); - halfAdd HA_1920_192(int_1_24, int_0_24, neg[12], pp_0_24); - r4bs r4bs_1920_272(yy[21], yy[22], single[1], double[1], neg[1], pp_1_24); - r4bs r4bs_1920_400(yy[19], yy[20], single[2], double[2], neg[2], pp_2_24); - r4bs r4bs_1920_528(yy[17], yy[18], single[3], double[3], neg[3], pp_3_24); - fullAdd_x FA_1920_656(int_3_24, int_2_24, pp_1_24, pp_2_24, pp_3_24); - r4bs r4bs_1920_872(yy[15], yy[16], single[4], double[4], neg[4], pp_4_24); - r4bs r4bs_1920_1000(yy[13], yy[14], single[5], double[5], neg[5], pp_5_24); - r4bs r4bs_1920_1128(yy[11], yy[12], single[6], double[6], neg[6], pp_6_24); - fullAdd_x FA_1920_1256(int_5_24, int_4_24, pp_4_24, pp_5_24, pp_6_24); - r4bs r4bs_1920_1472(yy[9], yy[10], single[7], double[7], neg[7], pp_7_24); - r4bs r4bs_1920_1600(yy[7], yy[8], single[8], double[8], neg[8], pp_8_24); - r4bs r4bs_1920_1728(yy[5], yy[6], single[9], double[9], neg[9], pp_9_24); - fullAdd_x FA_1920_1856(int_7_24, int_6_24, pp_7_24, pp_8_24, pp_9_24); - r4bs r4bs_1920_2072(yy[3], yy[4], single[10], double[10], neg[10], pp_10_24); - r4bs r4bs_1920_2200(yy[1], yy[2], single[11], double[11], neg[11], pp_11_24); - r4bs r4bs_1920_2328(gnd, yy[0], single[12], double[12], neg[12], pp_12_24); - fullAdd_x FA_1920_2456(int_9_24, int_8_24, pp_10_24, pp_11_24, pp_12_24); - fullAdd_x FA_1920_2672(int_11_24, int_10_24, int_1_23, int_3_23, int_5_23); - fullAdd_x FA_1920_2888(int_13_24, int_12_24, int_7_23, int_0_24, int_9_23); - fullAdd_x FA_1920_3104(int_15_24, int_14_24, int_11_23, int_2_24, int_4_24); - fullAdd_x FA_1920_3320(int_17_24, int_16_24, int_6_24, int_8_24, int_13_23); - fullAdd_x FA_1920_3536(int_19_24, int_18_24, int_10_24, int_12_24, int_15_23); - fullAdd_x FA_1920_3752(int_21_24, int_20_24, int_17_23, int_14_24, int_16_24); - fullAdd_x FA_1920_3968(int_23_24, int_22_24, int_19_23, int_18_24, int_20_24); - assign Sum[24] = int_21_23; - assign Carry[24] = int_22_24; - - // Hardware for column 25 - - r4bs r4bs_2000_64(yy[24], yy[25], single[0], double[0], neg[0], pp_0_25); - r4bs r4bs_2000_192(yy[22], yy[23], single[1], double[1], neg[1], pp_1_25); - halfAdd HA_2000_320(int_1_25, int_0_25, pp_0_25, pp_1_25); - r4bs r4bs_2000_400(yy[20], yy[21], single[2], double[2], neg[2], pp_2_25); - r4bs r4bs_2000_528(yy[18], yy[19], single[3], double[3], neg[3], pp_3_25); - r4bs r4bs_2000_656(yy[16], yy[17], single[4], double[4], neg[4], pp_4_25); - fullAdd_x FA_2000_784(int_3_25, int_2_25, pp_2_25, pp_3_25, pp_4_25); - r4bs r4bs_2000_1000(yy[14], yy[15], single[5], double[5], neg[5], pp_5_25); - r4bs r4bs_2000_1128(yy[12], yy[13], single[6], double[6], neg[6], pp_6_25); - r4bs r4bs_2000_1256(yy[10], yy[11], single[7], double[7], neg[7], pp_7_25); - fullAdd_x FA_2000_1384(int_5_25, int_4_25, pp_5_25, pp_6_25, pp_7_25); - r4bs r4bs_2000_1600(yy[8], yy[9], single[8], double[8], neg[8], pp_8_25); - r4bs r4bs_2000_1728(yy[6], yy[7], single[9], double[9], neg[9], pp_9_25); - r4bs r4bs_2000_1856(yy[4], yy[5], single[10], double[10], neg[10], pp_10_25); - fullAdd_x FA_2000_1984(int_7_25, int_6_25, pp_8_25, pp_9_25, pp_10_25); - r4bs r4bs_2000_2200(yy[2], yy[3], single[11], double[11], neg[11], pp_11_25); - r4bs r4bs_2000_2328(yy[0], yy[1], single[12], double[12], neg[12], pp_12_25); - fullAdd_x FA_2000_2456(int_9_25, int_8_25, pp_11_25, pp_12_25, int_1_24); - fullAdd_x FA_2000_2672(int_11_25, int_10_25, int_3_24, int_5_24, int_7_24); - fullAdd_x FA_2000_2888(int_13_25, int_12_25, int_9_24, int_0_25, int_11_24); - fullAdd_x FA_2000_3104(int_15_25, int_14_25, int_2_25, int_4_25, int_6_25); - fullAdd_x FA_2000_3320(int_17_25, int_16_25, int_8_25, int_13_24, int_15_24); - fullAdd_x FA_2000_3536(int_19_25, int_18_25, int_10_25, int_12_25, int_17_24); - fullAdd_x FA_2000_3752(int_21_25, int_20_25, int_14_25, int_19_24, int_21_24); - fullAdd_x FA_2000_3968(int_23_25, int_22_25, int_16_25, int_18_25, int_20_25); - assign Sum[25] = int_23_24; - assign Carry[25] = int_22_25; - - // Hardware for column 26 - - r4bs r4bs_2080_64(yy[25], yy[26], single[0], double[0], neg[0], pp_0_26); - halfAdd HA_2080_192(int_1_26, int_0_26, neg[13], pp_0_26); - r4bs r4bs_2080_272(yy[23], yy[24], single[1], double[1], neg[1], pp_1_26); - r4bs r4bs_2080_400(yy[21], yy[22], single[2], double[2], neg[2], pp_2_26); - r4bs r4bs_2080_528(yy[19], yy[20], single[3], double[3], neg[3], pp_3_26); - fullAdd_x FA_2080_656(int_3_26, int_2_26, pp_1_26, pp_2_26, pp_3_26); - r4bs r4bs_2080_872(yy[17], yy[18], single[4], double[4], neg[4], pp_4_26); - r4bs r4bs_2080_1000(yy[15], yy[16], single[5], double[5], neg[5], pp_5_26); - r4bs r4bs_2080_1128(yy[13], yy[14], single[6], double[6], neg[6], pp_6_26); - fullAdd_x FA_2080_1256(int_5_26, int_4_26, pp_4_26, pp_5_26, pp_6_26); - r4bs r4bs_2080_1472(yy[11], yy[12], single[7], double[7], neg[7], pp_7_26); - r4bs r4bs_2080_1600(yy[9], yy[10], single[8], double[8], neg[8], pp_8_26); - r4bs r4bs_2080_1728(yy[7], yy[8], single[9], double[9], neg[9], pp_9_26); - fullAdd_x FA_2080_1856(int_7_26, int_6_26, pp_7_26, pp_8_26, pp_9_26); - r4bs r4bs_2080_2072(yy[5], yy[6], single[10], double[10], neg[10], pp_10_26); - r4bs r4bs_2080_2200(yy[3], yy[4], single[11], double[11], neg[11], pp_11_26); - r4bs r4bs_2080_2328(yy[1], yy[2], single[12], double[12], neg[12], pp_12_26); - fullAdd_x FA_2080_2456(int_9_26, int_8_26, pp_10_26, pp_11_26, pp_12_26); - r4bs r4bs_2080_2672(gnd, yy[0], single[13], double[13], neg[13], pp_13_26); - fullAdd_x FA_2080_2800(int_11_26, int_10_26, pp_13_26, int_1_25, int_3_25); - fullAdd_x FA_2080_3016(int_13_26, int_12_26, int_5_25, int_7_25, int_0_26); - fullAdd_x FA_2080_3232(int_15_26, int_14_26, int_9_25, int_11_25, int_2_26); - fullAdd_x FA_2080_3448(int_17_26, int_16_26, int_4_26, int_6_26, int_8_26); - fullAdd_x FA_2080_3664(int_19_26, int_18_26, int_10_26, int_13_25, int_15_25); - fullAdd_x FA_2080_3880(int_21_26, int_20_26, int_12_26, int_17_25, int_14_26); - fullAdd_x FA_2080_4096(int_23_26, int_22_26, int_16_26, int_19_25, int_18_26); - fullAdd_x FA_2080_4312(int_25_26, int_24_26, int_21_25, int_20_26, int_22_26); - assign Sum[26] = int_23_25; - assign Carry[26] = int_24_26; - - // Hardware for column 27 - - r4bs r4bs_2160_64(yy[26], yy[27], single[0], double[0], neg[0], pp_0_27); - r4bs r4bs_2160_192(yy[24], yy[25], single[1], double[1], neg[1], pp_1_27); - halfAdd HA_2160_320(int_1_27, int_0_27, pp_0_27, pp_1_27); - r4bs r4bs_2160_400(yy[22], yy[23], single[2], double[2], neg[2], pp_2_27); - r4bs r4bs_2160_528(yy[20], yy[21], single[3], double[3], neg[3], pp_3_27); - r4bs r4bs_2160_656(yy[18], yy[19], single[4], double[4], neg[4], pp_4_27); - fullAdd_x FA_2160_784(int_3_27, int_2_27, pp_2_27, pp_3_27, pp_4_27); - r4bs r4bs_2160_1000(yy[16], yy[17], single[5], double[5], neg[5], pp_5_27); - r4bs r4bs_2160_1128(yy[14], yy[15], single[6], double[6], neg[6], pp_6_27); - r4bs r4bs_2160_1256(yy[12], yy[13], single[7], double[7], neg[7], pp_7_27); - fullAdd_x FA_2160_1384(int_5_27, int_4_27, pp_5_27, pp_6_27, pp_7_27); - r4bs r4bs_2160_1600(yy[10], yy[11], single[8], double[8], neg[8], pp_8_27); - r4bs r4bs_2160_1728(yy[8], yy[9], single[9], double[9], neg[9], pp_9_27); - r4bs r4bs_2160_1856(yy[6], yy[7], single[10], double[10], neg[10], pp_10_27); - fullAdd_x FA_2160_1984(int_7_27, int_6_27, pp_8_27, pp_9_27, pp_10_27); - r4bs r4bs_2160_2200(yy[4], yy[5], single[11], double[11], neg[11], pp_11_27); - r4bs r4bs_2160_2328(yy[2], yy[3], single[12], double[12], neg[12], pp_12_27); - r4bs r4bs_2160_2456(yy[0], yy[1], single[13], double[13], neg[13], pp_13_27); - fullAdd_x FA_2160_2584(int_9_27, int_8_27, pp_11_27, pp_12_27, pp_13_27); - fullAdd_x FA_2160_2800(int_11_27, int_10_27, int_1_26, int_3_26, int_5_26); - fullAdd_x FA_2160_3016(int_13_27, int_12_27, int_7_26, int_9_26, int_0_27); - fullAdd_x FA_2160_3232(int_15_27, int_14_27, int_11_26, int_13_26, int_2_27); - fullAdd_x FA_2160_3448(int_17_27, int_16_27, int_4_27, int_6_27, int_8_27); - fullAdd_x FA_2160_3664(int_19_27, int_18_27, int_15_26, int_17_26, int_10_27); - fullAdd_x FA_2160_3880(int_21_27, int_20_27, int_12_27, int_19_26, int_14_27); - fullAdd_x FA_2160_4096(int_23_27, int_22_27, int_16_27, int_21_26, int_18_27); - fullAdd_x FA_2160_4312(int_25_27, int_24_27, int_23_26, int_20_27, int_22_27); - assign Sum[27] = int_25_26; - assign Carry[27] = int_24_27; - - // Hardware for column 28 - - r4bs r4bs_2240_64(yy[27], yy[28], single[0], double[0], neg[0], pp_0_28); - halfAdd HA_2240_192(int_1_28, int_0_28, neg[14], pp_0_28); - r4bs r4bs_2240_272(yy[25], yy[26], single[1], double[1], neg[1], pp_1_28); - r4bs r4bs_2240_400(yy[23], yy[24], single[2], double[2], neg[2], pp_2_28); - r4bs r4bs_2240_528(yy[21], yy[22], single[3], double[3], neg[3], pp_3_28); - fullAdd_x FA_2240_656(int_3_28, int_2_28, pp_1_28, pp_2_28, pp_3_28); - r4bs r4bs_2240_872(yy[19], yy[20], single[4], double[4], neg[4], pp_4_28); - r4bs r4bs_2240_1000(yy[17], yy[18], single[5], double[5], neg[5], pp_5_28); - r4bs r4bs_2240_1128(yy[15], yy[16], single[6], double[6], neg[6], pp_6_28); - fullAdd_x FA_2240_1256(int_5_28, int_4_28, pp_4_28, pp_5_28, pp_6_28); - r4bs r4bs_2240_1472(yy[13], yy[14], single[7], double[7], neg[7], pp_7_28); - r4bs r4bs_2240_1600(yy[11], yy[12], single[8], double[8], neg[8], pp_8_28); - r4bs r4bs_2240_1728(yy[9], yy[10], single[9], double[9], neg[9], pp_9_28); - fullAdd_x FA_2240_1856(int_7_28, int_6_28, pp_7_28, pp_8_28, pp_9_28); - r4bs r4bs_2240_2072(yy[7], yy[8], single[10], double[10], neg[10], pp_10_28); - r4bs r4bs_2240_2200(yy[5], yy[6], single[11], double[11], neg[11], pp_11_28); - r4bs r4bs_2240_2328(yy[3], yy[4], single[12], double[12], neg[12], pp_12_28); - fullAdd_x FA_2240_2456(int_9_28, int_8_28, pp_10_28, pp_11_28, pp_12_28); - r4bs r4bs_2240_2672(yy[1], yy[2], single[13], double[13], neg[13], pp_13_28); - r4bs r4bs_2240_2800(gnd, yy[0], single[14], double[14], neg[14], pp_14_28); - fullAdd_x FA_2240_2928(int_11_28, int_10_28, pp_13_28, pp_14_28, int_1_27); - fullAdd_x FA_2240_3144(int_13_28, int_12_28, int_3_27, int_5_27, int_7_27); - fullAdd_x FA_2240_3360(int_15_28, int_14_28, int_9_27, int_0_28, int_11_27); - fullAdd_x FA_2240_3576(int_17_28, int_16_28, int_13_27, int_2_28, int_4_28); - fullAdd_x FA_2240_3792(int_19_28, int_18_28, int_6_28, int_8_28, int_10_28); - fullAdd_x FA_2240_4008(int_21_28, int_20_28, int_15_27, int_17_27, int_12_28); - fullAdd_x FA_2240_4224(int_23_28, int_22_28, int_14_28, int_19_27, int_16_28); - fullAdd_x FA_2240_4440(int_25_28, int_24_28, int_18_28, int_21_27, int_20_28); - fullAdd_x FA_2240_4656(int_27_28, int_26_28, int_23_27, int_22_28, int_24_28); - assign Sum[28] = int_25_27; - assign Carry[28] = int_26_28; - - // Hardware for column 29 - - r4bs r4bs_2320_64(yy[28], yy[29], single[0], double[0], neg[0], pp_0_29); - r4bs r4bs_2320_192(yy[26], yy[27], single[1], double[1], neg[1], pp_1_29); - halfAdd HA_2320_320(int_1_29, int_0_29, pp_0_29, pp_1_29); - r4bs r4bs_2320_400(yy[24], yy[25], single[2], double[2], neg[2], pp_2_29); - r4bs r4bs_2320_528(yy[22], yy[23], single[3], double[3], neg[3], pp_3_29); - r4bs r4bs_2320_656(yy[20], yy[21], single[4], double[4], neg[4], pp_4_29); - fullAdd_x FA_2320_784(int_3_29, int_2_29, pp_2_29, pp_3_29, pp_4_29); - r4bs r4bs_2320_1000(yy[18], yy[19], single[5], double[5], neg[5], pp_5_29); - r4bs r4bs_2320_1128(yy[16], yy[17], single[6], double[6], neg[6], pp_6_29); - r4bs r4bs_2320_1256(yy[14], yy[15], single[7], double[7], neg[7], pp_7_29); - fullAdd_x FA_2320_1384(int_5_29, int_4_29, pp_5_29, pp_6_29, pp_7_29); - r4bs r4bs_2320_1600(yy[12], yy[13], single[8], double[8], neg[8], pp_8_29); - r4bs r4bs_2320_1728(yy[10], yy[11], single[9], double[9], neg[9], pp_9_29); - r4bs r4bs_2320_1856(yy[8], yy[9], single[10], double[10], neg[10], pp_10_29); - fullAdd_x FA_2320_1984(int_7_29, int_6_29, pp_8_29, pp_9_29, pp_10_29); - r4bs r4bs_2320_2200(yy[6], yy[7], single[11], double[11], neg[11], pp_11_29); - r4bs r4bs_2320_2328(yy[4], yy[5], single[12], double[12], neg[12], pp_12_29); - r4bs r4bs_2320_2456(yy[2], yy[3], single[13], double[13], neg[13], pp_13_29); - fullAdd_x FA_2320_2584(int_9_29, int_8_29, pp_11_29, pp_12_29, pp_13_29); - r4bs r4bs_2320_2800(yy[0], yy[1], single[14], double[14], neg[14], pp_14_29); - fullAdd_x FA_2320_2928(int_11_29, int_10_29, pp_14_29, int_1_28, int_3_28); - fullAdd_x FA_2320_3144(int_13_29, int_12_29, int_5_28, int_7_28, int_9_28); - fullAdd_x FA_2320_3360(int_15_29, int_14_29, int_0_29, int_11_28, int_13_28); - fullAdd_x FA_2320_3576(int_17_29, int_16_29, int_2_29, int_4_29, int_6_29); - fullAdd_x FA_2320_3792(int_19_29, int_18_29, int_8_29, int_10_29, int_15_28); - fullAdd_x FA_2320_4008(int_21_29, int_20_29, int_17_28, int_19_28, int_12_29); - fullAdd_x FA_2320_4224(int_23_29, int_22_29, int_14_29, int_21_28, int_16_29); - fullAdd_x FA_2320_4440(int_25_29, int_24_29, int_18_29, int_23_28, int_20_29); - fullAdd_x FA_2320_4656(int_27_29, int_26_29, int_25_28, int_22_29, int_24_29); - assign Sum[29] = int_27_28; - assign Carry[29] = int_26_29; - - // Hardware for column 30 - - r4bs r4bs_2400_64(yy[29], yy[30], single[0], double[0], neg[0], pp_0_30); - halfAdd HA_2400_192(int_1_30, int_0_30, neg[15], pp_0_30); - r4bs r4bs_2400_272(yy[27], yy[28], single[1], double[1], neg[1], pp_1_30); - r4bs r4bs_2400_400(yy[25], yy[26], single[2], double[2], neg[2], pp_2_30); - r4bs r4bs_2400_528(yy[23], yy[24], single[3], double[3], neg[3], pp_3_30); - fullAdd_x FA_2400_656(int_3_30, int_2_30, pp_1_30, pp_2_30, pp_3_30); - r4bs r4bs_2400_872(yy[21], yy[22], single[4], double[4], neg[4], pp_4_30); - r4bs r4bs_2400_1000(yy[19], yy[20], single[5], double[5], neg[5], pp_5_30); - r4bs r4bs_2400_1128(yy[17], yy[18], single[6], double[6], neg[6], pp_6_30); - fullAdd_x FA_2400_1256(int_5_30, int_4_30, pp_4_30, pp_5_30, pp_6_30); - r4bs r4bs_2400_1472(yy[15], yy[16], single[7], double[7], neg[7], pp_7_30); - r4bs r4bs_2400_1600(yy[13], yy[14], single[8], double[8], neg[8], pp_8_30); - r4bs r4bs_2400_1728(yy[11], yy[12], single[9], double[9], neg[9], pp_9_30); - fullAdd_x FA_2400_1856(int_7_30, int_6_30, pp_7_30, pp_8_30, pp_9_30); - r4bs r4bs_2400_2072(yy[9], yy[10], single[10], double[10], neg[10], pp_10_30); - r4bs r4bs_2400_2200(yy[7], yy[8], single[11], double[11], neg[11], pp_11_30); - r4bs r4bs_2400_2328(yy[5], yy[6], single[12], double[12], neg[12], pp_12_30); - fullAdd_x FA_2400_2456(int_9_30, int_8_30, pp_10_30, pp_11_30, pp_12_30); - r4bs r4bs_2400_2672(yy[3], yy[4], single[13], double[13], neg[13], pp_13_30); - r4bs r4bs_2400_2800(yy[1], yy[2], single[14], double[14], neg[14], pp_14_30); - r4bs r4bs_2400_2928(gnd, yy[0], single[15], double[15], neg[15], pp_15_30); - fullAdd_x FA_2400_3056(int_11_30, int_10_30, pp_13_30, pp_14_30, pp_15_30); - fullAdd_x FA_2400_3272(int_13_30, int_12_30, int_1_29, int_3_29, int_5_29); - fullAdd_x FA_2400_3488(int_15_30, int_14_30, int_7_29, int_9_29, int_0_30); - fullAdd_x FA_2400_3704(int_17_30, int_16_30, int_11_29, int_13_29, int_2_30); - fullAdd_x FA_2400_3920(int_19_30, int_18_30, int_4_30, int_6_30, int_8_30); - fullAdd_x FA_2400_4136(int_21_30, int_20_30, int_10_30, int_15_29, int_17_29); - fullAdd_x FA_2400_4352(int_23_30, int_22_30, int_12_30, int_14_30, int_19_29); - fullAdd_x FA_2400_4568(int_25_30, int_24_30, int_21_29, int_16_30, int_18_30); - fullAdd_x FA_2400_4784(int_27_30, int_26_30, int_23_29, int_20_30, int_22_30); - fullAdd_x FA_2400_5000(int_29_30, int_28_30, int_25_29, int_24_30, int_26_30); - assign Sum[30] = int_27_29; - assign Carry[30] = int_28_30; - - // Hardware for column 31 - - r4bs r4bs_2480_64(yy[30], yy[31], single[0], double[0], neg[0], pp_0_31); - r4bs r4bs_2480_192(yy[28], yy[29], single[1], double[1], neg[1], pp_1_31); - halfAdd HA_2480_320(int_1_31, int_0_31, pp_0_31, pp_1_31); - r4bs r4bs_2480_400(yy[26], yy[27], single[2], double[2], neg[2], pp_2_31); - r4bs r4bs_2480_528(yy[24], yy[25], single[3], double[3], neg[3], pp_3_31); - r4bs r4bs_2480_656(yy[22], yy[23], single[4], double[4], neg[4], pp_4_31); - fullAdd_x FA_2480_784(int_3_31, int_2_31, pp_2_31, pp_3_31, pp_4_31); - r4bs r4bs_2480_1000(yy[20], yy[21], single[5], double[5], neg[5], pp_5_31); - r4bs r4bs_2480_1128(yy[18], yy[19], single[6], double[6], neg[6], pp_6_31); - r4bs r4bs_2480_1256(yy[16], yy[17], single[7], double[7], neg[7], pp_7_31); - fullAdd_x FA_2480_1384(int_5_31, int_4_31, pp_5_31, pp_6_31, pp_7_31); - r4bs r4bs_2480_1600(yy[14], yy[15], single[8], double[8], neg[8], pp_8_31); - r4bs r4bs_2480_1728(yy[12], yy[13], single[9], double[9], neg[9], pp_9_31); - r4bs r4bs_2480_1856(yy[10], yy[11], single[10], double[10], neg[10], pp_10_31); - fullAdd_x FA_2480_1984(int_7_31, int_6_31, pp_8_31, pp_9_31, pp_10_31); - r4bs r4bs_2480_2200(yy[8], yy[9], single[11], double[11], neg[11], pp_11_31); - r4bs r4bs_2480_2328(yy[6], yy[7], single[12], double[12], neg[12], pp_12_31); - r4bs r4bs_2480_2456(yy[4], yy[5], single[13], double[13], neg[13], pp_13_31); - fullAdd_x FA_2480_2584(int_9_31, int_8_31, pp_11_31, pp_12_31, pp_13_31); - r4bs r4bs_2480_2800(yy[2], yy[3], single[14], double[14], neg[14], pp_14_31); - r4bs r4bs_2480_2928(yy[0], yy[1], single[15], double[15], neg[15], pp_15_31); - fullAdd_x FA_2480_3056(int_11_31, int_10_31, pp_14_31, pp_15_31, int_1_30); - fullAdd_x FA_2480_3272(int_13_31, int_12_31, int_3_30, int_5_30, int_7_30); - fullAdd_x FA_2480_3488(int_15_31, int_14_31, int_9_30, int_11_30, int_0_31); - fullAdd_x FA_2480_3704(int_17_31, int_16_31, int_13_30, int_15_30, int_2_31); - fullAdd_x FA_2480_3920(int_19_31, int_18_31, int_4_31, int_6_31, int_8_31); - fullAdd_x FA_2480_4136(int_21_31, int_20_31, int_10_31, int_17_30, int_19_30); - fullAdd_x FA_2480_4352(int_23_31, int_22_31, int_12_31, int_14_31, int_21_30); - fullAdd_x FA_2480_4568(int_25_31, int_24_31, int_16_31, int_18_31, int_23_30); - fullAdd_x FA_2480_4784(int_27_31, int_26_31, int_25_30, int_20_31, int_22_31); - fullAdd_x FA_2480_5000(int_29_31, int_28_31, int_27_30, int_24_31, int_26_31); - assign Sum[31] = int_29_30; - assign Carry[31] = int_28_31; - - // Hardware for column 32 - - r4bs r4bs_2560_64(yy[31], yy[32], single[0], double[0], neg[0], pp_0_32); - halfAdd HA_2560_192(int_1_32, int_0_32, neg[16], pp_0_32); - r4bs r4bs_2560_272(yy[29], yy[30], single[1], double[1], neg[1], pp_1_32); - r4bs r4bs_2560_400(yy[27], yy[28], single[2], double[2], neg[2], pp_2_32); - r4bs r4bs_2560_528(yy[25], yy[26], single[3], double[3], neg[3], pp_3_32); - fullAdd_x FA_2560_656(int_3_32, int_2_32, pp_1_32, pp_2_32, pp_3_32); - r4bs r4bs_2560_872(yy[23], yy[24], single[4], double[4], neg[4], pp_4_32); - r4bs r4bs_2560_1000(yy[21], yy[22], single[5], double[5], neg[5], pp_5_32); - r4bs r4bs_2560_1128(yy[19], yy[20], single[6], double[6], neg[6], pp_6_32); - fullAdd_x FA_2560_1256(int_5_32, int_4_32, pp_4_32, pp_5_32, pp_6_32); - r4bs r4bs_2560_1472(yy[17], yy[18], single[7], double[7], neg[7], pp_7_32); - r4bs r4bs_2560_1600(yy[15], yy[16], single[8], double[8], neg[8], pp_8_32); - r4bs r4bs_2560_1728(yy[13], yy[14], single[9], double[9], neg[9], pp_9_32); - fullAdd_x FA_2560_1856(int_7_32, int_6_32, pp_7_32, pp_8_32, pp_9_32); - r4bs r4bs_2560_2072(yy[11], yy[12], single[10], double[10], neg[10], pp_10_32); - r4bs r4bs_2560_2200(yy[9], yy[10], single[11], double[11], neg[11], pp_11_32); - r4bs r4bs_2560_2328(yy[7], yy[8], single[12], double[12], neg[12], pp_12_32); - fullAdd_x FA_2560_2456(int_9_32, int_8_32, pp_10_32, pp_11_32, pp_12_32); - r4bs r4bs_2560_2672(yy[5], yy[6], single[13], double[13], neg[13], pp_13_32); - r4bs r4bs_2560_2800(yy[3], yy[4], single[14], double[14], neg[14], pp_14_32); - r4bs r4bs_2560_2928(yy[1], yy[2], single[15], double[15], neg[15], pp_15_32); - fullAdd_x FA_2560_3056(int_11_32, int_10_32, pp_13_32, pp_14_32, pp_15_32); - r4bs r4bs_2560_3272(gnd, yy[0], single[16], double[16], neg[16], pp_16_32); - fullAdd_x FA_2560_3400(int_13_32, int_12_32, pp_16_32, int_1_31, int_3_31); - fullAdd_x FA_2560_3616(int_15_32, int_14_32, int_5_31, int_7_31, int_9_31); - fullAdd_x FA_2560_3832(int_17_32, int_16_32, int_0_32, int_11_31, int_13_31); - fullAdd_x FA_2560_4048(int_19_32, int_18_32, int_15_31, int_2_32, int_4_32); - fullAdd_x FA_2560_4264(int_21_32, int_20_32, int_6_32, int_8_32, int_10_32); - fullAdd_x FA_2560_4480(int_23_32, int_22_32, int_12_32, int_17_31, int_19_31); - fullAdd_x FA_2560_4696(int_25_32, int_24_32, int_14_32, int_16_32, int_21_31); - fullAdd_x FA_2560_4912(int_27_32, int_26_32, int_18_32, int_20_32, int_23_31); - fullAdd_x FA_2560_5128(int_29_32, int_28_32, int_22_32, int_24_32, int_25_31); - fullAdd_x FA_2560_5344(int_31_32, int_30_32, int_27_31, int_26_32, int_28_32); - assign Sum[32] = int_29_31; - assign Carry[32] = int_30_32; - - // Hardware for column 33 - - r4bs r4bs_2640_64(yy[32], yy[33], single[0], double[0], neg[0], pp_0_33); - r4bs r4bs_2640_192(yy[30], yy[31], single[1], double[1], neg[1], pp_1_33); - halfAdd HA_2640_320(int_1_33, int_0_33, pp_0_33, pp_1_33); - r4bs r4bs_2640_400(yy[28], yy[29], single[2], double[2], neg[2], pp_2_33); - r4bs r4bs_2640_528(yy[26], yy[27], single[3], double[3], neg[3], pp_3_33); - r4bs r4bs_2640_656(yy[24], yy[25], single[4], double[4], neg[4], pp_4_33); - fullAdd_x FA_2640_784(int_3_33, int_2_33, pp_2_33, pp_3_33, pp_4_33); - r4bs r4bs_2640_1000(yy[22], yy[23], single[5], double[5], neg[5], pp_5_33); - r4bs r4bs_2640_1128(yy[20], yy[21], single[6], double[6], neg[6], pp_6_33); - r4bs r4bs_2640_1256(yy[18], yy[19], single[7], double[7], neg[7], pp_7_33); - fullAdd_x FA_2640_1384(int_5_33, int_4_33, pp_5_33, pp_6_33, pp_7_33); - r4bs r4bs_2640_1600(yy[16], yy[17], single[8], double[8], neg[8], pp_8_33); - r4bs r4bs_2640_1728(yy[14], yy[15], single[9], double[9], neg[9], pp_9_33); - r4bs r4bs_2640_1856(yy[12], yy[13], single[10], double[10], neg[10], pp_10_33); - fullAdd_x FA_2640_1984(int_7_33, int_6_33, pp_8_33, pp_9_33, pp_10_33); - r4bs r4bs_2640_2200(yy[10], yy[11], single[11], double[11], neg[11], pp_11_33); - r4bs r4bs_2640_2328(yy[8], yy[9], single[12], double[12], neg[12], pp_12_33); - r4bs r4bs_2640_2456(yy[6], yy[7], single[13], double[13], neg[13], pp_13_33); - fullAdd_x FA_2640_2584(int_9_33, int_8_33, pp_11_33, pp_12_33, pp_13_33); - r4bs r4bs_2640_2800(yy[4], yy[5], single[14], double[14], neg[14], pp_14_33); - r4bs r4bs_2640_2928(yy[2], yy[3], single[15], double[15], neg[15], pp_15_33); - r4bs r4bs_2640_3056(yy[0], yy[1], single[16], double[16], neg[16], pp_16_33); - fullAdd_x FA_2640_3184(int_11_33, int_10_33, pp_14_33, pp_15_33, pp_16_33); - fullAdd_x FA_2640_3400(int_13_33, int_12_33, int_1_32, int_3_32, int_5_32); - fullAdd_x FA_2640_3616(int_15_33, int_14_33, int_7_32, int_9_32, int_11_32); - fullAdd_x FA_2640_3832(int_17_33, int_16_33, int_0_33, int_13_32, int_15_32); - fullAdd_x FA_2640_4048(int_19_33, int_18_33, int_2_33, int_4_33, int_6_33); - fullAdd_x FA_2640_4264(int_21_33, int_20_33, int_8_33, int_10_33, int_17_32); - fullAdd_x FA_2640_4480(int_23_33, int_22_33, int_19_32, int_21_32, int_12_33); - fullAdd_x FA_2640_4696(int_25_33, int_24_33, int_14_33, int_23_32, int_16_33); - fullAdd_x FA_2640_4912(int_27_33, int_26_33, int_18_33, int_20_33, int_25_32); - fullAdd_x FA_2640_5128(int_29_33, int_28_33, int_22_33, int_27_32, int_24_33); - fullAdd_x FA_2640_5344(int_31_33, int_30_33, int_26_33, int_29_32, int_28_33); - assign Sum[33] = int_31_32; - assign Carry[33] = int_30_33; - - // Hardware for column 34 - - r4bs r4bs_2720_64(yy[33], yy[34], single[0], double[0], neg[0], pp_0_34); - halfAdd HA_2720_192(int_1_34, int_0_34, neg[17], pp_0_34); - r4bs r4bs_2720_272(yy[31], yy[32], single[1], double[1], neg[1], pp_1_34); - r4bs r4bs_2720_400(yy[29], yy[30], single[2], double[2], neg[2], pp_2_34); - r4bs r4bs_2720_528(yy[27], yy[28], single[3], double[3], neg[3], pp_3_34); - fullAdd_x FA_2720_656(int_3_34, int_2_34, pp_1_34, pp_2_34, pp_3_34); - r4bs r4bs_2720_872(yy[25], yy[26], single[4], double[4], neg[4], pp_4_34); - r4bs r4bs_2720_1000(yy[23], yy[24], single[5], double[5], neg[5], pp_5_34); - r4bs r4bs_2720_1128(yy[21], yy[22], single[6], double[6], neg[6], pp_6_34); - fullAdd_x FA_2720_1256(int_5_34, int_4_34, pp_4_34, pp_5_34, pp_6_34); - r4bs r4bs_2720_1472(yy[19], yy[20], single[7], double[7], neg[7], pp_7_34); - r4bs r4bs_2720_1600(yy[17], yy[18], single[8], double[8], neg[8], pp_8_34); - r4bs r4bs_2720_1728(yy[15], yy[16], single[9], double[9], neg[9], pp_9_34); - fullAdd_x FA_2720_1856(int_7_34, int_6_34, pp_7_34, pp_8_34, pp_9_34); - r4bs r4bs_2720_2072(yy[13], yy[14], single[10], double[10], neg[10], pp_10_34); - r4bs r4bs_2720_2200(yy[11], yy[12], single[11], double[11], neg[11], pp_11_34); - r4bs r4bs_2720_2328(yy[9], yy[10], single[12], double[12], neg[12], pp_12_34); - fullAdd_x FA_2720_2456(int_9_34, int_8_34, pp_10_34, pp_11_34, pp_12_34); - r4bs r4bs_2720_2672(yy[7], yy[8], single[13], double[13], neg[13], pp_13_34); - r4bs r4bs_2720_2800(yy[5], yy[6], single[14], double[14], neg[14], pp_14_34); - r4bs r4bs_2720_2928(yy[3], yy[4], single[15], double[15], neg[15], pp_15_34); - fullAdd_x FA_2720_3056(int_11_34, int_10_34, pp_13_34, pp_14_34, pp_15_34); - r4bs r4bs_2720_3272(yy[1], yy[2], single[16], double[16], neg[16], pp_16_34); - r4bs r4bs_2720_3400(gnd, yy[0], single[17], double[17], neg[17], pp_17_34); - fullAdd_x FA_2720_3528(int_13_34, int_12_34, pp_16_34, pp_17_34, int_1_33); - fullAdd_x FA_2720_3744(int_15_34, int_14_34, int_3_33, int_5_33, int_7_33); - fullAdd_x FA_2720_3960(int_17_34, int_16_34, int_9_33, int_11_33, int_0_34); - fullAdd_x FA_2720_4176(int_19_34, int_18_34, int_13_33, int_15_33, int_2_34); - fullAdd_x FA_2720_4392(int_21_34, int_20_34, int_4_34, int_6_34, int_8_34); - fullAdd_x FA_2720_4608(int_23_34, int_22_34, int_10_34, int_12_34, int_17_33); - fullAdd_x FA_2720_4824(int_25_34, int_24_34, int_19_33, int_14_34, int_16_34); - fullAdd_x FA_2720_5040(int_27_34, int_26_34, int_21_33, int_23_33, int_18_34); - fullAdd_x FA_2720_5256(int_29_34, int_28_34, int_20_34, int_22_34, int_25_33); - fullAdd_x FA_2720_5472(int_31_34, int_30_34, int_24_34, int_27_33, int_26_34); - fullAdd_x FA_2720_5688(int_33_34, int_32_34, int_28_34, int_29_33, int_30_34); - assign Sum[34] = int_31_33; - assign Carry[34] = int_32_34; - - // Hardware for column 35 - - r4bs r4bs_2800_64(yy[34], yy[35], single[0], double[0], neg[0], pp_0_35); - r4bs r4bs_2800_192(yy[32], yy[33], single[1], double[1], neg[1], pp_1_35); - halfAdd HA_2800_320(int_1_35, int_0_35, pp_0_35, pp_1_35); - r4bs r4bs_2800_400(yy[30], yy[31], single[2], double[2], neg[2], pp_2_35); - r4bs r4bs_2800_528(yy[28], yy[29], single[3], double[3], neg[3], pp_3_35); - r4bs r4bs_2800_656(yy[26], yy[27], single[4], double[4], neg[4], pp_4_35); - fullAdd_x FA_2800_784(int_3_35, int_2_35, pp_2_35, pp_3_35, pp_4_35); - r4bs r4bs_2800_1000(yy[24], yy[25], single[5], double[5], neg[5], pp_5_35); - r4bs r4bs_2800_1128(yy[22], yy[23], single[6], double[6], neg[6], pp_6_35); - r4bs r4bs_2800_1256(yy[20], yy[21], single[7], double[7], neg[7], pp_7_35); - fullAdd_x FA_2800_1384(int_5_35, int_4_35, pp_5_35, pp_6_35, pp_7_35); - r4bs r4bs_2800_1600(yy[18], yy[19], single[8], double[8], neg[8], pp_8_35); - r4bs r4bs_2800_1728(yy[16], yy[17], single[9], double[9], neg[9], pp_9_35); - r4bs r4bs_2800_1856(yy[14], yy[15], single[10], double[10], neg[10], pp_10_35); - fullAdd_x FA_2800_1984(int_7_35, int_6_35, pp_8_35, pp_9_35, pp_10_35); - r4bs r4bs_2800_2200(yy[12], yy[13], single[11], double[11], neg[11], pp_11_35); - r4bs r4bs_2800_2328(yy[10], yy[11], single[12], double[12], neg[12], pp_12_35); - r4bs r4bs_2800_2456(yy[8], yy[9], single[13], double[13], neg[13], pp_13_35); - fullAdd_x FA_2800_2584(int_9_35, int_8_35, pp_11_35, pp_12_35, pp_13_35); - r4bs r4bs_2800_2800(yy[6], yy[7], single[14], double[14], neg[14], pp_14_35); - r4bs r4bs_2800_2928(yy[4], yy[5], single[15], double[15], neg[15], pp_15_35); - r4bs r4bs_2800_3056(yy[2], yy[3], single[16], double[16], neg[16], pp_16_35); - fullAdd_x FA_2800_3184(int_11_35, int_10_35, pp_14_35, pp_15_35, pp_16_35); - r4bs r4bs_2800_3400(yy[0], yy[1], single[17], double[17], neg[17], pp_17_35); - fullAdd_x FA_2800_3528(int_13_35, int_12_35, pp_17_35, int_1_34, int_3_34); - fullAdd_x FA_2800_3744(int_15_35, int_14_35, int_5_34, int_7_34, int_9_34); - fullAdd_x FA_2800_3960(int_17_35, int_16_35, int_11_34, int_0_35, int_13_34); - fullAdd_x FA_2800_4176(int_19_35, int_18_35, int_15_34, int_17_34, int_2_35); - fullAdd_x FA_2800_4392(int_21_35, int_20_35, int_4_35, int_6_35, int_8_35); - fullAdd_x FA_2800_4608(int_23_35, int_22_35, int_10_35, int_12_35, int_19_34); - fullAdd_x FA_2800_4824(int_25_35, int_24_35, int_21_34, int_14_35, int_16_35); - fullAdd_x FA_2800_5040(int_27_35, int_26_35, int_23_34, int_25_34, int_18_35); - fullAdd_x FA_2800_5256(int_29_35, int_28_35, int_20_35, int_22_35, int_27_34); - fullAdd_x FA_2800_5472(int_31_35, int_30_35, int_24_35, int_29_34, int_26_35); - fullAdd_x FA_2800_5688(int_33_35, int_32_35, int_28_35, int_31_34, int_30_35); - assign Sum[35] = int_33_34; - assign Carry[35] = int_32_35; - - // Hardware for column 36 - - r4bs r4bs_2880_64(yy[35], yy[36], single[0], double[0], neg[0], pp_0_36); - halfAdd HA_2880_192(int_1_36, int_0_36, neg[18], pp_0_36); - r4bs r4bs_2880_272(yy[33], yy[34], single[1], double[1], neg[1], pp_1_36); - r4bs r4bs_2880_400(yy[31], yy[32], single[2], double[2], neg[2], pp_2_36); - r4bs r4bs_2880_528(yy[29], yy[30], single[3], double[3], neg[3], pp_3_36); - fullAdd_x FA_2880_656(int_3_36, int_2_36, pp_1_36, pp_2_36, pp_3_36); - r4bs r4bs_2880_872(yy[27], yy[28], single[4], double[4], neg[4], pp_4_36); - r4bs r4bs_2880_1000(yy[25], yy[26], single[5], double[5], neg[5], pp_5_36); - r4bs r4bs_2880_1128(yy[23], yy[24], single[6], double[6], neg[6], pp_6_36); - fullAdd_x FA_2880_1256(int_5_36, int_4_36, pp_4_36, pp_5_36, pp_6_36); - r4bs r4bs_2880_1472(yy[21], yy[22], single[7], double[7], neg[7], pp_7_36); - r4bs r4bs_2880_1600(yy[19], yy[20], single[8], double[8], neg[8], pp_8_36); - r4bs r4bs_2880_1728(yy[17], yy[18], single[9], double[9], neg[9], pp_9_36); - fullAdd_x FA_2880_1856(int_7_36, int_6_36, pp_7_36, pp_8_36, pp_9_36); - r4bs r4bs_2880_2072(yy[15], yy[16], single[10], double[10], neg[10], pp_10_36); - r4bs r4bs_2880_2200(yy[13], yy[14], single[11], double[11], neg[11], pp_11_36); - r4bs r4bs_2880_2328(yy[11], yy[12], single[12], double[12], neg[12], pp_12_36); - fullAdd_x FA_2880_2456(int_9_36, int_8_36, pp_10_36, pp_11_36, pp_12_36); - r4bs r4bs_2880_2672(yy[9], yy[10], single[13], double[13], neg[13], pp_13_36); - r4bs r4bs_2880_2800(yy[7], yy[8], single[14], double[14], neg[14], pp_14_36); - r4bs r4bs_2880_2928(yy[5], yy[6], single[15], double[15], neg[15], pp_15_36); - fullAdd_x FA_2880_3056(int_11_36, int_10_36, pp_13_36, pp_14_36, pp_15_36); - r4bs r4bs_2880_3272(yy[3], yy[4], single[16], double[16], neg[16], pp_16_36); - r4bs r4bs_2880_3400(yy[1], yy[2], single[17], double[17], neg[17], pp_17_36); - r4bs r4bs_2880_3528(gnd, yy[0], single[18], double[18], neg[18], pp_18_36); - fullAdd_x FA_2880_3656(int_13_36, int_12_36, pp_16_36, pp_17_36, pp_18_36); - fullAdd_x FA_2880_3872(int_15_36, int_14_36, int_1_35, int_3_35, int_5_35); - fullAdd_x FA_2880_4088(int_17_36, int_16_36, int_7_35, int_9_35, int_11_35); - fullAdd_x FA_2880_4304(int_19_36, int_18_36, int_0_36, int_13_35, int_15_35); - fullAdd_x FA_2880_4520(int_21_36, int_20_36, int_2_36, int_4_36, int_6_36); - fullAdd_x FA_2880_4736(int_23_36, int_22_36, int_8_36, int_10_36, int_12_36); - fullAdd_x FA_2880_4952(int_25_36, int_24_36, int_17_35, int_19_35, int_21_35); - fullAdd_x FA_2880_5168(int_27_36, int_26_36, int_14_36, int_16_36, int_23_35); - fullAdd_x FA_2880_5384(int_29_36, int_28_36, int_25_35, int_18_36, int_20_36); - fullAdd_x FA_2880_5600(int_31_36, int_30_36, int_22_36, int_27_35, int_24_36); - fullAdd_x FA_2880_5816(int_33_36, int_32_36, int_26_36, int_29_35, int_28_36); - fullAdd_x FA_2880_6032(int_35_36, int_34_36, int_31_35, int_30_36, int_32_36); - assign Sum[36] = int_33_35; - assign Carry[36] = int_34_36; - - // Hardware for column 37 - - r4bs r4bs_2960_64(yy[36], yy[37], single[0], double[0], neg[0], pp_0_37); - r4bs r4bs_2960_192(yy[34], yy[35], single[1], double[1], neg[1], pp_1_37); - halfAdd HA_2960_320(int_1_37, int_0_37, pp_0_37, pp_1_37); - r4bs r4bs_2960_400(yy[32], yy[33], single[2], double[2], neg[2], pp_2_37); - r4bs r4bs_2960_528(yy[30], yy[31], single[3], double[3], neg[3], pp_3_37); - r4bs r4bs_2960_656(yy[28], yy[29], single[4], double[4], neg[4], pp_4_37); - fullAdd_x FA_2960_784(int_3_37, int_2_37, pp_2_37, pp_3_37, pp_4_37); - r4bs r4bs_2960_1000(yy[26], yy[27], single[5], double[5], neg[5], pp_5_37); - r4bs r4bs_2960_1128(yy[24], yy[25], single[6], double[6], neg[6], pp_6_37); - r4bs r4bs_2960_1256(yy[22], yy[23], single[7], double[7], neg[7], pp_7_37); - fullAdd_x FA_2960_1384(int_5_37, int_4_37, pp_5_37, pp_6_37, pp_7_37); - r4bs r4bs_2960_1600(yy[20], yy[21], single[8], double[8], neg[8], pp_8_37); - r4bs r4bs_2960_1728(yy[18], yy[19], single[9], double[9], neg[9], pp_9_37); - r4bs r4bs_2960_1856(yy[16], yy[17], single[10], double[10], neg[10], pp_10_37); - fullAdd_x FA_2960_1984(int_7_37, int_6_37, pp_8_37, pp_9_37, pp_10_37); - r4bs r4bs_2960_2200(yy[14], yy[15], single[11], double[11], neg[11], pp_11_37); - r4bs r4bs_2960_2328(yy[12], yy[13], single[12], double[12], neg[12], pp_12_37); - r4bs r4bs_2960_2456(yy[10], yy[11], single[13], double[13], neg[13], pp_13_37); - fullAdd_x FA_2960_2584(int_9_37, int_8_37, pp_11_37, pp_12_37, pp_13_37); - r4bs r4bs_2960_2800(yy[8], yy[9], single[14], double[14], neg[14], pp_14_37); - r4bs r4bs_2960_2928(yy[6], yy[7], single[15], double[15], neg[15], pp_15_37); - r4bs r4bs_2960_3056(yy[4], yy[5], single[16], double[16], neg[16], pp_16_37); - fullAdd_x FA_2960_3184(int_11_37, int_10_37, pp_14_37, pp_15_37, pp_16_37); - r4bs r4bs_2960_3400(yy[2], yy[3], single[17], double[17], neg[17], pp_17_37); - r4bs r4bs_2960_3528(yy[0], yy[1], single[18], double[18], neg[18], pp_18_37); - fullAdd_x FA_2960_3656(int_13_37, int_12_37, pp_17_37, pp_18_37, int_1_36); - fullAdd_x FA_2960_3872(int_15_37, int_14_37, int_3_36, int_5_36, int_7_36); - fullAdd_x FA_2960_4088(int_17_37, int_16_37, int_9_36, int_11_36, int_13_36); - fullAdd_x FA_2960_4304(int_19_37, int_18_37, int_0_37, int_15_36, int_17_36); - fullAdd_x FA_2960_4520(int_21_37, int_20_37, int_2_37, int_4_37, int_6_37); - fullAdd_x FA_2960_4736(int_23_37, int_22_37, int_8_37, int_10_37, int_12_37); - fullAdd_x FA_2960_4952(int_25_37, int_24_37, int_19_36, int_21_36, int_23_36); - fullAdd_x FA_2960_5168(int_27_37, int_26_37, int_14_37, int_16_37, int_25_36); - fullAdd_x FA_2960_5384(int_29_37, int_28_37, int_18_37, int_20_37, int_22_37); - fullAdd_x FA_2960_5600(int_31_37, int_30_37, int_27_36, int_29_36, int_24_37); - fullAdd_x FA_2960_5816(int_33_37, int_32_37, int_26_37, int_31_36, int_28_37); - fullAdd_x FA_2960_6032(int_35_37, int_34_37, int_33_36, int_30_37, int_32_37); - assign Sum[37] = int_35_36; - assign Carry[37] = int_34_37; - - // Hardware for column 38 - - r4bs r4bs_3040_64(yy[37], yy[38], single[0], double[0], neg[0], pp_0_38); - halfAdd HA_3040_192(int_1_38, int_0_38, neg[19], pp_0_38); - r4bs r4bs_3040_272(yy[35], yy[36], single[1], double[1], neg[1], pp_1_38); - r4bs r4bs_3040_400(yy[33], yy[34], single[2], double[2], neg[2], pp_2_38); - r4bs r4bs_3040_528(yy[31], yy[32], single[3], double[3], neg[3], pp_3_38); - fullAdd_x FA_3040_656(int_3_38, int_2_38, pp_1_38, pp_2_38, pp_3_38); - r4bs r4bs_3040_872(yy[29], yy[30], single[4], double[4], neg[4], pp_4_38); - r4bs r4bs_3040_1000(yy[27], yy[28], single[5], double[5], neg[5], pp_5_38); - r4bs r4bs_3040_1128(yy[25], yy[26], single[6], double[6], neg[6], pp_6_38); - fullAdd_x FA_3040_1256(int_5_38, int_4_38, pp_4_38, pp_5_38, pp_6_38); - r4bs r4bs_3040_1472(yy[23], yy[24], single[7], double[7], neg[7], pp_7_38); - r4bs r4bs_3040_1600(yy[21], yy[22], single[8], double[8], neg[8], pp_8_38); - r4bs r4bs_3040_1728(yy[19], yy[20], single[9], double[9], neg[9], pp_9_38); - fullAdd_x FA_3040_1856(int_7_38, int_6_38, pp_7_38, pp_8_38, pp_9_38); - r4bs r4bs_3040_2072(yy[17], yy[18], single[10], double[10], neg[10], pp_10_38); - r4bs r4bs_3040_2200(yy[15], yy[16], single[11], double[11], neg[11], pp_11_38); - r4bs r4bs_3040_2328(yy[13], yy[14], single[12], double[12], neg[12], pp_12_38); - fullAdd_x FA_3040_2456(int_9_38, int_8_38, pp_10_38, pp_11_38, pp_12_38); - r4bs r4bs_3040_2672(yy[11], yy[12], single[13], double[13], neg[13], pp_13_38); - r4bs r4bs_3040_2800(yy[9], yy[10], single[14], double[14], neg[14], pp_14_38); - r4bs r4bs_3040_2928(yy[7], yy[8], single[15], double[15], neg[15], pp_15_38); - fullAdd_x FA_3040_3056(int_11_38, int_10_38, pp_13_38, pp_14_38, pp_15_38); - r4bs r4bs_3040_3272(yy[5], yy[6], single[16], double[16], neg[16], pp_16_38); - r4bs r4bs_3040_3400(yy[3], yy[4], single[17], double[17], neg[17], pp_17_38); - r4bs r4bs_3040_3528(yy[1], yy[2], single[18], double[18], neg[18], pp_18_38); - fullAdd_x FA_3040_3656(int_13_38, int_12_38, pp_16_38, pp_17_38, pp_18_38); - r4bs r4bs_3040_3872(gnd, yy[0], single[19], double[19], neg[19], pp_19_38); - fullAdd_x FA_3040_4000(int_15_38, int_14_38, pp_19_38, int_1_37, int_3_37); - fullAdd_x FA_3040_4216(int_17_38, int_16_38, int_5_37, int_7_37, int_9_37); - fullAdd_x FA_3040_4432(int_19_38, int_18_38, int_11_37, int_0_38, int_13_37); - fullAdd_x FA_3040_4648(int_21_38, int_20_38, int_15_37, int_17_37, int_2_38); - fullAdd_x FA_3040_4864(int_23_38, int_22_38, int_4_38, int_6_38, int_8_38); - fullAdd_x FA_3040_5080(int_25_38, int_24_38, int_10_38, int_12_38, int_14_38); - fullAdd_x FA_3040_5296(int_27_38, int_26_38, int_19_37, int_21_37, int_23_37); - fullAdd_x FA_3040_5512(int_29_38, int_28_38, int_16_38, int_18_38, int_25_37); - fullAdd_x FA_3040_5728(int_31_38, int_30_38, int_20_38, int_22_38, int_24_38); - fullAdd_x FA_3040_5944(int_33_38, int_32_38, int_27_37, int_29_37, int_26_38); - fullAdd_x FA_3040_6160(int_35_38, int_34_38, int_28_38, int_31_37, int_30_38); - fullAdd_x FA_3040_6376(int_37_38, int_36_38, int_33_37, int_32_38, int_34_38); - assign Sum[38] = int_35_37; - assign Carry[38] = int_36_38; - - // Hardware for column 39 - - r4bs r4bs_3120_64(yy[38], yy[39], single[0], double[0], neg[0], pp_0_39); - r4bs r4bs_3120_192(yy[36], yy[37], single[1], double[1], neg[1], pp_1_39); - halfAdd HA_3120_320(int_1_39, int_0_39, pp_0_39, pp_1_39); - r4bs r4bs_3120_400(yy[34], yy[35], single[2], double[2], neg[2], pp_2_39); - r4bs r4bs_3120_528(yy[32], yy[33], single[3], double[3], neg[3], pp_3_39); - r4bs r4bs_3120_656(yy[30], yy[31], single[4], double[4], neg[4], pp_4_39); - fullAdd_x FA_3120_784(int_3_39, int_2_39, pp_2_39, pp_3_39, pp_4_39); - r4bs r4bs_3120_1000(yy[28], yy[29], single[5], double[5], neg[5], pp_5_39); - r4bs r4bs_3120_1128(yy[26], yy[27], single[6], double[6], neg[6], pp_6_39); - r4bs r4bs_3120_1256(yy[24], yy[25], single[7], double[7], neg[7], pp_7_39); - fullAdd_x FA_3120_1384(int_5_39, int_4_39, pp_5_39, pp_6_39, pp_7_39); - r4bs r4bs_3120_1600(yy[22], yy[23], single[8], double[8], neg[8], pp_8_39); - r4bs r4bs_3120_1728(yy[20], yy[21], single[9], double[9], neg[9], pp_9_39); - r4bs r4bs_3120_1856(yy[18], yy[19], single[10], double[10], neg[10], pp_10_39); - fullAdd_x FA_3120_1984(int_7_39, int_6_39, pp_8_39, pp_9_39, pp_10_39); - r4bs r4bs_3120_2200(yy[16], yy[17], single[11], double[11], neg[11], pp_11_39); - r4bs r4bs_3120_2328(yy[14], yy[15], single[12], double[12], neg[12], pp_12_39); - r4bs r4bs_3120_2456(yy[12], yy[13], single[13], double[13], neg[13], pp_13_39); - fullAdd_x FA_3120_2584(int_9_39, int_8_39, pp_11_39, pp_12_39, pp_13_39); - r4bs r4bs_3120_2800(yy[10], yy[11], single[14], double[14], neg[14], pp_14_39); - r4bs r4bs_3120_2928(yy[8], yy[9], single[15], double[15], neg[15], pp_15_39); - r4bs r4bs_3120_3056(yy[6], yy[7], single[16], double[16], neg[16], pp_16_39); - fullAdd_x FA_3120_3184(int_11_39, int_10_39, pp_14_39, pp_15_39, pp_16_39); - r4bs r4bs_3120_3400(yy[4], yy[5], single[17], double[17], neg[17], pp_17_39); - r4bs r4bs_3120_3528(yy[2], yy[3], single[18], double[18], neg[18], pp_18_39); - r4bs r4bs_3120_3656(yy[0], yy[1], single[19], double[19], neg[19], pp_19_39); - fullAdd_x FA_3120_3784(int_13_39, int_12_39, pp_17_39, pp_18_39, pp_19_39); - fullAdd_x FA_3120_4000(int_15_39, int_14_39, int_1_38, int_3_38, int_5_38); - fullAdd_x FA_3120_4216(int_17_39, int_16_39, int_7_38, int_9_38, int_11_38); - fullAdd_x FA_3120_4432(int_19_39, int_18_39, int_13_38, int_0_39, int_15_38); - fullAdd_x FA_3120_4648(int_21_39, int_20_39, int_17_38, int_2_39, int_4_39); - fullAdd_x FA_3120_4864(int_23_39, int_22_39, int_6_39, int_8_39, int_10_39); - fullAdd_x FA_3120_5080(int_25_39, int_24_39, int_12_39, int_19_38, int_21_38); - fullAdd_x FA_3120_5296(int_27_39, int_26_39, int_23_38, int_14_39, int_16_39); - fullAdd_x FA_3120_5512(int_29_39, int_28_39, int_18_39, int_25_38, int_27_38); - fullAdd_x FA_3120_5728(int_31_39, int_30_39, int_20_39, int_22_39, int_24_39); - fullAdd_x FA_3120_5944(int_33_39, int_32_39, int_29_38, int_31_38, int_26_39); - fullAdd_x FA_3120_6160(int_35_39, int_34_39, int_28_39, int_33_38, int_30_39); - fullAdd_x FA_3120_6376(int_37_39, int_36_39, int_35_38, int_32_39, int_34_39); - assign Sum[39] = int_37_38; - assign Carry[39] = int_36_39; - - // Hardware for column 40 - - r4bs r4bs_3200_64(yy[39], yy[40], single[0], double[0], neg[0], pp_0_40); - halfAdd HA_3200_192(int_1_40, int_0_40, neg[20], pp_0_40); - r4bs r4bs_3200_272(yy[37], yy[38], single[1], double[1], neg[1], pp_1_40); - r4bs r4bs_3200_400(yy[35], yy[36], single[2], double[2], neg[2], pp_2_40); - r4bs r4bs_3200_528(yy[33], yy[34], single[3], double[3], neg[3], pp_3_40); - fullAdd_x FA_3200_656(int_3_40, int_2_40, pp_1_40, pp_2_40, pp_3_40); - r4bs r4bs_3200_872(yy[31], yy[32], single[4], double[4], neg[4], pp_4_40); - r4bs r4bs_3200_1000(yy[29], yy[30], single[5], double[5], neg[5], pp_5_40); - r4bs r4bs_3200_1128(yy[27], yy[28], single[6], double[6], neg[6], pp_6_40); - fullAdd_x FA_3200_1256(int_5_40, int_4_40, pp_4_40, pp_5_40, pp_6_40); - r4bs r4bs_3200_1472(yy[25], yy[26], single[7], double[7], neg[7], pp_7_40); - r4bs r4bs_3200_1600(yy[23], yy[24], single[8], double[8], neg[8], pp_8_40); - r4bs r4bs_3200_1728(yy[21], yy[22], single[9], double[9], neg[9], pp_9_40); - fullAdd_x FA_3200_1856(int_7_40, int_6_40, pp_7_40, pp_8_40, pp_9_40); - r4bs r4bs_3200_2072(yy[19], yy[20], single[10], double[10], neg[10], pp_10_40); - r4bs r4bs_3200_2200(yy[17], yy[18], single[11], double[11], neg[11], pp_11_40); - r4bs r4bs_3200_2328(yy[15], yy[16], single[12], double[12], neg[12], pp_12_40); - fullAdd_x FA_3200_2456(int_9_40, int_8_40, pp_10_40, pp_11_40, pp_12_40); - r4bs r4bs_3200_2672(yy[13], yy[14], single[13], double[13], neg[13], pp_13_40); - r4bs r4bs_3200_2800(yy[11], yy[12], single[14], double[14], neg[14], pp_14_40); - r4bs r4bs_3200_2928(yy[9], yy[10], single[15], double[15], neg[15], pp_15_40); - fullAdd_x FA_3200_3056(int_11_40, int_10_40, pp_13_40, pp_14_40, pp_15_40); - r4bs r4bs_3200_3272(yy[7], yy[8], single[16], double[16], neg[16], pp_16_40); - r4bs r4bs_3200_3400(yy[5], yy[6], single[17], double[17], neg[17], pp_17_40); - r4bs r4bs_3200_3528(yy[3], yy[4], single[18], double[18], neg[18], pp_18_40); - fullAdd_x FA_3200_3656(int_13_40, int_12_40, pp_16_40, pp_17_40, pp_18_40); - r4bs r4bs_3200_3872(yy[1], yy[2], single[19], double[19], neg[19], pp_19_40); - r4bs r4bs_3200_4000(gnd, yy[0], single[20], double[20], neg[20], pp_20_40); - fullAdd_x FA_3200_4128(int_15_40, int_14_40, pp_19_40, pp_20_40, int_1_39); - fullAdd_x FA_3200_4344(int_17_40, int_16_40, int_3_39, int_5_39, int_7_39); - fullAdd_x FA_3200_4560(int_19_40, int_18_40, int_9_39, int_11_39, int_13_39); - fullAdd_x FA_3200_4776(int_21_40, int_20_40, int_0_40, int_15_39, int_17_39); - fullAdd_x FA_3200_4992(int_23_40, int_22_40, int_2_40, int_4_40, int_6_40); - fullAdd_x FA_3200_5208(int_25_40, int_24_40, int_8_40, int_10_40, int_12_40); - fullAdd_x FA_3200_5424(int_27_40, int_26_40, int_14_40, int_19_39, int_21_39); - fullAdd_x FA_3200_5640(int_29_40, int_28_40, int_23_39, int_16_40, int_18_40); - fullAdd_x FA_3200_5856(int_31_40, int_30_40, int_25_39, int_27_39, int_20_40); - fullAdd_x FA_3200_6072(int_33_40, int_32_40, int_22_40, int_24_40, int_29_39); - fullAdd_x FA_3200_6288(int_35_40, int_34_40, int_26_40, int_28_40, int_31_39); - fullAdd_x FA_3200_6504(int_37_40, int_36_40, int_33_39, int_30_40, int_32_40); - fullAdd_x FA_3200_6720(int_39_40, int_38_40, int_35_39, int_34_40, int_36_40); - assign Sum[40] = int_37_39; - assign Carry[40] = int_38_40; - - // Hardware for column 41 - - r4bs r4bs_3280_64(yy[40], yy[41], single[0], double[0], neg[0], pp_0_41); - r4bs r4bs_3280_192(yy[38], yy[39], single[1], double[1], neg[1], pp_1_41); - halfAdd HA_3280_320(int_1_41, int_0_41, pp_0_41, pp_1_41); - r4bs r4bs_3280_400(yy[36], yy[37], single[2], double[2], neg[2], pp_2_41); - r4bs r4bs_3280_528(yy[34], yy[35], single[3], double[3], neg[3], pp_3_41); - r4bs r4bs_3280_656(yy[32], yy[33], single[4], double[4], neg[4], pp_4_41); - fullAdd_x FA_3280_784(int_3_41, int_2_41, pp_2_41, pp_3_41, pp_4_41); - r4bs r4bs_3280_1000(yy[30], yy[31], single[5], double[5], neg[5], pp_5_41); - r4bs r4bs_3280_1128(yy[28], yy[29], single[6], double[6], neg[6], pp_6_41); - r4bs r4bs_3280_1256(yy[26], yy[27], single[7], double[7], neg[7], pp_7_41); - fullAdd_x FA_3280_1384(int_5_41, int_4_41, pp_5_41, pp_6_41, pp_7_41); - r4bs r4bs_3280_1600(yy[24], yy[25], single[8], double[8], neg[8], pp_8_41); - r4bs r4bs_3280_1728(yy[22], yy[23], single[9], double[9], neg[9], pp_9_41); - r4bs r4bs_3280_1856(yy[20], yy[21], single[10], double[10], neg[10], pp_10_41); - fullAdd_x FA_3280_1984(int_7_41, int_6_41, pp_8_41, pp_9_41, pp_10_41); - r4bs r4bs_3280_2200(yy[18], yy[19], single[11], double[11], neg[11], pp_11_41); - r4bs r4bs_3280_2328(yy[16], yy[17], single[12], double[12], neg[12], pp_12_41); - r4bs r4bs_3280_2456(yy[14], yy[15], single[13], double[13], neg[13], pp_13_41); - fullAdd_x FA_3280_2584(int_9_41, int_8_41, pp_11_41, pp_12_41, pp_13_41); - r4bs r4bs_3280_2800(yy[12], yy[13], single[14], double[14], neg[14], pp_14_41); - r4bs r4bs_3280_2928(yy[10], yy[11], single[15], double[15], neg[15], pp_15_41); - r4bs r4bs_3280_3056(yy[8], yy[9], single[16], double[16], neg[16], pp_16_41); - fullAdd_x FA_3280_3184(int_11_41, int_10_41, pp_14_41, pp_15_41, pp_16_41); - r4bs r4bs_3280_3400(yy[6], yy[7], single[17], double[17], neg[17], pp_17_41); - r4bs r4bs_3280_3528(yy[4], yy[5], single[18], double[18], neg[18], pp_18_41); - r4bs r4bs_3280_3656(yy[2], yy[3], single[19], double[19], neg[19], pp_19_41); - fullAdd_x FA_3280_3784(int_13_41, int_12_41, pp_17_41, pp_18_41, pp_19_41); - r4bs r4bs_3280_4000(yy[0], yy[1], single[20], double[20], neg[20], pp_20_41); - fullAdd_x FA_3280_4128(int_15_41, int_14_41, pp_20_41, int_1_40, int_3_40); - fullAdd_x FA_3280_4344(int_17_41, int_16_41, int_5_40, int_7_40, int_9_40); - fullAdd_x FA_3280_4560(int_19_41, int_18_41, int_11_40, int_13_40, int_0_41); - fullAdd_x FA_3280_4776(int_21_41, int_20_41, int_15_40, int_17_40, int_19_40); - fullAdd_x FA_3280_4992(int_23_41, int_22_41, int_2_41, int_4_41, int_6_41); - fullAdd_x FA_3280_5208(int_25_41, int_24_41, int_8_41, int_10_41, int_12_41); - fullAdd_x FA_3280_5424(int_27_41, int_26_41, int_14_41, int_21_40, int_23_40); - fullAdd_x FA_3280_5640(int_29_41, int_28_41, int_25_40, int_16_41, int_18_41); - fullAdd_x FA_3280_5856(int_31_41, int_30_41, int_27_40, int_29_40, int_20_41); - fullAdd_x FA_3280_6072(int_33_41, int_32_41, int_22_41, int_24_41, int_31_40); - fullAdd_x FA_3280_6288(int_35_41, int_34_41, int_26_41, int_28_41, int_33_40); - fullAdd_x FA_3280_6504(int_37_41, int_36_41, int_30_41, int_32_41, int_35_40); - fullAdd_x FA_3280_6720(int_39_41, int_38_41, int_37_40, int_34_41, int_36_41); - assign Sum[41] = int_39_40; - assign Carry[41] = int_38_41; - - // Hardware for column 42 - - r4bs r4bs_3360_64(yy[41], yy[42], single[0], double[0], neg[0], pp_0_42); - halfAdd HA_3360_192(int_1_42, int_0_42, neg[21], pp_0_42); - r4bs r4bs_3360_272(yy[39], yy[40], single[1], double[1], neg[1], pp_1_42); - r4bs r4bs_3360_400(yy[37], yy[38], single[2], double[2], neg[2], pp_2_42); - r4bs r4bs_3360_528(yy[35], yy[36], single[3], double[3], neg[3], pp_3_42); - fullAdd_x FA_3360_656(int_3_42, int_2_42, pp_1_42, pp_2_42, pp_3_42); - r4bs r4bs_3360_872(yy[33], yy[34], single[4], double[4], neg[4], pp_4_42); - r4bs r4bs_3360_1000(yy[31], yy[32], single[5], double[5], neg[5], pp_5_42); - r4bs r4bs_3360_1128(yy[29], yy[30], single[6], double[6], neg[6], pp_6_42); - fullAdd_x FA_3360_1256(int_5_42, int_4_42, pp_4_42, pp_5_42, pp_6_42); - r4bs r4bs_3360_1472(yy[27], yy[28], single[7], double[7], neg[7], pp_7_42); - r4bs r4bs_3360_1600(yy[25], yy[26], single[8], double[8], neg[8], pp_8_42); - r4bs r4bs_3360_1728(yy[23], yy[24], single[9], double[9], neg[9], pp_9_42); - fullAdd_x FA_3360_1856(int_7_42, int_6_42, pp_7_42, pp_8_42, pp_9_42); - r4bs r4bs_3360_2072(yy[21], yy[22], single[10], double[10], neg[10], pp_10_42); - r4bs r4bs_3360_2200(yy[19], yy[20], single[11], double[11], neg[11], pp_11_42); - r4bs r4bs_3360_2328(yy[17], yy[18], single[12], double[12], neg[12], pp_12_42); - fullAdd_x FA_3360_2456(int_9_42, int_8_42, pp_10_42, pp_11_42, pp_12_42); - r4bs r4bs_3360_2672(yy[15], yy[16], single[13], double[13], neg[13], pp_13_42); - r4bs r4bs_3360_2800(yy[13], yy[14], single[14], double[14], neg[14], pp_14_42); - r4bs r4bs_3360_2928(yy[11], yy[12], single[15], double[15], neg[15], pp_15_42); - fullAdd_x FA_3360_3056(int_11_42, int_10_42, pp_13_42, pp_14_42, pp_15_42); - r4bs r4bs_3360_3272(yy[9], yy[10], single[16], double[16], neg[16], pp_16_42); - r4bs r4bs_3360_3400(yy[7], yy[8], single[17], double[17], neg[17], pp_17_42); - r4bs r4bs_3360_3528(yy[5], yy[6], single[18], double[18], neg[18], pp_18_42); - fullAdd_x FA_3360_3656(int_13_42, int_12_42, pp_16_42, pp_17_42, pp_18_42); - r4bs r4bs_3360_3872(yy[3], yy[4], single[19], double[19], neg[19], pp_19_42); - r4bs r4bs_3360_4000(yy[1], yy[2], single[20], double[20], neg[20], pp_20_42); - r4bs r4bs_3360_4128(gnd, yy[0], single[21], double[21], neg[21], pp_21_42); - fullAdd_x FA_3360_4256(int_15_42, int_14_42, pp_19_42, pp_20_42, pp_21_42); - fullAdd_x FA_3360_4472(int_17_42, int_16_42, int_1_41, int_3_41, int_5_41); - fullAdd_x FA_3360_4688(int_19_42, int_18_42, int_7_41, int_9_41, int_11_41); - fullAdd_x FA_3360_4904(int_21_42, int_20_42, int_13_41, int_0_42, int_15_41); - fullAdd_x FA_3360_5120(int_23_42, int_22_42, int_17_41, int_19_41, int_2_42); - fullAdd_x FA_3360_5336(int_25_42, int_24_42, int_4_42, int_6_42, int_8_42); - fullAdd_x FA_3360_5552(int_27_42, int_26_42, int_10_42, int_12_42, int_14_42); - fullAdd_x FA_3360_5768(int_29_42, int_28_42, int_21_41, int_23_41, int_25_41); - fullAdd_x FA_3360_5984(int_31_42, int_30_42, int_16_42, int_18_42, int_20_42); - fullAdd_x FA_3360_6200(int_33_42, int_32_42, int_27_41, int_29_41, int_22_42); - fullAdd_x FA_3360_6416(int_35_42, int_34_42, int_24_42, int_26_42, int_31_41); - fullAdd_x FA_3360_6632(int_37_42, int_36_42, int_28_42, int_30_42, int_33_41); - fullAdd_x FA_3360_6848(int_39_42, int_38_42, int_32_42, int_34_42, int_35_41); - fullAdd_x FA_3360_7064(int_41_42, int_40_42, int_36_42, int_37_41, int_38_42); - assign Sum[42] = int_39_41; - assign Carry[42] = int_40_42; - - // Hardware for column 43 - - r4bs r4bs_3440_64(yy[42], yy[43], single[0], double[0], neg[0], pp_0_43); - r4bs r4bs_3440_192(yy[40], yy[41], single[1], double[1], neg[1], pp_1_43); - halfAdd HA_3440_320(int_1_43, int_0_43, pp_0_43, pp_1_43); - r4bs r4bs_3440_400(yy[38], yy[39], single[2], double[2], neg[2], pp_2_43); - r4bs r4bs_3440_528(yy[36], yy[37], single[3], double[3], neg[3], pp_3_43); - r4bs r4bs_3440_656(yy[34], yy[35], single[4], double[4], neg[4], pp_4_43); - fullAdd_x FA_3440_784(int_3_43, int_2_43, pp_2_43, pp_3_43, pp_4_43); - r4bs r4bs_3440_1000(yy[32], yy[33], single[5], double[5], neg[5], pp_5_43); - r4bs r4bs_3440_1128(yy[30], yy[31], single[6], double[6], neg[6], pp_6_43); - r4bs r4bs_3440_1256(yy[28], yy[29], single[7], double[7], neg[7], pp_7_43); - fullAdd_x FA_3440_1384(int_5_43, int_4_43, pp_5_43, pp_6_43, pp_7_43); - r4bs r4bs_3440_1600(yy[26], yy[27], single[8], double[8], neg[8], pp_8_43); - r4bs r4bs_3440_1728(yy[24], yy[25], single[9], double[9], neg[9], pp_9_43); - r4bs r4bs_3440_1856(yy[22], yy[23], single[10], double[10], neg[10], pp_10_43); - fullAdd_x FA_3440_1984(int_7_43, int_6_43, pp_8_43, pp_9_43, pp_10_43); - r4bs r4bs_3440_2200(yy[20], yy[21], single[11], double[11], neg[11], pp_11_43); - r4bs r4bs_3440_2328(yy[18], yy[19], single[12], double[12], neg[12], pp_12_43); - r4bs r4bs_3440_2456(yy[16], yy[17], single[13], double[13], neg[13], pp_13_43); - fullAdd_x FA_3440_2584(int_9_43, int_8_43, pp_11_43, pp_12_43, pp_13_43); - r4bs r4bs_3440_2800(yy[14], yy[15], single[14], double[14], neg[14], pp_14_43); - r4bs r4bs_3440_2928(yy[12], yy[13], single[15], double[15], neg[15], pp_15_43); - r4bs r4bs_3440_3056(yy[10], yy[11], single[16], double[16], neg[16], pp_16_43); - fullAdd_x FA_3440_3184(int_11_43, int_10_43, pp_14_43, pp_15_43, pp_16_43); - r4bs r4bs_3440_3400(yy[8], yy[9], single[17], double[17], neg[17], pp_17_43); - r4bs r4bs_3440_3528(yy[6], yy[7], single[18], double[18], neg[18], pp_18_43); - r4bs r4bs_3440_3656(yy[4], yy[5], single[19], double[19], neg[19], pp_19_43); - fullAdd_x FA_3440_3784(int_13_43, int_12_43, pp_17_43, pp_18_43, pp_19_43); - r4bs r4bs_3440_4000(yy[2], yy[3], single[20], double[20], neg[20], pp_20_43); - r4bs r4bs_3440_4128(yy[0], yy[1], single[21], double[21], neg[21], pp_21_43); - fullAdd_x FA_3440_4256(int_15_43, int_14_43, pp_20_43, pp_21_43, int_1_42); - fullAdd_x FA_3440_4472(int_17_43, int_16_43, int_3_42, int_5_42, int_7_42); - fullAdd_x FA_3440_4688(int_19_43, int_18_43, int_9_42, int_11_42, int_13_42); - fullAdd_x FA_3440_4904(int_21_43, int_20_43, int_15_42, int_0_43, int_17_42); - fullAdd_x FA_3440_5120(int_23_43, int_22_43, int_19_42, int_2_43, int_4_43); - fullAdd_x FA_3440_5336(int_25_43, int_24_43, int_6_43, int_8_43, int_10_43); - fullAdd_x FA_3440_5552(int_27_43, int_26_43, int_12_43, int_14_43, int_21_42); - fullAdd_x FA_3440_5768(int_29_43, int_28_43, int_23_42, int_25_42, int_27_42); - fullAdd_x FA_3440_5984(int_31_43, int_30_43, int_16_43, int_18_43, int_20_43); - fullAdd_x FA_3440_6200(int_33_43, int_32_43, int_29_42, int_31_42, int_22_43); - fullAdd_x FA_3440_6416(int_35_43, int_34_43, int_24_43, int_26_43, int_33_42); - fullAdd_x FA_3440_6632(int_37_43, int_36_43, int_28_43, int_30_43, int_35_42); - fullAdd_x FA_3440_6848(int_39_43, int_38_43, int_32_43, int_34_43, int_37_42); - fullAdd_x FA_3440_7064(int_41_43, int_40_43, int_36_43, int_39_42, int_38_43); - assign Sum[43] = int_41_42; - assign Carry[43] = int_40_43; - - // Hardware for column 44 - - r4bs r4bs_3520_64(yy[43], yy[44], single[0], double[0], neg[0], pp_0_44); - halfAdd HA_3520_192(int_1_44, int_0_44, neg[22], pp_0_44); - r4bs r4bs_3520_272(yy[41], yy[42], single[1], double[1], neg[1], pp_1_44); - r4bs r4bs_3520_400(yy[39], yy[40], single[2], double[2], neg[2], pp_2_44); - r4bs r4bs_3520_528(yy[37], yy[38], single[3], double[3], neg[3], pp_3_44); - fullAdd_x FA_3520_656(int_3_44, int_2_44, pp_1_44, pp_2_44, pp_3_44); - r4bs r4bs_3520_872(yy[35], yy[36], single[4], double[4], neg[4], pp_4_44); - r4bs r4bs_3520_1000(yy[33], yy[34], single[5], double[5], neg[5], pp_5_44); - r4bs r4bs_3520_1128(yy[31], yy[32], single[6], double[6], neg[6], pp_6_44); - fullAdd_x FA_3520_1256(int_5_44, int_4_44, pp_4_44, pp_5_44, pp_6_44); - r4bs r4bs_3520_1472(yy[29], yy[30], single[7], double[7], neg[7], pp_7_44); - r4bs r4bs_3520_1600(yy[27], yy[28], single[8], double[8], neg[8], pp_8_44); - r4bs r4bs_3520_1728(yy[25], yy[26], single[9], double[9], neg[9], pp_9_44); - fullAdd_x FA_3520_1856(int_7_44, int_6_44, pp_7_44, pp_8_44, pp_9_44); - r4bs r4bs_3520_2072(yy[23], yy[24], single[10], double[10], neg[10], pp_10_44); - r4bs r4bs_3520_2200(yy[21], yy[22], single[11], double[11], neg[11], pp_11_44); - r4bs r4bs_3520_2328(yy[19], yy[20], single[12], double[12], neg[12], pp_12_44); - fullAdd_x FA_3520_2456(int_9_44, int_8_44, pp_10_44, pp_11_44, pp_12_44); - r4bs r4bs_3520_2672(yy[17], yy[18], single[13], double[13], neg[13], pp_13_44); - r4bs r4bs_3520_2800(yy[15], yy[16], single[14], double[14], neg[14], pp_14_44); - r4bs r4bs_3520_2928(yy[13], yy[14], single[15], double[15], neg[15], pp_15_44); - fullAdd_x FA_3520_3056(int_11_44, int_10_44, pp_13_44, pp_14_44, pp_15_44); - r4bs r4bs_3520_3272(yy[11], yy[12], single[16], double[16], neg[16], pp_16_44); - r4bs r4bs_3520_3400(yy[9], yy[10], single[17], double[17], neg[17], pp_17_44); - r4bs r4bs_3520_3528(yy[7], yy[8], single[18], double[18], neg[18], pp_18_44); - fullAdd_x FA_3520_3656(int_13_44, int_12_44, pp_16_44, pp_17_44, pp_18_44); - r4bs r4bs_3520_3872(yy[5], yy[6], single[19], double[19], neg[19], pp_19_44); - r4bs r4bs_3520_4000(yy[3], yy[4], single[20], double[20], neg[20], pp_20_44); - r4bs r4bs_3520_4128(yy[1], yy[2], single[21], double[21], neg[21], pp_21_44); - fullAdd_x FA_3520_4256(int_15_44, int_14_44, pp_19_44, pp_20_44, pp_21_44); - r4bs r4bs_3520_4472(gnd, yy[0], single[22], double[22], neg[22], pp_22_44); - fullAdd_x FA_3520_4600(int_17_44, int_16_44, pp_22_44, int_1_43, int_3_43); - fullAdd_x FA_3520_4816(int_19_44, int_18_44, int_5_43, int_7_43, int_9_43); - fullAdd_x FA_3520_5032(int_21_44, int_20_44, int_11_43, int_13_43, int_0_44); - fullAdd_x FA_3520_5248(int_23_44, int_22_44, int_15_43, int_17_43, int_19_43); - fullAdd_x FA_3520_5464(int_25_44, int_24_44, int_2_44, int_4_44, int_6_44); - fullAdd_x FA_3520_5680(int_27_44, int_26_44, int_8_44, int_10_44, int_12_44); - fullAdd_x FA_3520_5896(int_29_44, int_28_44, int_14_44, int_16_44, int_21_43); - fullAdd_x FA_3520_6112(int_31_44, int_30_44, int_23_43, int_25_43, int_18_44); - fullAdd_x FA_3520_6328(int_33_44, int_32_44, int_20_44, int_27_43, int_29_43); - fullAdd_x FA_3520_6544(int_35_44, int_34_44, int_31_43, int_22_44, int_24_44); - fullAdd_x FA_3520_6760(int_37_44, int_36_44, int_26_44, int_28_44, int_33_43); - fullAdd_x FA_3520_6976(int_39_44, int_38_44, int_30_44, int_35_43, int_32_44); - fullAdd_x FA_3520_7192(int_41_44, int_40_44, int_34_44, int_36_44, int_37_43); - fullAdd_x FA_3520_7408(int_43_44, int_42_44, int_39_43, int_38_44, int_40_44); - assign Sum[44] = int_41_43; - assign Carry[44] = int_42_44; - - // Hardware for column 45 - - r4bs r4bs_3600_64(yy[44], yy[45], single[0], double[0], neg[0], pp_0_45); - r4bs r4bs_3600_192(yy[42], yy[43], single[1], double[1], neg[1], pp_1_45); - halfAdd HA_3600_320(int_1_45, int_0_45, pp_0_45, pp_1_45); - r4bs r4bs_3600_400(yy[40], yy[41], single[2], double[2], neg[2], pp_2_45); - r4bs r4bs_3600_528(yy[38], yy[39], single[3], double[3], neg[3], pp_3_45); - r4bs r4bs_3600_656(yy[36], yy[37], single[4], double[4], neg[4], pp_4_45); - fullAdd_x FA_3600_784(int_3_45, int_2_45, pp_2_45, pp_3_45, pp_4_45); - r4bs r4bs_3600_1000(yy[34], yy[35], single[5], double[5], neg[5], pp_5_45); - r4bs r4bs_3600_1128(yy[32], yy[33], single[6], double[6], neg[6], pp_6_45); - r4bs r4bs_3600_1256(yy[30], yy[31], single[7], double[7], neg[7], pp_7_45); - fullAdd_x FA_3600_1384(int_5_45, int_4_45, pp_5_45, pp_6_45, pp_7_45); - r4bs r4bs_3600_1600(yy[28], yy[29], single[8], double[8], neg[8], pp_8_45); - r4bs r4bs_3600_1728(yy[26], yy[27], single[9], double[9], neg[9], pp_9_45); - r4bs r4bs_3600_1856(yy[24], yy[25], single[10], double[10], neg[10], pp_10_45); - fullAdd_x FA_3600_1984(int_7_45, int_6_45, pp_8_45, pp_9_45, pp_10_45); - r4bs r4bs_3600_2200(yy[22], yy[23], single[11], double[11], neg[11], pp_11_45); - r4bs r4bs_3600_2328(yy[20], yy[21], single[12], double[12], neg[12], pp_12_45); - r4bs r4bs_3600_2456(yy[18], yy[19], single[13], double[13], neg[13], pp_13_45); - fullAdd_x FA_3600_2584(int_9_45, int_8_45, pp_11_45, pp_12_45, pp_13_45); - r4bs r4bs_3600_2800(yy[16], yy[17], single[14], double[14], neg[14], pp_14_45); - r4bs r4bs_3600_2928(yy[14], yy[15], single[15], double[15], neg[15], pp_15_45); - r4bs r4bs_3600_3056(yy[12], yy[13], single[16], double[16], neg[16], pp_16_45); - fullAdd_x FA_3600_3184(int_11_45, int_10_45, pp_14_45, pp_15_45, pp_16_45); - r4bs r4bs_3600_3400(yy[10], yy[11], single[17], double[17], neg[17], pp_17_45); - r4bs r4bs_3600_3528(yy[8], yy[9], single[18], double[18], neg[18], pp_18_45); - r4bs r4bs_3600_3656(yy[6], yy[7], single[19], double[19], neg[19], pp_19_45); - fullAdd_x FA_3600_3784(int_13_45, int_12_45, pp_17_45, pp_18_45, pp_19_45); - r4bs r4bs_3600_4000(yy[4], yy[5], single[20], double[20], neg[20], pp_20_45); - r4bs r4bs_3600_4128(yy[2], yy[3], single[21], double[21], neg[21], pp_21_45); - r4bs r4bs_3600_4256(yy[0], yy[1], single[22], double[22], neg[22], pp_22_45); - fullAdd_x FA_3600_4384(int_15_45, int_14_45, pp_20_45, pp_21_45, pp_22_45); - fullAdd_x FA_3600_4600(int_17_45, int_16_45, int_1_44, int_3_44, int_5_44); - fullAdd_x FA_3600_4816(int_19_45, int_18_45, int_7_44, int_9_44, int_11_44); - fullAdd_x FA_3600_5032(int_21_45, int_20_45, int_13_44, int_15_44, int_0_45); - fullAdd_x FA_3600_5248(int_23_45, int_22_45, int_17_44, int_19_44, int_21_44); - fullAdd_x FA_3600_5464(int_25_45, int_24_45, int_2_45, int_4_45, int_6_45); - fullAdd_x FA_3600_5680(int_27_45, int_26_45, int_8_45, int_10_45, int_12_45); - fullAdd_x FA_3600_5896(int_29_45, int_28_45, int_14_45, int_23_44, int_25_44); - fullAdd_x FA_3600_6112(int_31_45, int_30_45, int_27_44, int_16_45, int_18_45); - fullAdd_x FA_3600_6328(int_33_45, int_32_45, int_20_45, int_29_44, int_31_44); - fullAdd_x FA_3600_6544(int_35_45, int_34_45, int_22_45, int_24_45, int_26_45); - fullAdd_x FA_3600_6760(int_37_45, int_36_45, int_33_44, int_35_44, int_28_45); - fullAdd_x FA_3600_6976(int_39_45, int_38_45, int_30_45, int_37_44, int_32_45); - fullAdd_x FA_3600_7192(int_41_45, int_40_45, int_34_45, int_39_44, int_36_45); - fullAdd_x FA_3600_7408(int_43_45, int_42_45, int_41_44, int_38_45, int_40_45); - assign Sum[45] = int_43_44; - assign Carry[45] = int_42_45; - - // Hardware for column 46 - - r4bs r4bs_3680_64(yy[45], yy[46], single[0], double[0], neg[0], pp_0_46); - halfAdd HA_3680_192(int_1_46, int_0_46, neg[23], pp_0_46); - r4bs r4bs_3680_272(yy[43], yy[44], single[1], double[1], neg[1], pp_1_46); - r4bs r4bs_3680_400(yy[41], yy[42], single[2], double[2], neg[2], pp_2_46); - r4bs r4bs_3680_528(yy[39], yy[40], single[3], double[3], neg[3], pp_3_46); - fullAdd_x FA_3680_656(int_3_46, int_2_46, pp_1_46, pp_2_46, pp_3_46); - r4bs r4bs_3680_872(yy[37], yy[38], single[4], double[4], neg[4], pp_4_46); - r4bs r4bs_3680_1000(yy[35], yy[36], single[5], double[5], neg[5], pp_5_46); - r4bs r4bs_3680_1128(yy[33], yy[34], single[6], double[6], neg[6], pp_6_46); - fullAdd_x FA_3680_1256(int_5_46, int_4_46, pp_4_46, pp_5_46, pp_6_46); - r4bs r4bs_3680_1472(yy[31], yy[32], single[7], double[7], neg[7], pp_7_46); - r4bs r4bs_3680_1600(yy[29], yy[30], single[8], double[8], neg[8], pp_8_46); - r4bs r4bs_3680_1728(yy[27], yy[28], single[9], double[9], neg[9], pp_9_46); - fullAdd_x FA_3680_1856(int_7_46, int_6_46, pp_7_46, pp_8_46, pp_9_46); - r4bs r4bs_3680_2072(yy[25], yy[26], single[10], double[10], neg[10], pp_10_46); - r4bs r4bs_3680_2200(yy[23], yy[24], single[11], double[11], neg[11], pp_11_46); - r4bs r4bs_3680_2328(yy[21], yy[22], single[12], double[12], neg[12], pp_12_46); - fullAdd_x FA_3680_2456(int_9_46, int_8_46, pp_10_46, pp_11_46, pp_12_46); - r4bs r4bs_3680_2672(yy[19], yy[20], single[13], double[13], neg[13], pp_13_46); - r4bs r4bs_3680_2800(yy[17], yy[18], single[14], double[14], neg[14], pp_14_46); - r4bs r4bs_3680_2928(yy[15], yy[16], single[15], double[15], neg[15], pp_15_46); - fullAdd_x FA_3680_3056(int_11_46, int_10_46, pp_13_46, pp_14_46, pp_15_46); - r4bs r4bs_3680_3272(yy[13], yy[14], single[16], double[16], neg[16], pp_16_46); - r4bs r4bs_3680_3400(yy[11], yy[12], single[17], double[17], neg[17], pp_17_46); - r4bs r4bs_3680_3528(yy[9], yy[10], single[18], double[18], neg[18], pp_18_46); - fullAdd_x FA_3680_3656(int_13_46, int_12_46, pp_16_46, pp_17_46, pp_18_46); - r4bs r4bs_3680_3872(yy[7], yy[8], single[19], double[19], neg[19], pp_19_46); - r4bs r4bs_3680_4000(yy[5], yy[6], single[20], double[20], neg[20], pp_20_46); - r4bs r4bs_3680_4128(yy[3], yy[4], single[21], double[21], neg[21], pp_21_46); - fullAdd_x FA_3680_4256(int_15_46, int_14_46, pp_19_46, pp_20_46, pp_21_46); - r4bs r4bs_3680_4472(yy[1], yy[2], single[22], double[22], neg[22], pp_22_46); - r4bs r4bs_3680_4600(gnd, yy[0], single[23], double[23], neg[23], pp_23_46); - fullAdd_x FA_3680_4728(int_17_46, int_16_46, pp_22_46, pp_23_46, int_1_45); - fullAdd_x FA_3680_4944(int_19_46, int_18_46, int_3_45, int_5_45, int_7_45); - fullAdd_x FA_3680_5160(int_21_46, int_20_46, int_9_45, int_11_45, int_13_45); - fullAdd_x FA_3680_5376(int_23_46, int_22_46, int_15_45, int_0_46, int_17_45); - fullAdd_x FA_3680_5592(int_25_46, int_24_46, int_19_45, int_21_45, int_2_46); - fullAdd_x FA_3680_5808(int_27_46, int_26_46, int_4_46, int_6_46, int_8_46); - fullAdd_x FA_3680_6024(int_29_46, int_28_46, int_10_46, int_12_46, int_14_46); - fullAdd_x FA_3680_6240(int_31_46, int_30_46, int_16_46, int_23_45, int_25_45); - fullAdd_x FA_3680_6456(int_33_46, int_32_46, int_27_45, int_18_46, int_20_46); - fullAdd_x FA_3680_6672(int_35_46, int_34_46, int_22_46, int_29_45, int_31_45); - fullAdd_x FA_3680_6888(int_37_46, int_36_46, int_24_46, int_26_46, int_28_46); - fullAdd_x FA_3680_7104(int_39_46, int_38_46, int_33_45, int_35_45, int_30_46); - fullAdd_x FA_3680_7320(int_41_46, int_40_46, int_32_46, int_37_45, int_34_46); - fullAdd_x FA_3680_7536(int_43_46, int_42_46, int_36_46, int_39_45, int_38_46); - fullAdd_x FA_3680_7752(int_45_46, int_44_46, int_41_45, int_40_46, int_42_46); - assign Sum[46] = int_43_45; - assign Carry[46] = int_44_46; - - // Hardware for column 47 - - r4bs r4bs_3760_64(yy[46], yy[47], single[0], double[0], neg[0], pp_0_47); - r4bs r4bs_3760_192(yy[44], yy[45], single[1], double[1], neg[1], pp_1_47); - halfAdd HA_3760_320(int_1_47, int_0_47, pp_0_47, pp_1_47); - r4bs r4bs_3760_400(yy[42], yy[43], single[2], double[2], neg[2], pp_2_47); - r4bs r4bs_3760_528(yy[40], yy[41], single[3], double[3], neg[3], pp_3_47); - r4bs r4bs_3760_656(yy[38], yy[39], single[4], double[4], neg[4], pp_4_47); - fullAdd_x FA_3760_784(int_3_47, int_2_47, pp_2_47, pp_3_47, pp_4_47); - r4bs r4bs_3760_1000(yy[36], yy[37], single[5], double[5], neg[5], pp_5_47); - r4bs r4bs_3760_1128(yy[34], yy[35], single[6], double[6], neg[6], pp_6_47); - r4bs r4bs_3760_1256(yy[32], yy[33], single[7], double[7], neg[7], pp_7_47); - fullAdd_x FA_3760_1384(int_5_47, int_4_47, pp_5_47, pp_6_47, pp_7_47); - r4bs r4bs_3760_1600(yy[30], yy[31], single[8], double[8], neg[8], pp_8_47); - r4bs r4bs_3760_1728(yy[28], yy[29], single[9], double[9], neg[9], pp_9_47); - r4bs r4bs_3760_1856(yy[26], yy[27], single[10], double[10], neg[10], pp_10_47); - fullAdd_x FA_3760_1984(int_7_47, int_6_47, pp_8_47, pp_9_47, pp_10_47); - r4bs r4bs_3760_2200(yy[24], yy[25], single[11], double[11], neg[11], pp_11_47); - r4bs r4bs_3760_2328(yy[22], yy[23], single[12], double[12], neg[12], pp_12_47); - r4bs r4bs_3760_2456(yy[20], yy[21], single[13], double[13], neg[13], pp_13_47); - fullAdd_x FA_3760_2584(int_9_47, int_8_47, pp_11_47, pp_12_47, pp_13_47); - r4bs r4bs_3760_2800(yy[18], yy[19], single[14], double[14], neg[14], pp_14_47); - r4bs r4bs_3760_2928(yy[16], yy[17], single[15], double[15], neg[15], pp_15_47); - r4bs r4bs_3760_3056(yy[14], yy[15], single[16], double[16], neg[16], pp_16_47); - fullAdd_x FA_3760_3184(int_11_47, int_10_47, pp_14_47, pp_15_47, pp_16_47); - r4bs r4bs_3760_3400(yy[12], yy[13], single[17], double[17], neg[17], pp_17_47); - r4bs r4bs_3760_3528(yy[10], yy[11], single[18], double[18], neg[18], pp_18_47); - r4bs r4bs_3760_3656(yy[8], yy[9], single[19], double[19], neg[19], pp_19_47); - fullAdd_x FA_3760_3784(int_13_47, int_12_47, pp_17_47, pp_18_47, pp_19_47); - r4bs r4bs_3760_4000(yy[6], yy[7], single[20], double[20], neg[20], pp_20_47); - r4bs r4bs_3760_4128(yy[4], yy[5], single[21], double[21], neg[21], pp_21_47); - r4bs r4bs_3760_4256(yy[2], yy[3], single[22], double[22], neg[22], pp_22_47); - fullAdd_x FA_3760_4384(int_15_47, int_14_47, pp_20_47, pp_21_47, pp_22_47); - r4bs r4bs_3760_4600(yy[0], yy[1], single[23], double[23], neg[23], pp_23_47); - fullAdd_x FA_3760_4728(int_17_47, int_16_47, pp_23_47, int_1_46, int_3_46); - fullAdd_x FA_3760_4944(int_19_47, int_18_47, int_5_46, int_7_46, int_9_46); - fullAdd_x FA_3760_5160(int_21_47, int_20_47, int_11_46, int_13_46, int_15_46); - fullAdd_x FA_3760_5376(int_23_47, int_22_47, int_0_47, int_17_46, int_19_46); - fullAdd_x FA_3760_5592(int_25_47, int_24_47, int_21_46, int_2_47, int_4_47); - fullAdd_x FA_3760_5808(int_27_47, int_26_47, int_6_47, int_8_47, int_10_47); - fullAdd_x FA_3760_6024(int_29_47, int_28_47, int_12_47, int_14_47, int_16_47); - fullAdd_x FA_3760_6240(int_31_47, int_30_47, int_23_46, int_25_46, int_27_46); - fullAdd_x FA_3760_6456(int_33_47, int_32_47, int_29_46, int_18_47, int_20_47); - fullAdd_x FA_3760_6672(int_35_47, int_34_47, int_22_47, int_31_46, int_33_46); - fullAdd_x FA_3760_6888(int_37_47, int_36_47, int_24_47, int_26_47, int_28_47); - fullAdd_x FA_3760_7104(int_39_47, int_38_47, int_35_46, int_37_46, int_30_47); - fullAdd_x FA_3760_7320(int_41_47, int_40_47, int_32_47, int_39_46, int_34_47); - fullAdd_x FA_3760_7536(int_43_47, int_42_47, int_36_47, int_41_46, int_38_47); - fullAdd_x FA_3760_7752(int_45_47, int_44_47, int_43_46, int_40_47, int_42_47); - assign Sum[47] = int_45_46; - assign Carry[47] = int_44_47; - - // Hardware for column 48 - - r4bs r4bs_3840_64(yy[47], yy[48], single[0], double[0], neg[0], pp_0_48); - halfAdd HA_3840_192(int_1_48, int_0_48, neg[24], pp_0_48); - r4bs r4bs_3840_272(yy[45], yy[46], single[1], double[1], neg[1], pp_1_48); - r4bs r4bs_3840_400(yy[43], yy[44], single[2], double[2], neg[2], pp_2_48); - r4bs r4bs_3840_528(yy[41], yy[42], single[3], double[3], neg[3], pp_3_48); - fullAdd_x FA_3840_656(int_3_48, int_2_48, pp_1_48, pp_2_48, pp_3_48); - r4bs r4bs_3840_872(yy[39], yy[40], single[4], double[4], neg[4], pp_4_48); - r4bs r4bs_3840_1000(yy[37], yy[38], single[5], double[5], neg[5], pp_5_48); - r4bs r4bs_3840_1128(yy[35], yy[36], single[6], double[6], neg[6], pp_6_48); - fullAdd_x FA_3840_1256(int_5_48, int_4_48, pp_4_48, pp_5_48, pp_6_48); - r4bs r4bs_3840_1472(yy[33], yy[34], single[7], double[7], neg[7], pp_7_48); - r4bs r4bs_3840_1600(yy[31], yy[32], single[8], double[8], neg[8], pp_8_48); - r4bs r4bs_3840_1728(yy[29], yy[30], single[9], double[9], neg[9], pp_9_48); - fullAdd_x FA_3840_1856(int_7_48, int_6_48, pp_7_48, pp_8_48, pp_9_48); - r4bs r4bs_3840_2072(yy[27], yy[28], single[10], double[10], neg[10], pp_10_48); - r4bs r4bs_3840_2200(yy[25], yy[26], single[11], double[11], neg[11], pp_11_48); - r4bs r4bs_3840_2328(yy[23], yy[24], single[12], double[12], neg[12], pp_12_48); - fullAdd_x FA_3840_2456(int_9_48, int_8_48, pp_10_48, pp_11_48, pp_12_48); - r4bs r4bs_3840_2672(yy[21], yy[22], single[13], double[13], neg[13], pp_13_48); - r4bs r4bs_3840_2800(yy[19], yy[20], single[14], double[14], neg[14], pp_14_48); - r4bs r4bs_3840_2928(yy[17], yy[18], single[15], double[15], neg[15], pp_15_48); - fullAdd_x FA_3840_3056(int_11_48, int_10_48, pp_13_48, pp_14_48, pp_15_48); - r4bs r4bs_3840_3272(yy[15], yy[16], single[16], double[16], neg[16], pp_16_48); - r4bs r4bs_3840_3400(yy[13], yy[14], single[17], double[17], neg[17], pp_17_48); - r4bs r4bs_3840_3528(yy[11], yy[12], single[18], double[18], neg[18], pp_18_48); - fullAdd_x FA_3840_3656(int_13_48, int_12_48, pp_16_48, pp_17_48, pp_18_48); - r4bs r4bs_3840_3872(yy[9], yy[10], single[19], double[19], neg[19], pp_19_48); - r4bs r4bs_3840_4000(yy[7], yy[8], single[20], double[20], neg[20], pp_20_48); - r4bs r4bs_3840_4128(yy[5], yy[6], single[21], double[21], neg[21], pp_21_48); - fullAdd_x FA_3840_4256(int_15_48, int_14_48, pp_19_48, pp_20_48, pp_21_48); - r4bs r4bs_3840_4472(yy[3], yy[4], single[22], double[22], neg[22], pp_22_48); - r4bs r4bs_3840_4600(yy[1], yy[2], single[23], double[23], neg[23], pp_23_48); - r4bs r4bs_3840_4728(gnd, yy[0], single[24], double[24], neg[24], pp_24_48); - fullAdd_x FA_3840_4856(int_17_48, int_16_48, pp_22_48, pp_23_48, pp_24_48); - fullAdd_x FA_3840_5072(int_19_48, int_18_48, int_1_47, int_3_47, int_5_47); - fullAdd_x FA_3840_5288(int_21_48, int_20_48, int_7_47, int_9_47, int_11_47); - fullAdd_x FA_3840_5504(int_23_48, int_22_48, int_13_47, int_15_47, int_0_48); - fullAdd_x FA_3840_5720(int_25_48, int_24_48, int_17_47, int_19_47, int_21_47); - fullAdd_x FA_3840_5936(int_27_48, int_26_48, int_2_48, int_4_48, int_6_48); - fullAdd_x FA_3840_6152(int_29_48, int_28_48, int_8_48, int_10_48, int_12_48); - fullAdd_x FA_3840_6368(int_31_48, int_30_48, int_14_48, int_16_48, int_23_47); - fullAdd_x FA_3840_6584(int_33_48, int_32_48, int_25_47, int_27_47, int_18_48); - fullAdd_x FA_3840_6800(int_35_48, int_34_48, int_20_48, int_22_48, int_29_47); - fullAdd_x FA_3840_7016(int_37_48, int_36_48, int_31_47, int_33_47, int_24_48); - fullAdd_x FA_3840_7232(int_39_48, int_38_48, int_26_48, int_28_48, int_30_48); - fullAdd_x FA_3840_7448(int_41_48, int_40_48, int_35_47, int_37_47, int_32_48); - fullAdd_x FA_3840_7664(int_43_48, int_42_48, int_34_48, int_39_47, int_36_48); - fullAdd_x FA_3840_7880(int_45_48, int_44_48, int_38_48, int_41_47, int_40_48); - fullAdd_x FA_3840_8096(int_47_48, int_46_48, int_43_47, int_42_48, int_44_48); - assign Sum[48] = int_45_47; - assign Carry[48] = int_46_48; - - // Hardware for column 49 - - r4bs r4bs_3920_64(yy[48], yy[49], single[0], double[0], neg[0], pp_0_49); - r4bs r4bs_3920_192(yy[46], yy[47], single[1], double[1], neg[1], pp_1_49); - halfAdd HA_3920_320(int_1_49, int_0_49, pp_0_49, pp_1_49); - r4bs r4bs_3920_400(yy[44], yy[45], single[2], double[2], neg[2], pp_2_49); - r4bs r4bs_3920_528(yy[42], yy[43], single[3], double[3], neg[3], pp_3_49); - r4bs r4bs_3920_656(yy[40], yy[41], single[4], double[4], neg[4], pp_4_49); - fullAdd_x FA_3920_784(int_3_49, int_2_49, pp_2_49, pp_3_49, pp_4_49); - r4bs r4bs_3920_1000(yy[38], yy[39], single[5], double[5], neg[5], pp_5_49); - r4bs r4bs_3920_1128(yy[36], yy[37], single[6], double[6], neg[6], pp_6_49); - r4bs r4bs_3920_1256(yy[34], yy[35], single[7], double[7], neg[7], pp_7_49); - fullAdd_x FA_3920_1384(int_5_49, int_4_49, pp_5_49, pp_6_49, pp_7_49); - r4bs r4bs_3920_1600(yy[32], yy[33], single[8], double[8], neg[8], pp_8_49); - r4bs r4bs_3920_1728(yy[30], yy[31], single[9], double[9], neg[9], pp_9_49); - r4bs r4bs_3920_1856(yy[28], yy[29], single[10], double[10], neg[10], pp_10_49); - fullAdd_x FA_3920_1984(int_7_49, int_6_49, pp_8_49, pp_9_49, pp_10_49); - r4bs r4bs_3920_2200(yy[26], yy[27], single[11], double[11], neg[11], pp_11_49); - r4bs r4bs_3920_2328(yy[24], yy[25], single[12], double[12], neg[12], pp_12_49); - r4bs r4bs_3920_2456(yy[22], yy[23], single[13], double[13], neg[13], pp_13_49); - fullAdd_x FA_3920_2584(int_9_49, int_8_49, pp_11_49, pp_12_49, pp_13_49); - r4bs r4bs_3920_2800(yy[20], yy[21], single[14], double[14], neg[14], pp_14_49); - r4bs r4bs_3920_2928(yy[18], yy[19], single[15], double[15], neg[15], pp_15_49); - r4bs r4bs_3920_3056(yy[16], yy[17], single[16], double[16], neg[16], pp_16_49); - fullAdd_x FA_3920_3184(int_11_49, int_10_49, pp_14_49, pp_15_49, pp_16_49); - r4bs r4bs_3920_3400(yy[14], yy[15], single[17], double[17], neg[17], pp_17_49); - r4bs r4bs_3920_3528(yy[12], yy[13], single[18], double[18], neg[18], pp_18_49); - r4bs r4bs_3920_3656(yy[10], yy[11], single[19], double[19], neg[19], pp_19_49); - fullAdd_x FA_3920_3784(int_13_49, int_12_49, pp_17_49, pp_18_49, pp_19_49); - r4bs r4bs_3920_4000(yy[8], yy[9], single[20], double[20], neg[20], pp_20_49); - r4bs r4bs_3920_4128(yy[6], yy[7], single[21], double[21], neg[21], pp_21_49); - r4bs r4bs_3920_4256(yy[4], yy[5], single[22], double[22], neg[22], pp_22_49); - fullAdd_x FA_3920_4384(int_15_49, int_14_49, pp_20_49, pp_21_49, pp_22_49); - r4bs r4bs_3920_4600(yy[2], yy[3], single[23], double[23], neg[23], pp_23_49); - r4bs r4bs_3920_4728(yy[0], yy[1], single[24], double[24], neg[24], pp_24_49); - fullAdd_x FA_3920_4856(int_17_49, int_16_49, pp_23_49, pp_24_49, int_1_48); - fullAdd_x FA_3920_5072(int_19_49, int_18_49, int_3_48, int_5_48, int_7_48); - fullAdd_x FA_3920_5288(int_21_49, int_20_49, int_9_48, int_11_48, int_13_48); - fullAdd_x FA_3920_5504(int_23_49, int_22_49, int_15_48, int_17_48, int_0_49); - fullAdd_x FA_3920_5720(int_25_49, int_24_49, int_19_48, int_21_48, int_23_48); - fullAdd_x FA_3920_5936(int_27_49, int_26_49, int_2_49, int_4_49, int_6_49); - fullAdd_x FA_3920_6152(int_29_49, int_28_49, int_8_49, int_10_49, int_12_49); - fullAdd_x FA_3920_6368(int_31_49, int_30_49, int_14_49, int_16_49, int_25_48); - fullAdd_x FA_3920_6584(int_33_49, int_32_49, int_27_48, int_29_48, int_18_49); - fullAdd_x FA_3920_6800(int_35_49, int_34_49, int_20_49, int_22_49, int_31_48); - fullAdd_x FA_3920_7016(int_37_49, int_36_49, int_33_48, int_24_49, int_26_49); - fullAdd_x FA_3920_7232(int_39_49, int_38_49, int_28_49, int_30_49, int_35_48); - fullAdd_x FA_3920_7448(int_41_49, int_40_49, int_37_48, int_39_48, int_32_49); - fullAdd_x FA_3920_7664(int_43_49, int_42_49, int_34_49, int_41_48, int_36_49); - fullAdd_x FA_3920_7880(int_45_49, int_44_49, int_38_49, int_43_48, int_40_49); - fullAdd_x FA_3920_8096(int_47_49, int_46_49, int_45_48, int_42_49, int_44_49); - assign Sum[49] = int_47_48; - assign Carry[49] = int_46_49; - - // Hardware for column 50 - - r4bs r4bs_4000_64(yy[49], yy[50], single[0], double[0], neg[0], pp_0_50); - halfAdd HA_4000_192(int_1_50, int_0_50, neg[25], pp_0_50); - r4bs r4bs_4000_272(yy[47], yy[48], single[1], double[1], neg[1], pp_1_50); - r4bs r4bs_4000_400(yy[45], yy[46], single[2], double[2], neg[2], pp_2_50); - r4bs r4bs_4000_528(yy[43], yy[44], single[3], double[3], neg[3], pp_3_50); - fullAdd_x FA_4000_656(int_3_50, int_2_50, pp_1_50, pp_2_50, pp_3_50); - r4bs r4bs_4000_872(yy[41], yy[42], single[4], double[4], neg[4], pp_4_50); - r4bs r4bs_4000_1000(yy[39], yy[40], single[5], double[5], neg[5], pp_5_50); - r4bs r4bs_4000_1128(yy[37], yy[38], single[6], double[6], neg[6], pp_6_50); - fullAdd_x FA_4000_1256(int_5_50, int_4_50, pp_4_50, pp_5_50, pp_6_50); - r4bs r4bs_4000_1472(yy[35], yy[36], single[7], double[7], neg[7], pp_7_50); - r4bs r4bs_4000_1600(yy[33], yy[34], single[8], double[8], neg[8], pp_8_50); - r4bs r4bs_4000_1728(yy[31], yy[32], single[9], double[9], neg[9], pp_9_50); - fullAdd_x FA_4000_1856(int_7_50, int_6_50, pp_7_50, pp_8_50, pp_9_50); - r4bs r4bs_4000_2072(yy[29], yy[30], single[10], double[10], neg[10], pp_10_50); - r4bs r4bs_4000_2200(yy[27], yy[28], single[11], double[11], neg[11], pp_11_50); - r4bs r4bs_4000_2328(yy[25], yy[26], single[12], double[12], neg[12], pp_12_50); - fullAdd_x FA_4000_2456(int_9_50, int_8_50, pp_10_50, pp_11_50, pp_12_50); - r4bs r4bs_4000_2672(yy[23], yy[24], single[13], double[13], neg[13], pp_13_50); - r4bs r4bs_4000_2800(yy[21], yy[22], single[14], double[14], neg[14], pp_14_50); - r4bs r4bs_4000_2928(yy[19], yy[20], single[15], double[15], neg[15], pp_15_50); - fullAdd_x FA_4000_3056(int_11_50, int_10_50, pp_13_50, pp_14_50, pp_15_50); - r4bs r4bs_4000_3272(yy[17], yy[18], single[16], double[16], neg[16], pp_16_50); - r4bs r4bs_4000_3400(yy[15], yy[16], single[17], double[17], neg[17], pp_17_50); - r4bs r4bs_4000_3528(yy[13], yy[14], single[18], double[18], neg[18], pp_18_50); - fullAdd_x FA_4000_3656(int_13_50, int_12_50, pp_16_50, pp_17_50, pp_18_50); - r4bs r4bs_4000_3872(yy[11], yy[12], single[19], double[19], neg[19], pp_19_50); - r4bs r4bs_4000_4000(yy[9], yy[10], single[20], double[20], neg[20], pp_20_50); - r4bs r4bs_4000_4128(yy[7], yy[8], single[21], double[21], neg[21], pp_21_50); - fullAdd_x FA_4000_4256(int_15_50, int_14_50, pp_19_50, pp_20_50, pp_21_50); - r4bs r4bs_4000_4472(yy[5], yy[6], single[22], double[22], neg[22], pp_22_50); - r4bs r4bs_4000_4600(yy[3], yy[4], single[23], double[23], neg[23], pp_23_50); - r4bs r4bs_4000_4728(yy[1], yy[2], single[24], double[24], neg[24], pp_24_50); - fullAdd_x FA_4000_4856(int_17_50, int_16_50, pp_22_50, pp_23_50, pp_24_50); - r4bs r4bs_4000_5072(gnd, yy[0], single[25], double[25], neg[25], pp_25_50); - fullAdd_x FA_4000_5200(int_19_50, int_18_50, pp_25_50, int_1_49, int_3_49); - fullAdd_x FA_4000_5416(int_21_50, int_20_50, int_5_49, int_7_49, int_9_49); - fullAdd_x FA_4000_5632(int_23_50, int_22_50, int_11_49, int_13_49, int_15_49); - fullAdd_x FA_4000_5848(int_25_50, int_24_50, int_0_50, int_17_49, int_19_49); - fullAdd_x FA_4000_6064(int_27_50, int_26_50, int_21_49, int_23_49, int_2_50); - fullAdd_x FA_4000_6280(int_29_50, int_28_50, int_4_50, int_6_50, int_8_50); - fullAdd_x FA_4000_6496(int_31_50, int_30_50, int_10_50, int_12_50, int_14_50); - fullAdd_x FA_4000_6712(int_33_50, int_32_50, int_16_50, int_18_50, int_25_49); - fullAdd_x FA_4000_6928(int_35_50, int_34_50, int_27_49, int_29_49, int_20_50); - fullAdd_x FA_4000_7144(int_37_50, int_36_50, int_22_50, int_24_50, int_31_49); - fullAdd_x FA_4000_7360(int_39_50, int_38_50, int_33_49, int_26_50, int_28_50); - fullAdd_x FA_4000_7576(int_41_50, int_40_50, int_30_50, int_32_50, int_35_49); - fullAdd_x FA_4000_7792(int_43_50, int_42_50, int_37_49, int_34_50, int_39_49); - fullAdd_x FA_4000_8008(int_45_50, int_44_50, int_36_50, int_41_49, int_38_50); - fullAdd_x FA_4000_8224(int_47_50, int_46_50, int_40_50, int_43_49, int_42_50); - fullAdd_x FA_4000_8440(int_49_50, int_48_50, int_45_49, int_44_50, int_46_50); - assign Sum[50] = int_47_49; - assign Carry[50] = int_48_50; - - // Hardware for column 51 - - r4bs r4bs_4080_64(yy[50], yy[51], single[0], double[0], neg[0], pp_0_51); - r4bs r4bs_4080_192(yy[48], yy[49], single[1], double[1], neg[1], pp_1_51); - halfAdd HA_4080_320(int_1_51, int_0_51, pp_0_51, pp_1_51); - r4bs r4bs_4080_400(yy[46], yy[47], single[2], double[2], neg[2], pp_2_51); - r4bs r4bs_4080_528(yy[44], yy[45], single[3], double[3], neg[3], pp_3_51); - r4bs r4bs_4080_656(yy[42], yy[43], single[4], double[4], neg[4], pp_4_51); - fullAdd_x FA_4080_784(int_3_51, int_2_51, pp_2_51, pp_3_51, pp_4_51); - r4bs r4bs_4080_1000(yy[40], yy[41], single[5], double[5], neg[5], pp_5_51); - r4bs r4bs_4080_1128(yy[38], yy[39], single[6], double[6], neg[6], pp_6_51); - r4bs r4bs_4080_1256(yy[36], yy[37], single[7], double[7], neg[7], pp_7_51); - fullAdd_x FA_4080_1384(int_5_51, int_4_51, pp_5_51, pp_6_51, pp_7_51); - r4bs r4bs_4080_1600(yy[34], yy[35], single[8], double[8], neg[8], pp_8_51); - r4bs r4bs_4080_1728(yy[32], yy[33], single[9], double[9], neg[9], pp_9_51); - r4bs r4bs_4080_1856(yy[30], yy[31], single[10], double[10], neg[10], pp_10_51); - fullAdd_x FA_4080_1984(int_7_51, int_6_51, pp_8_51, pp_9_51, pp_10_51); - r4bs r4bs_4080_2200(yy[28], yy[29], single[11], double[11], neg[11], pp_11_51); - r4bs r4bs_4080_2328(yy[26], yy[27], single[12], double[12], neg[12], pp_12_51); - r4bs r4bs_4080_2456(yy[24], yy[25], single[13], double[13], neg[13], pp_13_51); - fullAdd_x FA_4080_2584(int_9_51, int_8_51, pp_11_51, pp_12_51, pp_13_51); - r4bs r4bs_4080_2800(yy[22], yy[23], single[14], double[14], neg[14], pp_14_51); - r4bs r4bs_4080_2928(yy[20], yy[21], single[15], double[15], neg[15], pp_15_51); - r4bs r4bs_4080_3056(yy[18], yy[19], single[16], double[16], neg[16], pp_16_51); - fullAdd_x FA_4080_3184(int_11_51, int_10_51, pp_14_51, pp_15_51, pp_16_51); - r4bs r4bs_4080_3400(yy[16], yy[17], single[17], double[17], neg[17], pp_17_51); - r4bs r4bs_4080_3528(yy[14], yy[15], single[18], double[18], neg[18], pp_18_51); - r4bs r4bs_4080_3656(yy[12], yy[13], single[19], double[19], neg[19], pp_19_51); - fullAdd_x FA_4080_3784(int_13_51, int_12_51, pp_17_51, pp_18_51, pp_19_51); - r4bs r4bs_4080_4000(yy[10], yy[11], single[20], double[20], neg[20], pp_20_51); - r4bs r4bs_4080_4128(yy[8], yy[9], single[21], double[21], neg[21], pp_21_51); - r4bs r4bs_4080_4256(yy[6], yy[7], single[22], double[22], neg[22], pp_22_51); - fullAdd_x FA_4080_4384(int_15_51, int_14_51, pp_20_51, pp_21_51, pp_22_51); - r4bs r4bs_4080_4600(yy[4], yy[5], single[23], double[23], neg[23], pp_23_51); - r4bs r4bs_4080_4728(yy[2], yy[3], single[24], double[24], neg[24], pp_24_51); - r4bs r4bs_4080_4856(yy[0], yy[1], single[25], double[25], neg[25], pp_25_51); - fullAdd_x FA_4080_4984(int_17_51, int_16_51, pp_23_51, pp_24_51, pp_25_51); - fullAdd_x FA_4080_5200(int_19_51, int_18_51, int_1_50, int_3_50, int_5_50); - fullAdd_x FA_4080_5416(int_21_51, int_20_51, int_7_50, int_9_50, int_11_50); - fullAdd_x FA_4080_5632(int_23_51, int_22_51, int_13_50, int_15_50, int_17_50); - fullAdd_x FA_4080_5848(int_25_51, int_24_51, int_0_51, int_19_50, int_21_50); - fullAdd_x FA_4080_6064(int_27_51, int_26_51, int_23_50, int_2_51, int_4_51); - fullAdd_x FA_4080_6280(int_29_51, int_28_51, int_6_51, int_8_51, int_10_51); - fullAdd_x FA_4080_6496(int_31_51, int_30_51, int_12_51, int_14_51, int_16_51); - fullAdd_x FA_4080_6712(int_33_51, int_32_51, int_25_50, int_27_50, int_29_50); - fullAdd_x FA_4080_6928(int_35_51, int_34_51, int_31_50, int_18_51, int_20_51); - fullAdd_x FA_4080_7144(int_37_51, int_36_51, int_22_51, int_33_50, int_35_50); - fullAdd_x FA_4080_7360(int_39_51, int_38_51, int_24_51, int_26_51, int_28_51); - fullAdd_x FA_4080_7576(int_41_51, int_40_51, int_30_51, int_37_50, int_39_50); - fullAdd_x FA_4080_7792(int_43_51, int_42_51, int_32_51, int_34_51, int_41_50); - fullAdd_x FA_4080_8008(int_45_51, int_44_51, int_36_51, int_38_51, int_43_50); - fullAdd_x FA_4080_8224(int_47_51, int_46_51, int_45_50, int_40_51, int_42_51); - fullAdd_x FA_4080_8440(int_49_51, int_48_51, int_47_50, int_44_51, int_46_51); - assign Sum[51] = int_49_50; - assign Carry[51] = int_48_51; - - // Hardware for column 52 - - r4bs r4bs_4160_64(yy[51], yy[52], single[0], double[0], neg[0], pp_0_52); - halfAdd HA_4160_192(int_1_52, int_0_52, neg[26], pp_0_52); - r4bs r4bs_4160_272(yy[49], yy[50], single[1], double[1], neg[1], pp_1_52); - r4bs r4bs_4160_400(yy[47], yy[48], single[2], double[2], neg[2], pp_2_52); - r4bs r4bs_4160_528(yy[45], yy[46], single[3], double[3], neg[3], pp_3_52); - fullAdd_x FA_4160_656(int_3_52, int_2_52, pp_1_52, pp_2_52, pp_3_52); - r4bs r4bs_4160_872(yy[43], yy[44], single[4], double[4], neg[4], pp_4_52); - r4bs r4bs_4160_1000(yy[41], yy[42], single[5], double[5], neg[5], pp_5_52); - r4bs r4bs_4160_1128(yy[39], yy[40], single[6], double[6], neg[6], pp_6_52); - fullAdd_x FA_4160_1256(int_5_52, int_4_52, pp_4_52, pp_5_52, pp_6_52); - r4bs r4bs_4160_1472(yy[37], yy[38], single[7], double[7], neg[7], pp_7_52); - r4bs r4bs_4160_1600(yy[35], yy[36], single[8], double[8], neg[8], pp_8_52); - r4bs r4bs_4160_1728(yy[33], yy[34], single[9], double[9], neg[9], pp_9_52); - fullAdd_x FA_4160_1856(int_7_52, int_6_52, pp_7_52, pp_8_52, pp_9_52); - r4bs r4bs_4160_2072(yy[31], yy[32], single[10], double[10], neg[10], pp_10_52); - r4bs r4bs_4160_2200(yy[29], yy[30], single[11], double[11], neg[11], pp_11_52); - r4bs r4bs_4160_2328(yy[27], yy[28], single[12], double[12], neg[12], pp_12_52); - fullAdd_x FA_4160_2456(int_9_52, int_8_52, pp_10_52, pp_11_52, pp_12_52); - r4bs r4bs_4160_2672(yy[25], yy[26], single[13], double[13], neg[13], pp_13_52); - r4bs r4bs_4160_2800(yy[23], yy[24], single[14], double[14], neg[14], pp_14_52); - r4bs r4bs_4160_2928(yy[21], yy[22], single[15], double[15], neg[15], pp_15_52); - fullAdd_x FA_4160_3056(int_11_52, int_10_52, pp_13_52, pp_14_52, pp_15_52); - r4bs r4bs_4160_3272(yy[19], yy[20], single[16], double[16], neg[16], pp_16_52); - r4bs r4bs_4160_3400(yy[17], yy[18], single[17], double[17], neg[17], pp_17_52); - r4bs r4bs_4160_3528(yy[15], yy[16], single[18], double[18], neg[18], pp_18_52); - fullAdd_x FA_4160_3656(int_13_52, int_12_52, pp_16_52, pp_17_52, pp_18_52); - r4bs r4bs_4160_3872(yy[13], yy[14], single[19], double[19], neg[19], pp_19_52); - r4bs r4bs_4160_4000(yy[11], yy[12], single[20], double[20], neg[20], pp_20_52); - r4bs r4bs_4160_4128(yy[9], yy[10], single[21], double[21], neg[21], pp_21_52); - fullAdd_x FA_4160_4256(int_15_52, int_14_52, pp_19_52, pp_20_52, pp_21_52); - r4bs r4bs_4160_4472(yy[7], yy[8], single[22], double[22], neg[22], pp_22_52); - r4bs r4bs_4160_4600(yy[5], yy[6], single[23], double[23], neg[23], pp_23_52); - r4bs r4bs_4160_4728(yy[3], yy[4], single[24], double[24], neg[24], pp_24_52); - fullAdd_x FA_4160_4856(int_17_52, int_16_52, pp_22_52, pp_23_52, pp_24_52); - r4bs r4bs_4160_5072(yy[1], yy[2], single[25], double[25], neg[25], pp_25_52); - r4bs r4bs_4160_5200(gnd, yy[0], single[26], double[26], neg[26], pp_26_52); - fullAdd_x FA_4160_5328(int_19_52, int_18_52, pp_25_52, pp_26_52, int_1_51); - fullAdd_x FA_4160_5544(int_21_52, int_20_52, int_3_51, int_5_51, int_7_51); - fullAdd_x FA_4160_5760(int_23_52, int_22_52, int_9_51, int_11_51, int_13_51); - fullAdd_x FA_4160_5976(int_25_52, int_24_52, int_15_51, int_17_51, int_0_52); - fullAdd_x FA_4160_6192(int_27_52, int_26_52, int_19_51, int_21_51, int_23_51); - fullAdd_x FA_4160_6408(int_29_52, int_28_52, int_2_52, int_4_52, int_6_52); - fullAdd_x FA_4160_6624(int_31_52, int_30_52, int_8_52, int_10_52, int_12_52); - fullAdd_x FA_4160_6840(int_33_52, int_32_52, int_14_52, int_16_52, int_18_52); - fullAdd_x FA_4160_7056(int_35_52, int_34_52, int_25_51, int_27_51, int_29_51); - fullAdd_x FA_4160_7272(int_37_52, int_36_52, int_31_51, int_20_52, int_22_52); - fullAdd_x FA_4160_7488(int_39_52, int_38_52, int_24_52, int_33_51, int_35_51); - fullAdd_x FA_4160_7704(int_41_52, int_40_52, int_26_52, int_28_52, int_30_52); - fullAdd_x FA_4160_7920(int_43_52, int_42_52, int_32_52, int_37_51, int_39_51); - fullAdd_x FA_4160_8136(int_45_52, int_44_52, int_34_52, int_36_52, int_41_51); - fullAdd_x FA_4160_8352(int_47_52, int_46_52, int_38_52, int_40_52, int_43_51); - fullAdd_x FA_4160_8568(int_49_52, int_48_52, int_42_52, int_44_52, int_45_51); - fullAdd_x FA_4160_8784(int_51_52, int_50_52, int_47_51, int_46_52, int_48_52); - assign Sum[52] = int_49_51; - assign Carry[52] = int_50_52; - - // Hardware for column 53 - - r4bs r4bs_4240_64(yy[52], yy[53], single[0], double[0], neg[0], pp_0_53); - r4bs r4bs_4240_192(yy[50], yy[51], single[1], double[1], neg[1], pp_1_53); - halfAdd HA_4240_320(int_1_53, int_0_53, pp_0_53, pp_1_53); - r4bs r4bs_4240_400(yy[48], yy[49], single[2], double[2], neg[2], pp_2_53); - r4bs r4bs_4240_528(yy[46], yy[47], single[3], double[3], neg[3], pp_3_53); - r4bs r4bs_4240_656(yy[44], yy[45], single[4], double[4], neg[4], pp_4_53); - fullAdd_x FA_4240_784(int_3_53, int_2_53, pp_2_53, pp_3_53, pp_4_53); - r4bs r4bs_4240_1000(yy[42], yy[43], single[5], double[5], neg[5], pp_5_53); - r4bs r4bs_4240_1128(yy[40], yy[41], single[6], double[6], neg[6], pp_6_53); - r4bs r4bs_4240_1256(yy[38], yy[39], single[7], double[7], neg[7], pp_7_53); - fullAdd_x FA_4240_1384(int_5_53, int_4_53, pp_5_53, pp_6_53, pp_7_53); - r4bs r4bs_4240_1600(yy[36], yy[37], single[8], double[8], neg[8], pp_8_53); - r4bs r4bs_4240_1728(yy[34], yy[35], single[9], double[9], neg[9], pp_9_53); - r4bs r4bs_4240_1856(yy[32], yy[33], single[10], double[10], neg[10], pp_10_53); - fullAdd_x FA_4240_1984(int_7_53, int_6_53, pp_8_53, pp_9_53, pp_10_53); - r4bs r4bs_4240_2200(yy[30], yy[31], single[11], double[11], neg[11], pp_11_53); - r4bs r4bs_4240_2328(yy[28], yy[29], single[12], double[12], neg[12], pp_12_53); - r4bs r4bs_4240_2456(yy[26], yy[27], single[13], double[13], neg[13], pp_13_53); - fullAdd_x FA_4240_2584(int_9_53, int_8_53, pp_11_53, pp_12_53, pp_13_53); - r4bs r4bs_4240_2800(yy[24], yy[25], single[14], double[14], neg[14], pp_14_53); - r4bs r4bs_4240_2928(yy[22], yy[23], single[15], double[15], neg[15], pp_15_53); - r4bs r4bs_4240_3056(yy[20], yy[21], single[16], double[16], neg[16], pp_16_53); - fullAdd_x FA_4240_3184(int_11_53, int_10_53, pp_14_53, pp_15_53, pp_16_53); - r4bs r4bs_4240_3400(yy[18], yy[19], single[17], double[17], neg[17], pp_17_53); - r4bs r4bs_4240_3528(yy[16], yy[17], single[18], double[18], neg[18], pp_18_53); - r4bs r4bs_4240_3656(yy[14], yy[15], single[19], double[19], neg[19], pp_19_53); - fullAdd_x FA_4240_3784(int_13_53, int_12_53, pp_17_53, pp_18_53, pp_19_53); - r4bs r4bs_4240_4000(yy[12], yy[13], single[20], double[20], neg[20], pp_20_53); - r4bs r4bs_4240_4128(yy[10], yy[11], single[21], double[21], neg[21], pp_21_53); - r4bs r4bs_4240_4256(yy[8], yy[9], single[22], double[22], neg[22], pp_22_53); - fullAdd_x FA_4240_4384(int_15_53, int_14_53, pp_20_53, pp_21_53, pp_22_53); - r4bs r4bs_4240_4600(yy[6], yy[7], single[23], double[23], neg[23], pp_23_53); - r4bs r4bs_4240_4728(yy[4], yy[5], single[24], double[24], neg[24], pp_24_53); - r4bs r4bs_4240_4856(yy[2], yy[3], single[25], double[25], neg[25], pp_25_53); - fullAdd_x FA_4240_4984(int_17_53, int_16_53, pp_23_53, pp_24_53, pp_25_53); - r4bs r4bs_4240_5200(yy[0], yy[1], single[26], double[26], neg[26], pp_26_53); - fullAdd_x FA_4240_5328(int_19_53, int_18_53, pp_26_53, int_1_52, int_3_52); - fullAdd_x FA_4240_5544(int_21_53, int_20_53, int_5_52, int_7_52, int_9_52); - fullAdd_x FA_4240_5760(int_23_53, int_22_53, int_11_52, int_13_52, int_15_52); - fullAdd_x FA_4240_5976(int_25_53, int_24_53, int_17_52, int_0_53, int_19_52); - fullAdd_x FA_4240_6192(int_27_53, int_26_53, int_21_52, int_23_52, int_25_52); - fullAdd_x FA_4240_6408(int_29_53, int_28_53, int_2_53, int_4_53, int_6_53); - fullAdd_x FA_4240_6624(int_31_53, int_30_53, int_8_53, int_10_53, int_12_53); - fullAdd_x FA_4240_6840(int_33_53, int_32_53, int_14_53, int_16_53, int_18_53); - fullAdd_x FA_4240_7056(int_35_53, int_34_53, int_27_52, int_29_52, int_31_52); - fullAdd_x FA_4240_7272(int_37_53, int_36_53, int_33_52, int_20_53, int_22_53); - fullAdd_x FA_4240_7488(int_39_53, int_38_53, int_24_53, int_35_52, int_37_52); - fullAdd_x FA_4240_7704(int_41_53, int_40_53, int_26_53, int_28_53, int_30_53); - fullAdd_x FA_4240_7920(int_43_53, int_42_53, int_32_53, int_39_52, int_41_52); - fullAdd_x FA_4240_8136(int_45_53, int_44_53, int_34_53, int_36_53, int_43_52); - fullAdd_x FA_4240_8352(int_47_53, int_46_53, int_38_53, int_40_53, int_45_52); - fullAdd_x FA_4240_8568(int_49_53, int_48_53, int_42_53, int_44_53, int_47_52); - fullAdd_x FA_4240_8784(int_51_53, int_50_53, int_46_53, int_49_52, int_48_53); - assign Sum[53] = int_51_52; - assign Carry[53] = int_50_53; - - // Hardware for column 54 - - r4bs r4bs_4320_64(yy[53], yy[54], single[0], double[0], neg[0], pp_0_54); - halfAdd HA_4320_192(int_1_54, int_0_54, neg[27], pp_0_54); - r4bs r4bs_4320_272(yy[51], yy[52], single[1], double[1], neg[1], pp_1_54); - r4bs r4bs_4320_400(yy[49], yy[50], single[2], double[2], neg[2], pp_2_54); - r4bs r4bs_4320_528(yy[47], yy[48], single[3], double[3], neg[3], pp_3_54); - fullAdd_x FA_4320_656(int_3_54, int_2_54, pp_1_54, pp_2_54, pp_3_54); - r4bs r4bs_4320_872(yy[45], yy[46], single[4], double[4], neg[4], pp_4_54); - r4bs r4bs_4320_1000(yy[43], yy[44], single[5], double[5], neg[5], pp_5_54); - r4bs r4bs_4320_1128(yy[41], yy[42], single[6], double[6], neg[6], pp_6_54); - fullAdd_x FA_4320_1256(int_5_54, int_4_54, pp_4_54, pp_5_54, pp_6_54); - r4bs r4bs_4320_1472(yy[39], yy[40], single[7], double[7], neg[7], pp_7_54); - r4bs r4bs_4320_1600(yy[37], yy[38], single[8], double[8], neg[8], pp_8_54); - r4bs r4bs_4320_1728(yy[35], yy[36], single[9], double[9], neg[9], pp_9_54); - fullAdd_x FA_4320_1856(int_7_54, int_6_54, pp_7_54, pp_8_54, pp_9_54); - r4bs r4bs_4320_2072(yy[33], yy[34], single[10], double[10], neg[10], pp_10_54); - r4bs r4bs_4320_2200(yy[31], yy[32], single[11], double[11], neg[11], pp_11_54); - r4bs r4bs_4320_2328(yy[29], yy[30], single[12], double[12], neg[12], pp_12_54); - fullAdd_x FA_4320_2456(int_9_54, int_8_54, pp_10_54, pp_11_54, pp_12_54); - r4bs r4bs_4320_2672(yy[27], yy[28], single[13], double[13], neg[13], pp_13_54); - r4bs r4bs_4320_2800(yy[25], yy[26], single[14], double[14], neg[14], pp_14_54); - r4bs r4bs_4320_2928(yy[23], yy[24], single[15], double[15], neg[15], pp_15_54); - fullAdd_x FA_4320_3056(int_11_54, int_10_54, pp_13_54, pp_14_54, pp_15_54); - r4bs r4bs_4320_3272(yy[21], yy[22], single[16], double[16], neg[16], pp_16_54); - r4bs r4bs_4320_3400(yy[19], yy[20], single[17], double[17], neg[17], pp_17_54); - r4bs r4bs_4320_3528(yy[17], yy[18], single[18], double[18], neg[18], pp_18_54); - fullAdd_x FA_4320_3656(int_13_54, int_12_54, pp_16_54, pp_17_54, pp_18_54); - r4bs r4bs_4320_3872(yy[15], yy[16], single[19], double[19], neg[19], pp_19_54); - r4bs r4bs_4320_4000(yy[13], yy[14], single[20], double[20], neg[20], pp_20_54); - r4bs r4bs_4320_4128(yy[11], yy[12], single[21], double[21], neg[21], pp_21_54); - fullAdd_x FA_4320_4256(int_15_54, int_14_54, pp_19_54, pp_20_54, pp_21_54); - r4bs r4bs_4320_4472(yy[9], yy[10], single[22], double[22], neg[22], pp_22_54); - r4bs r4bs_4320_4600(yy[7], yy[8], single[23], double[23], neg[23], pp_23_54); - r4bs r4bs_4320_4728(yy[5], yy[6], single[24], double[24], neg[24], pp_24_54); - fullAdd_x FA_4320_4856(int_17_54, int_16_54, pp_22_54, pp_23_54, pp_24_54); - r4bs r4bs_4320_5072(yy[3], yy[4], single[25], double[25], neg[25], pp_25_54); - r4bs r4bs_4320_5200(yy[1], yy[2], single[26], double[26], neg[26], pp_26_54); - r4bs r4bs_4320_5328(gnd, yy[0], single[27], double[27], neg[27], pp_27_54); - fullAdd_x FA_4320_5456(int_19_54, int_18_54, pp_25_54, pp_26_54, pp_27_54); - fullAdd_x FA_4320_5672(int_21_54, int_20_54, int_1_53, int_3_53, int_5_53); - fullAdd_x FA_4320_5888(int_23_54, int_22_54, int_7_53, int_9_53, int_11_53); - fullAdd_x FA_4320_6104(int_25_54, int_24_54, int_13_53, int_15_53, int_17_53); - fullAdd_x FA_4320_6320(int_27_54, int_26_54, int_0_54, int_19_53, int_21_53); - fullAdd_x FA_4320_6536(int_29_54, int_28_54, int_23_53, int_2_54, int_4_54); - fullAdd_x FA_4320_6752(int_31_54, int_30_54, int_6_54, int_8_54, int_10_54); - fullAdd_x FA_4320_6968(int_33_54, int_32_54, int_12_54, int_14_54, int_16_54); - fullAdd_x FA_4320_7184(int_35_54, int_34_54, int_18_54, int_25_53, int_27_53); - fullAdd_x FA_4320_7400(int_37_54, int_36_54, int_29_53, int_31_53, int_20_54); - fullAdd_x FA_4320_7616(int_39_54, int_38_54, int_22_54, int_24_54, int_33_53); - fullAdd_x FA_4320_7832(int_41_54, int_40_54, int_35_53, int_37_53, int_26_54); - fullAdd_x FA_4320_8048(int_43_54, int_42_54, int_28_54, int_30_54, int_32_54); - fullAdd_x FA_4320_8264(int_45_54, int_44_54, int_34_54, int_39_53, int_41_53); - fullAdd_x FA_4320_8480(int_47_54, int_46_54, int_36_54, int_38_54, int_43_53); - fullAdd_x FA_4320_8696(int_49_54, int_48_54, int_40_54, int_42_54, int_45_53); - fullAdd_x FA_4320_8912(int_51_54, int_50_54, int_44_54, int_46_54, int_47_53); - fullAdd_x FA_4320_9128(int_53_54, int_52_54, int_48_54, int_49_53, int_50_54); - assign Sum[54] = int_51_53; - assign Carry[54] = int_52_54; - - // Hardware for column 55 - - r4bs r4bs_4400_64(yy[54], yy[55], single[0], double[0], neg[0], pp_0_55); - r4bs r4bs_4400_192(yy[52], yy[53], single[1], double[1], neg[1], pp_1_55); - halfAdd HA_4400_320(int_1_55, int_0_55, pp_0_55, pp_1_55); - r4bs r4bs_4400_400(yy[50], yy[51], single[2], double[2], neg[2], pp_2_55); - r4bs r4bs_4400_528(yy[48], yy[49], single[3], double[3], neg[3], pp_3_55); - r4bs r4bs_4400_656(yy[46], yy[47], single[4], double[4], neg[4], pp_4_55); - fullAdd_x FA_4400_784(int_3_55, int_2_55, pp_2_55, pp_3_55, pp_4_55); - r4bs r4bs_4400_1000(yy[44], yy[45], single[5], double[5], neg[5], pp_5_55); - r4bs r4bs_4400_1128(yy[42], yy[43], single[6], double[6], neg[6], pp_6_55); - r4bs r4bs_4400_1256(yy[40], yy[41], single[7], double[7], neg[7], pp_7_55); - fullAdd_x FA_4400_1384(int_5_55, int_4_55, pp_5_55, pp_6_55, pp_7_55); - r4bs r4bs_4400_1600(yy[38], yy[39], single[8], double[8], neg[8], pp_8_55); - r4bs r4bs_4400_1728(yy[36], yy[37], single[9], double[9], neg[9], pp_9_55); - r4bs r4bs_4400_1856(yy[34], yy[35], single[10], double[10], neg[10], pp_10_55); - fullAdd_x FA_4400_1984(int_7_55, int_6_55, pp_8_55, pp_9_55, pp_10_55); - r4bs r4bs_4400_2200(yy[32], yy[33], single[11], double[11], neg[11], pp_11_55); - r4bs r4bs_4400_2328(yy[30], yy[31], single[12], double[12], neg[12], pp_12_55); - r4bs r4bs_4400_2456(yy[28], yy[29], single[13], double[13], neg[13], pp_13_55); - fullAdd_x FA_4400_2584(int_9_55, int_8_55, pp_11_55, pp_12_55, pp_13_55); - r4bs r4bs_4400_2800(yy[26], yy[27], single[14], double[14], neg[14], pp_14_55); - r4bs r4bs_4400_2928(yy[24], yy[25], single[15], double[15], neg[15], pp_15_55); - r4bs r4bs_4400_3056(yy[22], yy[23], single[16], double[16], neg[16], pp_16_55); - fullAdd_x FA_4400_3184(int_11_55, int_10_55, pp_14_55, pp_15_55, pp_16_55); - r4bs r4bs_4400_3400(yy[20], yy[21], single[17], double[17], neg[17], pp_17_55); - r4bs r4bs_4400_3528(yy[18], yy[19], single[18], double[18], neg[18], pp_18_55); - r4bs r4bs_4400_3656(yy[16], yy[17], single[19], double[19], neg[19], pp_19_55); - fullAdd_x FA_4400_3784(int_13_55, int_12_55, pp_17_55, pp_18_55, pp_19_55); - r4bs r4bs_4400_4000(yy[14], yy[15], single[20], double[20], neg[20], pp_20_55); - r4bs r4bs_4400_4128(yy[12], yy[13], single[21], double[21], neg[21], pp_21_55); - r4bs r4bs_4400_4256(yy[10], yy[11], single[22], double[22], neg[22], pp_22_55); - fullAdd_x FA_4400_4384(int_15_55, int_14_55, pp_20_55, pp_21_55, pp_22_55); - r4bs r4bs_4400_4600(yy[8], yy[9], single[23], double[23], neg[23], pp_23_55); - r4bs r4bs_4400_4728(yy[6], yy[7], single[24], double[24], neg[24], pp_24_55); - r4bs r4bs_4400_4856(yy[4], yy[5], single[25], double[25], neg[25], pp_25_55); - fullAdd_x FA_4400_4984(int_17_55, int_16_55, pp_23_55, pp_24_55, pp_25_55); - r4bs r4bs_4400_5200(yy[2], yy[3], single[26], double[26], neg[26], pp_26_55); - r4bs r4bs_4400_5328(yy[0], yy[1], single[27], double[27], neg[27], pp_27_55); - fullAdd_x FA_4400_5456(int_19_55, int_18_55, pp_26_55, pp_27_55, int_1_54); - fullAdd_x FA_4400_5672(int_21_55, int_20_55, int_3_54, int_5_54, int_7_54); - fullAdd_x FA_4400_5888(int_23_55, int_22_55, int_9_54, int_11_54, int_13_54); - fullAdd_x FA_4400_6104(int_25_55, int_24_55, int_15_54, int_17_54, int_19_54); - fullAdd_x FA_4400_6320(int_27_55, int_26_55, int_0_55, int_21_54, int_23_54); - fullAdd_x FA_4400_6536(int_29_55, int_28_55, int_25_54, int_2_55, int_4_55); - fullAdd_x FA_4400_6752(int_31_55, int_30_55, int_6_55, int_8_55, int_10_55); - fullAdd_x FA_4400_6968(int_33_55, int_32_55, int_12_55, int_14_55, int_16_55); - fullAdd_x FA_4400_7184(int_35_55, int_34_55, int_18_55, int_27_54, int_29_54); - fullAdd_x FA_4400_7400(int_37_55, int_36_55, int_31_54, int_33_54, int_20_55); - fullAdd_x FA_4400_7616(int_39_55, int_38_55, int_22_55, int_24_55, int_35_54); - fullAdd_x FA_4400_7832(int_41_55, int_40_55, int_37_54, int_26_55, int_28_55); - fullAdd_x FA_4400_8048(int_43_55, int_42_55, int_30_55, int_32_55, int_39_54); - fullAdd_x FA_4400_8264(int_45_55, int_44_55, int_41_54, int_43_54, int_34_55); - fullAdd_x FA_4400_8480(int_47_55, int_46_55, int_36_55, int_38_55, int_45_54); - fullAdd_x FA_4400_8696(int_49_55, int_48_55, int_40_55, int_42_55, int_47_54); - fullAdd_x FA_4400_8912(int_51_55, int_50_55, int_44_55, int_46_55, int_49_54); - fullAdd_x FA_4400_9128(int_53_55, int_52_55, int_48_55, int_51_54, int_50_55); - assign Sum[55] = int_53_54; - assign Carry[55] = int_52_55; - - // Hardware for column 56 - - r4bs r4bs_4480_64(yy[55], yy[56], single[0], double[0], neg[0], pp_0_56); - halfAdd HA_4480_192(int_1_56, int_0_56, neg[28], pp_0_56); - r4bs r4bs_4480_272(yy[53], yy[54], single[1], double[1], neg[1], pp_1_56); - r4bs r4bs_4480_400(yy[51], yy[52], single[2], double[2], neg[2], pp_2_56); - r4bs r4bs_4480_528(yy[49], yy[50], single[3], double[3], neg[3], pp_3_56); - fullAdd_x FA_4480_656(int_3_56, int_2_56, pp_1_56, pp_2_56, pp_3_56); - r4bs r4bs_4480_872(yy[47], yy[48], single[4], double[4], neg[4], pp_4_56); - r4bs r4bs_4480_1000(yy[45], yy[46], single[5], double[5], neg[5], pp_5_56); - r4bs r4bs_4480_1128(yy[43], yy[44], single[6], double[6], neg[6], pp_6_56); - fullAdd_x FA_4480_1256(int_5_56, int_4_56, pp_4_56, pp_5_56, pp_6_56); - r4bs r4bs_4480_1472(yy[41], yy[42], single[7], double[7], neg[7], pp_7_56); - r4bs r4bs_4480_1600(yy[39], yy[40], single[8], double[8], neg[8], pp_8_56); - r4bs r4bs_4480_1728(yy[37], yy[38], single[9], double[9], neg[9], pp_9_56); - fullAdd_x FA_4480_1856(int_7_56, int_6_56, pp_7_56, pp_8_56, pp_9_56); - r4bs r4bs_4480_2072(yy[35], yy[36], single[10], double[10], neg[10], pp_10_56); - r4bs r4bs_4480_2200(yy[33], yy[34], single[11], double[11], neg[11], pp_11_56); - r4bs r4bs_4480_2328(yy[31], yy[32], single[12], double[12], neg[12], pp_12_56); - fullAdd_x FA_4480_2456(int_9_56, int_8_56, pp_10_56, pp_11_56, pp_12_56); - r4bs r4bs_4480_2672(yy[29], yy[30], single[13], double[13], neg[13], pp_13_56); - r4bs r4bs_4480_2800(yy[27], yy[28], single[14], double[14], neg[14], pp_14_56); - r4bs r4bs_4480_2928(yy[25], yy[26], single[15], double[15], neg[15], pp_15_56); - fullAdd_x FA_4480_3056(int_11_56, int_10_56, pp_13_56, pp_14_56, pp_15_56); - r4bs r4bs_4480_3272(yy[23], yy[24], single[16], double[16], neg[16], pp_16_56); - r4bs r4bs_4480_3400(yy[21], yy[22], single[17], double[17], neg[17], pp_17_56); - r4bs r4bs_4480_3528(yy[19], yy[20], single[18], double[18], neg[18], pp_18_56); - fullAdd_x FA_4480_3656(int_13_56, int_12_56, pp_16_56, pp_17_56, pp_18_56); - r4bs r4bs_4480_3872(yy[17], yy[18], single[19], double[19], neg[19], pp_19_56); - r4bs r4bs_4480_4000(yy[15], yy[16], single[20], double[20], neg[20], pp_20_56); - r4bs r4bs_4480_4128(yy[13], yy[14], single[21], double[21], neg[21], pp_21_56); - fullAdd_x FA_4480_4256(int_15_56, int_14_56, pp_19_56, pp_20_56, pp_21_56); - r4bs r4bs_4480_4472(yy[11], yy[12], single[22], double[22], neg[22], pp_22_56); - r4bs r4bs_4480_4600(yy[9], yy[10], single[23], double[23], neg[23], pp_23_56); - r4bs r4bs_4480_4728(yy[7], yy[8], single[24], double[24], neg[24], pp_24_56); - fullAdd_x FA_4480_4856(int_17_56, int_16_56, pp_22_56, pp_23_56, pp_24_56); - r4bs r4bs_4480_5072(yy[5], yy[6], single[25], double[25], neg[25], pp_25_56); - r4bs r4bs_4480_5200(yy[3], yy[4], single[26], double[26], neg[26], pp_26_56); - r4bs r4bs_4480_5328(yy[1], yy[2], single[27], double[27], neg[27], pp_27_56); - fullAdd_x FA_4480_5456(int_19_56, int_18_56, pp_25_56, pp_26_56, pp_27_56); - r4bs r4bs_4480_5672(gnd, yy[0], single[28], double[28], neg[28], pp_28_56); - fullAdd_x FA_4480_5800(int_21_56, int_20_56, pp_28_56, int_1_55, int_3_55); - fullAdd_x FA_4480_6016(int_23_56, int_22_56, int_5_55, int_7_55, int_9_55); - fullAdd_x FA_4480_6232(int_25_56, int_24_56, int_11_55, int_13_55, int_15_55); - fullAdd_x FA_4480_6448(int_27_56, int_26_56, int_17_55, int_0_56, int_19_55); - fullAdd_x FA_4480_6664(int_29_56, int_28_56, int_21_55, int_23_55, int_25_55); - fullAdd_x FA_4480_6880(int_31_56, int_30_56, int_2_56, int_4_56, int_6_56); - fullAdd_x FA_4480_7096(int_33_56, int_32_56, int_8_56, int_10_56, int_12_56); - fullAdd_x FA_4480_7312(int_35_56, int_34_56, int_14_56, int_16_56, int_18_56); - fullAdd_x FA_4480_7528(int_37_56, int_36_56, int_20_56, int_27_55, int_29_55); - fullAdd_x FA_4480_7744(int_39_56, int_38_56, int_31_55, int_33_55, int_22_56); - fullAdd_x FA_4480_7960(int_41_56, int_40_56, int_24_56, int_26_56, int_35_55); - fullAdd_x FA_4480_8176(int_43_56, int_42_56, int_37_55, int_28_56, int_30_56); - fullAdd_x FA_4480_8392(int_45_56, int_44_56, int_32_56, int_34_56, int_39_55); - fullAdd_x FA_4480_8608(int_47_56, int_46_56, int_41_55, int_36_56, int_38_56); - fullAdd_x FA_4480_8824(int_49_56, int_48_56, int_40_56, int_43_55, int_45_55); - fullAdd_x FA_4480_9040(int_51_56, int_50_56, int_42_56, int_44_56, int_47_55); - fullAdd_x FA_4480_9256(int_53_56, int_52_56, int_46_56, int_48_56, int_49_55); - fullAdd_x FA_4480_9472(int_55_56, int_54_56, int_50_56, int_51_55, int_52_56); - assign Sum[56] = int_53_55; - assign Carry[56] = int_54_56; - - // Hardware for column 57 - - r4bs r4bs_4560_64(yy[56], yy[57], single[0], double[0], neg[0], pp_0_57); - r4bs r4bs_4560_192(yy[54], yy[55], single[1], double[1], neg[1], pp_1_57); - halfAdd HA_4560_320(int_1_57, int_0_57, pp_0_57, pp_1_57); - r4bs r4bs_4560_400(yy[52], yy[53], single[2], double[2], neg[2], pp_2_57); - r4bs r4bs_4560_528(yy[50], yy[51], single[3], double[3], neg[3], pp_3_57); - r4bs r4bs_4560_656(yy[48], yy[49], single[4], double[4], neg[4], pp_4_57); - fullAdd_x FA_4560_784(int_3_57, int_2_57, pp_2_57, pp_3_57, pp_4_57); - r4bs r4bs_4560_1000(yy[46], yy[47], single[5], double[5], neg[5], pp_5_57); - r4bs r4bs_4560_1128(yy[44], yy[45], single[6], double[6], neg[6], pp_6_57); - r4bs r4bs_4560_1256(yy[42], yy[43], single[7], double[7], neg[7], pp_7_57); - fullAdd_x FA_4560_1384(int_5_57, int_4_57, pp_5_57, pp_6_57, pp_7_57); - r4bs r4bs_4560_1600(yy[40], yy[41], single[8], double[8], neg[8], pp_8_57); - r4bs r4bs_4560_1728(yy[38], yy[39], single[9], double[9], neg[9], pp_9_57); - r4bs r4bs_4560_1856(yy[36], yy[37], single[10], double[10], neg[10], pp_10_57); - fullAdd_x FA_4560_1984(int_7_57, int_6_57, pp_8_57, pp_9_57, pp_10_57); - r4bs r4bs_4560_2200(yy[34], yy[35], single[11], double[11], neg[11], pp_11_57); - r4bs r4bs_4560_2328(yy[32], yy[33], single[12], double[12], neg[12], pp_12_57); - r4bs r4bs_4560_2456(yy[30], yy[31], single[13], double[13], neg[13], pp_13_57); - fullAdd_x FA_4560_2584(int_9_57, int_8_57, pp_11_57, pp_12_57, pp_13_57); - r4bs r4bs_4560_2800(yy[28], yy[29], single[14], double[14], neg[14], pp_14_57); - r4bs r4bs_4560_2928(yy[26], yy[27], single[15], double[15], neg[15], pp_15_57); - r4bs r4bs_4560_3056(yy[24], yy[25], single[16], double[16], neg[16], pp_16_57); - fullAdd_x FA_4560_3184(int_11_57, int_10_57, pp_14_57, pp_15_57, pp_16_57); - r4bs r4bs_4560_3400(yy[22], yy[23], single[17], double[17], neg[17], pp_17_57); - r4bs r4bs_4560_3528(yy[20], yy[21], single[18], double[18], neg[18], pp_18_57); - r4bs r4bs_4560_3656(yy[18], yy[19], single[19], double[19], neg[19], pp_19_57); - fullAdd_x FA_4560_3784(int_13_57, int_12_57, pp_17_57, pp_18_57, pp_19_57); - r4bs r4bs_4560_4000(yy[16], yy[17], single[20], double[20], neg[20], pp_20_57); - r4bs r4bs_4560_4128(yy[14], yy[15], single[21], double[21], neg[21], pp_21_57); - r4bs r4bs_4560_4256(yy[12], yy[13], single[22], double[22], neg[22], pp_22_57); - fullAdd_x FA_4560_4384(int_15_57, int_14_57, pp_20_57, pp_21_57, pp_22_57); - r4bs r4bs_4560_4600(yy[10], yy[11], single[23], double[23], neg[23], pp_23_57); - r4bs r4bs_4560_4728(yy[8], yy[9], single[24], double[24], neg[24], pp_24_57); - r4bs r4bs_4560_4856(yy[6], yy[7], single[25], double[25], neg[25], pp_25_57); - fullAdd_x FA_4560_4984(int_17_57, int_16_57, pp_23_57, pp_24_57, pp_25_57); - r4bs r4bs_4560_5200(yy[4], yy[5], single[26], double[26], neg[26], pp_26_57); - r4bs r4bs_4560_5328(yy[2], yy[3], single[27], double[27], neg[27], pp_27_57); - r4bs r4bs_4560_5456(yy[0], yy[1], single[28], double[28], neg[28], pp_28_57); - fullAdd_x FA_4560_5584(int_19_57, int_18_57, pp_26_57, pp_27_57, pp_28_57); - fullAdd_x FA_4560_5800(int_21_57, int_20_57, int_1_56, int_3_56, int_5_56); - fullAdd_x FA_4560_6016(int_23_57, int_22_57, int_7_56, int_9_56, int_11_56); - fullAdd_x FA_4560_6232(int_25_57, int_24_57, int_13_56, int_15_56, int_17_56); - fullAdd_x FA_4560_6448(int_27_57, int_26_57, int_19_56, int_0_57, int_21_56); - fullAdd_x FA_4560_6664(int_29_57, int_28_57, int_23_56, int_25_56, int_2_57); - fullAdd_x FA_4560_6880(int_31_57, int_30_57, int_4_57, int_6_57, int_8_57); - fullAdd_x FA_4560_7096(int_33_57, int_32_57, int_10_57, int_12_57, int_14_57); - fullAdd_x FA_4560_7312(int_35_57, int_34_57, int_16_57, int_18_57, int_27_56); - fullAdd_x FA_4560_7528(int_37_57, int_36_57, int_29_56, int_31_56, int_33_56); - fullAdd_x FA_4560_7744(int_39_57, int_38_57, int_35_56, int_20_57, int_22_57); - fullAdd_x FA_4560_7960(int_41_57, int_40_57, int_24_57, int_26_57, int_37_56); - fullAdd_x FA_4560_8176(int_43_57, int_42_57, int_39_56, int_28_57, int_30_57); - fullAdd_x FA_4560_8392(int_45_57, int_44_57, int_32_57, int_34_57, int_41_56); - fullAdd_x FA_4560_8608(int_47_57, int_46_57, int_43_56, int_36_57, int_38_57); - fullAdd_x FA_4560_8824(int_49_57, int_48_57, int_40_57, int_45_56, int_47_56); - fullAdd_x FA_4560_9040(int_51_57, int_50_57, int_42_57, int_44_57, int_49_56); - fullAdd_x FA_4560_9256(int_53_57, int_52_57, int_46_57, int_51_56, int_48_57); - fullAdd_x FA_4560_9472(int_55_57, int_54_57, int_50_57, int_53_56, int_52_57); - assign Sum[57] = int_55_56; - assign Carry[57] = int_54_57; - - // Hardware for column 58 - - r4bs r4bs_4640_64(yy[57], yy[58], single[0], double[0], neg[0], pp_0_58); - halfAdd HA_4640_192(int_1_58, int_0_58, neg[29], pp_0_58); - r4bs r4bs_4640_272(yy[55], yy[56], single[1], double[1], neg[1], pp_1_58); - r4bs r4bs_4640_400(yy[53], yy[54], single[2], double[2], neg[2], pp_2_58); - r4bs r4bs_4640_528(yy[51], yy[52], single[3], double[3], neg[3], pp_3_58); - fullAdd_x FA_4640_656(int_3_58, int_2_58, pp_1_58, pp_2_58, pp_3_58); - r4bs r4bs_4640_872(yy[49], yy[50], single[4], double[4], neg[4], pp_4_58); - r4bs r4bs_4640_1000(yy[47], yy[48], single[5], double[5], neg[5], pp_5_58); - r4bs r4bs_4640_1128(yy[45], yy[46], single[6], double[6], neg[6], pp_6_58); - fullAdd_x FA_4640_1256(int_5_58, int_4_58, pp_4_58, pp_5_58, pp_6_58); - r4bs r4bs_4640_1472(yy[43], yy[44], single[7], double[7], neg[7], pp_7_58); - r4bs r4bs_4640_1600(yy[41], yy[42], single[8], double[8], neg[8], pp_8_58); - r4bs r4bs_4640_1728(yy[39], yy[40], single[9], double[9], neg[9], pp_9_58); - fullAdd_x FA_4640_1856(int_7_58, int_6_58, pp_7_58, pp_8_58, pp_9_58); - r4bs r4bs_4640_2072(yy[37], yy[38], single[10], double[10], neg[10], pp_10_58); - r4bs r4bs_4640_2200(yy[35], yy[36], single[11], double[11], neg[11], pp_11_58); - r4bs r4bs_4640_2328(yy[33], yy[34], single[12], double[12], neg[12], pp_12_58); - fullAdd_x FA_4640_2456(int_9_58, int_8_58, pp_10_58, pp_11_58, pp_12_58); - r4bs r4bs_4640_2672(yy[31], yy[32], single[13], double[13], neg[13], pp_13_58); - r4bs r4bs_4640_2800(yy[29], yy[30], single[14], double[14], neg[14], pp_14_58); - r4bs r4bs_4640_2928(yy[27], yy[28], single[15], double[15], neg[15], pp_15_58); - fullAdd_x FA_4640_3056(int_11_58, int_10_58, pp_13_58, pp_14_58, pp_15_58); - r4bs r4bs_4640_3272(yy[25], yy[26], single[16], double[16], neg[16], pp_16_58); - r4bs r4bs_4640_3400(yy[23], yy[24], single[17], double[17], neg[17], pp_17_58); - r4bs r4bs_4640_3528(yy[21], yy[22], single[18], double[18], neg[18], pp_18_58); - fullAdd_x FA_4640_3656(int_13_58, int_12_58, pp_16_58, pp_17_58, pp_18_58); - r4bs r4bs_4640_3872(yy[19], yy[20], single[19], double[19], neg[19], pp_19_58); - r4bs r4bs_4640_4000(yy[17], yy[18], single[20], double[20], neg[20], pp_20_58); - r4bs r4bs_4640_4128(yy[15], yy[16], single[21], double[21], neg[21], pp_21_58); - fullAdd_x FA_4640_4256(int_15_58, int_14_58, pp_19_58, pp_20_58, pp_21_58); - r4bs r4bs_4640_4472(yy[13], yy[14], single[22], double[22], neg[22], pp_22_58); - r4bs r4bs_4640_4600(yy[11], yy[12], single[23], double[23], neg[23], pp_23_58); - r4bs r4bs_4640_4728(yy[9], yy[10], single[24], double[24], neg[24], pp_24_58); - fullAdd_x FA_4640_4856(int_17_58, int_16_58, pp_22_58, pp_23_58, pp_24_58); - r4bs r4bs_4640_5072(yy[7], yy[8], single[25], double[25], neg[25], pp_25_58); - r4bs r4bs_4640_5200(yy[5], yy[6], single[26], double[26], neg[26], pp_26_58); - r4bs r4bs_4640_5328(yy[3], yy[4], single[27], double[27], neg[27], pp_27_58); - fullAdd_x FA_4640_5456(int_19_58, int_18_58, pp_25_58, pp_26_58, pp_27_58); - r4bs r4bs_4640_5672(yy[1], yy[2], single[28], double[28], neg[28], pp_28_58); - r4bs r4bs_4640_5800(gnd, yy[0], single[29], double[29], neg[29], pp_29_58); - fullAdd_x FA_4640_5928(int_21_58, int_20_58, pp_28_58, pp_29_58, int_1_57); - fullAdd_x FA_4640_6144(int_23_58, int_22_58, int_3_57, int_5_57, int_7_57); - fullAdd_x FA_4640_6360(int_25_58, int_24_58, int_9_57, int_11_57, int_13_57); - fullAdd_x FA_4640_6576(int_27_58, int_26_58, int_15_57, int_17_57, int_19_57); - fullAdd_x FA_4640_6792(int_29_58, int_28_58, int_0_58, int_21_57, int_23_57); - fullAdd_x FA_4640_7008(int_31_58, int_30_58, int_25_57, int_2_58, int_4_58); - fullAdd_x FA_4640_7224(int_33_58, int_32_58, int_6_58, int_8_58, int_10_58); - fullAdd_x FA_4640_7440(int_35_58, int_34_58, int_12_58, int_14_58, int_16_58); - fullAdd_x FA_4640_7656(int_37_58, int_36_58, int_18_58, int_20_58, int_27_57); - fullAdd_x FA_4640_7872(int_39_58, int_38_58, int_29_57, int_31_57, int_33_57); - fullAdd_x FA_4640_8088(int_41_58, int_40_58, int_22_58, int_24_58, int_26_58); - fullAdd_x FA_4640_8304(int_43_58, int_42_58, int_35_57, int_37_57, int_39_57); - fullAdd_x FA_4640_8520(int_45_58, int_44_58, int_28_58, int_30_58, int_32_58); - fullAdd_x FA_4640_8736(int_47_58, int_46_58, int_34_58, int_36_58, int_41_57); - fullAdd_x FA_4640_8952(int_49_58, int_48_58, int_43_57, int_38_58, int_40_58); - fullAdd_x FA_4640_9168(int_51_58, int_50_58, int_45_57, int_47_57, int_42_58); - fullAdd_x FA_4640_9384(int_53_58, int_52_58, int_44_58, int_46_58, int_49_57); - fullAdd_x FA_4640_9600(int_55_58, int_54_58, int_48_58, int_51_57, int_50_58); - fullAdd_x FA_4640_9816(int_57_58, int_56_58, int_52_58, int_53_57, int_54_58); - assign Sum[58] = int_55_57; - assign Carry[58] = int_56_58; - - // Hardware for column 59 - - r4bs r4bs_4720_64(yy[58], yy[59], single[0], double[0], neg[0], pp_0_59); - r4bs r4bs_4720_192(yy[56], yy[57], single[1], double[1], neg[1], pp_1_59); - halfAdd HA_4720_320(int_1_59, int_0_59, pp_0_59, pp_1_59); - r4bs r4bs_4720_400(yy[54], yy[55], single[2], double[2], neg[2], pp_2_59); - r4bs r4bs_4720_528(yy[52], yy[53], single[3], double[3], neg[3], pp_3_59); - r4bs r4bs_4720_656(yy[50], yy[51], single[4], double[4], neg[4], pp_4_59); - fullAdd_x FA_4720_784(int_3_59, int_2_59, pp_2_59, pp_3_59, pp_4_59); - r4bs r4bs_4720_1000(yy[48], yy[49], single[5], double[5], neg[5], pp_5_59); - r4bs r4bs_4720_1128(yy[46], yy[47], single[6], double[6], neg[6], pp_6_59); - r4bs r4bs_4720_1256(yy[44], yy[45], single[7], double[7], neg[7], pp_7_59); - fullAdd_x FA_4720_1384(int_5_59, int_4_59, pp_5_59, pp_6_59, pp_7_59); - r4bs r4bs_4720_1600(yy[42], yy[43], single[8], double[8], neg[8], pp_8_59); - r4bs r4bs_4720_1728(yy[40], yy[41], single[9], double[9], neg[9], pp_9_59); - r4bs r4bs_4720_1856(yy[38], yy[39], single[10], double[10], neg[10], pp_10_59); - fullAdd_x FA_4720_1984(int_7_59, int_6_59, pp_8_59, pp_9_59, pp_10_59); - r4bs r4bs_4720_2200(yy[36], yy[37], single[11], double[11], neg[11], pp_11_59); - r4bs r4bs_4720_2328(yy[34], yy[35], single[12], double[12], neg[12], pp_12_59); - r4bs r4bs_4720_2456(yy[32], yy[33], single[13], double[13], neg[13], pp_13_59); - fullAdd_x FA_4720_2584(int_9_59, int_8_59, pp_11_59, pp_12_59, pp_13_59); - r4bs r4bs_4720_2800(yy[30], yy[31], single[14], double[14], neg[14], pp_14_59); - r4bs r4bs_4720_2928(yy[28], yy[29], single[15], double[15], neg[15], pp_15_59); - r4bs r4bs_4720_3056(yy[26], yy[27], single[16], double[16], neg[16], pp_16_59); - fullAdd_x FA_4720_3184(int_11_59, int_10_59, pp_14_59, pp_15_59, pp_16_59); - r4bs r4bs_4720_3400(yy[24], yy[25], single[17], double[17], neg[17], pp_17_59); - r4bs r4bs_4720_3528(yy[22], yy[23], single[18], double[18], neg[18], pp_18_59); - r4bs r4bs_4720_3656(yy[20], yy[21], single[19], double[19], neg[19], pp_19_59); - fullAdd_x FA_4720_3784(int_13_59, int_12_59, pp_17_59, pp_18_59, pp_19_59); - r4bs r4bs_4720_4000(yy[18], yy[19], single[20], double[20], neg[20], pp_20_59); - r4bs r4bs_4720_4128(yy[16], yy[17], single[21], double[21], neg[21], pp_21_59); - r4bs r4bs_4720_4256(yy[14], yy[15], single[22], double[22], neg[22], pp_22_59); - fullAdd_x FA_4720_4384(int_15_59, int_14_59, pp_20_59, pp_21_59, pp_22_59); - r4bs r4bs_4720_4600(yy[12], yy[13], single[23], double[23], neg[23], pp_23_59); - r4bs r4bs_4720_4728(yy[10], yy[11], single[24], double[24], neg[24], pp_24_59); - r4bs r4bs_4720_4856(yy[8], yy[9], single[25], double[25], neg[25], pp_25_59); - fullAdd_x FA_4720_4984(int_17_59, int_16_59, pp_23_59, pp_24_59, pp_25_59); - r4bs r4bs_4720_5200(yy[6], yy[7], single[26], double[26], neg[26], pp_26_59); - r4bs r4bs_4720_5328(yy[4], yy[5], single[27], double[27], neg[27], pp_27_59); - r4bs r4bs_4720_5456(yy[2], yy[3], single[28], double[28], neg[28], pp_28_59); - fullAdd_x FA_4720_5584(int_19_59, int_18_59, pp_26_59, pp_27_59, pp_28_59); - r4bs r4bs_4720_5800(yy[0], yy[1], single[29], double[29], neg[29], pp_29_59); - fullAdd_x FA_4720_5928(int_21_59, int_20_59, pp_29_59, int_1_58, int_3_58); - fullAdd_x FA_4720_6144(int_23_59, int_22_59, int_5_58, int_7_58, int_9_58); - fullAdd_x FA_4720_6360(int_25_59, int_24_59, int_11_58, int_13_58, int_15_58); - fullAdd_x FA_4720_6576(int_27_59, int_26_59, int_17_58, int_19_58, int_0_59); - fullAdd_x FA_4720_6792(int_29_59, int_28_59, int_21_58, int_23_58, int_25_58); - fullAdd_x FA_4720_7008(int_31_59, int_30_59, int_27_58, int_2_59, int_4_59); - fullAdd_x FA_4720_7224(int_33_59, int_32_59, int_6_59, int_8_59, int_10_59); - fullAdd_x FA_4720_7440(int_35_59, int_34_59, int_12_59, int_14_59, int_16_59); - fullAdd_x FA_4720_7656(int_37_59, int_36_59, int_18_59, int_20_59, int_29_58); - fullAdd_x FA_4720_7872(int_39_59, int_38_59, int_31_58, int_33_58, int_35_58); - fullAdd_x FA_4720_8088(int_41_59, int_40_59, int_22_59, int_24_59, int_26_59); - fullAdd_x FA_4720_8304(int_43_59, int_42_59, int_37_58, int_39_58, int_41_58); - fullAdd_x FA_4720_8520(int_45_59, int_44_59, int_28_59, int_30_59, int_32_59); - fullAdd_x FA_4720_8736(int_47_59, int_46_59, int_34_59, int_36_59, int_43_58); - fullAdd_x FA_4720_8952(int_49_59, int_48_59, int_45_58, int_38_59, int_40_59); - fullAdd_x FA_4720_9168(int_51_59, int_50_59, int_47_58, int_49_58, int_42_59); - fullAdd_x FA_4720_9384(int_53_59, int_52_59, int_44_59, int_46_59, int_51_58); - fullAdd_x FA_4720_9600(int_55_59, int_54_59, int_48_59, int_53_58, int_50_59); - fullAdd_x FA_4720_9816(int_57_59, int_56_59, int_52_59, int_55_58, int_54_59); - assign Sum[59] = int_57_58; - assign Carry[59] = int_56_59; - - // Hardware for column 60 - - r4bs r4bs_4800_64(yy[59], yy[60], single[0], double[0], neg[0], pp_0_60); - halfAdd HA_4800_192(int_1_60, int_0_60, neg[30], pp_0_60); - r4bs r4bs_4800_272(yy[57], yy[58], single[1], double[1], neg[1], pp_1_60); - r4bs r4bs_4800_400(yy[55], yy[56], single[2], double[2], neg[2], pp_2_60); - r4bs r4bs_4800_528(yy[53], yy[54], single[3], double[3], neg[3], pp_3_60); - fullAdd_x FA_4800_656(int_3_60, int_2_60, pp_1_60, pp_2_60, pp_3_60); - r4bs r4bs_4800_872(yy[51], yy[52], single[4], double[4], neg[4], pp_4_60); - r4bs r4bs_4800_1000(yy[49], yy[50], single[5], double[5], neg[5], pp_5_60); - r4bs r4bs_4800_1128(yy[47], yy[48], single[6], double[6], neg[6], pp_6_60); - fullAdd_x FA_4800_1256(int_5_60, int_4_60, pp_4_60, pp_5_60, pp_6_60); - r4bs r4bs_4800_1472(yy[45], yy[46], single[7], double[7], neg[7], pp_7_60); - r4bs r4bs_4800_1600(yy[43], yy[44], single[8], double[8], neg[8], pp_8_60); - r4bs r4bs_4800_1728(yy[41], yy[42], single[9], double[9], neg[9], pp_9_60); - fullAdd_x FA_4800_1856(int_7_60, int_6_60, pp_7_60, pp_8_60, pp_9_60); - r4bs r4bs_4800_2072(yy[39], yy[40], single[10], double[10], neg[10], pp_10_60); - r4bs r4bs_4800_2200(yy[37], yy[38], single[11], double[11], neg[11], pp_11_60); - r4bs r4bs_4800_2328(yy[35], yy[36], single[12], double[12], neg[12], pp_12_60); - fullAdd_x FA_4800_2456(int_9_60, int_8_60, pp_10_60, pp_11_60, pp_12_60); - r4bs r4bs_4800_2672(yy[33], yy[34], single[13], double[13], neg[13], pp_13_60); - r4bs r4bs_4800_2800(yy[31], yy[32], single[14], double[14], neg[14], pp_14_60); - r4bs r4bs_4800_2928(yy[29], yy[30], single[15], double[15], neg[15], pp_15_60); - fullAdd_x FA_4800_3056(int_11_60, int_10_60, pp_13_60, pp_14_60, pp_15_60); - r4bs r4bs_4800_3272(yy[27], yy[28], single[16], double[16], neg[16], pp_16_60); - r4bs r4bs_4800_3400(yy[25], yy[26], single[17], double[17], neg[17], pp_17_60); - r4bs r4bs_4800_3528(yy[23], yy[24], single[18], double[18], neg[18], pp_18_60); - fullAdd_x FA_4800_3656(int_13_60, int_12_60, pp_16_60, pp_17_60, pp_18_60); - r4bs r4bs_4800_3872(yy[21], yy[22], single[19], double[19], neg[19], pp_19_60); - r4bs r4bs_4800_4000(yy[19], yy[20], single[20], double[20], neg[20], pp_20_60); - r4bs r4bs_4800_4128(yy[17], yy[18], single[21], double[21], neg[21], pp_21_60); - fullAdd_x FA_4800_4256(int_15_60, int_14_60, pp_19_60, pp_20_60, pp_21_60); - r4bs r4bs_4800_4472(yy[15], yy[16], single[22], double[22], neg[22], pp_22_60); - r4bs r4bs_4800_4600(yy[13], yy[14], single[23], double[23], neg[23], pp_23_60); - r4bs r4bs_4800_4728(yy[11], yy[12], single[24], double[24], neg[24], pp_24_60); - fullAdd_x FA_4800_4856(int_17_60, int_16_60, pp_22_60, pp_23_60, pp_24_60); - r4bs r4bs_4800_5072(yy[9], yy[10], single[25], double[25], neg[25], pp_25_60); - r4bs r4bs_4800_5200(yy[7], yy[8], single[26], double[26], neg[26], pp_26_60); - r4bs r4bs_4800_5328(yy[5], yy[6], single[27], double[27], neg[27], pp_27_60); - fullAdd_x FA_4800_5456(int_19_60, int_18_60, pp_25_60, pp_26_60, pp_27_60); - r4bs r4bs_4800_5672(yy[3], yy[4], single[28], double[28], neg[28], pp_28_60); - r4bs r4bs_4800_5800(yy[1], yy[2], single[29], double[29], neg[29], pp_29_60); - r4bs r4bs_4800_5928(gnd, yy[0], single[30], double[30], neg[30], pp_30_60); - fullAdd_x FA_4800_6056(int_21_60, int_20_60, pp_28_60, pp_29_60, pp_30_60); - fullAdd_x FA_4800_6272(int_23_60, int_22_60, int_1_59, int_3_59, int_5_59); - fullAdd_x FA_4800_6488(int_25_60, int_24_60, int_7_59, int_9_59, int_11_59); - fullAdd_x FA_4800_6704(int_27_60, int_26_60, int_13_59, int_15_59, int_17_59); - fullAdd_x FA_4800_6920(int_29_60, int_28_60, int_19_59, int_0_60, int_21_59); - fullAdd_x FA_4800_7136(int_31_60, int_30_60, int_23_59, int_25_59, int_27_59); - fullAdd_x FA_4800_7352(int_33_60, int_32_60, int_2_60, int_4_60, int_6_60); - fullAdd_x FA_4800_7568(int_35_60, int_34_60, int_8_60, int_10_60, int_12_60); - fullAdd_x FA_4800_7784(int_37_60, int_36_60, int_14_60, int_16_60, int_18_60); - fullAdd_x FA_4800_8000(int_39_60, int_38_60, int_20_60, int_29_59, int_31_59); - fullAdd_x FA_4800_8216(int_41_60, int_40_60, int_33_59, int_35_59, int_22_60); - fullAdd_x FA_4800_8432(int_43_60, int_42_60, int_24_60, int_26_60, int_28_60); - fullAdd_x FA_4800_8648(int_45_60, int_44_60, int_37_59, int_39_59, int_41_59); - fullAdd_x FA_4800_8864(int_47_60, int_46_60, int_30_60, int_32_60, int_34_60); - fullAdd_x FA_4800_9080(int_49_60, int_48_60, int_36_60, int_43_59, int_45_59); - fullAdd_x FA_4800_9296(int_51_60, int_50_60, int_38_60, int_40_60, int_42_60); - fullAdd_x FA_4800_9512(int_53_60, int_52_60, int_47_59, int_49_59, int_44_60); - fullAdd_x FA_4800_9728(int_55_60, int_54_60, int_46_60, int_51_59, int_48_60); - fullAdd_x FA_4800_9944(int_57_60, int_56_60, int_50_60, int_53_59, int_52_60); - fullAdd_x FA_4800_10160(int_59_60, int_58_60, int_55_59, int_54_60, int_56_60); - assign Sum[60] = int_57_59; - assign Carry[60] = int_58_60; - - // Hardware for column 61 - - r4bs r4bs_4880_64(yy[60], yy[61], single[0], double[0], neg[0], pp_0_61); - r4bs r4bs_4880_192(yy[58], yy[59], single[1], double[1], neg[1], pp_1_61); - halfAdd HA_4880_320(int_1_61, int_0_61, pp_0_61, pp_1_61); - r4bs r4bs_4880_400(yy[56], yy[57], single[2], double[2], neg[2], pp_2_61); - r4bs r4bs_4880_528(yy[54], yy[55], single[3], double[3], neg[3], pp_3_61); - r4bs r4bs_4880_656(yy[52], yy[53], single[4], double[4], neg[4], pp_4_61); - fullAdd_x FA_4880_784(int_3_61, int_2_61, pp_2_61, pp_3_61, pp_4_61); - r4bs r4bs_4880_1000(yy[50], yy[51], single[5], double[5], neg[5], pp_5_61); - r4bs r4bs_4880_1128(yy[48], yy[49], single[6], double[6], neg[6], pp_6_61); - r4bs r4bs_4880_1256(yy[46], yy[47], single[7], double[7], neg[7], pp_7_61); - fullAdd_x FA_4880_1384(int_5_61, int_4_61, pp_5_61, pp_6_61, pp_7_61); - r4bs r4bs_4880_1600(yy[44], yy[45], single[8], double[8], neg[8], pp_8_61); - r4bs r4bs_4880_1728(yy[42], yy[43], single[9], double[9], neg[9], pp_9_61); - r4bs r4bs_4880_1856(yy[40], yy[41], single[10], double[10], neg[10], pp_10_61); - fullAdd_x FA_4880_1984(int_7_61, int_6_61, pp_8_61, pp_9_61, pp_10_61); - r4bs r4bs_4880_2200(yy[38], yy[39], single[11], double[11], neg[11], pp_11_61); - r4bs r4bs_4880_2328(yy[36], yy[37], single[12], double[12], neg[12], pp_12_61); - r4bs r4bs_4880_2456(yy[34], yy[35], single[13], double[13], neg[13], pp_13_61); - fullAdd_x FA_4880_2584(int_9_61, int_8_61, pp_11_61, pp_12_61, pp_13_61); - r4bs r4bs_4880_2800(yy[32], yy[33], single[14], double[14], neg[14], pp_14_61); - r4bs r4bs_4880_2928(yy[30], yy[31], single[15], double[15], neg[15], pp_15_61); - r4bs r4bs_4880_3056(yy[28], yy[29], single[16], double[16], neg[16], pp_16_61); - fullAdd_x FA_4880_3184(int_11_61, int_10_61, pp_14_61, pp_15_61, pp_16_61); - r4bs r4bs_4880_3400(yy[26], yy[27], single[17], double[17], neg[17], pp_17_61); - r4bs r4bs_4880_3528(yy[24], yy[25], single[18], double[18], neg[18], pp_18_61); - r4bs r4bs_4880_3656(yy[22], yy[23], single[19], double[19], neg[19], pp_19_61); - fullAdd_x FA_4880_3784(int_13_61, int_12_61, pp_17_61, pp_18_61, pp_19_61); - r4bs r4bs_4880_4000(yy[20], yy[21], single[20], double[20], neg[20], pp_20_61); - r4bs r4bs_4880_4128(yy[18], yy[19], single[21], double[21], neg[21], pp_21_61); - r4bs r4bs_4880_4256(yy[16], yy[17], single[22], double[22], neg[22], pp_22_61); - fullAdd_x FA_4880_4384(int_15_61, int_14_61, pp_20_61, pp_21_61, pp_22_61); - r4bs r4bs_4880_4600(yy[14], yy[15], single[23], double[23], neg[23], pp_23_61); - r4bs r4bs_4880_4728(yy[12], yy[13], single[24], double[24], neg[24], pp_24_61); - r4bs r4bs_4880_4856(yy[10], yy[11], single[25], double[25], neg[25], pp_25_61); - fullAdd_x FA_4880_4984(int_17_61, int_16_61, pp_23_61, pp_24_61, pp_25_61); - r4bs r4bs_4880_5200(yy[8], yy[9], single[26], double[26], neg[26], pp_26_61); - r4bs r4bs_4880_5328(yy[6], yy[7], single[27], double[27], neg[27], pp_27_61); - r4bs r4bs_4880_5456(yy[4], yy[5], single[28], double[28], neg[28], pp_28_61); - fullAdd_x FA_4880_5584(int_19_61, int_18_61, pp_26_61, pp_27_61, pp_28_61); - r4bs r4bs_4880_5800(yy[2], yy[3], single[29], double[29], neg[29], pp_29_61); - r4bs r4bs_4880_5928(yy[0], yy[1], single[30], double[30], neg[30], pp_30_61); - fullAdd_x FA_4880_6056(int_21_61, int_20_61, pp_29_61, pp_30_61, int_1_60); - fullAdd_x FA_4880_6272(int_23_61, int_22_61, int_3_60, int_5_60, int_7_60); - fullAdd_x FA_4880_6488(int_25_61, int_24_61, int_9_60, int_11_60, int_13_60); - fullAdd_x FA_4880_6704(int_27_61, int_26_61, int_15_60, int_17_60, int_19_60); - fullAdd_x FA_4880_6920(int_29_61, int_28_61, int_21_60, int_0_61, int_23_60); - fullAdd_x FA_4880_7136(int_31_61, int_30_61, int_25_60, int_27_60, int_2_61); - fullAdd_x FA_4880_7352(int_33_61, int_32_61, int_4_61, int_6_61, int_8_61); - fullAdd_x FA_4880_7568(int_35_61, int_34_61, int_10_61, int_12_61, int_14_61); - fullAdd_x FA_4880_7784(int_37_61, int_36_61, int_16_61, int_18_61, int_20_61); - fullAdd_x FA_4880_8000(int_39_61, int_38_61, int_29_60, int_31_60, int_33_60); - fullAdd_x FA_4880_8216(int_41_61, int_40_61, int_35_60, int_37_60, int_22_61); - fullAdd_x FA_4880_8432(int_43_61, int_42_61, int_24_61, int_26_61, int_28_61); - fullAdd_x FA_4880_8648(int_45_61, int_44_61, int_39_60, int_41_60, int_43_60); - fullAdd_x FA_4880_8864(int_47_61, int_46_61, int_30_61, int_32_61, int_34_61); - fullAdd_x FA_4880_9080(int_49_61, int_48_61, int_36_61, int_45_60, int_47_60); - fullAdd_x FA_4880_9296(int_51_61, int_50_61, int_38_61, int_40_61, int_42_61); - fullAdd_x FA_4880_9512(int_53_61, int_52_61, int_49_60, int_51_60, int_44_61); - fullAdd_x FA_4880_9728(int_55_61, int_54_61, int_46_61, int_53_60, int_48_61); - fullAdd_x FA_4880_9944(int_57_61, int_56_61, int_50_61, int_55_60, int_52_61); - fullAdd_x FA_4880_10160(int_59_61, int_58_61, int_57_60, int_54_61, int_56_61); - assign Sum[61] = int_59_60; - assign Carry[61] = int_58_61; - - // Hardware for column 62 - - r4bs r4bs_4960_64(yy[61], yy[62], single[0], double[0], neg[0], pp_0_62); - halfAdd HA_4960_192(int_1_62, int_0_62, neg[31], pp_0_62); - r4bs r4bs_4960_272(yy[59], yy[60], single[1], double[1], neg[1], pp_1_62); - r4bs r4bs_4960_400(yy[57], yy[58], single[2], double[2], neg[2], pp_2_62); - r4bs r4bs_4960_528(yy[55], yy[56], single[3], double[3], neg[3], pp_3_62); - fullAdd_x FA_4960_656(int_3_62, int_2_62, pp_1_62, pp_2_62, pp_3_62); - r4bs r4bs_4960_872(yy[53], yy[54], single[4], double[4], neg[4], pp_4_62); - r4bs r4bs_4960_1000(yy[51], yy[52], single[5], double[5], neg[5], pp_5_62); - r4bs r4bs_4960_1128(yy[49], yy[50], single[6], double[6], neg[6], pp_6_62); - fullAdd_x FA_4960_1256(int_5_62, int_4_62, pp_4_62, pp_5_62, pp_6_62); - r4bs r4bs_4960_1472(yy[47], yy[48], single[7], double[7], neg[7], pp_7_62); - r4bs r4bs_4960_1600(yy[45], yy[46], single[8], double[8], neg[8], pp_8_62); - r4bs r4bs_4960_1728(yy[43], yy[44], single[9], double[9], neg[9], pp_9_62); - fullAdd_x FA_4960_1856(int_7_62, int_6_62, pp_7_62, pp_8_62, pp_9_62); - r4bs r4bs_4960_2072(yy[41], yy[42], single[10], double[10], neg[10], pp_10_62); - r4bs r4bs_4960_2200(yy[39], yy[40], single[11], double[11], neg[11], pp_11_62); - r4bs r4bs_4960_2328(yy[37], yy[38], single[12], double[12], neg[12], pp_12_62); - fullAdd_x FA_4960_2456(int_9_62, int_8_62, pp_10_62, pp_11_62, pp_12_62); - r4bs r4bs_4960_2672(yy[35], yy[36], single[13], double[13], neg[13], pp_13_62); - r4bs r4bs_4960_2800(yy[33], yy[34], single[14], double[14], neg[14], pp_14_62); - r4bs r4bs_4960_2928(yy[31], yy[32], single[15], double[15], neg[15], pp_15_62); - fullAdd_x FA_4960_3056(int_11_62, int_10_62, pp_13_62, pp_14_62, pp_15_62); - r4bs r4bs_4960_3272(yy[29], yy[30], single[16], double[16], neg[16], pp_16_62); - r4bs r4bs_4960_3400(yy[27], yy[28], single[17], double[17], neg[17], pp_17_62); - r4bs r4bs_4960_3528(yy[25], yy[26], single[18], double[18], neg[18], pp_18_62); - fullAdd_x FA_4960_3656(int_13_62, int_12_62, pp_16_62, pp_17_62, pp_18_62); - r4bs r4bs_4960_3872(yy[23], yy[24], single[19], double[19], neg[19], pp_19_62); - r4bs r4bs_4960_4000(yy[21], yy[22], single[20], double[20], neg[20], pp_20_62); - r4bs r4bs_4960_4128(yy[19], yy[20], single[21], double[21], neg[21], pp_21_62); - fullAdd_x FA_4960_4256(int_15_62, int_14_62, pp_19_62, pp_20_62, pp_21_62); - r4bs r4bs_4960_4472(yy[17], yy[18], single[22], double[22], neg[22], pp_22_62); - r4bs r4bs_4960_4600(yy[15], yy[16], single[23], double[23], neg[23], pp_23_62); - r4bs r4bs_4960_4728(yy[13], yy[14], single[24], double[24], neg[24], pp_24_62); - fullAdd_x FA_4960_4856(int_17_62, int_16_62, pp_22_62, pp_23_62, pp_24_62); - r4bs r4bs_4960_5072(yy[11], yy[12], single[25], double[25], neg[25], pp_25_62); - r4bs r4bs_4960_5200(yy[9], yy[10], single[26], double[26], neg[26], pp_26_62); - r4bs r4bs_4960_5328(yy[7], yy[8], single[27], double[27], neg[27], pp_27_62); - fullAdd_x FA_4960_5456(int_19_62, int_18_62, pp_25_62, pp_26_62, pp_27_62); - r4bs r4bs_4960_5672(yy[5], yy[6], single[28], double[28], neg[28], pp_28_62); - r4bs r4bs_4960_5800(yy[3], yy[4], single[29], double[29], neg[29], pp_29_62); - r4bs r4bs_4960_5928(yy[1], yy[2], single[30], double[30], neg[30], pp_30_62); - fullAdd_x FA_4960_6056(int_21_62, int_20_62, pp_28_62, pp_29_62, pp_30_62); - r4bs r4bs_4960_6272(gnd, yy[0], single[31], double[31], neg[31], pp_31_62); - fullAdd_x FA_4960_6400(int_23_62, int_22_62, pp_31_62, int_1_61, int_3_61); - fullAdd_x FA_4960_6616(int_25_62, int_24_62, int_5_61, int_7_61, int_9_61); - fullAdd_x FA_4960_6832(int_27_62, int_26_62, int_11_61, int_13_61, int_15_61); - fullAdd_x FA_4960_7048(int_29_62, int_28_62, int_17_61, int_19_61, int_0_62); - fullAdd_x FA_4960_7264(int_31_62, int_30_62, int_21_61, int_23_61, int_25_61); - fullAdd_x FA_4960_7480(int_33_62, int_32_62, int_27_61, int_2_62, int_4_62); - fullAdd_x FA_4960_7696(int_35_62, int_34_62, int_6_62, int_8_62, int_10_62); - fullAdd_x FA_4960_7912(int_37_62, int_36_62, int_12_62, int_14_62, int_16_62); - fullAdd_x FA_4960_8128(int_39_62, int_38_62, int_18_62, int_20_62, int_22_62); - fullAdd_x FA_4960_8344(int_41_62, int_40_62, int_29_61, int_31_61, int_33_61); - fullAdd_x FA_4960_8560(int_43_62, int_42_62, int_35_61, int_37_61, int_24_62); - fullAdd_x FA_4960_8776(int_45_62, int_44_62, int_26_62, int_28_62, int_39_61); - fullAdd_x FA_4960_8992(int_47_62, int_46_62, int_41_61, int_43_61, int_30_62); - fullAdd_x FA_4960_9208(int_49_62, int_48_62, int_32_62, int_34_62, int_36_62); - fullAdd_x FA_4960_9424(int_51_62, int_50_62, int_38_62, int_45_61, int_47_61); - fullAdd_x FA_4960_9640(int_53_62, int_52_62, int_40_62, int_42_62, int_44_62); - fullAdd_x FA_4960_9856(int_55_62, int_54_62, int_49_61, int_51_61, int_46_62); - fullAdd_x FA_4960_10072(int_57_62, int_56_62, int_48_62, int_53_61, int_50_62); - fullAdd_x FA_4960_10288(int_59_62, int_58_62, int_52_62, int_55_61, int_54_62); - fullAdd_x FA_4960_10504(int_61_62, int_60_62, int_57_61, int_56_62, int_58_62); - assign Sum[62] = int_59_61; - assign Carry[62] = int_60_62; - - // Hardware for column 63 - - r4bs r4bs_5040_64(yy[62], yy[63], single[0], double[0], neg[0], pp_0_63); - r4bs r4bs_5040_192(yy[60], yy[61], single[1], double[1], neg[1], pp_1_63); - halfAdd HA_5040_320(int_1_63, int_0_63, pp_0_63, pp_1_63); - r4bs r4bs_5040_400(yy[58], yy[59], single[2], double[2], neg[2], pp_2_63); - r4bs r4bs_5040_528(yy[56], yy[57], single[3], double[3], neg[3], pp_3_63); - r4bs r4bs_5040_656(yy[54], yy[55], single[4], double[4], neg[4], pp_4_63); - fullAdd_x FA_5040_784(int_3_63, int_2_63, pp_2_63, pp_3_63, pp_4_63); - r4bs r4bs_5040_1000(yy[52], yy[53], single[5], double[5], neg[5], pp_5_63); - r4bs r4bs_5040_1128(yy[50], yy[51], single[6], double[6], neg[6], pp_6_63); - r4bs r4bs_5040_1256(yy[48], yy[49], single[7], double[7], neg[7], pp_7_63); - fullAdd_x FA_5040_1384(int_5_63, int_4_63, pp_5_63, pp_6_63, pp_7_63); - r4bs r4bs_5040_1600(yy[46], yy[47], single[8], double[8], neg[8], pp_8_63); - r4bs r4bs_5040_1728(yy[44], yy[45], single[9], double[9], neg[9], pp_9_63); - r4bs r4bs_5040_1856(yy[42], yy[43], single[10], double[10], neg[10], pp_10_63); - fullAdd_x FA_5040_1984(int_7_63, int_6_63, pp_8_63, pp_9_63, pp_10_63); - r4bs r4bs_5040_2200(yy[40], yy[41], single[11], double[11], neg[11], pp_11_63); - r4bs r4bs_5040_2328(yy[38], yy[39], single[12], double[12], neg[12], pp_12_63); - r4bs r4bs_5040_2456(yy[36], yy[37], single[13], double[13], neg[13], pp_13_63); - fullAdd_x FA_5040_2584(int_9_63, int_8_63, pp_11_63, pp_12_63, pp_13_63); - r4bs r4bs_5040_2800(yy[34], yy[35], single[14], double[14], neg[14], pp_14_63); - r4bs r4bs_5040_2928(yy[32], yy[33], single[15], double[15], neg[15], pp_15_63); - r4bs r4bs_5040_3056(yy[30], yy[31], single[16], double[16], neg[16], pp_16_63); - fullAdd_x FA_5040_3184(int_11_63, int_10_63, pp_14_63, pp_15_63, pp_16_63); - r4bs r4bs_5040_3400(yy[28], yy[29], single[17], double[17], neg[17], pp_17_63); - r4bs r4bs_5040_3528(yy[26], yy[27], single[18], double[18], neg[18], pp_18_63); - r4bs r4bs_5040_3656(yy[24], yy[25], single[19], double[19], neg[19], pp_19_63); - fullAdd_x FA_5040_3784(int_13_63, int_12_63, pp_17_63, pp_18_63, pp_19_63); - r4bs r4bs_5040_4000(yy[22], yy[23], single[20], double[20], neg[20], pp_20_63); - r4bs r4bs_5040_4128(yy[20], yy[21], single[21], double[21], neg[21], pp_21_63); - r4bs r4bs_5040_4256(yy[18], yy[19], single[22], double[22], neg[22], pp_22_63); - fullAdd_x FA_5040_4384(int_15_63, int_14_63, pp_20_63, pp_21_63, pp_22_63); - r4bs r4bs_5040_4600(yy[16], yy[17], single[23], double[23], neg[23], pp_23_63); - r4bs r4bs_5040_4728(yy[14], yy[15], single[24], double[24], neg[24], pp_24_63); - r4bs r4bs_5040_4856(yy[12], yy[13], single[25], double[25], neg[25], pp_25_63); - fullAdd_x FA_5040_4984(int_17_63, int_16_63, pp_23_63, pp_24_63, pp_25_63); - r4bs r4bs_5040_5200(yy[10], yy[11], single[26], double[26], neg[26], pp_26_63); - r4bs r4bs_5040_5328(yy[8], yy[9], single[27], double[27], neg[27], pp_27_63); - r4bs r4bs_5040_5456(yy[6], yy[7], single[28], double[28], neg[28], pp_28_63); - fullAdd_x FA_5040_5584(int_19_63, int_18_63, pp_26_63, pp_27_63, pp_28_63); - r4bs r4bs_5040_5800(yy[4], yy[5], single[29], double[29], neg[29], pp_29_63); - r4bs r4bs_5040_5928(yy[2], yy[3], single[30], double[30], neg[30], pp_30_63); - r4bs r4bs_5040_6056(yy[0], yy[1], single[31], double[31], neg[31], pp_31_63); - fullAdd_x FA_5040_6184(int_21_63, int_20_63, pp_29_63, pp_30_63, pp_31_63); - fullAdd_x FA_5040_6400(int_23_63, int_22_63, int_1_62, int_3_62, int_5_62); - fullAdd_x FA_5040_6616(int_25_63, int_24_63, int_7_62, int_9_62, int_11_62); - fullAdd_x FA_5040_6832(int_27_63, int_26_63, int_13_62, int_15_62, int_17_62); - fullAdd_x FA_5040_7048(int_29_63, int_28_63, int_19_62, int_21_62, int_0_63); - fullAdd_x FA_5040_7264(int_31_63, int_30_63, int_23_62, int_25_62, int_27_62); - fullAdd_x FA_5040_7480(int_33_63, int_32_63, int_29_62, int_2_63, int_4_63); - fullAdd_x FA_5040_7696(int_35_63, int_34_63, int_6_63, int_8_63, int_10_63); - fullAdd_x FA_5040_7912(int_37_63, int_36_63, int_12_63, int_14_63, int_16_63); - fullAdd_x FA_5040_8128(int_39_63, int_38_63, int_18_63, int_20_63, int_31_62); - fullAdd_x FA_5040_8344(int_41_63, int_40_63, int_33_62, int_35_62, int_37_62); - fullAdd_x FA_5040_8560(int_43_63, int_42_63, int_22_63, int_24_63, int_26_63); - fullAdd_x FA_5040_8776(int_45_63, int_44_63, int_28_63, int_39_62, int_41_62); - fullAdd_x FA_5040_8992(int_47_63, int_46_63, int_43_62, int_30_63, int_32_63); - fullAdd_x FA_5040_9208(int_49_63, int_48_63, int_34_63, int_36_63, int_38_63); - fullAdd_x FA_5040_9424(int_51_63, int_50_63, int_45_62, int_47_62, int_49_62); - fullAdd_x FA_5040_9640(int_53_63, int_52_63, int_40_63, int_42_63, int_44_63); - fullAdd_x FA_5040_9856(int_55_63, int_54_63, int_51_62, int_53_62, int_46_63); - fullAdd_x FA_5040_10072(int_57_63, int_56_63, int_48_63, int_55_62, int_50_63); - fullAdd_x FA_5040_10288(int_59_63, int_58_63, int_52_63, int_57_62, int_54_63); - fullAdd_x FA_5040_10504(int_61_63, int_60_63, int_59_62, int_56_63, int_58_63); - assign Sum[63] = int_61_62; - assign Carry[63] = int_60_63; - - // Hardware for column 64 - - r4bs r4bs_5120_0(yy[63], gnd, single[0], double[0], neg[0], pp_0_64); - r4bs r4bs_5120_128(yy[61], yy[62], single[1], double[1], neg[1], pp_1_64); - r4bs r4bs_5120_256(yy[59], yy[60], single[2], double[2], neg[2], pp_2_64); - fullAdd_x FA_5120_384(int_1_64, int_0_64, pp_0_64, pp_1_64, pp_2_64); - r4bs r4bs_5120_600(yy[57], yy[58], single[3], double[3], neg[3], pp_3_64); - r4bs r4bs_5120_728(yy[55], yy[56], single[4], double[4], neg[4], pp_4_64); - r4bs r4bs_5120_856(yy[53], yy[54], single[5], double[5], neg[5], pp_5_64); - fullAdd_x FA_5120_984(int_3_64, int_2_64, pp_3_64, pp_4_64, pp_5_64); - r4bs r4bs_5120_1200(yy[51], yy[52], single[6], double[6], neg[6], pp_6_64); - r4bs r4bs_5120_1328(yy[49], yy[50], single[7], double[7], neg[7], pp_7_64); - r4bs r4bs_5120_1456(yy[47], yy[48], single[8], double[8], neg[8], pp_8_64); - fullAdd_x FA_5120_1584(int_5_64, int_4_64, pp_6_64, pp_7_64, pp_8_64); - r4bs r4bs_5120_1800(yy[45], yy[46], single[9], double[9], neg[9], pp_9_64); - r4bs r4bs_5120_1928(yy[43], yy[44], single[10], double[10], neg[10], pp_10_64); - r4bs r4bs_5120_2056(yy[41], yy[42], single[11], double[11], neg[11], pp_11_64); - fullAdd_x FA_5120_2184(int_7_64, int_6_64, pp_9_64, pp_10_64, pp_11_64); - r4bs r4bs_5120_2400(yy[39], yy[40], single[12], double[12], neg[12], pp_12_64); - r4bs r4bs_5120_2528(yy[37], yy[38], single[13], double[13], neg[13], pp_13_64); - r4bs r4bs_5120_2656(yy[35], yy[36], single[14], double[14], neg[14], pp_14_64); - fullAdd_x FA_5120_2784(int_9_64, int_8_64, pp_12_64, pp_13_64, pp_14_64); - r4bs r4bs_5120_3000(yy[33], yy[34], single[15], double[15], neg[15], pp_15_64); - r4bs r4bs_5120_3128(yy[31], yy[32], single[16], double[16], neg[16], pp_16_64); - r4bs r4bs_5120_3256(yy[29], yy[30], single[17], double[17], neg[17], pp_17_64); - fullAdd_x FA_5120_3384(int_11_64, int_10_64, pp_15_64, pp_16_64, pp_17_64); - r4bs r4bs_5120_3600(yy[27], yy[28], single[18], double[18], neg[18], pp_18_64); - r4bs r4bs_5120_3728(yy[25], yy[26], single[19], double[19], neg[19], pp_19_64); - r4bs r4bs_5120_3856(yy[23], yy[24], single[20], double[20], neg[20], pp_20_64); - fullAdd_x FA_5120_3984(int_13_64, int_12_64, pp_18_64, pp_19_64, pp_20_64); - r4bs r4bs_5120_4200(yy[21], yy[22], single[21], double[21], neg[21], pp_21_64); - r4bs r4bs_5120_4328(yy[19], yy[20], single[22], double[22], neg[22], pp_22_64); - r4bs r4bs_5120_4456(yy[17], yy[18], single[23], double[23], neg[23], pp_23_64); - fullAdd_x FA_5120_4584(int_15_64, int_14_64, pp_21_64, pp_22_64, pp_23_64); - r4bs r4bs_5120_4800(yy[15], yy[16], single[24], double[24], neg[24], pp_24_64); - r4bs r4bs_5120_4928(yy[13], yy[14], single[25], double[25], neg[25], pp_25_64); - r4bs r4bs_5120_5056(yy[11], yy[12], single[26], double[26], neg[26], pp_26_64); - fullAdd_x FA_5120_5184(int_17_64, int_16_64, pp_24_64, pp_25_64, pp_26_64); - r4bs r4bs_5120_5400(yy[9], yy[10], single[27], double[27], neg[27], pp_27_64); - r4bs r4bs_5120_5528(yy[7], yy[8], single[28], double[28], neg[28], pp_28_64); - r4bs r4bs_5120_5656(yy[5], yy[6], single[29], double[29], neg[29], pp_29_64); - fullAdd_x FA_5120_5784(int_19_64, int_18_64, pp_27_64, pp_28_64, pp_29_64); - r4bs r4bs_5120_6000(yy[3], yy[4], single[30], double[30], neg[30], pp_30_64); - r4bs r4bs_5120_6128(yy[1], yy[2], single[31], double[31], neg[31], pp_31_64); - r4bs r4bs_5120_6256(gnd, yy[0], single[32], double[32], neg[32], pp_32_64); - fullAdd_x FA_5120_6384(int_21_64, int_20_64, pp_30_64, pp_31_64, pp_32_64); - fullAdd_x FA_5120_6600(int_23_64, int_22_64, int_1_63, int_3_63, int_5_63); - fullAdd_x FA_5120_6816(int_25_64, int_24_64, int_7_63, int_9_63, int_11_63); - fullAdd_x FA_5120_7032(int_27_64, int_26_64, int_13_63, int_15_63, int_17_63); - fullAdd_x FA_5120_7248(int_29_64, int_28_64, int_19_63, int_21_63, int_23_63); - fullAdd_x FA_5120_7464(int_31_64, int_30_64, int_25_63, int_27_63, int_29_63); - fullAdd_x FA_5120_7680(int_33_64, int_32_64, int_0_64, int_2_64, int_4_64); - fullAdd_x FA_5120_7896(int_35_64, int_34_64, int_6_64, int_8_64, int_10_64); - fullAdd_x FA_5120_8112(int_37_64, int_36_64, int_12_64, int_14_64, int_16_64); - fullAdd_x FA_5120_8328(int_39_64, int_38_64, int_18_64, int_20_64, int_31_63); - fullAdd_x FA_5120_8544(int_41_64, int_40_64, int_33_63, int_35_63, int_37_63); - fullAdd_x FA_5120_8760(int_43_64, int_42_64, int_22_64, int_24_64, int_26_64); - fullAdd_x FA_5120_8976(int_45_64, int_44_64, int_28_64, int_39_63, int_41_63); - fullAdd_x FA_5120_9192(int_47_64, int_46_64, int_43_63, int_30_64, int_32_64); - fullAdd_x FA_5120_9408(int_49_64, int_48_64, int_34_64, int_36_64, int_38_64); - fullAdd_x FA_5120_9624(int_51_64, int_50_64, int_45_63, int_47_63, int_49_63); - fullAdd_x FA_5120_9840(int_53_64, int_52_64, int_40_64, int_42_64, int_51_63); - fullAdd_x FA_5120_10056(int_55_64, int_54_64, int_44_64, int_46_64, int_48_64); - fullAdd_x FA_5120_10272(int_57_64, int_56_64, int_53_63, int_55_63, int_50_64); - fullAdd_x FA_5120_10488(int_59_64, int_58_64, int_52_64, int_57_63, int_54_64); - fullAdd_x FA_5120_10704(int_61_64, int_60_64, int_59_63, int_56_64, int_58_64); - assign Sum[64] = int_61_63; - assign Carry[64] = int_60_64; - - // Hardware for column 65 - - r4bs r4bs_5200_0(yy[62], yy[63], single[1], double[1], neg[1], pp_1_65); - r4bs r4bs_5200_128(yy[60], yy[61], single[2], double[2], neg[2], pp_2_65); - fullAdd_x FA_5200_256(int_1_65, int_0_65, neg[0], pp_1_65, pp_2_65); - r4bs r4bs_5200_472(yy[58], yy[59], single[3], double[3], neg[3], pp_3_65); - r4bs r4bs_5200_600(yy[56], yy[57], single[4], double[4], neg[4], pp_4_65); - r4bs r4bs_5200_728(yy[54], yy[55], single[5], double[5], neg[5], pp_5_65); - fullAdd_x FA_5200_856(int_3_65, int_2_65, pp_3_65, pp_4_65, pp_5_65); - r4bs r4bs_5200_1072(yy[52], yy[53], single[6], double[6], neg[6], pp_6_65); - r4bs r4bs_5200_1200(yy[50], yy[51], single[7], double[7], neg[7], pp_7_65); - r4bs r4bs_5200_1328(yy[48], yy[49], single[8], double[8], neg[8], pp_8_65); - fullAdd_x FA_5200_1456(int_5_65, int_4_65, pp_6_65, pp_7_65, pp_8_65); - r4bs r4bs_5200_1672(yy[46], yy[47], single[9], double[9], neg[9], pp_9_65); - r4bs r4bs_5200_1800(yy[44], yy[45], single[10], double[10], neg[10], pp_10_65); - r4bs r4bs_5200_1928(yy[42], yy[43], single[11], double[11], neg[11], pp_11_65); - fullAdd_x FA_5200_2056(int_7_65, int_6_65, pp_9_65, pp_10_65, pp_11_65); - r4bs r4bs_5200_2272(yy[40], yy[41], single[12], double[12], neg[12], pp_12_65); - r4bs r4bs_5200_2400(yy[38], yy[39], single[13], double[13], neg[13], pp_13_65); - r4bs r4bs_5200_2528(yy[36], yy[37], single[14], double[14], neg[14], pp_14_65); - fullAdd_x FA_5200_2656(int_9_65, int_8_65, pp_12_65, pp_13_65, pp_14_65); - r4bs r4bs_5200_2872(yy[34], yy[35], single[15], double[15], neg[15], pp_15_65); - r4bs r4bs_5200_3000(yy[32], yy[33], single[16], double[16], neg[16], pp_16_65); - r4bs r4bs_5200_3128(yy[30], yy[31], single[17], double[17], neg[17], pp_17_65); - fullAdd_x FA_5200_3256(int_11_65, int_10_65, pp_15_65, pp_16_65, pp_17_65); - r4bs r4bs_5200_3472(yy[28], yy[29], single[18], double[18], neg[18], pp_18_65); - r4bs r4bs_5200_3600(yy[26], yy[27], single[19], double[19], neg[19], pp_19_65); - r4bs r4bs_5200_3728(yy[24], yy[25], single[20], double[20], neg[20], pp_20_65); - fullAdd_x FA_5200_3856(int_13_65, int_12_65, pp_18_65, pp_19_65, pp_20_65); - r4bs r4bs_5200_4072(yy[22], yy[23], single[21], double[21], neg[21], pp_21_65); - r4bs r4bs_5200_4200(yy[20], yy[21], single[22], double[22], neg[22], pp_22_65); - r4bs r4bs_5200_4328(yy[18], yy[19], single[23], double[23], neg[23], pp_23_65); - fullAdd_x FA_5200_4456(int_15_65, int_14_65, pp_21_65, pp_22_65, pp_23_65); - r4bs r4bs_5200_4672(yy[16], yy[17], single[24], double[24], neg[24], pp_24_65); - r4bs r4bs_5200_4800(yy[14], yy[15], single[25], double[25], neg[25], pp_25_65); - r4bs r4bs_5200_4928(yy[12], yy[13], single[26], double[26], neg[26], pp_26_65); - fullAdd_x FA_5200_5056(int_17_65, int_16_65, pp_24_65, pp_25_65, pp_26_65); - r4bs r4bs_5200_5272(yy[10], yy[11], single[27], double[27], neg[27], pp_27_65); - r4bs r4bs_5200_5400(yy[8], yy[9], single[28], double[28], neg[28], pp_28_65); - r4bs r4bs_5200_5528(yy[6], yy[7], single[29], double[29], neg[29], pp_29_65); - fullAdd_x FA_5200_5656(int_19_65, int_18_65, pp_27_65, pp_28_65, pp_29_65); - r4bs r4bs_5200_5872(yy[4], yy[5], single[30], double[30], neg[30], pp_30_65); - r4bs r4bs_5200_6000(yy[2], yy[3], single[31], double[31], neg[31], pp_31_65); - r4bs r4bs_5200_6128(yy[0], yy[1], single[32], double[32], neg[32], pp_32_65); - fullAdd_x FA_5200_6256(int_21_65, int_20_65, pp_30_65, pp_31_65, pp_32_65); - fullAdd_x FA_5200_6472(int_23_65, int_22_65, int_1_64, int_3_64, int_5_64); - fullAdd_x FA_5200_6688(int_25_65, int_24_65, int_7_64, int_9_64, int_11_64); - fullAdd_x FA_5200_6904(int_27_65, int_26_65, int_13_64, int_15_64, int_17_64); - fullAdd_x FA_5200_7120(int_29_65, int_28_65, int_19_64, int_21_64, int_23_64); - fullAdd_x FA_5200_7336(int_31_65, int_30_65, int_25_64, int_27_64, int_0_65); - fullAdd_x FA_5200_7552(int_33_65, int_32_65, int_2_65, int_4_65, int_6_65); - fullAdd_x FA_5200_7768(int_35_65, int_34_65, int_8_65, int_10_65, int_12_65); - fullAdd_x FA_5200_7984(int_37_65, int_36_65, int_14_65, int_16_65, int_18_65); - fullAdd_x FA_5200_8200(int_39_65, int_38_65, int_20_65, int_29_64, int_31_64); - fullAdd_x FA_5200_8416(int_41_65, int_40_65, int_33_64, int_35_64, int_37_64); - fullAdd_x FA_5200_8632(int_43_65, int_42_65, int_22_65, int_24_65, int_26_65); - fullAdd_x FA_5200_8848(int_45_65, int_44_65, int_28_65, int_39_64, int_41_64); - fullAdd_x FA_5200_9064(int_47_65, int_46_65, int_43_64, int_30_65, int_32_65); - fullAdd_x FA_5200_9280(int_49_65, int_48_65, int_34_65, int_36_65, int_45_64); - fullAdd_x FA_5200_9496(int_51_65, int_50_65, int_47_64, int_49_64, int_38_65); - fullAdd_x FA_5200_9712(int_53_65, int_52_65, int_40_65, int_42_65, int_51_64); - fullAdd_x FA_5200_9928(int_55_65, int_54_65, int_44_65, int_46_65, int_48_65); - fullAdd_x FA_5200_10144(int_57_65, int_56_65, int_53_64, int_55_64, int_50_65); - fullAdd_x FA_5200_10360(int_59_65, int_58_65, int_52_65, int_57_64, int_54_65); - fullAdd_x FA_5200_10576(int_61_65, int_60_65, int_59_64, int_56_65, int_58_65); - assign Sum[65] = int_61_64; - assign Carry[65] = int_60_65; - - // Hardware for column 66 - - r4bs r4bs_5280_0(yy[63], gnd, single[1], double[1], neg[1], pp_1_66); - r4bs r4bs_5280_128(yy[61], yy[62], single[2], double[2], neg[2], pp_2_66); - fullAdd_x FA_5280_256(int_1_66, int_0_66, neg[0], pp_1_66, pp_2_66); - r4bs r4bs_5280_472(yy[59], yy[60], single[3], double[3], neg[3], pp_3_66); - r4bs r4bs_5280_600(yy[57], yy[58], single[4], double[4], neg[4], pp_4_66); - r4bs r4bs_5280_728(yy[55], yy[56], single[5], double[5], neg[5], pp_5_66); - fullAdd_x FA_5280_856(int_3_66, int_2_66, pp_3_66, pp_4_66, pp_5_66); - r4bs r4bs_5280_1072(yy[53], yy[54], single[6], double[6], neg[6], pp_6_66); - r4bs r4bs_5280_1200(yy[51], yy[52], single[7], double[7], neg[7], pp_7_66); - r4bs r4bs_5280_1328(yy[49], yy[50], single[8], double[8], neg[8], pp_8_66); - fullAdd_x FA_5280_1456(int_5_66, int_4_66, pp_6_66, pp_7_66, pp_8_66); - r4bs r4bs_5280_1672(yy[47], yy[48], single[9], double[9], neg[9], pp_9_66); - r4bs r4bs_5280_1800(yy[45], yy[46], single[10], double[10], neg[10], pp_10_66); - r4bs r4bs_5280_1928(yy[43], yy[44], single[11], double[11], neg[11], pp_11_66); - fullAdd_x FA_5280_2056(int_7_66, int_6_66, pp_9_66, pp_10_66, pp_11_66); - r4bs r4bs_5280_2272(yy[41], yy[42], single[12], double[12], neg[12], pp_12_66); - r4bs r4bs_5280_2400(yy[39], yy[40], single[13], double[13], neg[13], pp_13_66); - r4bs r4bs_5280_2528(yy[37], yy[38], single[14], double[14], neg[14], pp_14_66); - fullAdd_x FA_5280_2656(int_9_66, int_8_66, pp_12_66, pp_13_66, pp_14_66); - r4bs r4bs_5280_2872(yy[35], yy[36], single[15], double[15], neg[15], pp_15_66); - r4bs r4bs_5280_3000(yy[33], yy[34], single[16], double[16], neg[16], pp_16_66); - r4bs r4bs_5280_3128(yy[31], yy[32], single[17], double[17], neg[17], pp_17_66); - fullAdd_x FA_5280_3256(int_11_66, int_10_66, pp_15_66, pp_16_66, pp_17_66); - r4bs r4bs_5280_3472(yy[29], yy[30], single[18], double[18], neg[18], pp_18_66); - r4bs r4bs_5280_3600(yy[27], yy[28], single[19], double[19], neg[19], pp_19_66); - r4bs r4bs_5280_3728(yy[25], yy[26], single[20], double[20], neg[20], pp_20_66); - fullAdd_x FA_5280_3856(int_13_66, int_12_66, pp_18_66, pp_19_66, pp_20_66); - r4bs r4bs_5280_4072(yy[23], yy[24], single[21], double[21], neg[21], pp_21_66); - r4bs r4bs_5280_4200(yy[21], yy[22], single[22], double[22], neg[22], pp_22_66); - r4bs r4bs_5280_4328(yy[19], yy[20], single[23], double[23], neg[23], pp_23_66); - fullAdd_x FA_5280_4456(int_15_66, int_14_66, pp_21_66, pp_22_66, pp_23_66); - r4bs r4bs_5280_4672(yy[17], yy[18], single[24], double[24], neg[24], pp_24_66); - r4bs r4bs_5280_4800(yy[15], yy[16], single[25], double[25], neg[25], pp_25_66); - r4bs r4bs_5280_4928(yy[13], yy[14], single[26], double[26], neg[26], pp_26_66); - fullAdd_x FA_5280_5056(int_17_66, int_16_66, pp_24_66, pp_25_66, pp_26_66); - r4bs r4bs_5280_5272(yy[11], yy[12], single[27], double[27], neg[27], pp_27_66); - r4bs r4bs_5280_5400(yy[9], yy[10], single[28], double[28], neg[28], pp_28_66); - r4bs r4bs_5280_5528(yy[7], yy[8], single[29], double[29], neg[29], pp_29_66); - fullAdd_x FA_5280_5656(int_19_66, int_18_66, pp_27_66, pp_28_66, pp_29_66); - r4bs r4bs_5280_5872(yy[5], yy[6], single[30], double[30], neg[30], pp_30_66); - r4bs r4bs_5280_6000(yy[3], yy[4], single[31], double[31], neg[31], pp_31_66); - r4bs r4bs_5280_6128(yy[1], yy[2], single[32], double[32], neg[32], pp_32_66); - fullAdd_x FA_5280_6256(int_21_66, int_20_66, pp_30_66, pp_31_66, pp_32_66); - fullAdd_x FA_5280_6472(int_23_66, int_22_66, int_1_65, int_3_65, int_5_65); - fullAdd_x FA_5280_6688(int_25_66, int_24_66, int_7_65, int_9_65, int_11_65); - fullAdd_x FA_5280_6904(int_27_66, int_26_66, int_13_65, int_15_65, int_17_65); - fullAdd_x FA_5280_7120(int_29_66, int_28_66, int_19_65, int_21_65, int_23_65); - fullAdd_x FA_5280_7336(int_31_66, int_30_66, int_25_65, int_27_65, int_0_66); - fullAdd_x FA_5280_7552(int_33_66, int_32_66, int_2_66, int_4_66, int_6_66); - fullAdd_x FA_5280_7768(int_35_66, int_34_66, int_8_66, int_10_66, int_12_66); - fullAdd_x FA_5280_7984(int_37_66, int_36_66, int_14_66, int_16_66, int_18_66); - fullAdd_x FA_5280_8200(int_39_66, int_38_66, int_20_66, int_29_65, int_31_65); - fullAdd_x FA_5280_8416(int_41_66, int_40_66, int_33_65, int_35_65, int_37_65); - fullAdd_x FA_5280_8632(int_43_66, int_42_66, int_22_66, int_24_66, int_26_66); - fullAdd_x FA_5280_8848(int_45_66, int_44_66, int_28_66, int_39_65, int_41_65); - fullAdd_x FA_5280_9064(int_47_66, int_46_66, int_43_65, int_30_66, int_32_66); - fullAdd_x FA_5280_9280(int_49_66, int_48_66, int_34_66, int_36_66, int_45_65); - fullAdd_x FA_5280_9496(int_51_66, int_50_66, int_47_65, int_38_66, int_40_66); - fullAdd_x FA_5280_9712(int_53_66, int_52_66, int_42_66, int_49_65, int_51_65); - fullAdd_x FA_5280_9928(int_55_66, int_54_66, int_44_66, int_46_66, int_48_66); - fullAdd_x FA_5280_10144(int_57_66, int_56_66, int_53_65, int_55_65, int_50_66); - fullAdd_x FA_5280_10360(int_59_66, int_58_66, int_57_65, int_52_66, int_54_66); - fullAdd_x FA_5280_10576(int_61_66, int_60_66, int_59_65, int_56_66, int_58_66); - assign Sum[66] = int_61_65; - assign Carry[66] = int_60_66; - - // Hardware for column 67 - - r4bs r4bs_5360_0(yy[62], yy[63], single[2], double[2], neg[2], pp_2_67); - fullAdd_x FA_5360_128(int_1_67, int_0_67, negbar[0], negbar[1], pp_2_67); - r4bs r4bs_5360_344(yy[60], yy[61], single[3], double[3], neg[3], pp_3_67); - r4bs r4bs_5360_472(yy[58], yy[59], single[4], double[4], neg[4], pp_4_67); - r4bs r4bs_5360_600(yy[56], yy[57], single[5], double[5], neg[5], pp_5_67); - fullAdd_x FA_5360_728(int_3_67, int_2_67, pp_3_67, pp_4_67, pp_5_67); - r4bs r4bs_5360_944(yy[54], yy[55], single[6], double[6], neg[6], pp_6_67); - r4bs r4bs_5360_1072(yy[52], yy[53], single[7], double[7], neg[7], pp_7_67); - r4bs r4bs_5360_1200(yy[50], yy[51], single[8], double[8], neg[8], pp_8_67); - fullAdd_x FA_5360_1328(int_5_67, int_4_67, pp_6_67, pp_7_67, pp_8_67); - r4bs r4bs_5360_1544(yy[48], yy[49], single[9], double[9], neg[9], pp_9_67); - r4bs r4bs_5360_1672(yy[46], yy[47], single[10], double[10], neg[10], pp_10_67); - r4bs r4bs_5360_1800(yy[44], yy[45], single[11], double[11], neg[11], pp_11_67); - fullAdd_x FA_5360_1928(int_7_67, int_6_67, pp_9_67, pp_10_67, pp_11_67); - r4bs r4bs_5360_2144(yy[42], yy[43], single[12], double[12], neg[12], pp_12_67); - r4bs r4bs_5360_2272(yy[40], yy[41], single[13], double[13], neg[13], pp_13_67); - r4bs r4bs_5360_2400(yy[38], yy[39], single[14], double[14], neg[14], pp_14_67); - fullAdd_x FA_5360_2528(int_9_67, int_8_67, pp_12_67, pp_13_67, pp_14_67); - r4bs r4bs_5360_2744(yy[36], yy[37], single[15], double[15], neg[15], pp_15_67); - r4bs r4bs_5360_2872(yy[34], yy[35], single[16], double[16], neg[16], pp_16_67); - r4bs r4bs_5360_3000(yy[32], yy[33], single[17], double[17], neg[17], pp_17_67); - fullAdd_x FA_5360_3128(int_11_67, int_10_67, pp_15_67, pp_16_67, pp_17_67); - r4bs r4bs_5360_3344(yy[30], yy[31], single[18], double[18], neg[18], pp_18_67); - r4bs r4bs_5360_3472(yy[28], yy[29], single[19], double[19], neg[19], pp_19_67); - r4bs r4bs_5360_3600(yy[26], yy[27], single[20], double[20], neg[20], pp_20_67); - fullAdd_x FA_5360_3728(int_13_67, int_12_67, pp_18_67, pp_19_67, pp_20_67); - r4bs r4bs_5360_3944(yy[24], yy[25], single[21], double[21], neg[21], pp_21_67); - r4bs r4bs_5360_4072(yy[22], yy[23], single[22], double[22], neg[22], pp_22_67); - r4bs r4bs_5360_4200(yy[20], yy[21], single[23], double[23], neg[23], pp_23_67); - fullAdd_x FA_5360_4328(int_15_67, int_14_67, pp_21_67, pp_22_67, pp_23_67); - r4bs r4bs_5360_4544(yy[18], yy[19], single[24], double[24], neg[24], pp_24_67); - r4bs r4bs_5360_4672(yy[16], yy[17], single[25], double[25], neg[25], pp_25_67); - r4bs r4bs_5360_4800(yy[14], yy[15], single[26], double[26], neg[26], pp_26_67); - fullAdd_x FA_5360_4928(int_17_67, int_16_67, pp_24_67, pp_25_67, pp_26_67); - r4bs r4bs_5360_5144(yy[12], yy[13], single[27], double[27], neg[27], pp_27_67); - r4bs r4bs_5360_5272(yy[10], yy[11], single[28], double[28], neg[28], pp_28_67); - r4bs r4bs_5360_5400(yy[8], yy[9], single[29], double[29], neg[29], pp_29_67); - fullAdd_x FA_5360_5528(int_19_67, int_18_67, pp_27_67, pp_28_67, pp_29_67); - r4bs r4bs_5360_5744(yy[6], yy[7], single[30], double[30], neg[30], pp_30_67); - r4bs r4bs_5360_5872(yy[4], yy[5], single[31], double[31], neg[31], pp_31_67); - r4bs r4bs_5360_6000(yy[2], yy[3], single[32], double[32], neg[32], pp_32_67); - fullAdd_x FA_5360_6128(int_21_67, int_20_67, pp_30_67, pp_31_67, pp_32_67); - fullAdd_x FA_5360_6344(int_23_67, int_22_67, int_1_66, int_3_66, int_5_66); - fullAdd_x FA_5360_6560(int_25_67, int_24_67, int_7_66, int_9_66, int_11_66); - fullAdd_x FA_5360_6776(int_27_67, int_26_67, int_13_66, int_15_66, int_17_66); - fullAdd_x FA_5360_6992(int_29_67, int_28_67, int_19_66, int_21_66, int_0_67); - fullAdd_x FA_5360_7208(int_31_67, int_30_67, int_23_66, int_25_66, int_27_66); - fullAdd_x FA_5360_7424(int_33_67, int_32_67, int_2_67, int_4_67, int_6_67); - fullAdd_x FA_5360_7640(int_35_67, int_34_67, int_8_67, int_10_67, int_12_67); - fullAdd_x FA_5360_7856(int_37_67, int_36_67, int_14_67, int_16_67, int_18_67); - fullAdd_x FA_5360_8072(int_39_67, int_38_67, int_20_67, int_29_66, int_31_66); - fullAdd_x FA_5360_8288(int_41_67, int_40_67, int_33_66, int_35_66, int_37_66); - fullAdd_x FA_5360_8504(int_43_67, int_42_67, int_22_67, int_24_67, int_26_67); - fullAdd_x FA_5360_8720(int_45_67, int_44_67, int_28_67, int_39_66, int_41_66); - fullAdd_x FA_5360_8936(int_47_67, int_46_67, int_43_66, int_30_67, int_32_67); - fullAdd_x FA_5360_9152(int_49_67, int_48_67, int_34_67, int_36_67, int_45_66); - fullAdd_x FA_5360_9368(int_51_67, int_50_67, int_47_66, int_38_67, int_40_67); - fullAdd_x FA_5360_9584(int_53_67, int_52_67, int_42_67, int_49_66, int_51_66); - fullAdd_x FA_5360_9800(int_55_67, int_54_67, int_44_67, int_46_67, int_48_67); - fullAdd_x FA_5360_10016(int_57_67, int_56_67, int_53_66, int_55_66, int_50_67); - fullAdd_x FA_5360_10232(int_59_67, int_58_67, int_57_66, int_52_67, int_54_67); - fullAdd_x FA_5360_10448(int_61_67, int_60_67, int_59_66, int_56_67, int_58_67); - assign Sum[67] = int_61_66; - assign Carry[67] = int_60_67; - - // Hardware for column 68 - - r4bs r4bs_5440_0(yy[63], gnd, single[2], double[2], neg[2], pp_2_68); - halfAdd HA_5440_128(int_1_68, int_0_68, 1'b1, pp_2_68); - r4bs r4bs_5440_208(yy[61], yy[62], single[3], double[3], neg[3], pp_3_68); - r4bs r4bs_5440_336(yy[59], yy[60], single[4], double[4], neg[4], pp_4_68); - r4bs r4bs_5440_464(yy[57], yy[58], single[5], double[5], neg[5], pp_5_68); - fullAdd_x FA_5440_592(int_3_68, int_2_68, pp_3_68, pp_4_68, pp_5_68); - r4bs r4bs_5440_808(yy[55], yy[56], single[6], double[6], neg[6], pp_6_68); - r4bs r4bs_5440_936(yy[53], yy[54], single[7], double[7], neg[7], pp_7_68); - r4bs r4bs_5440_1064(yy[51], yy[52], single[8], double[8], neg[8], pp_8_68); - fullAdd_x FA_5440_1192(int_5_68, int_4_68, pp_6_68, pp_7_68, pp_8_68); - r4bs r4bs_5440_1408(yy[49], yy[50], single[9], double[9], neg[9], pp_9_68); - r4bs r4bs_5440_1536(yy[47], yy[48], single[10], double[10], neg[10], pp_10_68); - r4bs r4bs_5440_1664(yy[45], yy[46], single[11], double[11], neg[11], pp_11_68); - fullAdd_x FA_5440_1792(int_7_68, int_6_68, pp_9_68, pp_10_68, pp_11_68); - r4bs r4bs_5440_2008(yy[43], yy[44], single[12], double[12], neg[12], pp_12_68); - r4bs r4bs_5440_2136(yy[41], yy[42], single[13], double[13], neg[13], pp_13_68); - r4bs r4bs_5440_2264(yy[39], yy[40], single[14], double[14], neg[14], pp_14_68); - fullAdd_x FA_5440_2392(int_9_68, int_8_68, pp_12_68, pp_13_68, pp_14_68); - r4bs r4bs_5440_2608(yy[37], yy[38], single[15], double[15], neg[15], pp_15_68); - r4bs r4bs_5440_2736(yy[35], yy[36], single[16], double[16], neg[16], pp_16_68); - r4bs r4bs_5440_2864(yy[33], yy[34], single[17], double[17], neg[17], pp_17_68); - fullAdd_x FA_5440_2992(int_11_68, int_10_68, pp_15_68, pp_16_68, pp_17_68); - r4bs r4bs_5440_3208(yy[31], yy[32], single[18], double[18], neg[18], pp_18_68); - r4bs r4bs_5440_3336(yy[29], yy[30], single[19], double[19], neg[19], pp_19_68); - r4bs r4bs_5440_3464(yy[27], yy[28], single[20], double[20], neg[20], pp_20_68); - fullAdd_x FA_5440_3592(int_13_68, int_12_68, pp_18_68, pp_19_68, pp_20_68); - r4bs r4bs_5440_3808(yy[25], yy[26], single[21], double[21], neg[21], pp_21_68); - r4bs r4bs_5440_3936(yy[23], yy[24], single[22], double[22], neg[22], pp_22_68); - r4bs r4bs_5440_4064(yy[21], yy[22], single[23], double[23], neg[23], pp_23_68); - fullAdd_x FA_5440_4192(int_15_68, int_14_68, pp_21_68, pp_22_68, pp_23_68); - r4bs r4bs_5440_4408(yy[19], yy[20], single[24], double[24], neg[24], pp_24_68); - r4bs r4bs_5440_4536(yy[17], yy[18], single[25], double[25], neg[25], pp_25_68); - r4bs r4bs_5440_4664(yy[15], yy[16], single[26], double[26], neg[26], pp_26_68); - fullAdd_x FA_5440_4792(int_17_68, int_16_68, pp_24_68, pp_25_68, pp_26_68); - r4bs r4bs_5440_5008(yy[13], yy[14], single[27], double[27], neg[27], pp_27_68); - r4bs r4bs_5440_5136(yy[11], yy[12], single[28], double[28], neg[28], pp_28_68); - r4bs r4bs_5440_5264(yy[9], yy[10], single[29], double[29], neg[29], pp_29_68); - fullAdd_x FA_5440_5392(int_19_68, int_18_68, pp_27_68, pp_28_68, pp_29_68); - r4bs r4bs_5440_5608(yy[7], yy[8], single[30], double[30], neg[30], pp_30_68); - r4bs r4bs_5440_5736(yy[5], yy[6], single[31], double[31], neg[31], pp_31_68); - r4bs r4bs_5440_5864(yy[3], yy[4], single[32], double[32], neg[32], pp_32_68); - fullAdd_x FA_5440_5992(int_21_68, int_20_68, pp_30_68, pp_31_68, pp_32_68); - fullAdd_x FA_5440_6208(int_23_68, int_22_68, int_1_67, int_3_67, int_5_67); - fullAdd_x FA_5440_6424(int_25_68, int_24_68, int_7_67, int_9_67, int_11_67); - fullAdd_x FA_5440_6640(int_27_68, int_26_68, int_13_67, int_15_67, int_17_67); - fullAdd_x FA_5440_6856(int_29_68, int_28_68, int_19_67, int_21_67, int_0_68); - fullAdd_x FA_5440_7072(int_31_68, int_30_68, int_23_67, int_25_67, int_27_67); - fullAdd_x FA_5440_7288(int_33_68, int_32_68, int_29_67, int_2_68, int_4_68); - fullAdd_x FA_5440_7504(int_35_68, int_34_68, int_6_68, int_8_68, int_10_68); - fullAdd_x FA_5440_7720(int_37_68, int_36_68, int_12_68, int_14_68, int_16_68); - fullAdd_x FA_5440_7936(int_39_68, int_38_68, int_18_68, int_20_68, int_31_67); - fullAdd_x FA_5440_8152(int_41_68, int_40_68, int_33_67, int_35_67, int_37_67); - fullAdd_x FA_5440_8368(int_43_68, int_42_68, int_22_68, int_24_68, int_26_68); - fullAdd_x FA_5440_8584(int_45_68, int_44_68, int_28_68, int_39_67, int_41_67); - fullAdd_x FA_5440_8800(int_47_68, int_46_68, int_43_67, int_30_68, int_32_68); - fullAdd_x FA_5440_9016(int_49_68, int_48_68, int_34_68, int_36_68, int_38_68); - fullAdd_x FA_5440_9232(int_51_68, int_50_68, int_45_67, int_47_67, int_40_68); - fullAdd_x FA_5440_9448(int_53_68, int_52_68, int_42_68, int_49_67, int_51_67); - fullAdd_x FA_5440_9664(int_55_68, int_54_68, int_44_68, int_46_68, int_48_68); - fullAdd_x FA_5440_9880(int_57_68, int_56_68, int_53_67, int_55_67, int_50_68); - fullAdd_x FA_5440_10096(int_59_68, int_58_68, int_57_67, int_52_68, int_54_68); - fullAdd_x FA_5440_10312(int_61_68, int_60_68, int_59_67, int_56_68, int_58_68); - assign Sum[68] = int_61_67; - assign Carry[68] = int_60_68; - - // Hardware for column 69 - - r4bs r4bs_5520_0(yy[62], yy[63], single[3], double[3], neg[3], pp_3_69); - r4bs r4bs_5520_128(yy[60], yy[61], single[4], double[4], neg[4], pp_4_69); - fullAdd_x FA_5520_256(int_1_69, int_0_69, negbar[2], pp_3_69, pp_4_69); - r4bs r4bs_5520_472(yy[58], yy[59], single[5], double[5], neg[5], pp_5_69); - r4bs r4bs_5520_600(yy[56], yy[57], single[6], double[6], neg[6], pp_6_69); - r4bs r4bs_5520_728(yy[54], yy[55], single[7], double[7], neg[7], pp_7_69); - fullAdd_x FA_5520_856(int_3_69, int_2_69, pp_5_69, pp_6_69, pp_7_69); - r4bs r4bs_5520_1072(yy[52], yy[53], single[8], double[8], neg[8], pp_8_69); - r4bs r4bs_5520_1200(yy[50], yy[51], single[9], double[9], neg[9], pp_9_69); - r4bs r4bs_5520_1328(yy[48], yy[49], single[10], double[10], neg[10], pp_10_69); - fullAdd_x FA_5520_1456(int_5_69, int_4_69, pp_8_69, pp_9_69, pp_10_69); - r4bs r4bs_5520_1672(yy[46], yy[47], single[11], double[11], neg[11], pp_11_69); - r4bs r4bs_5520_1800(yy[44], yy[45], single[12], double[12], neg[12], pp_12_69); - r4bs r4bs_5520_1928(yy[42], yy[43], single[13], double[13], neg[13], pp_13_69); - fullAdd_x FA_5520_2056(int_7_69, int_6_69, pp_11_69, pp_12_69, pp_13_69); - r4bs r4bs_5520_2272(yy[40], yy[41], single[14], double[14], neg[14], pp_14_69); - r4bs r4bs_5520_2400(yy[38], yy[39], single[15], double[15], neg[15], pp_15_69); - r4bs r4bs_5520_2528(yy[36], yy[37], single[16], double[16], neg[16], pp_16_69); - fullAdd_x FA_5520_2656(int_9_69, int_8_69, pp_14_69, pp_15_69, pp_16_69); - r4bs r4bs_5520_2872(yy[34], yy[35], single[17], double[17], neg[17], pp_17_69); - r4bs r4bs_5520_3000(yy[32], yy[33], single[18], double[18], neg[18], pp_18_69); - r4bs r4bs_5520_3128(yy[30], yy[31], single[19], double[19], neg[19], pp_19_69); - fullAdd_x FA_5520_3256(int_11_69, int_10_69, pp_17_69, pp_18_69, pp_19_69); - r4bs r4bs_5520_3472(yy[28], yy[29], single[20], double[20], neg[20], pp_20_69); - r4bs r4bs_5520_3600(yy[26], yy[27], single[21], double[21], neg[21], pp_21_69); - r4bs r4bs_5520_3728(yy[24], yy[25], single[22], double[22], neg[22], pp_22_69); - fullAdd_x FA_5520_3856(int_13_69, int_12_69, pp_20_69, pp_21_69, pp_22_69); - r4bs r4bs_5520_4072(yy[22], yy[23], single[23], double[23], neg[23], pp_23_69); - r4bs r4bs_5520_4200(yy[20], yy[21], single[24], double[24], neg[24], pp_24_69); - r4bs r4bs_5520_4328(yy[18], yy[19], single[25], double[25], neg[25], pp_25_69); - fullAdd_x FA_5520_4456(int_15_69, int_14_69, pp_23_69, pp_24_69, pp_25_69); - r4bs r4bs_5520_4672(yy[16], yy[17], single[26], double[26], neg[26], pp_26_69); - r4bs r4bs_5520_4800(yy[14], yy[15], single[27], double[27], neg[27], pp_27_69); - r4bs r4bs_5520_4928(yy[12], yy[13], single[28], double[28], neg[28], pp_28_69); - fullAdd_x FA_5520_5056(int_17_69, int_16_69, pp_26_69, pp_27_69, pp_28_69); - r4bs r4bs_5520_5272(yy[10], yy[11], single[29], double[29], neg[29], pp_29_69); - r4bs r4bs_5520_5400(yy[8], yy[9], single[30], double[30], neg[30], pp_30_69); - r4bs r4bs_5520_5528(yy[6], yy[7], single[31], double[31], neg[31], pp_31_69); - fullAdd_x FA_5520_5656(int_19_69, int_18_69, pp_29_69, pp_30_69, pp_31_69); - r4bs r4bs_5520_5872(yy[4], yy[5], single[32], double[32], neg[32], pp_32_69); - fullAdd_x FA_5520_6000(int_21_69, int_20_69, pp_32_69, int_1_68, int_3_68); - fullAdd_x FA_5520_6216(int_23_69, int_22_69, int_5_68, int_7_68, int_9_68); - fullAdd_x FA_5520_6432(int_25_69, int_24_69, int_11_68, int_13_68, int_15_68); - fullAdd_x FA_5520_6648(int_27_69, int_26_69, int_17_68, int_19_68, int_21_68); - fullAdd_x FA_5520_6864(int_29_69, int_28_69, int_23_68, int_25_68, int_27_68); - fullAdd_x FA_5520_7080(int_31_69, int_30_69, int_29_68, int_0_69, int_2_69); - fullAdd_x FA_5520_7296(int_33_69, int_32_69, int_4_69, int_6_69, int_8_69); - fullAdd_x FA_5520_7512(int_35_69, int_34_69, int_10_69, int_12_69, int_14_69); - fullAdd_x FA_5520_7728(int_37_69, int_36_69, int_16_69, int_18_69, int_20_69); - fullAdd_x FA_5520_7944(int_39_69, int_38_69, int_31_68, int_33_68, int_35_68); - fullAdd_x FA_5520_8160(int_41_69, int_40_69, int_37_68, int_22_69, int_24_69); - fullAdd_x FA_5520_8376(int_43_69, int_42_69, int_26_69, int_39_68, int_41_68); - fullAdd_x FA_5520_8592(int_45_69, int_44_69, int_43_68, int_28_69, int_30_69); - fullAdd_x FA_5520_8808(int_47_69, int_46_69, int_32_69, int_34_69, int_36_69); - fullAdd_x FA_5520_9024(int_49_69, int_48_69, int_45_68, int_47_68, int_49_68); - fullAdd_x FA_5520_9240(int_51_69, int_50_69, int_38_69, int_40_69, int_51_68); - fullAdd_x FA_5520_9456(int_53_69, int_52_69, int_42_69, int_44_69, int_46_69); - fullAdd_x FA_5520_9672(int_55_69, int_54_69, int_53_68, int_55_68, int_48_69); - fullAdd_x FA_5520_9888(int_57_69, int_56_69, int_50_69, int_57_68, int_52_69); - fullAdd_x FA_5520_10104(int_59_69, int_58_69, int_59_68, int_54_69, int_56_69); - assign Sum[69] = int_61_68; - assign Carry[69] = int_58_69; - - // Hardware for column 70 - - r4bs r4bs_5600_0(yy[63], gnd, single[3], double[3], neg[3], pp_3_70); - halfAdd HA_5600_128(int_1_70, int_0_70, 1'b1, pp_3_70); - r4bs r4bs_5600_208(yy[61], yy[62], single[4], double[4], neg[4], pp_4_70); - r4bs r4bs_5600_336(yy[59], yy[60], single[5], double[5], neg[5], pp_5_70); - r4bs r4bs_5600_464(yy[57], yy[58], single[6], double[6], neg[6], pp_6_70); - fullAdd_x FA_5600_592(int_3_70, int_2_70, pp_4_70, pp_5_70, pp_6_70); - r4bs r4bs_5600_808(yy[55], yy[56], single[7], double[7], neg[7], pp_7_70); - r4bs r4bs_5600_936(yy[53], yy[54], single[8], double[8], neg[8], pp_8_70); - r4bs r4bs_5600_1064(yy[51], yy[52], single[9], double[9], neg[9], pp_9_70); - fullAdd_x FA_5600_1192(int_5_70, int_4_70, pp_7_70, pp_8_70, pp_9_70); - r4bs r4bs_5600_1408(yy[49], yy[50], single[10], double[10], neg[10], pp_10_70); - r4bs r4bs_5600_1536(yy[47], yy[48], single[11], double[11], neg[11], pp_11_70); - r4bs r4bs_5600_1664(yy[45], yy[46], single[12], double[12], neg[12], pp_12_70); - fullAdd_x FA_5600_1792(int_7_70, int_6_70, pp_10_70, pp_11_70, pp_12_70); - r4bs r4bs_5600_2008(yy[43], yy[44], single[13], double[13], neg[13], pp_13_70); - r4bs r4bs_5600_2136(yy[41], yy[42], single[14], double[14], neg[14], pp_14_70); - r4bs r4bs_5600_2264(yy[39], yy[40], single[15], double[15], neg[15], pp_15_70); - fullAdd_x FA_5600_2392(int_9_70, int_8_70, pp_13_70, pp_14_70, pp_15_70); - r4bs r4bs_5600_2608(yy[37], yy[38], single[16], double[16], neg[16], pp_16_70); - r4bs r4bs_5600_2736(yy[35], yy[36], single[17], double[17], neg[17], pp_17_70); - r4bs r4bs_5600_2864(yy[33], yy[34], single[18], double[18], neg[18], pp_18_70); - fullAdd_x FA_5600_2992(int_11_70, int_10_70, pp_16_70, pp_17_70, pp_18_70); - r4bs r4bs_5600_3208(yy[31], yy[32], single[19], double[19], neg[19], pp_19_70); - r4bs r4bs_5600_3336(yy[29], yy[30], single[20], double[20], neg[20], pp_20_70); - r4bs r4bs_5600_3464(yy[27], yy[28], single[21], double[21], neg[21], pp_21_70); - fullAdd_x FA_5600_3592(int_13_70, int_12_70, pp_19_70, pp_20_70, pp_21_70); - r4bs r4bs_5600_3808(yy[25], yy[26], single[22], double[22], neg[22], pp_22_70); - r4bs r4bs_5600_3936(yy[23], yy[24], single[23], double[23], neg[23], pp_23_70); - r4bs r4bs_5600_4064(yy[21], yy[22], single[24], double[24], neg[24], pp_24_70); - fullAdd_x FA_5600_4192(int_15_70, int_14_70, pp_22_70, pp_23_70, pp_24_70); - r4bs r4bs_5600_4408(yy[19], yy[20], single[25], double[25], neg[25], pp_25_70); - r4bs r4bs_5600_4536(yy[17], yy[18], single[26], double[26], neg[26], pp_26_70); - r4bs r4bs_5600_4664(yy[15], yy[16], single[27], double[27], neg[27], pp_27_70); - fullAdd_x FA_5600_4792(int_17_70, int_16_70, pp_25_70, pp_26_70, pp_27_70); - r4bs r4bs_5600_5008(yy[13], yy[14], single[28], double[28], neg[28], pp_28_70); - r4bs r4bs_5600_5136(yy[11], yy[12], single[29], double[29], neg[29], pp_29_70); - r4bs r4bs_5600_5264(yy[9], yy[10], single[30], double[30], neg[30], pp_30_70); - fullAdd_x FA_5600_5392(int_19_70, int_18_70, pp_28_70, pp_29_70, pp_30_70); - r4bs r4bs_5600_5608(yy[7], yy[8], single[31], double[31], neg[31], pp_31_70); - r4bs r4bs_5600_5736(yy[5], yy[6], single[32], double[32], neg[32], pp_32_70); - fullAdd_x FA_5600_5864(int_21_70, int_20_70, pp_31_70, pp_32_70, int_1_69); - fullAdd_x FA_5600_6080(int_23_70, int_22_70, int_3_69, int_5_69, int_7_69); - fullAdd_x FA_5600_6296(int_25_70, int_24_70, int_9_69, int_11_69, int_13_69); - fullAdd_x FA_5600_6512(int_27_70, int_26_70, int_15_69, int_17_69, int_19_69); - fullAdd_x FA_5600_6728(int_29_70, int_28_70, int_0_70, int_21_69, int_23_69); - fullAdd_x FA_5600_6944(int_31_70, int_30_70, int_25_69, int_27_69, int_2_70); - fullAdd_x FA_5600_7160(int_33_70, int_32_70, int_4_70, int_6_70, int_8_70); - fullAdd_x FA_5600_7376(int_35_70, int_34_70, int_10_70, int_12_70, int_14_70); - fullAdd_x FA_5600_7592(int_37_70, int_36_70, int_16_70, int_18_70, int_20_70); - fullAdd_x FA_5600_7808(int_39_70, int_38_70, int_29_69, int_31_69, int_33_69); - fullAdd_x FA_5600_8024(int_41_70, int_40_70, int_35_69, int_22_70, int_24_70); - fullAdd_x FA_5600_8240(int_43_70, int_42_70, int_26_70, int_37_69, int_39_69); - fullAdd_x FA_5600_8456(int_45_70, int_44_70, int_41_69, int_28_70, int_30_70); - fullAdd_x FA_5600_8672(int_47_70, int_46_70, int_32_70, int_34_70, int_36_70); - fullAdd_x FA_5600_8888(int_49_70, int_48_70, int_43_69, int_45_69, int_47_69); - fullAdd_x FA_5600_9104(int_51_70, int_50_70, int_38_70, int_40_70, int_42_70); - fullAdd_x FA_5600_9320(int_53_70, int_52_70, int_49_69, int_44_70, int_46_70); - fullAdd_x FA_5600_9536(int_55_70, int_54_70, int_51_69, int_53_69, int_48_70); - fullAdd_x FA_5600_9752(int_57_70, int_56_70, int_50_70, int_55_69, int_52_70); - fullAdd_x FA_5600_9968(int_59_70, int_58_70, int_57_69, int_54_70, int_56_70); - assign Sum[70] = int_59_69; - assign Carry[70] = int_58_70; - - // Hardware for column 71 - - r4bs r4bs_5680_0(yy[62], yy[63], single[4], double[4], neg[4], pp_4_71); - r4bs r4bs_5680_128(yy[60], yy[61], single[5], double[5], neg[5], pp_5_71); - fullAdd_x FA_5680_256(int_1_71, int_0_71, negbar[3], pp_4_71, pp_5_71); - r4bs r4bs_5680_472(yy[58], yy[59], single[6], double[6], neg[6], pp_6_71); - r4bs r4bs_5680_600(yy[56], yy[57], single[7], double[7], neg[7], pp_7_71); - r4bs r4bs_5680_728(yy[54], yy[55], single[8], double[8], neg[8], pp_8_71); - fullAdd_x FA_5680_856(int_3_71, int_2_71, pp_6_71, pp_7_71, pp_8_71); - r4bs r4bs_5680_1072(yy[52], yy[53], single[9], double[9], neg[9], pp_9_71); - r4bs r4bs_5680_1200(yy[50], yy[51], single[10], double[10], neg[10], pp_10_71); - r4bs r4bs_5680_1328(yy[48], yy[49], single[11], double[11], neg[11], pp_11_71); - fullAdd_x FA_5680_1456(int_5_71, int_4_71, pp_9_71, pp_10_71, pp_11_71); - r4bs r4bs_5680_1672(yy[46], yy[47], single[12], double[12], neg[12], pp_12_71); - r4bs r4bs_5680_1800(yy[44], yy[45], single[13], double[13], neg[13], pp_13_71); - r4bs r4bs_5680_1928(yy[42], yy[43], single[14], double[14], neg[14], pp_14_71); - fullAdd_x FA_5680_2056(int_7_71, int_6_71, pp_12_71, pp_13_71, pp_14_71); - r4bs r4bs_5680_2272(yy[40], yy[41], single[15], double[15], neg[15], pp_15_71); - r4bs r4bs_5680_2400(yy[38], yy[39], single[16], double[16], neg[16], pp_16_71); - r4bs r4bs_5680_2528(yy[36], yy[37], single[17], double[17], neg[17], pp_17_71); - fullAdd_x FA_5680_2656(int_9_71, int_8_71, pp_15_71, pp_16_71, pp_17_71); - r4bs r4bs_5680_2872(yy[34], yy[35], single[18], double[18], neg[18], pp_18_71); - r4bs r4bs_5680_3000(yy[32], yy[33], single[19], double[19], neg[19], pp_19_71); - r4bs r4bs_5680_3128(yy[30], yy[31], single[20], double[20], neg[20], pp_20_71); - fullAdd_x FA_5680_3256(int_11_71, int_10_71, pp_18_71, pp_19_71, pp_20_71); - r4bs r4bs_5680_3472(yy[28], yy[29], single[21], double[21], neg[21], pp_21_71); - r4bs r4bs_5680_3600(yy[26], yy[27], single[22], double[22], neg[22], pp_22_71); - r4bs r4bs_5680_3728(yy[24], yy[25], single[23], double[23], neg[23], pp_23_71); - fullAdd_x FA_5680_3856(int_13_71, int_12_71, pp_21_71, pp_22_71, pp_23_71); - r4bs r4bs_5680_4072(yy[22], yy[23], single[24], double[24], neg[24], pp_24_71); - r4bs r4bs_5680_4200(yy[20], yy[21], single[25], double[25], neg[25], pp_25_71); - r4bs r4bs_5680_4328(yy[18], yy[19], single[26], double[26], neg[26], pp_26_71); - fullAdd_x FA_5680_4456(int_15_71, int_14_71, pp_24_71, pp_25_71, pp_26_71); - r4bs r4bs_5680_4672(yy[16], yy[17], single[27], double[27], neg[27], pp_27_71); - r4bs r4bs_5680_4800(yy[14], yy[15], single[28], double[28], neg[28], pp_28_71); - r4bs r4bs_5680_4928(yy[12], yy[13], single[29], double[29], neg[29], pp_29_71); - fullAdd_x FA_5680_5056(int_17_71, int_16_71, pp_27_71, pp_28_71, pp_29_71); - r4bs r4bs_5680_5272(yy[10], yy[11], single[30], double[30], neg[30], pp_30_71); - r4bs r4bs_5680_5400(yy[8], yy[9], single[31], double[31], neg[31], pp_31_71); - r4bs r4bs_5680_5528(yy[6], yy[7], single[32], double[32], neg[32], pp_32_71); - fullAdd_x FA_5680_5656(int_19_71, int_18_71, pp_30_71, pp_31_71, pp_32_71); - fullAdd_x FA_5680_5872(int_21_71, int_20_71, int_1_70, int_3_70, int_5_70); - fullAdd_x FA_5680_6088(int_23_71, int_22_71, int_7_70, int_9_70, int_11_70); - fullAdd_x FA_5680_6304(int_25_71, int_24_71, int_13_70, int_15_70, int_17_70); - fullAdd_x FA_5680_6520(int_27_71, int_26_71, int_19_70, int_21_70, int_23_70); - fullAdd_x FA_5680_6736(int_29_71, int_28_71, int_25_70, int_27_70, int_0_71); - fullAdd_x FA_5680_6952(int_31_71, int_30_71, int_2_71, int_4_71, int_6_71); - fullAdd_x FA_5680_7168(int_33_71, int_32_71, int_8_71, int_10_71, int_12_71); - fullAdd_x FA_5680_7384(int_35_71, int_34_71, int_14_71, int_16_71, int_18_71); - fullAdd_x FA_5680_7600(int_37_71, int_36_71, int_29_70, int_31_70, int_33_70); - fullAdd_x FA_5680_7816(int_39_71, int_38_71, int_35_70, int_37_70, int_20_71); - fullAdd_x FA_5680_8032(int_41_71, int_40_71, int_22_71, int_24_71, int_39_70); - fullAdd_x FA_5680_8248(int_43_71, int_42_71, int_41_70, int_26_71, int_28_71); - fullAdd_x FA_5680_8464(int_45_71, int_44_71, int_30_71, int_32_71, int_34_71); - fullAdd_x FA_5680_8680(int_47_71, int_46_71, int_43_70, int_45_70, int_47_70); - fullAdd_x FA_5680_8896(int_49_71, int_48_71, int_36_71, int_38_71, int_40_71); - fullAdd_x FA_5680_9112(int_51_71, int_50_71, int_49_70, int_42_71, int_44_71); - fullAdd_x FA_5680_9328(int_53_71, int_52_71, int_51_70, int_53_70, int_46_71); - fullAdd_x FA_5680_9544(int_55_71, int_54_71, int_48_71, int_55_70, int_50_71); - fullAdd_x FA_5680_9760(int_57_71, int_56_71, int_57_70, int_52_71, int_54_71); - assign Sum[71] = int_59_70; - assign Carry[71] = int_56_71; - - // Hardware for column 72 - - r4bs r4bs_5760_0(yy[63], gnd, single[4], double[4], neg[4], pp_4_72); - halfAdd HA_5760_128(int_1_72, int_0_72, 1'b1, pp_4_72); - r4bs r4bs_5760_208(yy[61], yy[62], single[5], double[5], neg[5], pp_5_72); - r4bs r4bs_5760_336(yy[59], yy[60], single[6], double[6], neg[6], pp_6_72); - r4bs r4bs_5760_464(yy[57], yy[58], single[7], double[7], neg[7], pp_7_72); - fullAdd_x FA_5760_592(int_3_72, int_2_72, pp_5_72, pp_6_72, pp_7_72); - r4bs r4bs_5760_808(yy[55], yy[56], single[8], double[8], neg[8], pp_8_72); - r4bs r4bs_5760_936(yy[53], yy[54], single[9], double[9], neg[9], pp_9_72); - r4bs r4bs_5760_1064(yy[51], yy[52], single[10], double[10], neg[10], pp_10_72); - fullAdd_x FA_5760_1192(int_5_72, int_4_72, pp_8_72, pp_9_72, pp_10_72); - r4bs r4bs_5760_1408(yy[49], yy[50], single[11], double[11], neg[11], pp_11_72); - r4bs r4bs_5760_1536(yy[47], yy[48], single[12], double[12], neg[12], pp_12_72); - r4bs r4bs_5760_1664(yy[45], yy[46], single[13], double[13], neg[13], pp_13_72); - fullAdd_x FA_5760_1792(int_7_72, int_6_72, pp_11_72, pp_12_72, pp_13_72); - r4bs r4bs_5760_2008(yy[43], yy[44], single[14], double[14], neg[14], pp_14_72); - r4bs r4bs_5760_2136(yy[41], yy[42], single[15], double[15], neg[15], pp_15_72); - r4bs r4bs_5760_2264(yy[39], yy[40], single[16], double[16], neg[16], pp_16_72); - fullAdd_x FA_5760_2392(int_9_72, int_8_72, pp_14_72, pp_15_72, pp_16_72); - r4bs r4bs_5760_2608(yy[37], yy[38], single[17], double[17], neg[17], pp_17_72); - r4bs r4bs_5760_2736(yy[35], yy[36], single[18], double[18], neg[18], pp_18_72); - r4bs r4bs_5760_2864(yy[33], yy[34], single[19], double[19], neg[19], pp_19_72); - fullAdd_x FA_5760_2992(int_11_72, int_10_72, pp_17_72, pp_18_72, pp_19_72); - r4bs r4bs_5760_3208(yy[31], yy[32], single[20], double[20], neg[20], pp_20_72); - r4bs r4bs_5760_3336(yy[29], yy[30], single[21], double[21], neg[21], pp_21_72); - r4bs r4bs_5760_3464(yy[27], yy[28], single[22], double[22], neg[22], pp_22_72); - fullAdd_x FA_5760_3592(int_13_72, int_12_72, pp_20_72, pp_21_72, pp_22_72); - r4bs r4bs_5760_3808(yy[25], yy[26], single[23], double[23], neg[23], pp_23_72); - r4bs r4bs_5760_3936(yy[23], yy[24], single[24], double[24], neg[24], pp_24_72); - r4bs r4bs_5760_4064(yy[21], yy[22], single[25], double[25], neg[25], pp_25_72); - fullAdd_x FA_5760_4192(int_15_72, int_14_72, pp_23_72, pp_24_72, pp_25_72); - r4bs r4bs_5760_4408(yy[19], yy[20], single[26], double[26], neg[26], pp_26_72); - r4bs r4bs_5760_4536(yy[17], yy[18], single[27], double[27], neg[27], pp_27_72); - r4bs r4bs_5760_4664(yy[15], yy[16], single[28], double[28], neg[28], pp_28_72); - fullAdd_x FA_5760_4792(int_17_72, int_16_72, pp_26_72, pp_27_72, pp_28_72); - r4bs r4bs_5760_5008(yy[13], yy[14], single[29], double[29], neg[29], pp_29_72); - r4bs r4bs_5760_5136(yy[11], yy[12], single[30], double[30], neg[30], pp_30_72); - r4bs r4bs_5760_5264(yy[9], yy[10], single[31], double[31], neg[31], pp_31_72); - fullAdd_x FA_5760_5392(int_19_72, int_18_72, pp_29_72, pp_30_72, pp_31_72); - r4bs r4bs_5760_5608(yy[7], yy[8], single[32], double[32], neg[32], pp_32_72); - fullAdd_x FA_5760_5736(int_21_72, int_20_72, pp_32_72, int_1_71, int_3_71); - fullAdd_x FA_5760_5952(int_23_72, int_22_72, int_5_71, int_7_71, int_9_71); - fullAdd_x FA_5760_6168(int_25_72, int_24_72, int_11_71, int_13_71, int_15_71); - fullAdd_x FA_5760_6384(int_27_72, int_26_72, int_17_71, int_19_71, int_0_72); - fullAdd_x FA_5760_6600(int_29_72, int_28_72, int_21_71, int_23_71, int_25_71); - fullAdd_x FA_5760_6816(int_31_72, int_30_72, int_2_72, int_4_72, int_6_72); - fullAdd_x FA_5760_7032(int_33_72, int_32_72, int_8_72, int_10_72, int_12_72); - fullAdd_x FA_5760_7248(int_35_72, int_34_72, int_14_72, int_16_72, int_18_72); - fullAdd_x FA_5760_7464(int_37_72, int_36_72, int_27_71, int_29_71, int_31_71); - fullAdd_x FA_5760_7680(int_39_72, int_38_72, int_33_71, int_35_71, int_20_72); - fullAdd_x FA_5760_7896(int_41_72, int_40_72, int_22_72, int_24_72, int_26_72); - fullAdd_x FA_5760_8112(int_43_72, int_42_72, int_37_71, int_39_71, int_28_72); - fullAdd_x FA_5760_8328(int_45_72, int_44_72, int_30_72, int_32_72, int_34_72); - fullAdd_x FA_5760_8544(int_47_72, int_46_72, int_41_71, int_43_71, int_45_71); - fullAdd_x FA_5760_8760(int_49_72, int_48_72, int_36_72, int_38_72, int_40_72); - fullAdd_x FA_5760_8976(int_51_72, int_50_72, int_47_71, int_49_71, int_42_72); - fullAdd_x FA_5760_9192(int_53_72, int_52_72, int_44_72, int_51_71, int_46_72); - fullAdd_x FA_5760_9408(int_55_72, int_54_72, int_48_72, int_53_71, int_50_72); - fullAdd_x FA_5760_9624(int_57_72, int_56_72, int_55_71, int_52_72, int_54_72); - assign Sum[72] = int_57_71; - assign Carry[72] = int_56_72; - - // Hardware for column 73 - - r4bs r4bs_5840_0(yy[62], yy[63], single[5], double[5], neg[5], pp_5_73); - r4bs r4bs_5840_128(yy[60], yy[61], single[6], double[6], neg[6], pp_6_73); - fullAdd_x FA_5840_256(int_1_73, int_0_73, negbar[4], pp_5_73, pp_6_73); - r4bs r4bs_5840_472(yy[58], yy[59], single[7], double[7], neg[7], pp_7_73); - r4bs r4bs_5840_600(yy[56], yy[57], single[8], double[8], neg[8], pp_8_73); - r4bs r4bs_5840_728(yy[54], yy[55], single[9], double[9], neg[9], pp_9_73); - fullAdd_x FA_5840_856(int_3_73, int_2_73, pp_7_73, pp_8_73, pp_9_73); - r4bs r4bs_5840_1072(yy[52], yy[53], single[10], double[10], neg[10], pp_10_73); - r4bs r4bs_5840_1200(yy[50], yy[51], single[11], double[11], neg[11], pp_11_73); - r4bs r4bs_5840_1328(yy[48], yy[49], single[12], double[12], neg[12], pp_12_73); - fullAdd_x FA_5840_1456(int_5_73, int_4_73, pp_10_73, pp_11_73, pp_12_73); - r4bs r4bs_5840_1672(yy[46], yy[47], single[13], double[13], neg[13], pp_13_73); - r4bs r4bs_5840_1800(yy[44], yy[45], single[14], double[14], neg[14], pp_14_73); - r4bs r4bs_5840_1928(yy[42], yy[43], single[15], double[15], neg[15], pp_15_73); - fullAdd_x FA_5840_2056(int_7_73, int_6_73, pp_13_73, pp_14_73, pp_15_73); - r4bs r4bs_5840_2272(yy[40], yy[41], single[16], double[16], neg[16], pp_16_73); - r4bs r4bs_5840_2400(yy[38], yy[39], single[17], double[17], neg[17], pp_17_73); - r4bs r4bs_5840_2528(yy[36], yy[37], single[18], double[18], neg[18], pp_18_73); - fullAdd_x FA_5840_2656(int_9_73, int_8_73, pp_16_73, pp_17_73, pp_18_73); - r4bs r4bs_5840_2872(yy[34], yy[35], single[19], double[19], neg[19], pp_19_73); - r4bs r4bs_5840_3000(yy[32], yy[33], single[20], double[20], neg[20], pp_20_73); - r4bs r4bs_5840_3128(yy[30], yy[31], single[21], double[21], neg[21], pp_21_73); - fullAdd_x FA_5840_3256(int_11_73, int_10_73, pp_19_73, pp_20_73, pp_21_73); - r4bs r4bs_5840_3472(yy[28], yy[29], single[22], double[22], neg[22], pp_22_73); - r4bs r4bs_5840_3600(yy[26], yy[27], single[23], double[23], neg[23], pp_23_73); - r4bs r4bs_5840_3728(yy[24], yy[25], single[24], double[24], neg[24], pp_24_73); - fullAdd_x FA_5840_3856(int_13_73, int_12_73, pp_22_73, pp_23_73, pp_24_73); - r4bs r4bs_5840_4072(yy[22], yy[23], single[25], double[25], neg[25], pp_25_73); - r4bs r4bs_5840_4200(yy[20], yy[21], single[26], double[26], neg[26], pp_26_73); - r4bs r4bs_5840_4328(yy[18], yy[19], single[27], double[27], neg[27], pp_27_73); - fullAdd_x FA_5840_4456(int_15_73, int_14_73, pp_25_73, pp_26_73, pp_27_73); - r4bs r4bs_5840_4672(yy[16], yy[17], single[28], double[28], neg[28], pp_28_73); - r4bs r4bs_5840_4800(yy[14], yy[15], single[29], double[29], neg[29], pp_29_73); - r4bs r4bs_5840_4928(yy[12], yy[13], single[30], double[30], neg[30], pp_30_73); - fullAdd_x FA_5840_5056(int_17_73, int_16_73, pp_28_73, pp_29_73, pp_30_73); - r4bs r4bs_5840_5272(yy[10], yy[11], single[31], double[31], neg[31], pp_31_73); - r4bs r4bs_5840_5400(yy[8], yy[9], single[32], double[32], neg[32], pp_32_73); - fullAdd_x FA_5840_5528(int_19_73, int_18_73, pp_31_73, pp_32_73, int_1_72); - fullAdd_x FA_5840_5744(int_21_73, int_20_73, int_3_72, int_5_72, int_7_72); - fullAdd_x FA_5840_5960(int_23_73, int_22_73, int_9_72, int_11_72, int_13_72); - fullAdd_x FA_5840_6176(int_25_73, int_24_73, int_15_72, int_17_72, int_19_72); - fullAdd_x FA_5840_6392(int_27_73, int_26_73, int_21_72, int_23_72, int_25_72); - fullAdd_x FA_5840_6608(int_29_73, int_28_73, int_27_72, int_0_73, int_2_73); - fullAdd_x FA_5840_6824(int_31_73, int_30_73, int_4_73, int_6_73, int_8_73); - fullAdd_x FA_5840_7040(int_33_73, int_32_73, int_10_73, int_12_73, int_14_73); - fullAdd_x FA_5840_7256(int_35_73, int_34_73, int_16_73, int_18_73, int_29_72); - fullAdd_x FA_5840_7472(int_37_73, int_36_73, int_31_72, int_33_72, int_35_72); - fullAdd_x FA_5840_7688(int_39_73, int_38_73, int_20_73, int_22_73, int_24_73); - fullAdd_x FA_5840_7904(int_41_73, int_40_73, int_37_72, int_39_72, int_41_72); - fullAdd_x FA_5840_8120(int_43_73, int_42_73, int_26_73, int_28_73, int_30_73); - fullAdd_x FA_5840_8336(int_45_73, int_44_73, int_32_73, int_34_73, int_43_72); - fullAdd_x FA_5840_8552(int_47_73, int_46_73, int_45_72, int_36_73, int_38_73); - fullAdd_x FA_5840_8768(int_49_73, int_48_73, int_47_72, int_49_72, int_40_73); - fullAdd_x FA_5840_8984(int_51_73, int_50_73, int_42_73, int_44_73, int_51_72); - fullAdd_x FA_5840_9200(int_53_73, int_52_73, int_46_73, int_53_72, int_48_73); - fullAdd_x FA_5840_9416(int_55_73, int_54_73, int_50_73, int_55_72, int_52_73); - assign Sum[73] = int_57_72; - assign Carry[73] = int_54_73; - - // Hardware for column 74 - - r4bs r4bs_5920_0(yy[63], gnd, single[5], double[5], neg[5], pp_5_74); - halfAdd HA_5920_128(int_1_74, int_0_74, 1'b1, pp_5_74); - r4bs r4bs_5920_208(yy[61], yy[62], single[6], double[6], neg[6], pp_6_74); - r4bs r4bs_5920_336(yy[59], yy[60], single[7], double[7], neg[7], pp_7_74); - r4bs r4bs_5920_464(yy[57], yy[58], single[8], double[8], neg[8], pp_8_74); - fullAdd_x FA_5920_592(int_3_74, int_2_74, pp_6_74, pp_7_74, pp_8_74); - r4bs r4bs_5920_808(yy[55], yy[56], single[9], double[9], neg[9], pp_9_74); - r4bs r4bs_5920_936(yy[53], yy[54], single[10], double[10], neg[10], pp_10_74); - r4bs r4bs_5920_1064(yy[51], yy[52], single[11], double[11], neg[11], pp_11_74); - fullAdd_x FA_5920_1192(int_5_74, int_4_74, pp_9_74, pp_10_74, pp_11_74); - r4bs r4bs_5920_1408(yy[49], yy[50], single[12], double[12], neg[12], pp_12_74); - r4bs r4bs_5920_1536(yy[47], yy[48], single[13], double[13], neg[13], pp_13_74); - r4bs r4bs_5920_1664(yy[45], yy[46], single[14], double[14], neg[14], pp_14_74); - fullAdd_x FA_5920_1792(int_7_74, int_6_74, pp_12_74, pp_13_74, pp_14_74); - r4bs r4bs_5920_2008(yy[43], yy[44], single[15], double[15], neg[15], pp_15_74); - r4bs r4bs_5920_2136(yy[41], yy[42], single[16], double[16], neg[16], pp_16_74); - r4bs r4bs_5920_2264(yy[39], yy[40], single[17], double[17], neg[17], pp_17_74); - fullAdd_x FA_5920_2392(int_9_74, int_8_74, pp_15_74, pp_16_74, pp_17_74); - r4bs r4bs_5920_2608(yy[37], yy[38], single[18], double[18], neg[18], pp_18_74); - r4bs r4bs_5920_2736(yy[35], yy[36], single[19], double[19], neg[19], pp_19_74); - r4bs r4bs_5920_2864(yy[33], yy[34], single[20], double[20], neg[20], pp_20_74); - fullAdd_x FA_5920_2992(int_11_74, int_10_74, pp_18_74, pp_19_74, pp_20_74); - r4bs r4bs_5920_3208(yy[31], yy[32], single[21], double[21], neg[21], pp_21_74); - r4bs r4bs_5920_3336(yy[29], yy[30], single[22], double[22], neg[22], pp_22_74); - r4bs r4bs_5920_3464(yy[27], yy[28], single[23], double[23], neg[23], pp_23_74); - fullAdd_x FA_5920_3592(int_13_74, int_12_74, pp_21_74, pp_22_74, pp_23_74); - r4bs r4bs_5920_3808(yy[25], yy[26], single[24], double[24], neg[24], pp_24_74); - r4bs r4bs_5920_3936(yy[23], yy[24], single[25], double[25], neg[25], pp_25_74); - r4bs r4bs_5920_4064(yy[21], yy[22], single[26], double[26], neg[26], pp_26_74); - fullAdd_x FA_5920_4192(int_15_74, int_14_74, pp_24_74, pp_25_74, pp_26_74); - r4bs r4bs_5920_4408(yy[19], yy[20], single[27], double[27], neg[27], pp_27_74); - r4bs r4bs_5920_4536(yy[17], yy[18], single[28], double[28], neg[28], pp_28_74); - r4bs r4bs_5920_4664(yy[15], yy[16], single[29], double[29], neg[29], pp_29_74); - fullAdd_x FA_5920_4792(int_17_74, int_16_74, pp_27_74, pp_28_74, pp_29_74); - r4bs r4bs_5920_5008(yy[13], yy[14], single[30], double[30], neg[30], pp_30_74); - r4bs r4bs_5920_5136(yy[11], yy[12], single[31], double[31], neg[31], pp_31_74); - r4bs r4bs_5920_5264(yy[9], yy[10], single[32], double[32], neg[32], pp_32_74); - fullAdd_x FA_5920_5392(int_19_74, int_18_74, pp_30_74, pp_31_74, pp_32_74); - fullAdd_x FA_5920_5608(int_21_74, int_20_74, int_1_73, int_3_73, int_5_73); - fullAdd_x FA_5920_5824(int_23_74, int_22_74, int_7_73, int_9_73, int_11_73); - fullAdd_x FA_5920_6040(int_25_74, int_24_74, int_13_73, int_15_73, int_17_73); - fullAdd_x FA_5920_6256(int_27_74, int_26_74, int_0_74, int_19_73, int_21_73); - fullAdd_x FA_5920_6472(int_29_74, int_28_74, int_23_73, int_25_73, int_2_74); - fullAdd_x FA_5920_6688(int_31_74, int_30_74, int_4_74, int_6_74, int_8_74); - fullAdd_x FA_5920_6904(int_33_74, int_32_74, int_10_74, int_12_74, int_14_74); - fullAdd_x FA_5920_7120(int_35_74, int_34_74, int_16_74, int_18_74, int_27_73); - fullAdd_x FA_5920_7336(int_37_74, int_36_74, int_29_73, int_31_73, int_33_73); - fullAdd_x FA_5920_7552(int_39_74, int_38_74, int_20_74, int_22_74, int_24_74); - fullAdd_x FA_5920_7768(int_41_74, int_40_74, int_26_74, int_35_73, int_37_73); - fullAdd_x FA_5920_7984(int_43_74, int_42_74, int_39_73, int_28_74, int_30_74); - fullAdd_x FA_5920_8200(int_45_74, int_44_74, int_32_74, int_34_74, int_41_73); - fullAdd_x FA_5920_8416(int_47_74, int_46_74, int_43_73, int_36_74, int_38_74); - fullAdd_x FA_5920_8632(int_49_74, int_48_74, int_45_73, int_47_73, int_40_74); - fullAdd_x FA_5920_8848(int_51_74, int_50_74, int_42_74, int_44_74, int_49_73); - fullAdd_x FA_5920_9064(int_53_74, int_52_74, int_46_74, int_51_73, int_48_74); - fullAdd_x FA_5920_9280(int_55_74, int_54_74, int_50_74, int_53_73, int_52_74); - assign Sum[74] = int_55_73; - assign Carry[74] = int_54_74; - - // Hardware for column 75 - - r4bs r4bs_6000_0(yy[62], yy[63], single[6], double[6], neg[6], pp_6_75); - r4bs r4bs_6000_128(yy[60], yy[61], single[7], double[7], neg[7], pp_7_75); - fullAdd_x FA_6000_256(int_1_75, int_0_75, negbar[5], pp_6_75, pp_7_75); - r4bs r4bs_6000_472(yy[58], yy[59], single[8], double[8], neg[8], pp_8_75); - r4bs r4bs_6000_600(yy[56], yy[57], single[9], double[9], neg[9], pp_9_75); - r4bs r4bs_6000_728(yy[54], yy[55], single[10], double[10], neg[10], pp_10_75); - fullAdd_x FA_6000_856(int_3_75, int_2_75, pp_8_75, pp_9_75, pp_10_75); - r4bs r4bs_6000_1072(yy[52], yy[53], single[11], double[11], neg[11], pp_11_75); - r4bs r4bs_6000_1200(yy[50], yy[51], single[12], double[12], neg[12], pp_12_75); - r4bs r4bs_6000_1328(yy[48], yy[49], single[13], double[13], neg[13], pp_13_75); - fullAdd_x FA_6000_1456(int_5_75, int_4_75, pp_11_75, pp_12_75, pp_13_75); - r4bs r4bs_6000_1672(yy[46], yy[47], single[14], double[14], neg[14], pp_14_75); - r4bs r4bs_6000_1800(yy[44], yy[45], single[15], double[15], neg[15], pp_15_75); - r4bs r4bs_6000_1928(yy[42], yy[43], single[16], double[16], neg[16], pp_16_75); - fullAdd_x FA_6000_2056(int_7_75, int_6_75, pp_14_75, pp_15_75, pp_16_75); - r4bs r4bs_6000_2272(yy[40], yy[41], single[17], double[17], neg[17], pp_17_75); - r4bs r4bs_6000_2400(yy[38], yy[39], single[18], double[18], neg[18], pp_18_75); - r4bs r4bs_6000_2528(yy[36], yy[37], single[19], double[19], neg[19], pp_19_75); - fullAdd_x FA_6000_2656(int_9_75, int_8_75, pp_17_75, pp_18_75, pp_19_75); - r4bs r4bs_6000_2872(yy[34], yy[35], single[20], double[20], neg[20], pp_20_75); - r4bs r4bs_6000_3000(yy[32], yy[33], single[21], double[21], neg[21], pp_21_75); - r4bs r4bs_6000_3128(yy[30], yy[31], single[22], double[22], neg[22], pp_22_75); - fullAdd_x FA_6000_3256(int_11_75, int_10_75, pp_20_75, pp_21_75, pp_22_75); - r4bs r4bs_6000_3472(yy[28], yy[29], single[23], double[23], neg[23], pp_23_75); - r4bs r4bs_6000_3600(yy[26], yy[27], single[24], double[24], neg[24], pp_24_75); - r4bs r4bs_6000_3728(yy[24], yy[25], single[25], double[25], neg[25], pp_25_75); - fullAdd_x FA_6000_3856(int_13_75, int_12_75, pp_23_75, pp_24_75, pp_25_75); - r4bs r4bs_6000_4072(yy[22], yy[23], single[26], double[26], neg[26], pp_26_75); - r4bs r4bs_6000_4200(yy[20], yy[21], single[27], double[27], neg[27], pp_27_75); - r4bs r4bs_6000_4328(yy[18], yy[19], single[28], double[28], neg[28], pp_28_75); - fullAdd_x FA_6000_4456(int_15_75, int_14_75, pp_26_75, pp_27_75, pp_28_75); - r4bs r4bs_6000_4672(yy[16], yy[17], single[29], double[29], neg[29], pp_29_75); - r4bs r4bs_6000_4800(yy[14], yy[15], single[30], double[30], neg[30], pp_30_75); - r4bs r4bs_6000_4928(yy[12], yy[13], single[31], double[31], neg[31], pp_31_75); - fullAdd_x FA_6000_5056(int_17_75, int_16_75, pp_29_75, pp_30_75, pp_31_75); - r4bs r4bs_6000_5272(yy[10], yy[11], single[32], double[32], neg[32], pp_32_75); - fullAdd_x FA_6000_5400(int_19_75, int_18_75, pp_32_75, int_1_74, int_3_74); - fullAdd_x FA_6000_5616(int_21_75, int_20_75, int_5_74, int_7_74, int_9_74); - fullAdd_x FA_6000_5832(int_23_75, int_22_75, int_11_74, int_13_74, int_15_74); - fullAdd_x FA_6000_6048(int_25_75, int_24_75, int_17_74, int_19_74, int_21_74); - fullAdd_x FA_6000_6264(int_27_75, int_26_75, int_23_74, int_25_74, int_0_75); - fullAdd_x FA_6000_6480(int_29_75, int_28_75, int_2_75, int_4_75, int_6_75); - fullAdd_x FA_6000_6696(int_31_75, int_30_75, int_8_75, int_10_75, int_12_75); - fullAdd_x FA_6000_6912(int_33_75, int_32_75, int_14_75, int_16_75, int_18_75); - fullAdd_x FA_6000_7128(int_35_75, int_34_75, int_27_74, int_29_74, int_31_74); - fullAdd_x FA_6000_7344(int_37_75, int_36_75, int_33_74, int_20_75, int_22_75); - fullAdd_x FA_6000_7560(int_39_75, int_38_75, int_24_75, int_35_74, int_37_74); - fullAdd_x FA_6000_7776(int_41_75, int_40_75, int_39_74, int_26_75, int_28_75); - fullAdd_x FA_6000_7992(int_43_75, int_42_75, int_30_75, int_32_75, int_41_74); - fullAdd_x FA_6000_8208(int_45_75, int_44_75, int_43_74, int_34_75, int_36_75); - fullAdd_x FA_6000_8424(int_47_75, int_46_75, int_45_74, int_47_74, int_38_75); - fullAdd_x FA_6000_8640(int_49_75, int_48_75, int_40_75, int_42_75, int_49_74); - fullAdd_x FA_6000_8856(int_51_75, int_50_75, int_44_75, int_51_74, int_46_75); - fullAdd_x FA_6000_9072(int_53_75, int_52_75, int_48_75, int_53_74, int_50_75); - assign Sum[75] = int_55_74; - assign Carry[75] = int_52_75; - - // Hardware for column 76 - - r4bs r4bs_6080_0(yy[63], gnd, single[6], double[6], neg[6], pp_6_76); - halfAdd HA_6080_128(int_1_76, int_0_76, 1'b1, pp_6_76); - r4bs r4bs_6080_208(yy[61], yy[62], single[7], double[7], neg[7], pp_7_76); - r4bs r4bs_6080_336(yy[59], yy[60], single[8], double[8], neg[8], pp_8_76); - r4bs r4bs_6080_464(yy[57], yy[58], single[9], double[9], neg[9], pp_9_76); - fullAdd_x FA_6080_592(int_3_76, int_2_76, pp_7_76, pp_8_76, pp_9_76); - r4bs r4bs_6080_808(yy[55], yy[56], single[10], double[10], neg[10], pp_10_76); - r4bs r4bs_6080_936(yy[53], yy[54], single[11], double[11], neg[11], pp_11_76); - r4bs r4bs_6080_1064(yy[51], yy[52], single[12], double[12], neg[12], pp_12_76); - fullAdd_x FA_6080_1192(int_5_76, int_4_76, pp_10_76, pp_11_76, pp_12_76); - r4bs r4bs_6080_1408(yy[49], yy[50], single[13], double[13], neg[13], pp_13_76); - r4bs r4bs_6080_1536(yy[47], yy[48], single[14], double[14], neg[14], pp_14_76); - r4bs r4bs_6080_1664(yy[45], yy[46], single[15], double[15], neg[15], pp_15_76); - fullAdd_x FA_6080_1792(int_7_76, int_6_76, pp_13_76, pp_14_76, pp_15_76); - r4bs r4bs_6080_2008(yy[43], yy[44], single[16], double[16], neg[16], pp_16_76); - r4bs r4bs_6080_2136(yy[41], yy[42], single[17], double[17], neg[17], pp_17_76); - r4bs r4bs_6080_2264(yy[39], yy[40], single[18], double[18], neg[18], pp_18_76); - fullAdd_x FA_6080_2392(int_9_76, int_8_76, pp_16_76, pp_17_76, pp_18_76); - r4bs r4bs_6080_2608(yy[37], yy[38], single[19], double[19], neg[19], pp_19_76); - r4bs r4bs_6080_2736(yy[35], yy[36], single[20], double[20], neg[20], pp_20_76); - r4bs r4bs_6080_2864(yy[33], yy[34], single[21], double[21], neg[21], pp_21_76); - fullAdd_x FA_6080_2992(int_11_76, int_10_76, pp_19_76, pp_20_76, pp_21_76); - r4bs r4bs_6080_3208(yy[31], yy[32], single[22], double[22], neg[22], pp_22_76); - r4bs r4bs_6080_3336(yy[29], yy[30], single[23], double[23], neg[23], pp_23_76); - r4bs r4bs_6080_3464(yy[27], yy[28], single[24], double[24], neg[24], pp_24_76); - fullAdd_x FA_6080_3592(int_13_76, int_12_76, pp_22_76, pp_23_76, pp_24_76); - r4bs r4bs_6080_3808(yy[25], yy[26], single[25], double[25], neg[25], pp_25_76); - r4bs r4bs_6080_3936(yy[23], yy[24], single[26], double[26], neg[26], pp_26_76); - r4bs r4bs_6080_4064(yy[21], yy[22], single[27], double[27], neg[27], pp_27_76); - fullAdd_x FA_6080_4192(int_15_76, int_14_76, pp_25_76, pp_26_76, pp_27_76); - r4bs r4bs_6080_4408(yy[19], yy[20], single[28], double[28], neg[28], pp_28_76); - r4bs r4bs_6080_4536(yy[17], yy[18], single[29], double[29], neg[29], pp_29_76); - r4bs r4bs_6080_4664(yy[15], yy[16], single[30], double[30], neg[30], pp_30_76); - fullAdd_x FA_6080_4792(int_17_76, int_16_76, pp_28_76, pp_29_76, pp_30_76); - r4bs r4bs_6080_5008(yy[13], yy[14], single[31], double[31], neg[31], pp_31_76); - r4bs r4bs_6080_5136(yy[11], yy[12], single[32], double[32], neg[32], pp_32_76); - fullAdd_x FA_6080_5264(int_19_76, int_18_76, pp_31_76, pp_32_76, int_1_75); - fullAdd_x FA_6080_5480(int_21_76, int_20_76, int_3_75, int_5_75, int_7_75); - fullAdd_x FA_6080_5696(int_23_76, int_22_76, int_9_75, int_11_75, int_13_75); - fullAdd_x FA_6080_5912(int_25_76, int_24_76, int_15_75, int_17_75, int_0_76); - fullAdd_x FA_6080_6128(int_27_76, int_26_76, int_19_75, int_21_75, int_23_75); - fullAdd_x FA_6080_6344(int_29_76, int_28_76, int_2_76, int_4_76, int_6_76); - fullAdd_x FA_6080_6560(int_31_76, int_30_76, int_8_76, int_10_76, int_12_76); - fullAdd_x FA_6080_6776(int_33_76, int_32_76, int_14_76, int_16_76, int_18_76); - fullAdd_x FA_6080_6992(int_35_76, int_34_76, int_25_75, int_27_75, int_29_75); - fullAdd_x FA_6080_7208(int_37_76, int_36_76, int_31_75, int_20_76, int_22_76); - fullAdd_x FA_6080_7424(int_39_76, int_38_76, int_24_76, int_33_75, int_35_75); - fullAdd_x FA_6080_7640(int_41_76, int_40_76, int_37_75, int_26_76, int_28_76); - fullAdd_x FA_6080_7856(int_43_76, int_42_76, int_30_76, int_32_76, int_39_75); - fullAdd_x FA_6080_8072(int_45_76, int_44_76, int_41_75, int_34_76, int_36_76); - fullAdd_x FA_6080_8288(int_47_76, int_46_76, int_38_76, int_43_75, int_45_75); - fullAdd_x FA_6080_8504(int_49_76, int_48_76, int_40_76, int_42_76, int_47_75); - fullAdd_x FA_6080_8720(int_51_76, int_50_76, int_44_76, int_49_75, int_46_76); - fullAdd_x FA_6080_8936(int_53_76, int_52_76, int_48_76, int_51_75, int_50_76); - assign Sum[76] = int_53_75; - assign Carry[76] = int_52_76; - - // Hardware for column 77 - - r4bs r4bs_6160_0(yy[62], yy[63], single[7], double[7], neg[7], pp_7_77); - r4bs r4bs_6160_128(yy[60], yy[61], single[8], double[8], neg[8], pp_8_77); - fullAdd_x FA_6160_256(int_1_77, int_0_77, negbar[6], pp_7_77, pp_8_77); - r4bs r4bs_6160_472(yy[58], yy[59], single[9], double[9], neg[9], pp_9_77); - r4bs r4bs_6160_600(yy[56], yy[57], single[10], double[10], neg[10], pp_10_77); - r4bs r4bs_6160_728(yy[54], yy[55], single[11], double[11], neg[11], pp_11_77); - fullAdd_x FA_6160_856(int_3_77, int_2_77, pp_9_77, pp_10_77, pp_11_77); - r4bs r4bs_6160_1072(yy[52], yy[53], single[12], double[12], neg[12], pp_12_77); - r4bs r4bs_6160_1200(yy[50], yy[51], single[13], double[13], neg[13], pp_13_77); - r4bs r4bs_6160_1328(yy[48], yy[49], single[14], double[14], neg[14], pp_14_77); - fullAdd_x FA_6160_1456(int_5_77, int_4_77, pp_12_77, pp_13_77, pp_14_77); - r4bs r4bs_6160_1672(yy[46], yy[47], single[15], double[15], neg[15], pp_15_77); - r4bs r4bs_6160_1800(yy[44], yy[45], single[16], double[16], neg[16], pp_16_77); - r4bs r4bs_6160_1928(yy[42], yy[43], single[17], double[17], neg[17], pp_17_77); - fullAdd_x FA_6160_2056(int_7_77, int_6_77, pp_15_77, pp_16_77, pp_17_77); - r4bs r4bs_6160_2272(yy[40], yy[41], single[18], double[18], neg[18], pp_18_77); - r4bs r4bs_6160_2400(yy[38], yy[39], single[19], double[19], neg[19], pp_19_77); - r4bs r4bs_6160_2528(yy[36], yy[37], single[20], double[20], neg[20], pp_20_77); - fullAdd_x FA_6160_2656(int_9_77, int_8_77, pp_18_77, pp_19_77, pp_20_77); - r4bs r4bs_6160_2872(yy[34], yy[35], single[21], double[21], neg[21], pp_21_77); - r4bs r4bs_6160_3000(yy[32], yy[33], single[22], double[22], neg[22], pp_22_77); - r4bs r4bs_6160_3128(yy[30], yy[31], single[23], double[23], neg[23], pp_23_77); - fullAdd_x FA_6160_3256(int_11_77, int_10_77, pp_21_77, pp_22_77, pp_23_77); - r4bs r4bs_6160_3472(yy[28], yy[29], single[24], double[24], neg[24], pp_24_77); - r4bs r4bs_6160_3600(yy[26], yy[27], single[25], double[25], neg[25], pp_25_77); - r4bs r4bs_6160_3728(yy[24], yy[25], single[26], double[26], neg[26], pp_26_77); - fullAdd_x FA_6160_3856(int_13_77, int_12_77, pp_24_77, pp_25_77, pp_26_77); - r4bs r4bs_6160_4072(yy[22], yy[23], single[27], double[27], neg[27], pp_27_77); - r4bs r4bs_6160_4200(yy[20], yy[21], single[28], double[28], neg[28], pp_28_77); - r4bs r4bs_6160_4328(yy[18], yy[19], single[29], double[29], neg[29], pp_29_77); - fullAdd_x FA_6160_4456(int_15_77, int_14_77, pp_27_77, pp_28_77, pp_29_77); - r4bs r4bs_6160_4672(yy[16], yy[17], single[30], double[30], neg[30], pp_30_77); - r4bs r4bs_6160_4800(yy[14], yy[15], single[31], double[31], neg[31], pp_31_77); - r4bs r4bs_6160_4928(yy[12], yy[13], single[32], double[32], neg[32], pp_32_77); - fullAdd_x FA_6160_5056(int_17_77, int_16_77, pp_30_77, pp_31_77, pp_32_77); - fullAdd_x FA_6160_5272(int_19_77, int_18_77, int_1_76, int_3_76, int_5_76); - fullAdd_x FA_6160_5488(int_21_77, int_20_77, int_7_76, int_9_76, int_11_76); - fullAdd_x FA_6160_5704(int_23_77, int_22_77, int_13_76, int_15_76, int_17_76); - fullAdd_x FA_6160_5920(int_25_77, int_24_77, int_19_76, int_21_76, int_23_76); - fullAdd_x FA_6160_6136(int_27_77, int_26_77, int_25_76, int_0_77, int_2_77); - fullAdd_x FA_6160_6352(int_29_77, int_28_77, int_4_77, int_6_77, int_8_77); - fullAdd_x FA_6160_6568(int_31_77, int_30_77, int_10_77, int_12_77, int_14_77); - fullAdd_x FA_6160_6784(int_33_77, int_32_77, int_16_77, int_27_76, int_29_76); - fullAdd_x FA_6160_7000(int_35_77, int_34_77, int_31_76, int_33_76, int_18_77); - fullAdd_x FA_6160_7216(int_37_77, int_36_77, int_20_77, int_22_77, int_35_76); - fullAdd_x FA_6160_7432(int_39_77, int_38_77, int_37_76, int_24_77, int_26_77); - fullAdd_x FA_6160_7648(int_41_77, int_40_77, int_28_77, int_30_77, int_39_76); - fullAdd_x FA_6160_7864(int_43_77, int_42_77, int_41_76, int_32_77, int_34_77); - fullAdd_x FA_6160_8080(int_45_77, int_44_77, int_36_77, int_43_76, int_45_76); - fullAdd_x FA_6160_8296(int_47_77, int_46_77, int_38_77, int_40_77, int_47_76); - fullAdd_x FA_6160_8512(int_49_77, int_48_77, int_42_77, int_49_76, int_44_77); - fullAdd_x FA_6160_8728(int_51_77, int_50_77, int_46_77, int_51_76, int_48_77); - assign Sum[77] = int_53_76; - assign Carry[77] = int_50_77; - - // Hardware for column 78 - - r4bs r4bs_6240_0(yy[63], gnd, single[7], double[7], neg[7], pp_7_78); - halfAdd HA_6240_128(int_1_78, int_0_78, 1'b1, pp_7_78); - r4bs r4bs_6240_208(yy[61], yy[62], single[8], double[8], neg[8], pp_8_78); - r4bs r4bs_6240_336(yy[59], yy[60], single[9], double[9], neg[9], pp_9_78); - r4bs r4bs_6240_464(yy[57], yy[58], single[10], double[10], neg[10], pp_10_78); - fullAdd_x FA_6240_592(int_3_78, int_2_78, pp_8_78, pp_9_78, pp_10_78); - r4bs r4bs_6240_808(yy[55], yy[56], single[11], double[11], neg[11], pp_11_78); - r4bs r4bs_6240_936(yy[53], yy[54], single[12], double[12], neg[12], pp_12_78); - r4bs r4bs_6240_1064(yy[51], yy[52], single[13], double[13], neg[13], pp_13_78); - fullAdd_x FA_6240_1192(int_5_78, int_4_78, pp_11_78, pp_12_78, pp_13_78); - r4bs r4bs_6240_1408(yy[49], yy[50], single[14], double[14], neg[14], pp_14_78); - r4bs r4bs_6240_1536(yy[47], yy[48], single[15], double[15], neg[15], pp_15_78); - r4bs r4bs_6240_1664(yy[45], yy[46], single[16], double[16], neg[16], pp_16_78); - fullAdd_x FA_6240_1792(int_7_78, int_6_78, pp_14_78, pp_15_78, pp_16_78); - r4bs r4bs_6240_2008(yy[43], yy[44], single[17], double[17], neg[17], pp_17_78); - r4bs r4bs_6240_2136(yy[41], yy[42], single[18], double[18], neg[18], pp_18_78); - r4bs r4bs_6240_2264(yy[39], yy[40], single[19], double[19], neg[19], pp_19_78); - fullAdd_x FA_6240_2392(int_9_78, int_8_78, pp_17_78, pp_18_78, pp_19_78); - r4bs r4bs_6240_2608(yy[37], yy[38], single[20], double[20], neg[20], pp_20_78); - r4bs r4bs_6240_2736(yy[35], yy[36], single[21], double[21], neg[21], pp_21_78); - r4bs r4bs_6240_2864(yy[33], yy[34], single[22], double[22], neg[22], pp_22_78); - fullAdd_x FA_6240_2992(int_11_78, int_10_78, pp_20_78, pp_21_78, pp_22_78); - r4bs r4bs_6240_3208(yy[31], yy[32], single[23], double[23], neg[23], pp_23_78); - r4bs r4bs_6240_3336(yy[29], yy[30], single[24], double[24], neg[24], pp_24_78); - r4bs r4bs_6240_3464(yy[27], yy[28], single[25], double[25], neg[25], pp_25_78); - fullAdd_x FA_6240_3592(int_13_78, int_12_78, pp_23_78, pp_24_78, pp_25_78); - r4bs r4bs_6240_3808(yy[25], yy[26], single[26], double[26], neg[26], pp_26_78); - r4bs r4bs_6240_3936(yy[23], yy[24], single[27], double[27], neg[27], pp_27_78); - r4bs r4bs_6240_4064(yy[21], yy[22], single[28], double[28], neg[28], pp_28_78); - fullAdd_x FA_6240_4192(int_15_78, int_14_78, pp_26_78, pp_27_78, pp_28_78); - r4bs r4bs_6240_4408(yy[19], yy[20], single[29], double[29], neg[29], pp_29_78); - r4bs r4bs_6240_4536(yy[17], yy[18], single[30], double[30], neg[30], pp_30_78); - r4bs r4bs_6240_4664(yy[15], yy[16], single[31], double[31], neg[31], pp_31_78); - fullAdd_x FA_6240_4792(int_17_78, int_16_78, pp_29_78, pp_30_78, pp_31_78); - r4bs r4bs_6240_5008(yy[13], yy[14], single[32], double[32], neg[32], pp_32_78); - fullAdd_x FA_6240_5136(int_19_78, int_18_78, pp_32_78, int_1_77, int_3_77); - fullAdd_x FA_6240_5352(int_21_78, int_20_78, int_5_77, int_7_77, int_9_77); - fullAdd_x FA_6240_5568(int_23_78, int_22_78, int_11_77, int_13_77, int_15_77); - fullAdd_x FA_6240_5784(int_25_78, int_24_78, int_17_77, int_0_78, int_19_77); - fullAdd_x FA_6240_6000(int_27_78, int_26_78, int_21_77, int_23_77, int_2_78); - fullAdd_x FA_6240_6216(int_29_78, int_28_78, int_4_78, int_6_78, int_8_78); - fullAdd_x FA_6240_6432(int_31_78, int_30_78, int_10_78, int_12_78, int_14_78); - fullAdd_x FA_6240_6648(int_33_78, int_32_78, int_16_78, int_25_77, int_27_77); - fullAdd_x FA_6240_6864(int_35_78, int_34_78, int_29_77, int_31_77, int_18_78); - fullAdd_x FA_6240_7080(int_37_78, int_36_78, int_20_78, int_22_78, int_24_78); - fullAdd_x FA_6240_7296(int_39_78, int_38_78, int_33_77, int_35_77, int_26_78); - fullAdd_x FA_6240_7512(int_41_78, int_40_78, int_28_78, int_30_78, int_37_77); - fullAdd_x FA_6240_7728(int_43_78, int_42_78, int_39_77, int_32_78, int_34_78); - fullAdd_x FA_6240_7944(int_45_78, int_44_78, int_36_78, int_41_77, int_43_77); - fullAdd_x FA_6240_8160(int_47_78, int_46_78, int_38_78, int_40_78, int_45_77); - fullAdd_x FA_6240_8376(int_49_78, int_48_78, int_42_78, int_47_77, int_44_78); - fullAdd_x FA_6240_8592(int_51_78, int_50_78, int_46_78, int_49_77, int_48_78); - assign Sum[78] = int_51_77; - assign Carry[78] = int_50_78; - - // Hardware for column 79 - - r4bs r4bs_6320_0(yy[62], yy[63], single[8], double[8], neg[8], pp_8_79); - r4bs r4bs_6320_128(yy[60], yy[61], single[9], double[9], neg[9], pp_9_79); - fullAdd_x FA_6320_256(int_1_79, int_0_79, negbar[7], pp_8_79, pp_9_79); - r4bs r4bs_6320_472(yy[58], yy[59], single[10], double[10], neg[10], pp_10_79); - r4bs r4bs_6320_600(yy[56], yy[57], single[11], double[11], neg[11], pp_11_79); - r4bs r4bs_6320_728(yy[54], yy[55], single[12], double[12], neg[12], pp_12_79); - fullAdd_x FA_6320_856(int_3_79, int_2_79, pp_10_79, pp_11_79, pp_12_79); - r4bs r4bs_6320_1072(yy[52], yy[53], single[13], double[13], neg[13], pp_13_79); - r4bs r4bs_6320_1200(yy[50], yy[51], single[14], double[14], neg[14], pp_14_79); - r4bs r4bs_6320_1328(yy[48], yy[49], single[15], double[15], neg[15], pp_15_79); - fullAdd_x FA_6320_1456(int_5_79, int_4_79, pp_13_79, pp_14_79, pp_15_79); - r4bs r4bs_6320_1672(yy[46], yy[47], single[16], double[16], neg[16], pp_16_79); - r4bs r4bs_6320_1800(yy[44], yy[45], single[17], double[17], neg[17], pp_17_79); - r4bs r4bs_6320_1928(yy[42], yy[43], single[18], double[18], neg[18], pp_18_79); - fullAdd_x FA_6320_2056(int_7_79, int_6_79, pp_16_79, pp_17_79, pp_18_79); - r4bs r4bs_6320_2272(yy[40], yy[41], single[19], double[19], neg[19], pp_19_79); - r4bs r4bs_6320_2400(yy[38], yy[39], single[20], double[20], neg[20], pp_20_79); - r4bs r4bs_6320_2528(yy[36], yy[37], single[21], double[21], neg[21], pp_21_79); - fullAdd_x FA_6320_2656(int_9_79, int_8_79, pp_19_79, pp_20_79, pp_21_79); - r4bs r4bs_6320_2872(yy[34], yy[35], single[22], double[22], neg[22], pp_22_79); - r4bs r4bs_6320_3000(yy[32], yy[33], single[23], double[23], neg[23], pp_23_79); - r4bs r4bs_6320_3128(yy[30], yy[31], single[24], double[24], neg[24], pp_24_79); - fullAdd_x FA_6320_3256(int_11_79, int_10_79, pp_22_79, pp_23_79, pp_24_79); - r4bs r4bs_6320_3472(yy[28], yy[29], single[25], double[25], neg[25], pp_25_79); - r4bs r4bs_6320_3600(yy[26], yy[27], single[26], double[26], neg[26], pp_26_79); - r4bs r4bs_6320_3728(yy[24], yy[25], single[27], double[27], neg[27], pp_27_79); - fullAdd_x FA_6320_3856(int_13_79, int_12_79, pp_25_79, pp_26_79, pp_27_79); - r4bs r4bs_6320_4072(yy[22], yy[23], single[28], double[28], neg[28], pp_28_79); - r4bs r4bs_6320_4200(yy[20], yy[21], single[29], double[29], neg[29], pp_29_79); - r4bs r4bs_6320_4328(yy[18], yy[19], single[30], double[30], neg[30], pp_30_79); - fullAdd_x FA_6320_4456(int_15_79, int_14_79, pp_28_79, pp_29_79, pp_30_79); - r4bs r4bs_6320_4672(yy[16], yy[17], single[31], double[31], neg[31], pp_31_79); - r4bs r4bs_6320_4800(yy[14], yy[15], single[32], double[32], neg[32], pp_32_79); - fullAdd_x FA_6320_4928(int_17_79, int_16_79, pp_31_79, pp_32_79, int_1_78); - fullAdd_x FA_6320_5144(int_19_79, int_18_79, int_3_78, int_5_78, int_7_78); - fullAdd_x FA_6320_5360(int_21_79, int_20_79, int_9_78, int_11_78, int_13_78); - fullAdd_x FA_6320_5576(int_23_79, int_22_79, int_15_78, int_17_78, int_19_78); - fullAdd_x FA_6320_5792(int_25_79, int_24_79, int_21_78, int_23_78, int_0_79); - fullAdd_x FA_6320_6008(int_27_79, int_26_79, int_2_79, int_4_79, int_6_79); - fullAdd_x FA_6320_6224(int_29_79, int_28_79, int_8_79, int_10_79, int_12_79); - fullAdd_x FA_6320_6440(int_31_79, int_30_79, int_14_79, int_16_79, int_25_78); - fullAdd_x FA_6320_6656(int_33_79, int_32_79, int_27_78, int_29_78, int_31_78); - fullAdd_x FA_6320_6872(int_35_79, int_34_79, int_18_79, int_20_79, int_22_79); - fullAdd_x FA_6320_7088(int_37_79, int_36_79, int_33_78, int_35_78, int_37_78); - fullAdd_x FA_6320_7304(int_39_79, int_38_79, int_24_79, int_26_79, int_28_79); - fullAdd_x FA_6320_7520(int_41_79, int_40_79, int_30_79, int_39_78, int_32_79); - fullAdd_x FA_6320_7736(int_43_79, int_42_79, int_34_79, int_41_78, int_43_78); - fullAdd_x FA_6320_7952(int_45_79, int_44_79, int_36_79, int_38_79, int_45_78); - fullAdd_x FA_6320_8168(int_47_79, int_46_79, int_40_79, int_47_78, int_42_79); - fullAdd_x FA_6320_8384(int_49_79, int_48_79, int_44_79, int_49_78, int_46_79); - assign Sum[79] = int_51_78; - assign Carry[79] = int_48_79; - - // Hardware for column 80 - - r4bs r4bs_6400_0(yy[63], gnd, single[8], double[8], neg[8], pp_8_80); - halfAdd HA_6400_128(int_1_80, int_0_80, 1'b1, pp_8_80); - r4bs r4bs_6400_208(yy[61], yy[62], single[9], double[9], neg[9], pp_9_80); - r4bs r4bs_6400_336(yy[59], yy[60], single[10], double[10], neg[10], pp_10_80); - r4bs r4bs_6400_464(yy[57], yy[58], single[11], double[11], neg[11], pp_11_80); - fullAdd_x FA_6400_592(int_3_80, int_2_80, pp_9_80, pp_10_80, pp_11_80); - r4bs r4bs_6400_808(yy[55], yy[56], single[12], double[12], neg[12], pp_12_80); - r4bs r4bs_6400_936(yy[53], yy[54], single[13], double[13], neg[13], pp_13_80); - r4bs r4bs_6400_1064(yy[51], yy[52], single[14], double[14], neg[14], pp_14_80); - fullAdd_x FA_6400_1192(int_5_80, int_4_80, pp_12_80, pp_13_80, pp_14_80); - r4bs r4bs_6400_1408(yy[49], yy[50], single[15], double[15], neg[15], pp_15_80); - r4bs r4bs_6400_1536(yy[47], yy[48], single[16], double[16], neg[16], pp_16_80); - r4bs r4bs_6400_1664(yy[45], yy[46], single[17], double[17], neg[17], pp_17_80); - fullAdd_x FA_6400_1792(int_7_80, int_6_80, pp_15_80, pp_16_80, pp_17_80); - r4bs r4bs_6400_2008(yy[43], yy[44], single[18], double[18], neg[18], pp_18_80); - r4bs r4bs_6400_2136(yy[41], yy[42], single[19], double[19], neg[19], pp_19_80); - r4bs r4bs_6400_2264(yy[39], yy[40], single[20], double[20], neg[20], pp_20_80); - fullAdd_x FA_6400_2392(int_9_80, int_8_80, pp_18_80, pp_19_80, pp_20_80); - r4bs r4bs_6400_2608(yy[37], yy[38], single[21], double[21], neg[21], pp_21_80); - r4bs r4bs_6400_2736(yy[35], yy[36], single[22], double[22], neg[22], pp_22_80); - r4bs r4bs_6400_2864(yy[33], yy[34], single[23], double[23], neg[23], pp_23_80); - fullAdd_x FA_6400_2992(int_11_80, int_10_80, pp_21_80, pp_22_80, pp_23_80); - r4bs r4bs_6400_3208(yy[31], yy[32], single[24], double[24], neg[24], pp_24_80); - r4bs r4bs_6400_3336(yy[29], yy[30], single[25], double[25], neg[25], pp_25_80); - r4bs r4bs_6400_3464(yy[27], yy[28], single[26], double[26], neg[26], pp_26_80); - fullAdd_x FA_6400_3592(int_13_80, int_12_80, pp_24_80, pp_25_80, pp_26_80); - r4bs r4bs_6400_3808(yy[25], yy[26], single[27], double[27], neg[27], pp_27_80); - r4bs r4bs_6400_3936(yy[23], yy[24], single[28], double[28], neg[28], pp_28_80); - r4bs r4bs_6400_4064(yy[21], yy[22], single[29], double[29], neg[29], pp_29_80); - fullAdd_x FA_6400_4192(int_15_80, int_14_80, pp_27_80, pp_28_80, pp_29_80); - r4bs r4bs_6400_4408(yy[19], yy[20], single[30], double[30], neg[30], pp_30_80); - r4bs r4bs_6400_4536(yy[17], yy[18], single[31], double[31], neg[31], pp_31_80); - r4bs r4bs_6400_4664(yy[15], yy[16], single[32], double[32], neg[32], pp_32_80); - fullAdd_x FA_6400_4792(int_17_80, int_16_80, pp_30_80, pp_31_80, pp_32_80); - fullAdd_x FA_6400_5008(int_19_80, int_18_80, int_1_79, int_3_79, int_5_79); - fullAdd_x FA_6400_5224(int_21_80, int_20_80, int_7_79, int_9_79, int_11_79); - fullAdd_x FA_6400_5440(int_23_80, int_22_80, int_13_79, int_15_79, int_0_80); - fullAdd_x FA_6400_5656(int_25_80, int_24_80, int_17_79, int_19_79, int_21_79); - fullAdd_x FA_6400_5872(int_27_80, int_26_80, int_2_80, int_4_80, int_6_80); - fullAdd_x FA_6400_6088(int_29_80, int_28_80, int_8_80, int_10_80, int_12_80); - fullAdd_x FA_6400_6304(int_31_80, int_30_80, int_14_80, int_16_80, int_23_79); - fullAdd_x FA_6400_6520(int_33_80, int_32_80, int_25_79, int_27_79, int_29_79); - fullAdd_x FA_6400_6736(int_35_80, int_34_80, int_18_80, int_20_80, int_22_80); - fullAdd_x FA_6400_6952(int_37_80, int_36_80, int_31_79, int_33_79, int_35_79); - fullAdd_x FA_6400_7168(int_39_80, int_38_80, int_24_80, int_26_80, int_28_80); - fullAdd_x FA_6400_7384(int_41_80, int_40_80, int_30_80, int_37_79, int_39_79); - fullAdd_x FA_6400_7600(int_43_80, int_42_80, int_32_80, int_34_80, int_41_79); - fullAdd_x FA_6400_7816(int_45_80, int_44_80, int_36_80, int_38_80, int_43_79); - fullAdd_x FA_6400_8032(int_47_80, int_46_80, int_40_80, int_42_80, int_45_79); - fullAdd_x FA_6400_8248(int_49_80, int_48_80, int_44_80, int_47_79, int_46_80); - assign Sum[80] = int_49_79; - assign Carry[80] = int_48_80; - - // Hardware for column 81 - - r4bs r4bs_6480_0(yy[62], yy[63], single[9], double[9], neg[9], pp_9_81); - r4bs r4bs_6480_128(yy[60], yy[61], single[10], double[10], neg[10], pp_10_81); - fullAdd_x FA_6480_256(int_1_81, int_0_81, negbar[8], pp_9_81, pp_10_81); - r4bs r4bs_6480_472(yy[58], yy[59], single[11], double[11], neg[11], pp_11_81); - r4bs r4bs_6480_600(yy[56], yy[57], single[12], double[12], neg[12], pp_12_81); - r4bs r4bs_6480_728(yy[54], yy[55], single[13], double[13], neg[13], pp_13_81); - fullAdd_x FA_6480_856(int_3_81, int_2_81, pp_11_81, pp_12_81, pp_13_81); - r4bs r4bs_6480_1072(yy[52], yy[53], single[14], double[14], neg[14], pp_14_81); - r4bs r4bs_6480_1200(yy[50], yy[51], single[15], double[15], neg[15], pp_15_81); - r4bs r4bs_6480_1328(yy[48], yy[49], single[16], double[16], neg[16], pp_16_81); - fullAdd_x FA_6480_1456(int_5_81, int_4_81, pp_14_81, pp_15_81, pp_16_81); - r4bs r4bs_6480_1672(yy[46], yy[47], single[17], double[17], neg[17], pp_17_81); - r4bs r4bs_6480_1800(yy[44], yy[45], single[18], double[18], neg[18], pp_18_81); - r4bs r4bs_6480_1928(yy[42], yy[43], single[19], double[19], neg[19], pp_19_81); - fullAdd_x FA_6480_2056(int_7_81, int_6_81, pp_17_81, pp_18_81, pp_19_81); - r4bs r4bs_6480_2272(yy[40], yy[41], single[20], double[20], neg[20], pp_20_81); - r4bs r4bs_6480_2400(yy[38], yy[39], single[21], double[21], neg[21], pp_21_81); - r4bs r4bs_6480_2528(yy[36], yy[37], single[22], double[22], neg[22], pp_22_81); - fullAdd_x FA_6480_2656(int_9_81, int_8_81, pp_20_81, pp_21_81, pp_22_81); - r4bs r4bs_6480_2872(yy[34], yy[35], single[23], double[23], neg[23], pp_23_81); - r4bs r4bs_6480_3000(yy[32], yy[33], single[24], double[24], neg[24], pp_24_81); - r4bs r4bs_6480_3128(yy[30], yy[31], single[25], double[25], neg[25], pp_25_81); - fullAdd_x FA_6480_3256(int_11_81, int_10_81, pp_23_81, pp_24_81, pp_25_81); - r4bs r4bs_6480_3472(yy[28], yy[29], single[26], double[26], neg[26], pp_26_81); - r4bs r4bs_6480_3600(yy[26], yy[27], single[27], double[27], neg[27], pp_27_81); - r4bs r4bs_6480_3728(yy[24], yy[25], single[28], double[28], neg[28], pp_28_81); - fullAdd_x FA_6480_3856(int_13_81, int_12_81, pp_26_81, pp_27_81, pp_28_81); - r4bs r4bs_6480_4072(yy[22], yy[23], single[29], double[29], neg[29], pp_29_81); - r4bs r4bs_6480_4200(yy[20], yy[21], single[30], double[30], neg[30], pp_30_81); - r4bs r4bs_6480_4328(yy[18], yy[19], single[31], double[31], neg[31], pp_31_81); - fullAdd_x FA_6480_4456(int_15_81, int_14_81, pp_29_81, pp_30_81, pp_31_81); - r4bs r4bs_6480_4672(yy[16], yy[17], single[32], double[32], neg[32], pp_32_81); - fullAdd_x FA_6480_4800(int_17_81, int_16_81, pp_32_81, int_1_80, int_3_80); - fullAdd_x FA_6480_5016(int_19_81, int_18_81, int_5_80, int_7_80, int_9_80); - fullAdd_x FA_6480_5232(int_21_81, int_20_81, int_11_80, int_13_80, int_15_80); - fullAdd_x FA_6480_5448(int_23_81, int_22_81, int_17_80, int_19_80, int_21_80); - fullAdd_x FA_6480_5664(int_25_81, int_24_81, int_23_80, int_0_81, int_2_81); - fullAdd_x FA_6480_5880(int_27_81, int_26_81, int_4_81, int_6_81, int_8_81); - fullAdd_x FA_6480_6096(int_29_81, int_28_81, int_10_81, int_12_81, int_14_81); - fullAdd_x FA_6480_6312(int_31_81, int_30_81, int_16_81, int_25_80, int_27_80); - fullAdd_x FA_6480_6528(int_33_81, int_32_81, int_29_80, int_18_81, int_20_81); - fullAdd_x FA_6480_6744(int_35_81, int_34_81, int_31_80, int_33_80, int_35_80); - fullAdd_x FA_6480_6960(int_37_81, int_36_81, int_22_81, int_24_81, int_26_81); - fullAdd_x FA_6480_7176(int_39_81, int_38_81, int_28_81, int_37_80, int_39_80); - fullAdd_x FA_6480_7392(int_41_81, int_40_81, int_30_81, int_32_81, int_41_80); - fullAdd_x FA_6480_7608(int_43_81, int_42_81, int_34_81, int_36_81, int_43_80); - fullAdd_x FA_6480_7824(int_45_81, int_44_81, int_38_81, int_40_81, int_45_80); - fullAdd_x FA_6480_8040(int_47_81, int_46_81, int_42_81, int_47_80, int_44_81); - assign Sum[81] = int_49_80; - assign Carry[81] = int_46_81; - - // Hardware for column 82 - - r4bs r4bs_6560_0(yy[63], gnd, single[9], double[9], neg[9], pp_9_82); - halfAdd HA_6560_128(int_1_82, int_0_82, 1'b1, pp_9_82); - r4bs r4bs_6560_208(yy[61], yy[62], single[10], double[10], neg[10], pp_10_82); - r4bs r4bs_6560_336(yy[59], yy[60], single[11], double[11], neg[11], pp_11_82); - r4bs r4bs_6560_464(yy[57], yy[58], single[12], double[12], neg[12], pp_12_82); - fullAdd_x FA_6560_592(int_3_82, int_2_82, pp_10_82, pp_11_82, pp_12_82); - r4bs r4bs_6560_808(yy[55], yy[56], single[13], double[13], neg[13], pp_13_82); - r4bs r4bs_6560_936(yy[53], yy[54], single[14], double[14], neg[14], pp_14_82); - r4bs r4bs_6560_1064(yy[51], yy[52], single[15], double[15], neg[15], pp_15_82); - fullAdd_x FA_6560_1192(int_5_82, int_4_82, pp_13_82, pp_14_82, pp_15_82); - r4bs r4bs_6560_1408(yy[49], yy[50], single[16], double[16], neg[16], pp_16_82); - r4bs r4bs_6560_1536(yy[47], yy[48], single[17], double[17], neg[17], pp_17_82); - r4bs r4bs_6560_1664(yy[45], yy[46], single[18], double[18], neg[18], pp_18_82); - fullAdd_x FA_6560_1792(int_7_82, int_6_82, pp_16_82, pp_17_82, pp_18_82); - r4bs r4bs_6560_2008(yy[43], yy[44], single[19], double[19], neg[19], pp_19_82); - r4bs r4bs_6560_2136(yy[41], yy[42], single[20], double[20], neg[20], pp_20_82); - r4bs r4bs_6560_2264(yy[39], yy[40], single[21], double[21], neg[21], pp_21_82); - fullAdd_x FA_6560_2392(int_9_82, int_8_82, pp_19_82, pp_20_82, pp_21_82); - r4bs r4bs_6560_2608(yy[37], yy[38], single[22], double[22], neg[22], pp_22_82); - r4bs r4bs_6560_2736(yy[35], yy[36], single[23], double[23], neg[23], pp_23_82); - r4bs r4bs_6560_2864(yy[33], yy[34], single[24], double[24], neg[24], pp_24_82); - fullAdd_x FA_6560_2992(int_11_82, int_10_82, pp_22_82, pp_23_82, pp_24_82); - r4bs r4bs_6560_3208(yy[31], yy[32], single[25], double[25], neg[25], pp_25_82); - r4bs r4bs_6560_3336(yy[29], yy[30], single[26], double[26], neg[26], pp_26_82); - r4bs r4bs_6560_3464(yy[27], yy[28], single[27], double[27], neg[27], pp_27_82); - fullAdd_x FA_6560_3592(int_13_82, int_12_82, pp_25_82, pp_26_82, pp_27_82); - r4bs r4bs_6560_3808(yy[25], yy[26], single[28], double[28], neg[28], pp_28_82); - r4bs r4bs_6560_3936(yy[23], yy[24], single[29], double[29], neg[29], pp_29_82); - r4bs r4bs_6560_4064(yy[21], yy[22], single[30], double[30], neg[30], pp_30_82); - fullAdd_x FA_6560_4192(int_15_82, int_14_82, pp_28_82, pp_29_82, pp_30_82); - r4bs r4bs_6560_4408(yy[19], yy[20], single[31], double[31], neg[31], pp_31_82); - r4bs r4bs_6560_4536(yy[17], yy[18], single[32], double[32], neg[32], pp_32_82); - fullAdd_x FA_6560_4664(int_17_82, int_16_82, pp_31_82, pp_32_82, int_1_81); - fullAdd_x FA_6560_4880(int_19_82, int_18_82, int_3_81, int_5_81, int_7_81); - fullAdd_x FA_6560_5096(int_21_82, int_20_82, int_9_81, int_11_81, int_13_81); - fullAdd_x FA_6560_5312(int_23_82, int_22_82, int_15_81, int_0_82, int_17_81); - fullAdd_x FA_6560_5528(int_25_82, int_24_82, int_19_81, int_21_81, int_2_82); - fullAdd_x FA_6560_5744(int_27_82, int_26_82, int_4_82, int_6_82, int_8_82); - fullAdd_x FA_6560_5960(int_29_82, int_28_82, int_10_82, int_12_82, int_14_82); - fullAdd_x FA_6560_6176(int_31_82, int_30_82, int_16_82, int_23_81, int_25_81); - fullAdd_x FA_6560_6392(int_33_82, int_32_82, int_27_81, int_29_81, int_18_82); - fullAdd_x FA_6560_6608(int_35_82, int_34_82, int_20_82, int_22_82, int_31_81); - fullAdd_x FA_6560_6824(int_37_82, int_36_82, int_33_81, int_24_82, int_26_82); - fullAdd_x FA_6560_7040(int_39_82, int_38_82, int_28_82, int_35_81, int_37_81); - fullAdd_x FA_6560_7256(int_41_82, int_40_82, int_30_82, int_32_82, int_34_82); - fullAdd_x FA_6560_7472(int_43_82, int_42_82, int_39_81, int_36_82, int_41_81); - fullAdd_x FA_6560_7688(int_45_82, int_44_82, int_38_82, int_40_82, int_43_81); - fullAdd_x FA_6560_7904(int_47_82, int_46_82, int_42_82, int_45_81, int_44_82); - assign Sum[82] = int_47_81; - assign Carry[82] = int_46_82; - - // Hardware for column 83 - - r4bs r4bs_6640_0(yy[62], yy[63], single[10], double[10], neg[10], pp_10_83); - r4bs r4bs_6640_128(yy[60], yy[61], single[11], double[11], neg[11], pp_11_83); - fullAdd_x FA_6640_256(int_1_83, int_0_83, negbar[9], pp_10_83, pp_11_83); - r4bs r4bs_6640_472(yy[58], yy[59], single[12], double[12], neg[12], pp_12_83); - r4bs r4bs_6640_600(yy[56], yy[57], single[13], double[13], neg[13], pp_13_83); - r4bs r4bs_6640_728(yy[54], yy[55], single[14], double[14], neg[14], pp_14_83); - fullAdd_x FA_6640_856(int_3_83, int_2_83, pp_12_83, pp_13_83, pp_14_83); - r4bs r4bs_6640_1072(yy[52], yy[53], single[15], double[15], neg[15], pp_15_83); - r4bs r4bs_6640_1200(yy[50], yy[51], single[16], double[16], neg[16], pp_16_83); - r4bs r4bs_6640_1328(yy[48], yy[49], single[17], double[17], neg[17], pp_17_83); - fullAdd_x FA_6640_1456(int_5_83, int_4_83, pp_15_83, pp_16_83, pp_17_83); - r4bs r4bs_6640_1672(yy[46], yy[47], single[18], double[18], neg[18], pp_18_83); - r4bs r4bs_6640_1800(yy[44], yy[45], single[19], double[19], neg[19], pp_19_83); - r4bs r4bs_6640_1928(yy[42], yy[43], single[20], double[20], neg[20], pp_20_83); - fullAdd_x FA_6640_2056(int_7_83, int_6_83, pp_18_83, pp_19_83, pp_20_83); - r4bs r4bs_6640_2272(yy[40], yy[41], single[21], double[21], neg[21], pp_21_83); - r4bs r4bs_6640_2400(yy[38], yy[39], single[22], double[22], neg[22], pp_22_83); - r4bs r4bs_6640_2528(yy[36], yy[37], single[23], double[23], neg[23], pp_23_83); - fullAdd_x FA_6640_2656(int_9_83, int_8_83, pp_21_83, pp_22_83, pp_23_83); - r4bs r4bs_6640_2872(yy[34], yy[35], single[24], double[24], neg[24], pp_24_83); - r4bs r4bs_6640_3000(yy[32], yy[33], single[25], double[25], neg[25], pp_25_83); - r4bs r4bs_6640_3128(yy[30], yy[31], single[26], double[26], neg[26], pp_26_83); - fullAdd_x FA_6640_3256(int_11_83, int_10_83, pp_24_83, pp_25_83, pp_26_83); - r4bs r4bs_6640_3472(yy[28], yy[29], single[27], double[27], neg[27], pp_27_83); - r4bs r4bs_6640_3600(yy[26], yy[27], single[28], double[28], neg[28], pp_28_83); - r4bs r4bs_6640_3728(yy[24], yy[25], single[29], double[29], neg[29], pp_29_83); - fullAdd_x FA_6640_3856(int_13_83, int_12_83, pp_27_83, pp_28_83, pp_29_83); - r4bs r4bs_6640_4072(yy[22], yy[23], single[30], double[30], neg[30], pp_30_83); - r4bs r4bs_6640_4200(yy[20], yy[21], single[31], double[31], neg[31], pp_31_83); - r4bs r4bs_6640_4328(yy[18], yy[19], single[32], double[32], neg[32], pp_32_83); - fullAdd_x FA_6640_4456(int_15_83, int_14_83, pp_30_83, pp_31_83, pp_32_83); - fullAdd_x FA_6640_4672(int_17_83, int_16_83, int_1_82, int_3_82, int_5_82); - fullAdd_x FA_6640_4888(int_19_83, int_18_83, int_7_82, int_9_82, int_11_82); - fullAdd_x FA_6640_5104(int_21_83, int_20_83, int_13_82, int_15_82, int_17_82); - fullAdd_x FA_6640_5320(int_23_83, int_22_83, int_19_82, int_21_82, int_0_83); - fullAdd_x FA_6640_5536(int_25_83, int_24_83, int_2_83, int_4_83, int_6_83); - fullAdd_x FA_6640_5752(int_27_83, int_26_83, int_8_83, int_10_83, int_12_83); - fullAdd_x FA_6640_5968(int_29_83, int_28_83, int_14_83, int_23_82, int_25_82); - fullAdd_x FA_6640_6184(int_31_83, int_30_83, int_27_82, int_29_82, int_16_83); - fullAdd_x FA_6640_6400(int_33_83, int_32_83, int_18_83, int_20_83, int_31_82); - fullAdd_x FA_6640_6616(int_35_83, int_34_83, int_33_82, int_22_83, int_24_83); - fullAdd_x FA_6640_6832(int_37_83, int_36_83, int_26_83, int_35_82, int_37_82); - fullAdd_x FA_6640_7048(int_39_83, int_38_83, int_28_83, int_30_83, int_32_83); - fullAdd_x FA_6640_7264(int_41_83, int_40_83, int_39_82, int_41_82, int_34_83); - fullAdd_x FA_6640_7480(int_43_83, int_42_83, int_36_83, int_38_83, int_43_82); - fullAdd_x FA_6640_7696(int_45_83, int_44_83, int_40_83, int_45_82, int_42_83); - assign Sum[83] = int_47_82; - assign Carry[83] = int_44_83; - - // Hardware for column 84 - - r4bs r4bs_6720_0(yy[63], gnd, single[10], double[10], neg[10], pp_10_84); - halfAdd HA_6720_128(int_1_84, int_0_84, 1'b1, pp_10_84); - r4bs r4bs_6720_208(yy[61], yy[62], single[11], double[11], neg[11], pp_11_84); - r4bs r4bs_6720_336(yy[59], yy[60], single[12], double[12], neg[12], pp_12_84); - r4bs r4bs_6720_464(yy[57], yy[58], single[13], double[13], neg[13], pp_13_84); - fullAdd_x FA_6720_592(int_3_84, int_2_84, pp_11_84, pp_12_84, pp_13_84); - r4bs r4bs_6720_808(yy[55], yy[56], single[14], double[14], neg[14], pp_14_84); - r4bs r4bs_6720_936(yy[53], yy[54], single[15], double[15], neg[15], pp_15_84); - r4bs r4bs_6720_1064(yy[51], yy[52], single[16], double[16], neg[16], pp_16_84); - fullAdd_x FA_6720_1192(int_5_84, int_4_84, pp_14_84, pp_15_84, pp_16_84); - r4bs r4bs_6720_1408(yy[49], yy[50], single[17], double[17], neg[17], pp_17_84); - r4bs r4bs_6720_1536(yy[47], yy[48], single[18], double[18], neg[18], pp_18_84); - r4bs r4bs_6720_1664(yy[45], yy[46], single[19], double[19], neg[19], pp_19_84); - fullAdd_x FA_6720_1792(int_7_84, int_6_84, pp_17_84, pp_18_84, pp_19_84); - r4bs r4bs_6720_2008(yy[43], yy[44], single[20], double[20], neg[20], pp_20_84); - r4bs r4bs_6720_2136(yy[41], yy[42], single[21], double[21], neg[21], pp_21_84); - r4bs r4bs_6720_2264(yy[39], yy[40], single[22], double[22], neg[22], pp_22_84); - fullAdd_x FA_6720_2392(int_9_84, int_8_84, pp_20_84, pp_21_84, pp_22_84); - r4bs r4bs_6720_2608(yy[37], yy[38], single[23], double[23], neg[23], pp_23_84); - r4bs r4bs_6720_2736(yy[35], yy[36], single[24], double[24], neg[24], pp_24_84); - r4bs r4bs_6720_2864(yy[33], yy[34], single[25], double[25], neg[25], pp_25_84); - fullAdd_x FA_6720_2992(int_11_84, int_10_84, pp_23_84, pp_24_84, pp_25_84); - r4bs r4bs_6720_3208(yy[31], yy[32], single[26], double[26], neg[26], pp_26_84); - r4bs r4bs_6720_3336(yy[29], yy[30], single[27], double[27], neg[27], pp_27_84); - r4bs r4bs_6720_3464(yy[27], yy[28], single[28], double[28], neg[28], pp_28_84); - fullAdd_x FA_6720_3592(int_13_84, int_12_84, pp_26_84, pp_27_84, pp_28_84); - r4bs r4bs_6720_3808(yy[25], yy[26], single[29], double[29], neg[29], pp_29_84); - r4bs r4bs_6720_3936(yy[23], yy[24], single[30], double[30], neg[30], pp_30_84); - r4bs r4bs_6720_4064(yy[21], yy[22], single[31], double[31], neg[31], pp_31_84); - fullAdd_x FA_6720_4192(int_15_84, int_14_84, pp_29_84, pp_30_84, pp_31_84); - r4bs r4bs_6720_4408(yy[19], yy[20], single[32], double[32], neg[32], pp_32_84); - fullAdd_x FA_6720_4536(int_17_84, int_16_84, pp_32_84, int_1_83, int_3_83); - fullAdd_x FA_6720_4752(int_19_84, int_18_84, int_5_83, int_7_83, int_9_83); - fullAdd_x FA_6720_4968(int_21_84, int_20_84, int_11_83, int_13_83, int_15_83); - fullAdd_x FA_6720_5184(int_23_84, int_22_84, int_0_84, int_17_83, int_19_83); - fullAdd_x FA_6720_5400(int_25_84, int_24_84, int_2_84, int_4_84, int_6_84); - fullAdd_x FA_6720_5616(int_27_84, int_26_84, int_8_84, int_10_84, int_12_84); - fullAdd_x FA_6720_5832(int_29_84, int_28_84, int_14_84, int_21_83, int_23_83); - fullAdd_x FA_6720_6048(int_31_84, int_30_84, int_25_83, int_27_83, int_16_84); - fullAdd_x FA_6720_6264(int_33_84, int_32_84, int_18_84, int_20_84, int_29_83); - fullAdd_x FA_6720_6480(int_35_84, int_34_84, int_31_83, int_22_84, int_24_84); - fullAdd_x FA_6720_6696(int_37_84, int_36_84, int_26_84, int_33_83, int_35_83); - fullAdd_x FA_6720_6912(int_39_84, int_38_84, int_28_84, int_30_84, int_32_84); - fullAdd_x FA_6720_7128(int_41_84, int_40_84, int_37_83, int_39_83, int_34_84); - fullAdd_x FA_6720_7344(int_43_84, int_42_84, int_41_83, int_36_84, int_38_84); - fullAdd_x FA_6720_7560(int_45_84, int_44_84, int_40_84, int_43_83, int_42_84); - assign Sum[84] = int_45_83; - assign Carry[84] = int_44_84; - - // Hardware for column 85 - - r4bs r4bs_6800_0(yy[62], yy[63], single[11], double[11], neg[11], pp_11_85); - r4bs r4bs_6800_128(yy[60], yy[61], single[12], double[12], neg[12], pp_12_85); - fullAdd_x FA_6800_256(int_1_85, int_0_85, negbar[10], pp_11_85, pp_12_85); - r4bs r4bs_6800_472(yy[58], yy[59], single[13], double[13], neg[13], pp_13_85); - r4bs r4bs_6800_600(yy[56], yy[57], single[14], double[14], neg[14], pp_14_85); - r4bs r4bs_6800_728(yy[54], yy[55], single[15], double[15], neg[15], pp_15_85); - fullAdd_x FA_6800_856(int_3_85, int_2_85, pp_13_85, pp_14_85, pp_15_85); - r4bs r4bs_6800_1072(yy[52], yy[53], single[16], double[16], neg[16], pp_16_85); - r4bs r4bs_6800_1200(yy[50], yy[51], single[17], double[17], neg[17], pp_17_85); - r4bs r4bs_6800_1328(yy[48], yy[49], single[18], double[18], neg[18], pp_18_85); - fullAdd_x FA_6800_1456(int_5_85, int_4_85, pp_16_85, pp_17_85, pp_18_85); - r4bs r4bs_6800_1672(yy[46], yy[47], single[19], double[19], neg[19], pp_19_85); - r4bs r4bs_6800_1800(yy[44], yy[45], single[20], double[20], neg[20], pp_20_85); - r4bs r4bs_6800_1928(yy[42], yy[43], single[21], double[21], neg[21], pp_21_85); - fullAdd_x FA_6800_2056(int_7_85, int_6_85, pp_19_85, pp_20_85, pp_21_85); - r4bs r4bs_6800_2272(yy[40], yy[41], single[22], double[22], neg[22], pp_22_85); - r4bs r4bs_6800_2400(yy[38], yy[39], single[23], double[23], neg[23], pp_23_85); - r4bs r4bs_6800_2528(yy[36], yy[37], single[24], double[24], neg[24], pp_24_85); - fullAdd_x FA_6800_2656(int_9_85, int_8_85, pp_22_85, pp_23_85, pp_24_85); - r4bs r4bs_6800_2872(yy[34], yy[35], single[25], double[25], neg[25], pp_25_85); - r4bs r4bs_6800_3000(yy[32], yy[33], single[26], double[26], neg[26], pp_26_85); - r4bs r4bs_6800_3128(yy[30], yy[31], single[27], double[27], neg[27], pp_27_85); - fullAdd_x FA_6800_3256(int_11_85, int_10_85, pp_25_85, pp_26_85, pp_27_85); - r4bs r4bs_6800_3472(yy[28], yy[29], single[28], double[28], neg[28], pp_28_85); - r4bs r4bs_6800_3600(yy[26], yy[27], single[29], double[29], neg[29], pp_29_85); - r4bs r4bs_6800_3728(yy[24], yy[25], single[30], double[30], neg[30], pp_30_85); - fullAdd_x FA_6800_3856(int_13_85, int_12_85, pp_28_85, pp_29_85, pp_30_85); - r4bs r4bs_6800_4072(yy[22], yy[23], single[31], double[31], neg[31], pp_31_85); - r4bs r4bs_6800_4200(yy[20], yy[21], single[32], double[32], neg[32], pp_32_85); - fullAdd_x FA_6800_4328(int_15_85, int_14_85, pp_31_85, pp_32_85, int_1_84); - fullAdd_x FA_6800_4544(int_17_85, int_16_85, int_3_84, int_5_84, int_7_84); - fullAdd_x FA_6800_4760(int_19_85, int_18_85, int_9_84, int_11_84, int_13_84); - fullAdd_x FA_6800_4976(int_21_85, int_20_85, int_15_84, int_17_84, int_19_84); - fullAdd_x FA_6800_5192(int_23_85, int_22_85, int_21_84, int_0_85, int_2_85); - fullAdd_x FA_6800_5408(int_25_85, int_24_85, int_4_85, int_6_85, int_8_85); - fullAdd_x FA_6800_5624(int_27_85, int_26_85, int_10_85, int_12_85, int_14_85); - fullAdd_x FA_6800_5840(int_29_85, int_28_85, int_23_84, int_25_84, int_27_84); - fullAdd_x FA_6800_6056(int_31_85, int_30_85, int_16_85, int_18_85, int_29_84); - fullAdd_x FA_6800_6272(int_33_85, int_32_85, int_31_84, int_20_85, int_22_85); - fullAdd_x FA_6800_6488(int_35_85, int_34_85, int_24_85, int_26_85, int_33_84); - fullAdd_x FA_6800_6704(int_37_85, int_36_85, int_35_84, int_28_85, int_30_85); - fullAdd_x FA_6800_6920(int_39_85, int_38_85, int_37_84, int_39_84, int_32_85); - fullAdd_x FA_6800_7136(int_41_85, int_40_85, int_34_85, int_41_84, int_36_85); - fullAdd_x FA_6800_7352(int_43_85, int_42_85, int_43_84, int_38_85, int_40_85); - assign Sum[85] = int_45_84; - assign Carry[85] = int_42_85; - - // Hardware for column 86 - - r4bs r4bs_6880_0(yy[63], gnd, single[11], double[11], neg[11], pp_11_86); - halfAdd HA_6880_128(int_1_86, int_0_86, 1'b1, pp_11_86); - r4bs r4bs_6880_208(yy[61], yy[62], single[12], double[12], neg[12], pp_12_86); - r4bs r4bs_6880_336(yy[59], yy[60], single[13], double[13], neg[13], pp_13_86); - r4bs r4bs_6880_464(yy[57], yy[58], single[14], double[14], neg[14], pp_14_86); - fullAdd_x FA_6880_592(int_3_86, int_2_86, pp_12_86, pp_13_86, pp_14_86); - r4bs r4bs_6880_808(yy[55], yy[56], single[15], double[15], neg[15], pp_15_86); - r4bs r4bs_6880_936(yy[53], yy[54], single[16], double[16], neg[16], pp_16_86); - r4bs r4bs_6880_1064(yy[51], yy[52], single[17], double[17], neg[17], pp_17_86); - fullAdd_x FA_6880_1192(int_5_86, int_4_86, pp_15_86, pp_16_86, pp_17_86); - r4bs r4bs_6880_1408(yy[49], yy[50], single[18], double[18], neg[18], pp_18_86); - r4bs r4bs_6880_1536(yy[47], yy[48], single[19], double[19], neg[19], pp_19_86); - r4bs r4bs_6880_1664(yy[45], yy[46], single[20], double[20], neg[20], pp_20_86); - fullAdd_x FA_6880_1792(int_7_86, int_6_86, pp_18_86, pp_19_86, pp_20_86); - r4bs r4bs_6880_2008(yy[43], yy[44], single[21], double[21], neg[21], pp_21_86); - r4bs r4bs_6880_2136(yy[41], yy[42], single[22], double[22], neg[22], pp_22_86); - r4bs r4bs_6880_2264(yy[39], yy[40], single[23], double[23], neg[23], pp_23_86); - fullAdd_x FA_6880_2392(int_9_86, int_8_86, pp_21_86, pp_22_86, pp_23_86); - r4bs r4bs_6880_2608(yy[37], yy[38], single[24], double[24], neg[24], pp_24_86); - r4bs r4bs_6880_2736(yy[35], yy[36], single[25], double[25], neg[25], pp_25_86); - r4bs r4bs_6880_2864(yy[33], yy[34], single[26], double[26], neg[26], pp_26_86); - fullAdd_x FA_6880_2992(int_11_86, int_10_86, pp_24_86, pp_25_86, pp_26_86); - r4bs r4bs_6880_3208(yy[31], yy[32], single[27], double[27], neg[27], pp_27_86); - r4bs r4bs_6880_3336(yy[29], yy[30], single[28], double[28], neg[28], pp_28_86); - r4bs r4bs_6880_3464(yy[27], yy[28], single[29], double[29], neg[29], pp_29_86); - fullAdd_x FA_6880_3592(int_13_86, int_12_86, pp_27_86, pp_28_86, pp_29_86); - r4bs r4bs_6880_3808(yy[25], yy[26], single[30], double[30], neg[30], pp_30_86); - r4bs r4bs_6880_3936(yy[23], yy[24], single[31], double[31], neg[31], pp_31_86); - r4bs r4bs_6880_4064(yy[21], yy[22], single[32], double[32], neg[32], pp_32_86); - fullAdd_x FA_6880_4192(int_15_86, int_14_86, pp_30_86, pp_31_86, pp_32_86); - fullAdd_x FA_6880_4408(int_17_86, int_16_86, int_1_85, int_3_85, int_5_85); - fullAdd_x FA_6880_4624(int_19_86, int_18_86, int_7_85, int_9_85, int_11_85); - fullAdd_x FA_6880_4840(int_21_86, int_20_86, int_13_85, int_0_86, int_15_85); - fullAdd_x FA_6880_5056(int_23_86, int_22_86, int_17_85, int_19_85, int_2_86); - fullAdd_x FA_6880_5272(int_25_86, int_24_86, int_4_86, int_6_86, int_8_86); - fullAdd_x FA_6880_5488(int_27_86, int_26_86, int_10_86, int_12_86, int_14_86); - fullAdd_x FA_6880_5704(int_29_86, int_28_86, int_21_85, int_23_85, int_25_85); - fullAdd_x FA_6880_5920(int_31_86, int_30_86, int_27_85, int_16_86, int_18_86); - fullAdd_x FA_6880_6136(int_33_86, int_32_86, int_20_86, int_29_85, int_22_86); - fullAdd_x FA_6880_6352(int_35_86, int_34_86, int_24_86, int_26_86, int_31_85); - fullAdd_x FA_6880_6568(int_37_86, int_36_86, int_33_85, int_28_86, int_30_86); - fullAdd_x FA_6880_6784(int_39_86, int_38_86, int_35_85, int_37_85, int_32_86); - fullAdd_x FA_6880_7000(int_41_86, int_40_86, int_34_86, int_39_85, int_36_86); - fullAdd_x FA_6880_7216(int_43_86, int_42_86, int_41_85, int_38_86, int_40_86); - assign Sum[86] = int_43_85; - assign Carry[86] = int_42_86; - - // Hardware for column 87 - - r4bs r4bs_6960_0(yy[62], yy[63], single[12], double[12], neg[12], pp_12_87); - r4bs r4bs_6960_128(yy[60], yy[61], single[13], double[13], neg[13], pp_13_87); - fullAdd_x FA_6960_256(int_1_87, int_0_87, negbar[11], pp_12_87, pp_13_87); - r4bs r4bs_6960_472(yy[58], yy[59], single[14], double[14], neg[14], pp_14_87); - r4bs r4bs_6960_600(yy[56], yy[57], single[15], double[15], neg[15], pp_15_87); - r4bs r4bs_6960_728(yy[54], yy[55], single[16], double[16], neg[16], pp_16_87); - fullAdd_x FA_6960_856(int_3_87, int_2_87, pp_14_87, pp_15_87, pp_16_87); - r4bs r4bs_6960_1072(yy[52], yy[53], single[17], double[17], neg[17], pp_17_87); - r4bs r4bs_6960_1200(yy[50], yy[51], single[18], double[18], neg[18], pp_18_87); - r4bs r4bs_6960_1328(yy[48], yy[49], single[19], double[19], neg[19], pp_19_87); - fullAdd_x FA_6960_1456(int_5_87, int_4_87, pp_17_87, pp_18_87, pp_19_87); - r4bs r4bs_6960_1672(yy[46], yy[47], single[20], double[20], neg[20], pp_20_87); - r4bs r4bs_6960_1800(yy[44], yy[45], single[21], double[21], neg[21], pp_21_87); - r4bs r4bs_6960_1928(yy[42], yy[43], single[22], double[22], neg[22], pp_22_87); - fullAdd_x FA_6960_2056(int_7_87, int_6_87, pp_20_87, pp_21_87, pp_22_87); - r4bs r4bs_6960_2272(yy[40], yy[41], single[23], double[23], neg[23], pp_23_87); - r4bs r4bs_6960_2400(yy[38], yy[39], single[24], double[24], neg[24], pp_24_87); - r4bs r4bs_6960_2528(yy[36], yy[37], single[25], double[25], neg[25], pp_25_87); - fullAdd_x FA_6960_2656(int_9_87, int_8_87, pp_23_87, pp_24_87, pp_25_87); - r4bs r4bs_6960_2872(yy[34], yy[35], single[26], double[26], neg[26], pp_26_87); - r4bs r4bs_6960_3000(yy[32], yy[33], single[27], double[27], neg[27], pp_27_87); - r4bs r4bs_6960_3128(yy[30], yy[31], single[28], double[28], neg[28], pp_28_87); - fullAdd_x FA_6960_3256(int_11_87, int_10_87, pp_26_87, pp_27_87, pp_28_87); - r4bs r4bs_6960_3472(yy[28], yy[29], single[29], double[29], neg[29], pp_29_87); - r4bs r4bs_6960_3600(yy[26], yy[27], single[30], double[30], neg[30], pp_30_87); - r4bs r4bs_6960_3728(yy[24], yy[25], single[31], double[31], neg[31], pp_31_87); - fullAdd_x FA_6960_3856(int_13_87, int_12_87, pp_29_87, pp_30_87, pp_31_87); - r4bs r4bs_6960_4072(yy[22], yy[23], single[32], double[32], neg[32], pp_32_87); - fullAdd_x FA_6960_4200(int_15_87, int_14_87, pp_32_87, int_1_86, int_3_86); - fullAdd_x FA_6960_4416(int_17_87, int_16_87, int_5_86, int_7_86, int_9_86); - fullAdd_x FA_6960_4632(int_19_87, int_18_87, int_11_86, int_13_86, int_15_86); - fullAdd_x FA_6960_4848(int_21_87, int_20_87, int_17_86, int_19_86, int_0_87); - fullAdd_x FA_6960_5064(int_23_87, int_22_87, int_2_87, int_4_87, int_6_87); - fullAdd_x FA_6960_5280(int_25_87, int_24_87, int_8_87, int_10_87, int_12_87); - fullAdd_x FA_6960_5496(int_27_87, int_26_87, int_21_86, int_14_87, int_23_86); - fullAdd_x FA_6960_5712(int_29_87, int_28_87, int_25_86, int_27_86, int_16_87); - fullAdd_x FA_6960_5928(int_31_87, int_30_87, int_18_87, int_29_86, int_31_86); - fullAdd_x FA_6960_6144(int_33_87, int_32_87, int_20_87, int_22_87, int_24_87); - fullAdd_x FA_6960_6360(int_35_87, int_34_87, int_26_87, int_33_86, int_28_87); - fullAdd_x FA_6960_6576(int_37_87, int_36_87, int_35_86, int_37_86, int_30_87); - fullAdd_x FA_6960_6792(int_39_87, int_38_87, int_32_87, int_39_86, int_34_87); - fullAdd_x FA_6960_7008(int_41_87, int_40_87, int_41_86, int_36_87, int_38_87); - assign Sum[87] = int_43_86; - assign Carry[87] = int_40_87; - - // Hardware for column 88 - - r4bs r4bs_7040_0(yy[63], gnd, single[12], double[12], neg[12], pp_12_88); - halfAdd HA_7040_128(int_1_88, int_0_88, 1'b1, pp_12_88); - r4bs r4bs_7040_208(yy[61], yy[62], single[13], double[13], neg[13], pp_13_88); - r4bs r4bs_7040_336(yy[59], yy[60], single[14], double[14], neg[14], pp_14_88); - r4bs r4bs_7040_464(yy[57], yy[58], single[15], double[15], neg[15], pp_15_88); - fullAdd_x FA_7040_592(int_3_88, int_2_88, pp_13_88, pp_14_88, pp_15_88); - r4bs r4bs_7040_808(yy[55], yy[56], single[16], double[16], neg[16], pp_16_88); - r4bs r4bs_7040_936(yy[53], yy[54], single[17], double[17], neg[17], pp_17_88); - r4bs r4bs_7040_1064(yy[51], yy[52], single[18], double[18], neg[18], pp_18_88); - fullAdd_x FA_7040_1192(int_5_88, int_4_88, pp_16_88, pp_17_88, pp_18_88); - r4bs r4bs_7040_1408(yy[49], yy[50], single[19], double[19], neg[19], pp_19_88); - r4bs r4bs_7040_1536(yy[47], yy[48], single[20], double[20], neg[20], pp_20_88); - r4bs r4bs_7040_1664(yy[45], yy[46], single[21], double[21], neg[21], pp_21_88); - fullAdd_x FA_7040_1792(int_7_88, int_6_88, pp_19_88, pp_20_88, pp_21_88); - r4bs r4bs_7040_2008(yy[43], yy[44], single[22], double[22], neg[22], pp_22_88); - r4bs r4bs_7040_2136(yy[41], yy[42], single[23], double[23], neg[23], pp_23_88); - r4bs r4bs_7040_2264(yy[39], yy[40], single[24], double[24], neg[24], pp_24_88); - fullAdd_x FA_7040_2392(int_9_88, int_8_88, pp_22_88, pp_23_88, pp_24_88); - r4bs r4bs_7040_2608(yy[37], yy[38], single[25], double[25], neg[25], pp_25_88); - r4bs r4bs_7040_2736(yy[35], yy[36], single[26], double[26], neg[26], pp_26_88); - r4bs r4bs_7040_2864(yy[33], yy[34], single[27], double[27], neg[27], pp_27_88); - fullAdd_x FA_7040_2992(int_11_88, int_10_88, pp_25_88, pp_26_88, pp_27_88); - r4bs r4bs_7040_3208(yy[31], yy[32], single[28], double[28], neg[28], pp_28_88); - r4bs r4bs_7040_3336(yy[29], yy[30], single[29], double[29], neg[29], pp_29_88); - r4bs r4bs_7040_3464(yy[27], yy[28], single[30], double[30], neg[30], pp_30_88); - fullAdd_x FA_7040_3592(int_13_88, int_12_88, pp_28_88, pp_29_88, pp_30_88); - r4bs r4bs_7040_3808(yy[25], yy[26], single[31], double[31], neg[31], pp_31_88); - r4bs r4bs_7040_3936(yy[23], yy[24], single[32], double[32], neg[32], pp_32_88); - fullAdd_x FA_7040_4064(int_15_88, int_14_88, pp_31_88, pp_32_88, int_1_87); - fullAdd_x FA_7040_4280(int_17_88, int_16_88, int_3_87, int_5_87, int_7_87); - fullAdd_x FA_7040_4496(int_19_88, int_18_88, int_9_87, int_11_87, int_13_87); - fullAdd_x FA_7040_4712(int_21_88, int_20_88, int_0_88, int_15_87, int_17_87); - fullAdd_x FA_7040_4928(int_23_88, int_22_88, int_19_87, int_2_88, int_4_88); - fullAdd_x FA_7040_5144(int_25_88, int_24_88, int_6_88, int_8_88, int_10_88); - fullAdd_x FA_7040_5360(int_27_88, int_26_88, int_12_88, int_14_88, int_21_87); - fullAdd_x FA_7040_5576(int_29_88, int_28_88, int_23_87, int_25_87, int_16_88); - fullAdd_x FA_7040_5792(int_31_88, int_30_88, int_18_88, int_27_87, int_29_87); - fullAdd_x FA_7040_6008(int_33_88, int_32_88, int_20_88, int_22_88, int_24_88); - fullAdd_x FA_7040_6224(int_35_88, int_34_88, int_26_88, int_31_87, int_33_87); - fullAdd_x FA_7040_6440(int_37_88, int_36_88, int_28_88, int_35_87, int_30_88); - fullAdd_x FA_7040_6656(int_39_88, int_38_88, int_32_88, int_37_87, int_34_88); - fullAdd_x FA_7040_6872(int_41_88, int_40_88, int_39_87, int_36_88, int_38_88); - assign Sum[88] = int_41_87; - assign Carry[88] = int_40_88; - - // Hardware for column 89 - - r4bs r4bs_7120_0(yy[62], yy[63], single[13], double[13], neg[13], pp_13_89); - r4bs r4bs_7120_128(yy[60], yy[61], single[14], double[14], neg[14], pp_14_89); - fullAdd_x FA_7120_256(int_1_89, int_0_89, negbar[12], pp_13_89, pp_14_89); - r4bs r4bs_7120_472(yy[58], yy[59], single[15], double[15], neg[15], pp_15_89); - r4bs r4bs_7120_600(yy[56], yy[57], single[16], double[16], neg[16], pp_16_89); - r4bs r4bs_7120_728(yy[54], yy[55], single[17], double[17], neg[17], pp_17_89); - fullAdd_x FA_7120_856(int_3_89, int_2_89, pp_15_89, pp_16_89, pp_17_89); - r4bs r4bs_7120_1072(yy[52], yy[53], single[18], double[18], neg[18], pp_18_89); - r4bs r4bs_7120_1200(yy[50], yy[51], single[19], double[19], neg[19], pp_19_89); - r4bs r4bs_7120_1328(yy[48], yy[49], single[20], double[20], neg[20], pp_20_89); - fullAdd_x FA_7120_1456(int_5_89, int_4_89, pp_18_89, pp_19_89, pp_20_89); - r4bs r4bs_7120_1672(yy[46], yy[47], single[21], double[21], neg[21], pp_21_89); - r4bs r4bs_7120_1800(yy[44], yy[45], single[22], double[22], neg[22], pp_22_89); - r4bs r4bs_7120_1928(yy[42], yy[43], single[23], double[23], neg[23], pp_23_89); - fullAdd_x FA_7120_2056(int_7_89, int_6_89, pp_21_89, pp_22_89, pp_23_89); - r4bs r4bs_7120_2272(yy[40], yy[41], single[24], double[24], neg[24], pp_24_89); - r4bs r4bs_7120_2400(yy[38], yy[39], single[25], double[25], neg[25], pp_25_89); - r4bs r4bs_7120_2528(yy[36], yy[37], single[26], double[26], neg[26], pp_26_89); - fullAdd_x FA_7120_2656(int_9_89, int_8_89, pp_24_89, pp_25_89, pp_26_89); - r4bs r4bs_7120_2872(yy[34], yy[35], single[27], double[27], neg[27], pp_27_89); - r4bs r4bs_7120_3000(yy[32], yy[33], single[28], double[28], neg[28], pp_28_89); - r4bs r4bs_7120_3128(yy[30], yy[31], single[29], double[29], neg[29], pp_29_89); - fullAdd_x FA_7120_3256(int_11_89, int_10_89, pp_27_89, pp_28_89, pp_29_89); - r4bs r4bs_7120_3472(yy[28], yy[29], single[30], double[30], neg[30], pp_30_89); - r4bs r4bs_7120_3600(yy[26], yy[27], single[31], double[31], neg[31], pp_31_89); - r4bs r4bs_7120_3728(yy[24], yy[25], single[32], double[32], neg[32], pp_32_89); - fullAdd_x FA_7120_3856(int_13_89, int_12_89, pp_30_89, pp_31_89, pp_32_89); - fullAdd_x FA_7120_4072(int_15_89, int_14_89, int_1_88, int_3_88, int_5_88); - fullAdd_x FA_7120_4288(int_17_89, int_16_89, int_7_88, int_9_88, int_11_88); - fullAdd_x FA_7120_4504(int_19_89, int_18_89, int_13_88, int_15_88, int_17_88); - fullAdd_x FA_7120_4720(int_21_89, int_20_89, int_19_88, int_0_89, int_2_89); - fullAdd_x FA_7120_4936(int_23_89, int_22_89, int_4_89, int_6_89, int_8_89); - fullAdd_x FA_7120_5152(int_25_89, int_24_89, int_10_89, int_12_89, int_21_88); - fullAdd_x FA_7120_5368(int_27_89, int_26_89, int_23_88, int_25_88, int_14_89); - fullAdd_x FA_7120_5584(int_29_89, int_28_89, int_16_89, int_27_88, int_29_88); - fullAdd_x FA_7120_5800(int_31_89, int_30_89, int_18_89, int_20_89, int_22_89); - fullAdd_x FA_7120_6016(int_33_89, int_32_89, int_24_89, int_31_88, int_33_88); - fullAdd_x FA_7120_6232(int_35_89, int_34_89, int_26_89, int_35_88, int_28_89); - fullAdd_x FA_7120_6448(int_37_89, int_36_89, int_30_89, int_37_88, int_32_89); - fullAdd_x FA_7120_6664(int_39_89, int_38_89, int_39_88, int_34_89, int_36_89); - assign Sum[89] = int_41_88; - assign Carry[89] = int_38_89; - - // Hardware for column 90 - - r4bs r4bs_7200_0(yy[63], gnd, single[13], double[13], neg[13], pp_13_90); - halfAdd HA_7200_128(int_1_90, int_0_90, 1'b1, pp_13_90); - r4bs r4bs_7200_208(yy[61], yy[62], single[14], double[14], neg[14], pp_14_90); - r4bs r4bs_7200_336(yy[59], yy[60], single[15], double[15], neg[15], pp_15_90); - r4bs r4bs_7200_464(yy[57], yy[58], single[16], double[16], neg[16], pp_16_90); - fullAdd_x FA_7200_592(int_3_90, int_2_90, pp_14_90, pp_15_90, pp_16_90); - r4bs r4bs_7200_808(yy[55], yy[56], single[17], double[17], neg[17], pp_17_90); - r4bs r4bs_7200_936(yy[53], yy[54], single[18], double[18], neg[18], pp_18_90); - r4bs r4bs_7200_1064(yy[51], yy[52], single[19], double[19], neg[19], pp_19_90); - fullAdd_x FA_7200_1192(int_5_90, int_4_90, pp_17_90, pp_18_90, pp_19_90); - r4bs r4bs_7200_1408(yy[49], yy[50], single[20], double[20], neg[20], pp_20_90); - r4bs r4bs_7200_1536(yy[47], yy[48], single[21], double[21], neg[21], pp_21_90); - r4bs r4bs_7200_1664(yy[45], yy[46], single[22], double[22], neg[22], pp_22_90); - fullAdd_x FA_7200_1792(int_7_90, int_6_90, pp_20_90, pp_21_90, pp_22_90); - r4bs r4bs_7200_2008(yy[43], yy[44], single[23], double[23], neg[23], pp_23_90); - r4bs r4bs_7200_2136(yy[41], yy[42], single[24], double[24], neg[24], pp_24_90); - r4bs r4bs_7200_2264(yy[39], yy[40], single[25], double[25], neg[25], pp_25_90); - fullAdd_x FA_7200_2392(int_9_90, int_8_90, pp_23_90, pp_24_90, pp_25_90); - r4bs r4bs_7200_2608(yy[37], yy[38], single[26], double[26], neg[26], pp_26_90); - r4bs r4bs_7200_2736(yy[35], yy[36], single[27], double[27], neg[27], pp_27_90); - r4bs r4bs_7200_2864(yy[33], yy[34], single[28], double[28], neg[28], pp_28_90); - fullAdd_x FA_7200_2992(int_11_90, int_10_90, pp_26_90, pp_27_90, pp_28_90); - r4bs r4bs_7200_3208(yy[31], yy[32], single[29], double[29], neg[29], pp_29_90); - r4bs r4bs_7200_3336(yy[29], yy[30], single[30], double[30], neg[30], pp_30_90); - r4bs r4bs_7200_3464(yy[27], yy[28], single[31], double[31], neg[31], pp_31_90); - fullAdd_x FA_7200_3592(int_13_90, int_12_90, pp_29_90, pp_30_90, pp_31_90); - r4bs r4bs_7200_3808(yy[25], yy[26], single[32], double[32], neg[32], pp_32_90); - fullAdd_x FA_7200_3936(int_15_90, int_14_90, pp_32_90, int_1_89, int_3_89); - fullAdd_x FA_7200_4152(int_17_90, int_16_90, int_5_89, int_7_89, int_9_89); - fullAdd_x FA_7200_4368(int_19_90, int_18_90, int_11_89, int_13_89, int_0_90); - fullAdd_x FA_7200_4584(int_21_90, int_20_90, int_15_89, int_17_89, int_2_90); - fullAdd_x FA_7200_4800(int_23_90, int_22_90, int_4_90, int_6_90, int_8_90); - fullAdd_x FA_7200_5016(int_25_90, int_24_90, int_10_90, int_12_90, int_19_89); - fullAdd_x FA_7200_5232(int_27_90, int_26_90, int_21_89, int_23_89, int_14_90); - fullAdd_x FA_7200_5448(int_29_90, int_28_90, int_16_90, int_18_90, int_25_89); - fullAdd_x FA_7200_5664(int_31_90, int_30_90, int_27_89, int_20_90, int_22_90); - fullAdd_x FA_7200_5880(int_33_90, int_32_90, int_24_90, int_29_89, int_31_89); - fullAdd_x FA_7200_6096(int_35_90, int_34_90, int_26_90, int_28_90, int_33_89); - fullAdd_x FA_7200_6312(int_37_90, int_36_90, int_30_90, int_35_89, int_32_90); - fullAdd_x FA_7200_6528(int_39_90, int_38_90, int_34_90, int_37_89, int_36_90); - assign Sum[90] = int_39_89; - assign Carry[90] = int_38_90; - - // Hardware for column 91 - - r4bs r4bs_7280_0(yy[62], yy[63], single[14], double[14], neg[14], pp_14_91); - r4bs r4bs_7280_128(yy[60], yy[61], single[15], double[15], neg[15], pp_15_91); - fullAdd_x FA_7280_256(int_1_91, int_0_91, negbar[13], pp_14_91, pp_15_91); - r4bs r4bs_7280_472(yy[58], yy[59], single[16], double[16], neg[16], pp_16_91); - r4bs r4bs_7280_600(yy[56], yy[57], single[17], double[17], neg[17], pp_17_91); - r4bs r4bs_7280_728(yy[54], yy[55], single[18], double[18], neg[18], pp_18_91); - fullAdd_x FA_7280_856(int_3_91, int_2_91, pp_16_91, pp_17_91, pp_18_91); - r4bs r4bs_7280_1072(yy[52], yy[53], single[19], double[19], neg[19], pp_19_91); - r4bs r4bs_7280_1200(yy[50], yy[51], single[20], double[20], neg[20], pp_20_91); - r4bs r4bs_7280_1328(yy[48], yy[49], single[21], double[21], neg[21], pp_21_91); - fullAdd_x FA_7280_1456(int_5_91, int_4_91, pp_19_91, pp_20_91, pp_21_91); - r4bs r4bs_7280_1672(yy[46], yy[47], single[22], double[22], neg[22], pp_22_91); - r4bs r4bs_7280_1800(yy[44], yy[45], single[23], double[23], neg[23], pp_23_91); - r4bs r4bs_7280_1928(yy[42], yy[43], single[24], double[24], neg[24], pp_24_91); - fullAdd_x FA_7280_2056(int_7_91, int_6_91, pp_22_91, pp_23_91, pp_24_91); - r4bs r4bs_7280_2272(yy[40], yy[41], single[25], double[25], neg[25], pp_25_91); - r4bs r4bs_7280_2400(yy[38], yy[39], single[26], double[26], neg[26], pp_26_91); - r4bs r4bs_7280_2528(yy[36], yy[37], single[27], double[27], neg[27], pp_27_91); - fullAdd_x FA_7280_2656(int_9_91, int_8_91, pp_25_91, pp_26_91, pp_27_91); - r4bs r4bs_7280_2872(yy[34], yy[35], single[28], double[28], neg[28], pp_28_91); - r4bs r4bs_7280_3000(yy[32], yy[33], single[29], double[29], neg[29], pp_29_91); - r4bs r4bs_7280_3128(yy[30], yy[31], single[30], double[30], neg[30], pp_30_91); - fullAdd_x FA_7280_3256(int_11_91, int_10_91, pp_28_91, pp_29_91, pp_30_91); - r4bs r4bs_7280_3472(yy[28], yy[29], single[31], double[31], neg[31], pp_31_91); - r4bs r4bs_7280_3600(yy[26], yy[27], single[32], double[32], neg[32], pp_32_91); - fullAdd_x FA_7280_3728(int_13_91, int_12_91, pp_31_91, pp_32_91, int_1_90); - fullAdd_x FA_7280_3944(int_15_91, int_14_91, int_3_90, int_5_90, int_7_90); - fullAdd_x FA_7280_4160(int_17_91, int_16_91, int_9_90, int_11_90, int_13_90); - fullAdd_x FA_7280_4376(int_19_91, int_18_91, int_15_90, int_17_90, int_19_90); - fullAdd_x FA_7280_4592(int_21_91, int_20_91, int_0_91, int_2_91, int_4_91); - fullAdd_x FA_7280_4808(int_23_91, int_22_91, int_6_91, int_8_91, int_10_91); - fullAdd_x FA_7280_5024(int_25_91, int_24_91, int_12_91, int_21_90, int_23_90); - fullAdd_x FA_7280_5240(int_27_91, int_26_91, int_14_91, int_16_91, int_25_90); - fullAdd_x FA_7280_5456(int_29_91, int_28_91, int_27_90, int_18_91, int_20_91); - fullAdd_x FA_7280_5672(int_31_91, int_30_91, int_22_91, int_29_90, int_31_90); - fullAdd_x FA_7280_5888(int_33_91, int_32_91, int_24_91, int_26_91, int_33_90); - fullAdd_x FA_7280_6104(int_35_91, int_34_91, int_28_91, int_35_90, int_30_91); - fullAdd_x FA_7280_6320(int_37_91, int_36_91, int_32_91, int_37_90, int_34_91); - assign Sum[91] = int_39_90; - assign Carry[91] = int_36_91; - - // Hardware for column 92 - - r4bs r4bs_7360_0(yy[63], gnd, single[14], double[14], neg[14], pp_14_92); - halfAdd HA_7360_128(int_1_92, int_0_92, 1'b1, pp_14_92); - r4bs r4bs_7360_208(yy[61], yy[62], single[15], double[15], neg[15], pp_15_92); - r4bs r4bs_7360_336(yy[59], yy[60], single[16], double[16], neg[16], pp_16_92); - r4bs r4bs_7360_464(yy[57], yy[58], single[17], double[17], neg[17], pp_17_92); - fullAdd_x FA_7360_592(int_3_92, int_2_92, pp_15_92, pp_16_92, pp_17_92); - r4bs r4bs_7360_808(yy[55], yy[56], single[18], double[18], neg[18], pp_18_92); - r4bs r4bs_7360_936(yy[53], yy[54], single[19], double[19], neg[19], pp_19_92); - r4bs r4bs_7360_1064(yy[51], yy[52], single[20], double[20], neg[20], pp_20_92); - fullAdd_x FA_7360_1192(int_5_92, int_4_92, pp_18_92, pp_19_92, pp_20_92); - r4bs r4bs_7360_1408(yy[49], yy[50], single[21], double[21], neg[21], pp_21_92); - r4bs r4bs_7360_1536(yy[47], yy[48], single[22], double[22], neg[22], pp_22_92); - r4bs r4bs_7360_1664(yy[45], yy[46], single[23], double[23], neg[23], pp_23_92); - fullAdd_x FA_7360_1792(int_7_92, int_6_92, pp_21_92, pp_22_92, pp_23_92); - r4bs r4bs_7360_2008(yy[43], yy[44], single[24], double[24], neg[24], pp_24_92); - r4bs r4bs_7360_2136(yy[41], yy[42], single[25], double[25], neg[25], pp_25_92); - r4bs r4bs_7360_2264(yy[39], yy[40], single[26], double[26], neg[26], pp_26_92); - fullAdd_x FA_7360_2392(int_9_92, int_8_92, pp_24_92, pp_25_92, pp_26_92); - r4bs r4bs_7360_2608(yy[37], yy[38], single[27], double[27], neg[27], pp_27_92); - r4bs r4bs_7360_2736(yy[35], yy[36], single[28], double[28], neg[28], pp_28_92); - r4bs r4bs_7360_2864(yy[33], yy[34], single[29], double[29], neg[29], pp_29_92); - fullAdd_x FA_7360_2992(int_11_92, int_10_92, pp_27_92, pp_28_92, pp_29_92); - r4bs r4bs_7360_3208(yy[31], yy[32], single[30], double[30], neg[30], pp_30_92); - r4bs r4bs_7360_3336(yy[29], yy[30], single[31], double[31], neg[31], pp_31_92); - r4bs r4bs_7360_3464(yy[27], yy[28], single[32], double[32], neg[32], pp_32_92); - fullAdd_x FA_7360_3592(int_13_92, int_12_92, pp_30_92, pp_31_92, pp_32_92); - fullAdd_x FA_7360_3808(int_15_92, int_14_92, int_1_91, int_3_91, int_5_91); - fullAdd_x FA_7360_4024(int_17_92, int_16_92, int_7_91, int_9_91, int_11_91); - fullAdd_x FA_7360_4240(int_19_92, int_18_92, int_0_92, int_13_91, int_15_91); - fullAdd_x FA_7360_4456(int_21_92, int_20_92, int_17_91, int_2_92, int_4_92); - fullAdd_x FA_7360_4672(int_23_92, int_22_92, int_6_92, int_8_92, int_10_92); - fullAdd_x FA_7360_4888(int_25_92, int_24_92, int_12_92, int_19_91, int_21_91); - fullAdd_x FA_7360_5104(int_27_92, int_26_92, int_23_91, int_14_92, int_16_92); - fullAdd_x FA_7360_5320(int_29_92, int_28_92, int_18_92, int_25_91, int_20_92); - fullAdd_x FA_7360_5536(int_31_92, int_30_92, int_22_92, int_27_91, int_29_91); - fullAdd_x FA_7360_5752(int_33_92, int_32_92, int_24_92, int_26_92, int_31_91); - fullAdd_x FA_7360_5968(int_35_92, int_34_92, int_28_92, int_33_91, int_30_92); - fullAdd_x FA_7360_6184(int_37_92, int_36_92, int_32_92, int_35_91, int_34_92); - assign Sum[92] = int_37_91; - assign Carry[92] = int_36_92; - - // Hardware for column 93 - - r4bs r4bs_7440_0(yy[62], yy[63], single[15], double[15], neg[15], pp_15_93); - r4bs r4bs_7440_128(yy[60], yy[61], single[16], double[16], neg[16], pp_16_93); - fullAdd_x FA_7440_256(int_1_93, int_0_93, negbar[14], pp_15_93, pp_16_93); - r4bs r4bs_7440_472(yy[58], yy[59], single[17], double[17], neg[17], pp_17_93); - r4bs r4bs_7440_600(yy[56], yy[57], single[18], double[18], neg[18], pp_18_93); - r4bs r4bs_7440_728(yy[54], yy[55], single[19], double[19], neg[19], pp_19_93); - fullAdd_x FA_7440_856(int_3_93, int_2_93, pp_17_93, pp_18_93, pp_19_93); - r4bs r4bs_7440_1072(yy[52], yy[53], single[20], double[20], neg[20], pp_20_93); - r4bs r4bs_7440_1200(yy[50], yy[51], single[21], double[21], neg[21], pp_21_93); - r4bs r4bs_7440_1328(yy[48], yy[49], single[22], double[22], neg[22], pp_22_93); - fullAdd_x FA_7440_1456(int_5_93, int_4_93, pp_20_93, pp_21_93, pp_22_93); - r4bs r4bs_7440_1672(yy[46], yy[47], single[23], double[23], neg[23], pp_23_93); - r4bs r4bs_7440_1800(yy[44], yy[45], single[24], double[24], neg[24], pp_24_93); - r4bs r4bs_7440_1928(yy[42], yy[43], single[25], double[25], neg[25], pp_25_93); - fullAdd_x FA_7440_2056(int_7_93, int_6_93, pp_23_93, pp_24_93, pp_25_93); - r4bs r4bs_7440_2272(yy[40], yy[41], single[26], double[26], neg[26], pp_26_93); - r4bs r4bs_7440_2400(yy[38], yy[39], single[27], double[27], neg[27], pp_27_93); - r4bs r4bs_7440_2528(yy[36], yy[37], single[28], double[28], neg[28], pp_28_93); - fullAdd_x FA_7440_2656(int_9_93, int_8_93, pp_26_93, pp_27_93, pp_28_93); - r4bs r4bs_7440_2872(yy[34], yy[35], single[29], double[29], neg[29], pp_29_93); - r4bs r4bs_7440_3000(yy[32], yy[33], single[30], double[30], neg[30], pp_30_93); - r4bs r4bs_7440_3128(yy[30], yy[31], single[31], double[31], neg[31], pp_31_93); - fullAdd_x FA_7440_3256(int_11_93, int_10_93, pp_29_93, pp_30_93, pp_31_93); - r4bs r4bs_7440_3472(yy[28], yy[29], single[32], double[32], neg[32], pp_32_93); - fullAdd_x FA_7440_3600(int_13_93, int_12_93, pp_32_93, int_1_92, int_3_92); - fullAdd_x FA_7440_3816(int_15_93, int_14_93, int_5_92, int_7_92, int_9_92); - fullAdd_x FA_7440_4032(int_17_93, int_16_93, int_11_92, int_13_92, int_15_92); - fullAdd_x FA_7440_4248(int_19_93, int_18_93, int_17_92, int_0_93, int_2_93); - fullAdd_x FA_7440_4464(int_21_93, int_20_93, int_4_93, int_6_93, int_8_93); - fullAdd_x FA_7440_4680(int_23_93, int_22_93, int_10_93, int_12_93, int_19_92); - fullAdd_x FA_7440_4896(int_25_93, int_24_93, int_21_92, int_23_92, int_14_93); - fullAdd_x FA_7440_5112(int_27_93, int_26_93, int_16_93, int_25_92, int_27_92); - fullAdd_x FA_7440_5328(int_29_93, int_28_93, int_18_93, int_20_93, int_22_93); - fullAdd_x FA_7440_5544(int_31_93, int_30_93, int_29_92, int_24_93, int_31_92); - fullAdd_x FA_7440_5760(int_33_93, int_32_93, int_26_93, int_28_93, int_33_92); - fullAdd_x FA_7440_5976(int_35_93, int_34_93, int_30_93, int_35_92, int_32_93); - assign Sum[93] = int_37_92; - assign Carry[93] = int_34_93; - - // Hardware for column 94 - - r4bs r4bs_7520_0(yy[63], gnd, single[15], double[15], neg[15], pp_15_94); - halfAdd HA_7520_128(int_1_94, int_0_94, 1'b1, pp_15_94); - r4bs r4bs_7520_208(yy[61], yy[62], single[16], double[16], neg[16], pp_16_94); - r4bs r4bs_7520_336(yy[59], yy[60], single[17], double[17], neg[17], pp_17_94); - r4bs r4bs_7520_464(yy[57], yy[58], single[18], double[18], neg[18], pp_18_94); - fullAdd_x FA_7520_592(int_3_94, int_2_94, pp_16_94, pp_17_94, pp_18_94); - r4bs r4bs_7520_808(yy[55], yy[56], single[19], double[19], neg[19], pp_19_94); - r4bs r4bs_7520_936(yy[53], yy[54], single[20], double[20], neg[20], pp_20_94); - r4bs r4bs_7520_1064(yy[51], yy[52], single[21], double[21], neg[21], pp_21_94); - fullAdd_x FA_7520_1192(int_5_94, int_4_94, pp_19_94, pp_20_94, pp_21_94); - r4bs r4bs_7520_1408(yy[49], yy[50], single[22], double[22], neg[22], pp_22_94); - r4bs r4bs_7520_1536(yy[47], yy[48], single[23], double[23], neg[23], pp_23_94); - r4bs r4bs_7520_1664(yy[45], yy[46], single[24], double[24], neg[24], pp_24_94); - fullAdd_x FA_7520_1792(int_7_94, int_6_94, pp_22_94, pp_23_94, pp_24_94); - r4bs r4bs_7520_2008(yy[43], yy[44], single[25], double[25], neg[25], pp_25_94); - r4bs r4bs_7520_2136(yy[41], yy[42], single[26], double[26], neg[26], pp_26_94); - r4bs r4bs_7520_2264(yy[39], yy[40], single[27], double[27], neg[27], pp_27_94); - fullAdd_x FA_7520_2392(int_9_94, int_8_94, pp_25_94, pp_26_94, pp_27_94); - r4bs r4bs_7520_2608(yy[37], yy[38], single[28], double[28], neg[28], pp_28_94); - r4bs r4bs_7520_2736(yy[35], yy[36], single[29], double[29], neg[29], pp_29_94); - r4bs r4bs_7520_2864(yy[33], yy[34], single[30], double[30], neg[30], pp_30_94); - fullAdd_x FA_7520_2992(int_11_94, int_10_94, pp_28_94, pp_29_94, pp_30_94); - r4bs r4bs_7520_3208(yy[31], yy[32], single[31], double[31], neg[31], pp_31_94); - r4bs r4bs_7520_3336(yy[29], yy[30], single[32], double[32], neg[32], pp_32_94); - fullAdd_x FA_7520_3464(int_13_94, int_12_94, pp_31_94, pp_32_94, int_1_93); - fullAdd_x FA_7520_3680(int_15_94, int_14_94, int_3_93, int_5_93, int_7_93); - fullAdd_x FA_7520_3896(int_17_94, int_16_94, int_9_93, int_11_93, int_0_94); - fullAdd_x FA_7520_4112(int_19_94, int_18_94, int_13_93, int_15_93, int_2_94); - fullAdd_x FA_7520_4328(int_21_94, int_20_94, int_4_94, int_6_94, int_8_94); - fullAdd_x FA_7520_4544(int_23_94, int_22_94, int_10_94, int_12_94, int_17_93); - fullAdd_x FA_7520_4760(int_25_94, int_24_94, int_19_93, int_21_93, int_14_94); - fullAdd_x FA_7520_4976(int_27_94, int_26_94, int_16_94, int_23_93, int_25_93); - fullAdd_x FA_7520_5192(int_29_94, int_28_94, int_18_94, int_20_94, int_22_94); - fullAdd_x FA_7520_5408(int_31_94, int_30_94, int_27_93, int_24_94, int_29_93); - fullAdd_x FA_7520_5624(int_33_94, int_32_94, int_26_94, int_28_94, int_31_93); - fullAdd_x FA_7520_5840(int_35_94, int_34_94, int_30_94, int_33_93, int_32_94); - assign Sum[94] = int_35_93; - assign Carry[94] = int_34_94; - - // Hardware for column 95 - - r4bs r4bs_7600_0(yy[62], yy[63], single[16], double[16], neg[16], pp_16_95); - r4bs r4bs_7600_128(yy[60], yy[61], single[17], double[17], neg[17], pp_17_95); - fullAdd_x FA_7600_256(int_1_95, int_0_95, negbar[15], pp_16_95, pp_17_95); - r4bs r4bs_7600_472(yy[58], yy[59], single[18], double[18], neg[18], pp_18_95); - r4bs r4bs_7600_600(yy[56], yy[57], single[19], double[19], neg[19], pp_19_95); - r4bs r4bs_7600_728(yy[54], yy[55], single[20], double[20], neg[20], pp_20_95); - fullAdd_x FA_7600_856(int_3_95, int_2_95, pp_18_95, pp_19_95, pp_20_95); - r4bs r4bs_7600_1072(yy[52], yy[53], single[21], double[21], neg[21], pp_21_95); - r4bs r4bs_7600_1200(yy[50], yy[51], single[22], double[22], neg[22], pp_22_95); - r4bs r4bs_7600_1328(yy[48], yy[49], single[23], double[23], neg[23], pp_23_95); - fullAdd_x FA_7600_1456(int_5_95, int_4_95, pp_21_95, pp_22_95, pp_23_95); - r4bs r4bs_7600_1672(yy[46], yy[47], single[24], double[24], neg[24], pp_24_95); - r4bs r4bs_7600_1800(yy[44], yy[45], single[25], double[25], neg[25], pp_25_95); - r4bs r4bs_7600_1928(yy[42], yy[43], single[26], double[26], neg[26], pp_26_95); - fullAdd_x FA_7600_2056(int_7_95, int_6_95, pp_24_95, pp_25_95, pp_26_95); - r4bs r4bs_7600_2272(yy[40], yy[41], single[27], double[27], neg[27], pp_27_95); - r4bs r4bs_7600_2400(yy[38], yy[39], single[28], double[28], neg[28], pp_28_95); - r4bs r4bs_7600_2528(yy[36], yy[37], single[29], double[29], neg[29], pp_29_95); - fullAdd_x FA_7600_2656(int_9_95, int_8_95, pp_27_95, pp_28_95, pp_29_95); - r4bs r4bs_7600_2872(yy[34], yy[35], single[30], double[30], neg[30], pp_30_95); - r4bs r4bs_7600_3000(yy[32], yy[33], single[31], double[31], neg[31], pp_31_95); - r4bs r4bs_7600_3128(yy[30], yy[31], single[32], double[32], neg[32], pp_32_95); - fullAdd_x FA_7600_3256(int_11_95, int_10_95, pp_30_95, pp_31_95, pp_32_95); - fullAdd_x FA_7600_3472(int_13_95, int_12_95, int_1_94, int_3_94, int_5_94); - fullAdd_x FA_7600_3688(int_15_95, int_14_95, int_7_94, int_9_94, int_11_94); - fullAdd_x FA_7600_3904(int_17_95, int_16_95, int_13_94, int_15_94, int_17_94); - fullAdd_x FA_7600_4120(int_19_95, int_18_95, int_0_95, int_2_95, int_4_95); - fullAdd_x FA_7600_4336(int_21_95, int_20_95, int_6_95, int_8_95, int_10_95); - fullAdd_x FA_7600_4552(int_23_95, int_22_95, int_19_94, int_21_94, int_12_95); - fullAdd_x FA_7600_4768(int_25_95, int_24_95, int_14_95, int_23_94, int_25_94); - fullAdd_x FA_7600_4984(int_27_95, int_26_95, int_16_95, int_18_95, int_20_95); - fullAdd_x FA_7600_5200(int_29_95, int_28_95, int_27_94, int_29_94, int_22_95); - fullAdd_x FA_7600_5416(int_31_95, int_30_95, int_24_95, int_26_95, int_31_94); - fullAdd_x FA_7600_5632(int_33_95, int_32_95, int_28_95, int_33_94, int_30_95); - assign Sum[95] = int_35_94; - assign Carry[95] = int_32_95; - - // Hardware for column 96 - - r4bs r4bs_7680_0(yy[63], gnd, single[16], double[16], neg[16], pp_16_96); - halfAdd HA_7680_128(int_1_96, int_0_96, 1'b1, pp_16_96); - r4bs r4bs_7680_208(yy[61], yy[62], single[17], double[17], neg[17], pp_17_96); - r4bs r4bs_7680_336(yy[59], yy[60], single[18], double[18], neg[18], pp_18_96); - r4bs r4bs_7680_464(yy[57], yy[58], single[19], double[19], neg[19], pp_19_96); - fullAdd_x FA_7680_592(int_3_96, int_2_96, pp_17_96, pp_18_96, pp_19_96); - r4bs r4bs_7680_808(yy[55], yy[56], single[20], double[20], neg[20], pp_20_96); - r4bs r4bs_7680_936(yy[53], yy[54], single[21], double[21], neg[21], pp_21_96); - r4bs r4bs_7680_1064(yy[51], yy[52], single[22], double[22], neg[22], pp_22_96); - fullAdd_x FA_7680_1192(int_5_96, int_4_96, pp_20_96, pp_21_96, pp_22_96); - r4bs r4bs_7680_1408(yy[49], yy[50], single[23], double[23], neg[23], pp_23_96); - r4bs r4bs_7680_1536(yy[47], yy[48], single[24], double[24], neg[24], pp_24_96); - r4bs r4bs_7680_1664(yy[45], yy[46], single[25], double[25], neg[25], pp_25_96); - fullAdd_x FA_7680_1792(int_7_96, int_6_96, pp_23_96, pp_24_96, pp_25_96); - r4bs r4bs_7680_2008(yy[43], yy[44], single[26], double[26], neg[26], pp_26_96); - r4bs r4bs_7680_2136(yy[41], yy[42], single[27], double[27], neg[27], pp_27_96); - r4bs r4bs_7680_2264(yy[39], yy[40], single[28], double[28], neg[28], pp_28_96); - fullAdd_x FA_7680_2392(int_9_96, int_8_96, pp_26_96, pp_27_96, pp_28_96); - r4bs r4bs_7680_2608(yy[37], yy[38], single[29], double[29], neg[29], pp_29_96); - r4bs r4bs_7680_2736(yy[35], yy[36], single[30], double[30], neg[30], pp_30_96); - r4bs r4bs_7680_2864(yy[33], yy[34], single[31], double[31], neg[31], pp_31_96); - fullAdd_x FA_7680_2992(int_11_96, int_10_96, pp_29_96, pp_30_96, pp_31_96); - r4bs r4bs_7680_3208(yy[31], yy[32], single[32], double[32], neg[32], pp_32_96); - fullAdd_x FA_7680_3336(int_13_96, int_12_96, pp_32_96, int_1_95, int_3_95); - fullAdd_x FA_7680_3552(int_15_96, int_14_96, int_5_95, int_7_95, int_9_95); - fullAdd_x FA_7680_3768(int_17_96, int_16_96, int_11_95, int_0_96, int_13_95); - fullAdd_x FA_7680_3984(int_19_96, int_18_96, int_15_95, int_2_96, int_4_96); - fullAdd_x FA_7680_4200(int_21_96, int_20_96, int_6_96, int_8_96, int_10_96); - fullAdd_x FA_7680_4416(int_23_96, int_22_96, int_17_95, int_19_95, int_21_95); - fullAdd_x FA_7680_4632(int_25_96, int_24_96, int_12_96, int_14_96, int_16_96); - fullAdd_x FA_7680_4848(int_27_96, int_26_96, int_23_95, int_18_96, int_20_96); - fullAdd_x FA_7680_5064(int_29_96, int_28_96, int_25_95, int_27_95, int_22_96); - fullAdd_x FA_7680_5280(int_31_96, int_30_96, int_24_96, int_29_95, int_26_96); - fullAdd_x FA_7680_5496(int_33_96, int_32_96, int_28_96, int_31_95, int_30_96); - assign Sum[96] = int_33_95; - assign Carry[96] = int_32_96; - - // Hardware for column 97 - - r4bs r4bs_7760_0(yy[62], yy[63], single[17], double[17], neg[17], pp_17_97); - r4bs r4bs_7760_128(yy[60], yy[61], single[18], double[18], neg[18], pp_18_97); - fullAdd_x FA_7760_256(int_1_97, int_0_97, negbar[16], pp_17_97, pp_18_97); - r4bs r4bs_7760_472(yy[58], yy[59], single[19], double[19], neg[19], pp_19_97); - r4bs r4bs_7760_600(yy[56], yy[57], single[20], double[20], neg[20], pp_20_97); - r4bs r4bs_7760_728(yy[54], yy[55], single[21], double[21], neg[21], pp_21_97); - fullAdd_x FA_7760_856(int_3_97, int_2_97, pp_19_97, pp_20_97, pp_21_97); - r4bs r4bs_7760_1072(yy[52], yy[53], single[22], double[22], neg[22], pp_22_97); - r4bs r4bs_7760_1200(yy[50], yy[51], single[23], double[23], neg[23], pp_23_97); - r4bs r4bs_7760_1328(yy[48], yy[49], single[24], double[24], neg[24], pp_24_97); - fullAdd_x FA_7760_1456(int_5_97, int_4_97, pp_22_97, pp_23_97, pp_24_97); - r4bs r4bs_7760_1672(yy[46], yy[47], single[25], double[25], neg[25], pp_25_97); - r4bs r4bs_7760_1800(yy[44], yy[45], single[26], double[26], neg[26], pp_26_97); - r4bs r4bs_7760_1928(yy[42], yy[43], single[27], double[27], neg[27], pp_27_97); - fullAdd_x FA_7760_2056(int_7_97, int_6_97, pp_25_97, pp_26_97, pp_27_97); - r4bs r4bs_7760_2272(yy[40], yy[41], single[28], double[28], neg[28], pp_28_97); - r4bs r4bs_7760_2400(yy[38], yy[39], single[29], double[29], neg[29], pp_29_97); - r4bs r4bs_7760_2528(yy[36], yy[37], single[30], double[30], neg[30], pp_30_97); - fullAdd_x FA_7760_2656(int_9_97, int_8_97, pp_28_97, pp_29_97, pp_30_97); - r4bs r4bs_7760_2872(yy[34], yy[35], single[31], double[31], neg[31], pp_31_97); - r4bs r4bs_7760_3000(yy[32], yy[33], single[32], double[32], neg[32], pp_32_97); - fullAdd_x FA_7760_3128(int_11_97, int_10_97, pp_31_97, pp_32_97, int_1_96); - fullAdd_x FA_7760_3344(int_13_97, int_12_97, int_3_96, int_5_96, int_7_96); - fullAdd_x FA_7760_3560(int_15_97, int_14_97, int_9_96, int_11_96, int_13_96); - fullAdd_x FA_7760_3776(int_17_97, int_16_97, int_15_96, int_0_97, int_2_97); - fullAdd_x FA_7760_3992(int_19_97, int_18_97, int_4_97, int_6_97, int_8_97); - fullAdd_x FA_7760_4208(int_21_97, int_20_97, int_10_97, int_17_96, int_19_96); - fullAdd_x FA_7760_4424(int_23_97, int_22_97, int_21_96, int_12_97, int_14_97); - fullAdd_x FA_7760_4640(int_25_97, int_24_97, int_23_96, int_25_96, int_16_97); - fullAdd_x FA_7760_4856(int_27_97, int_26_97, int_18_97, int_27_96, int_20_97); - fullAdd_x FA_7760_5072(int_29_97, int_28_97, int_22_97, int_29_96, int_24_97); - fullAdd_x FA_7760_5288(int_31_97, int_30_97, int_31_96, int_26_97, int_28_97); - assign Sum[97] = int_33_96; - assign Carry[97] = int_30_97; - - // Hardware for column 98 - - r4bs r4bs_7840_0(yy[63], gnd, single[17], double[17], neg[17], pp_17_98); - halfAdd HA_7840_128(int_1_98, int_0_98, 1'b1, pp_17_98); - r4bs r4bs_7840_208(yy[61], yy[62], single[18], double[18], neg[18], pp_18_98); - r4bs r4bs_7840_336(yy[59], yy[60], single[19], double[19], neg[19], pp_19_98); - r4bs r4bs_7840_464(yy[57], yy[58], single[20], double[20], neg[20], pp_20_98); - fullAdd_x FA_7840_592(int_3_98, int_2_98, pp_18_98, pp_19_98, pp_20_98); - r4bs r4bs_7840_808(yy[55], yy[56], single[21], double[21], neg[21], pp_21_98); - r4bs r4bs_7840_936(yy[53], yy[54], single[22], double[22], neg[22], pp_22_98); - r4bs r4bs_7840_1064(yy[51], yy[52], single[23], double[23], neg[23], pp_23_98); - fullAdd_x FA_7840_1192(int_5_98, int_4_98, pp_21_98, pp_22_98, pp_23_98); - r4bs r4bs_7840_1408(yy[49], yy[50], single[24], double[24], neg[24], pp_24_98); - r4bs r4bs_7840_1536(yy[47], yy[48], single[25], double[25], neg[25], pp_25_98); - r4bs r4bs_7840_1664(yy[45], yy[46], single[26], double[26], neg[26], pp_26_98); - fullAdd_x FA_7840_1792(int_7_98, int_6_98, pp_24_98, pp_25_98, pp_26_98); - r4bs r4bs_7840_2008(yy[43], yy[44], single[27], double[27], neg[27], pp_27_98); - r4bs r4bs_7840_2136(yy[41], yy[42], single[28], double[28], neg[28], pp_28_98); - r4bs r4bs_7840_2264(yy[39], yy[40], single[29], double[29], neg[29], pp_29_98); - fullAdd_x FA_7840_2392(int_9_98, int_8_98, pp_27_98, pp_28_98, pp_29_98); - r4bs r4bs_7840_2608(yy[37], yy[38], single[30], double[30], neg[30], pp_30_98); - r4bs r4bs_7840_2736(yy[35], yy[36], single[31], double[31], neg[31], pp_31_98); - r4bs r4bs_7840_2864(yy[33], yy[34], single[32], double[32], neg[32], pp_32_98); - fullAdd_x FA_7840_2992(int_11_98, int_10_98, pp_30_98, pp_31_98, pp_32_98); - fullAdd_x FA_7840_3208(int_13_98, int_12_98, int_1_97, int_3_97, int_5_97); - fullAdd_x FA_7840_3424(int_15_98, int_14_98, int_7_97, int_9_97, int_0_98); - fullAdd_x FA_7840_3640(int_17_98, int_16_98, int_11_97, int_13_97, int_2_98); - fullAdd_x FA_7840_3856(int_19_98, int_18_98, int_4_98, int_6_98, int_8_98); - fullAdd_x FA_7840_4072(int_21_98, int_20_98, int_10_98, int_15_97, int_17_97); - fullAdd_x FA_7840_4288(int_23_98, int_22_98, int_19_97, int_12_98, int_14_98); - fullAdd_x FA_7840_4504(int_25_98, int_24_98, int_21_97, int_23_97, int_16_98); - fullAdd_x FA_7840_4720(int_27_98, int_26_98, int_18_98, int_25_97, int_20_98); - fullAdd_x FA_7840_4936(int_29_98, int_28_98, int_22_98, int_27_97, int_24_98); - fullAdd_x FA_7840_5152(int_31_98, int_30_98, int_29_97, int_26_98, int_28_98); - assign Sum[98] = int_31_97; - assign Carry[98] = int_30_98; - - // Hardware for column 99 - - r4bs r4bs_7920_0(yy[62], yy[63], single[18], double[18], neg[18], pp_18_99); - r4bs r4bs_7920_128(yy[60], yy[61], single[19], double[19], neg[19], pp_19_99); - fullAdd_x FA_7920_256(int_1_99, int_0_99, negbar[17], pp_18_99, pp_19_99); - r4bs r4bs_7920_472(yy[58], yy[59], single[20], double[20], neg[20], pp_20_99); - r4bs r4bs_7920_600(yy[56], yy[57], single[21], double[21], neg[21], pp_21_99); - r4bs r4bs_7920_728(yy[54], yy[55], single[22], double[22], neg[22], pp_22_99); - fullAdd_x FA_7920_856(int_3_99, int_2_99, pp_20_99, pp_21_99, pp_22_99); - r4bs r4bs_7920_1072(yy[52], yy[53], single[23], double[23], neg[23], pp_23_99); - r4bs r4bs_7920_1200(yy[50], yy[51], single[24], double[24], neg[24], pp_24_99); - r4bs r4bs_7920_1328(yy[48], yy[49], single[25], double[25], neg[25], pp_25_99); - fullAdd_x FA_7920_1456(int_5_99, int_4_99, pp_23_99, pp_24_99, pp_25_99); - r4bs r4bs_7920_1672(yy[46], yy[47], single[26], double[26], neg[26], pp_26_99); - r4bs r4bs_7920_1800(yy[44], yy[45], single[27], double[27], neg[27], pp_27_99); - r4bs r4bs_7920_1928(yy[42], yy[43], single[28], double[28], neg[28], pp_28_99); - fullAdd_x FA_7920_2056(int_7_99, int_6_99, pp_26_99, pp_27_99, pp_28_99); - r4bs r4bs_7920_2272(yy[40], yy[41], single[29], double[29], neg[29], pp_29_99); - r4bs r4bs_7920_2400(yy[38], yy[39], single[30], double[30], neg[30], pp_30_99); - r4bs r4bs_7920_2528(yy[36], yy[37], single[31], double[31], neg[31], pp_31_99); - fullAdd_x FA_7920_2656(int_9_99, int_8_99, pp_29_99, pp_30_99, pp_31_99); - r4bs r4bs_7920_2872(yy[34], yy[35], single[32], double[32], neg[32], pp_32_99); - fullAdd_x FA_7920_3000(int_11_99, int_10_99, pp_32_99, int_1_98, int_3_98); - fullAdd_x FA_7920_3216(int_13_99, int_12_99, int_5_98, int_7_98, int_9_98); - fullAdd_x FA_7920_3432(int_15_99, int_14_99, int_11_98, int_13_98, int_15_98); - fullAdd_x FA_7920_3648(int_17_99, int_16_99, int_0_99, int_2_99, int_4_99); - fullAdd_x FA_7920_3864(int_19_99, int_18_99, int_6_99, int_8_99, int_10_99); - fullAdd_x FA_7920_4080(int_21_99, int_20_99, int_17_98, int_19_98, int_12_99); - fullAdd_x FA_7920_4296(int_23_99, int_22_99, int_21_98, int_23_98, int_14_99); - fullAdd_x FA_7920_4512(int_25_99, int_24_99, int_16_99, int_18_99, int_25_98); - fullAdd_x FA_7920_4728(int_27_99, int_26_99, int_20_99, int_27_98, int_22_99); - fullAdd_x FA_7920_4944(int_29_99, int_28_99, int_24_99, int_29_98, int_26_99); - assign Sum[99] = int_31_98; - assign Carry[99] = int_28_99; - - // Hardware for column 100 - - r4bs r4bs_8000_0(yy[63], gnd, single[18], double[18], neg[18], pp_18_100); - halfAdd HA_8000_128(int_1_100, int_0_100, 1'b1, pp_18_100); - r4bs r4bs_8000_208(yy[61], yy[62], single[19], double[19], neg[19], pp_19_100); - r4bs r4bs_8000_336(yy[59], yy[60], single[20], double[20], neg[20], pp_20_100); - r4bs r4bs_8000_464(yy[57], yy[58], single[21], double[21], neg[21], pp_21_100); - fullAdd_x FA_8000_592(int_3_100, int_2_100, pp_19_100, pp_20_100, pp_21_100); - r4bs r4bs_8000_808(yy[55], yy[56], single[22], double[22], neg[22], pp_22_100); - r4bs r4bs_8000_936(yy[53], yy[54], single[23], double[23], neg[23], pp_23_100); - r4bs r4bs_8000_1064(yy[51], yy[52], single[24], double[24], neg[24], pp_24_100); - fullAdd_x FA_8000_1192(int_5_100, int_4_100, pp_22_100, pp_23_100, pp_24_100); - r4bs r4bs_8000_1408(yy[49], yy[50], single[25], double[25], neg[25], pp_25_100); - r4bs r4bs_8000_1536(yy[47], yy[48], single[26], double[26], neg[26], pp_26_100); - r4bs r4bs_8000_1664(yy[45], yy[46], single[27], double[27], neg[27], pp_27_100); - fullAdd_x FA_8000_1792(int_7_100, int_6_100, pp_25_100, pp_26_100, pp_27_100); - r4bs r4bs_8000_2008(yy[43], yy[44], single[28], double[28], neg[28], pp_28_100); - r4bs r4bs_8000_2136(yy[41], yy[42], single[29], double[29], neg[29], pp_29_100); - r4bs r4bs_8000_2264(yy[39], yy[40], single[30], double[30], neg[30], pp_30_100); - fullAdd_x FA_8000_2392(int_9_100, int_8_100, pp_28_100, pp_29_100, pp_30_100); - r4bs r4bs_8000_2608(yy[37], yy[38], single[31], double[31], neg[31], pp_31_100); - r4bs r4bs_8000_2736(yy[35], yy[36], single[32], double[32], neg[32], pp_32_100); - fullAdd_x FA_8000_2864(int_11_100, int_10_100, pp_31_100, pp_32_100, int_1_99); - fullAdd_x FA_8000_3080(int_13_100, int_12_100, int_3_99, int_5_99, int_7_99); - fullAdd_x FA_8000_3296(int_15_100, int_14_100, int_9_99, int_0_100, int_11_99); - fullAdd_x FA_8000_3512(int_17_100, int_16_100, int_13_99, int_2_100, int_4_100); - fullAdd_x FA_8000_3728(int_19_100, int_18_100, int_6_100, int_8_100, int_10_100); - fullAdd_x FA_8000_3944(int_21_100, int_20_100, int_15_99, int_17_99, int_12_100); - fullAdd_x FA_8000_4160(int_23_100, int_22_100, int_14_100, int_19_99, int_21_99); - fullAdd_x FA_8000_4376(int_25_100, int_24_100, int_16_100, int_18_100, int_23_99); - fullAdd_x FA_8000_4592(int_27_100, int_26_100, int_20_100, int_22_100, int_25_99); - fullAdd_x FA_8000_4808(int_29_100, int_28_100, int_24_100, int_27_99, int_26_100); - assign Sum[100] = int_29_99; - assign Carry[100] = int_28_100; - - // Hardware for column 101 - - r4bs r4bs_8080_0(yy[62], yy[63], single[19], double[19], neg[19], pp_19_101); - r4bs r4bs_8080_128(yy[60], yy[61], single[20], double[20], neg[20], pp_20_101); - fullAdd_x FA_8080_256(int_1_101, int_0_101, negbar[18], pp_19_101, pp_20_101); - r4bs r4bs_8080_472(yy[58], yy[59], single[21], double[21], neg[21], pp_21_101); - r4bs r4bs_8080_600(yy[56], yy[57], single[22], double[22], neg[22], pp_22_101); - r4bs r4bs_8080_728(yy[54], yy[55], single[23], double[23], neg[23], pp_23_101); - fullAdd_x FA_8080_856(int_3_101, int_2_101, pp_21_101, pp_22_101, pp_23_101); - r4bs r4bs_8080_1072(yy[52], yy[53], single[24], double[24], neg[24], pp_24_101); - r4bs r4bs_8080_1200(yy[50], yy[51], single[25], double[25], neg[25], pp_25_101); - r4bs r4bs_8080_1328(yy[48], yy[49], single[26], double[26], neg[26], pp_26_101); - fullAdd_x FA_8080_1456(int_5_101, int_4_101, pp_24_101, pp_25_101, pp_26_101); - r4bs r4bs_8080_1672(yy[46], yy[47], single[27], double[27], neg[27], pp_27_101); - r4bs r4bs_8080_1800(yy[44], yy[45], single[28], double[28], neg[28], pp_28_101); - r4bs r4bs_8080_1928(yy[42], yy[43], single[29], double[29], neg[29], pp_29_101); - fullAdd_x FA_8080_2056(int_7_101, int_6_101, pp_27_101, pp_28_101, pp_29_101); - r4bs r4bs_8080_2272(yy[40], yy[41], single[30], double[30], neg[30], pp_30_101); - r4bs r4bs_8080_2400(yy[38], yy[39], single[31], double[31], neg[31], pp_31_101); - r4bs r4bs_8080_2528(yy[36], yy[37], single[32], double[32], neg[32], pp_32_101); - fullAdd_x FA_8080_2656(int_9_101, int_8_101, pp_30_101, pp_31_101, pp_32_101); - fullAdd_x FA_8080_2872(int_11_101, int_10_101, int_1_100, int_3_100, int_5_100); - fullAdd_x FA_8080_3088(int_13_101, int_12_101, int_7_100, int_9_100, int_11_100); - fullAdd_x FA_8080_3304(int_15_101, int_14_101, int_13_100, int_0_101, int_2_101); - fullAdd_x FA_8080_3520(int_17_101, int_16_101, int_4_101, int_6_101, int_8_101); - fullAdd_x FA_8080_3736(int_19_101, int_18_101, int_15_100, int_17_100, int_19_100); - fullAdd_x FA_8080_3952(int_21_101, int_20_101, int_10_101, int_12_101, int_21_100); - fullAdd_x FA_8080_4168(int_23_101, int_22_101, int_14_101, int_16_101, int_23_100); - fullAdd_x FA_8080_4384(int_25_101, int_24_101, int_18_101, int_20_101, int_25_100); - fullAdd_x FA_8080_4600(int_27_101, int_26_101, int_22_101, int_27_100, int_24_101); - assign Sum[101] = int_29_100; - assign Carry[101] = int_26_101; - - // Hardware for column 102 - - r4bs r4bs_8160_0(yy[63], gnd, single[19], double[19], neg[19], pp_19_102); - halfAdd HA_8160_128(int_1_102, int_0_102, 1'b1, pp_19_102); - r4bs r4bs_8160_208(yy[61], yy[62], single[20], double[20], neg[20], pp_20_102); - r4bs r4bs_8160_336(yy[59], yy[60], single[21], double[21], neg[21], pp_21_102); - r4bs r4bs_8160_464(yy[57], yy[58], single[22], double[22], neg[22], pp_22_102); - fullAdd_x FA_8160_592(int_3_102, int_2_102, pp_20_102, pp_21_102, pp_22_102); - r4bs r4bs_8160_808(yy[55], yy[56], single[23], double[23], neg[23], pp_23_102); - r4bs r4bs_8160_936(yy[53], yy[54], single[24], double[24], neg[24], pp_24_102); - r4bs r4bs_8160_1064(yy[51], yy[52], single[25], double[25], neg[25], pp_25_102); - fullAdd_x FA_8160_1192(int_5_102, int_4_102, pp_23_102, pp_24_102, pp_25_102); - r4bs r4bs_8160_1408(yy[49], yy[50], single[26], double[26], neg[26], pp_26_102); - r4bs r4bs_8160_1536(yy[47], yy[48], single[27], double[27], neg[27], pp_27_102); - r4bs r4bs_8160_1664(yy[45], yy[46], single[28], double[28], neg[28], pp_28_102); - fullAdd_x FA_8160_1792(int_7_102, int_6_102, pp_26_102, pp_27_102, pp_28_102); - r4bs r4bs_8160_2008(yy[43], yy[44], single[29], double[29], neg[29], pp_29_102); - r4bs r4bs_8160_2136(yy[41], yy[42], single[30], double[30], neg[30], pp_30_102); - r4bs r4bs_8160_2264(yy[39], yy[40], single[31], double[31], neg[31], pp_31_102); - fullAdd_x FA_8160_2392(int_9_102, int_8_102, pp_29_102, pp_30_102, pp_31_102); - r4bs r4bs_8160_2608(yy[37], yy[38], single[32], double[32], neg[32], pp_32_102); - fullAdd_x FA_8160_2736(int_11_102, int_10_102, pp_32_102, int_1_101, int_3_101); - fullAdd_x FA_8160_2952(int_13_102, int_12_102, int_5_101, int_7_101, int_9_101); - fullAdd_x FA_8160_3168(int_15_102, int_14_102, int_0_102, int_11_101, int_2_102); - fullAdd_x FA_8160_3384(int_17_102, int_16_102, int_4_102, int_6_102, int_8_102); - fullAdd_x FA_8160_3600(int_19_102, int_18_102, int_13_101, int_15_101, int_17_101); - fullAdd_x FA_8160_3816(int_21_102, int_20_102, int_10_102, int_12_102, int_19_101); - fullAdd_x FA_8160_4032(int_23_102, int_22_102, int_14_102, int_16_102, int_21_101); - fullAdd_x FA_8160_4248(int_25_102, int_24_102, int_18_102, int_20_102, int_23_101); - fullAdd_x FA_8160_4464(int_27_102, int_26_102, int_22_102, int_25_101, int_24_102); - assign Sum[102] = int_27_101; - assign Carry[102] = int_26_102; - - // Hardware for column 103 - - r4bs r4bs_8240_0(yy[62], yy[63], single[20], double[20], neg[20], pp_20_103); - r4bs r4bs_8240_128(yy[60], yy[61], single[21], double[21], neg[21], pp_21_103); - fullAdd_x FA_8240_256(int_1_103, int_0_103, negbar[19], pp_20_103, pp_21_103); - r4bs r4bs_8240_472(yy[58], yy[59], single[22], double[22], neg[22], pp_22_103); - r4bs r4bs_8240_600(yy[56], yy[57], single[23], double[23], neg[23], pp_23_103); - r4bs r4bs_8240_728(yy[54], yy[55], single[24], double[24], neg[24], pp_24_103); - fullAdd_x FA_8240_856(int_3_103, int_2_103, pp_22_103, pp_23_103, pp_24_103); - r4bs r4bs_8240_1072(yy[52], yy[53], single[25], double[25], neg[25], pp_25_103); - r4bs r4bs_8240_1200(yy[50], yy[51], single[26], double[26], neg[26], pp_26_103); - r4bs r4bs_8240_1328(yy[48], yy[49], single[27], double[27], neg[27], pp_27_103); - fullAdd_x FA_8240_1456(int_5_103, int_4_103, pp_25_103, pp_26_103, pp_27_103); - r4bs r4bs_8240_1672(yy[46], yy[47], single[28], double[28], neg[28], pp_28_103); - r4bs r4bs_8240_1800(yy[44], yy[45], single[29], double[29], neg[29], pp_29_103); - r4bs r4bs_8240_1928(yy[42], yy[43], single[30], double[30], neg[30], pp_30_103); - fullAdd_x FA_8240_2056(int_7_103, int_6_103, pp_28_103, pp_29_103, pp_30_103); - r4bs r4bs_8240_2272(yy[40], yy[41], single[31], double[31], neg[31], pp_31_103); - r4bs r4bs_8240_2400(yy[38], yy[39], single[32], double[32], neg[32], pp_32_103); - fullAdd_x FA_8240_2528(int_9_103, int_8_103, pp_31_103, pp_32_103, int_1_102); - fullAdd_x FA_8240_2744(int_11_103, int_10_103, int_3_102, int_5_102, int_7_102); - fullAdd_x FA_8240_2960(int_13_103, int_12_103, int_9_102, int_11_102, int_13_102); - fullAdd_x FA_8240_3176(int_15_103, int_14_103, int_0_103, int_2_103, int_4_103); - fullAdd_x FA_8240_3392(int_17_103, int_16_103, int_6_103, int_8_103, int_15_102); - fullAdd_x FA_8240_3608(int_19_103, int_18_103, int_17_102, int_10_103, int_19_102); - fullAdd_x FA_8240_3824(int_21_103, int_20_103, int_12_103, int_14_103, int_16_103); - fullAdd_x FA_8240_4040(int_23_103, int_22_103, int_21_102, int_18_103, int_23_102); - fullAdd_x FA_8240_4256(int_25_103, int_24_103, int_20_103, int_25_102, int_22_103); - assign Sum[103] = int_27_102; - assign Carry[103] = int_24_103; - - // Hardware for column 104 - - r4bs r4bs_8320_0(yy[63], gnd, single[20], double[20], neg[20], pp_20_104); - halfAdd HA_8320_128(int_1_104, int_0_104, 1'b1, pp_20_104); - r4bs r4bs_8320_208(yy[61], yy[62], single[21], double[21], neg[21], pp_21_104); - r4bs r4bs_8320_336(yy[59], yy[60], single[22], double[22], neg[22], pp_22_104); - r4bs r4bs_8320_464(yy[57], yy[58], single[23], double[23], neg[23], pp_23_104); - fullAdd_x FA_8320_592(int_3_104, int_2_104, pp_21_104, pp_22_104, pp_23_104); - r4bs r4bs_8320_808(yy[55], yy[56], single[24], double[24], neg[24], pp_24_104); - r4bs r4bs_8320_936(yy[53], yy[54], single[25], double[25], neg[25], pp_25_104); - r4bs r4bs_8320_1064(yy[51], yy[52], single[26], double[26], neg[26], pp_26_104); - fullAdd_x FA_8320_1192(int_5_104, int_4_104, pp_24_104, pp_25_104, pp_26_104); - r4bs r4bs_8320_1408(yy[49], yy[50], single[27], double[27], neg[27], pp_27_104); - r4bs r4bs_8320_1536(yy[47], yy[48], single[28], double[28], neg[28], pp_28_104); - r4bs r4bs_8320_1664(yy[45], yy[46], single[29], double[29], neg[29], pp_29_104); - fullAdd_x FA_8320_1792(int_7_104, int_6_104, pp_27_104, pp_28_104, pp_29_104); - r4bs r4bs_8320_2008(yy[43], yy[44], single[30], double[30], neg[30], pp_30_104); - r4bs r4bs_8320_2136(yy[41], yy[42], single[31], double[31], neg[31], pp_31_104); - r4bs r4bs_8320_2264(yy[39], yy[40], single[32], double[32], neg[32], pp_32_104); - fullAdd_x FA_8320_2392(int_9_104, int_8_104, pp_30_104, pp_31_104, pp_32_104); - fullAdd_x FA_8320_2608(int_11_104, int_10_104, int_1_103, int_3_103, int_5_103); - fullAdd_x FA_8320_2824(int_13_104, int_12_104, int_7_103, int_0_104, int_9_103); - fullAdd_x FA_8320_3040(int_15_104, int_14_104, int_11_103, int_2_104, int_4_104); - fullAdd_x FA_8320_3256(int_17_104, int_16_104, int_6_104, int_8_104, int_13_103); - fullAdd_x FA_8320_3472(int_19_104, int_18_104, int_15_103, int_10_104, int_12_104); - fullAdd_x FA_8320_3688(int_21_104, int_20_104, int_17_103, int_14_104, int_16_104); - fullAdd_x FA_8320_3904(int_23_104, int_22_104, int_19_103, int_21_103, int_18_104); - fullAdd_x FA_8320_4120(int_25_104, int_24_104, int_20_104, int_23_103, int_22_104); - assign Sum[104] = int_25_103; - assign Carry[104] = int_24_104; - - // Hardware for column 105 - - r4bs r4bs_8400_0(yy[62], yy[63], single[21], double[21], neg[21], pp_21_105); - r4bs r4bs_8400_128(yy[60], yy[61], single[22], double[22], neg[22], pp_22_105); - fullAdd_x FA_8400_256(int_1_105, int_0_105, negbar[20], pp_21_105, pp_22_105); - r4bs r4bs_8400_472(yy[58], yy[59], single[23], double[23], neg[23], pp_23_105); - r4bs r4bs_8400_600(yy[56], yy[57], single[24], double[24], neg[24], pp_24_105); - r4bs r4bs_8400_728(yy[54], yy[55], single[25], double[25], neg[25], pp_25_105); - fullAdd_x FA_8400_856(int_3_105, int_2_105, pp_23_105, pp_24_105, pp_25_105); - r4bs r4bs_8400_1072(yy[52], yy[53], single[26], double[26], neg[26], pp_26_105); - r4bs r4bs_8400_1200(yy[50], yy[51], single[27], double[27], neg[27], pp_27_105); - r4bs r4bs_8400_1328(yy[48], yy[49], single[28], double[28], neg[28], pp_28_105); - fullAdd_x FA_8400_1456(int_5_105, int_4_105, pp_26_105, pp_27_105, pp_28_105); - r4bs r4bs_8400_1672(yy[46], yy[47], single[29], double[29], neg[29], pp_29_105); - r4bs r4bs_8400_1800(yy[44], yy[45], single[30], double[30], neg[30], pp_30_105); - r4bs r4bs_8400_1928(yy[42], yy[43], single[31], double[31], neg[31], pp_31_105); - fullAdd_x FA_8400_2056(int_7_105, int_6_105, pp_29_105, pp_30_105, pp_31_105); - r4bs r4bs_8400_2272(yy[40], yy[41], single[32], double[32], neg[32], pp_32_105); - fullAdd_x FA_8400_2400(int_9_105, int_8_105, pp_32_105, int_1_104, int_3_104); - fullAdd_x FA_8400_2616(int_11_105, int_10_105, int_5_104, int_7_104, int_9_104); - fullAdd_x FA_8400_2832(int_13_105, int_12_105, int_11_104, int_0_105, int_2_105); - fullAdd_x FA_8400_3048(int_15_105, int_14_105, int_4_105, int_6_105, int_13_104); - fullAdd_x FA_8400_3264(int_17_105, int_16_105, int_8_105, int_15_104, int_10_105); - fullAdd_x FA_8400_3480(int_19_105, int_18_105, int_17_104, int_19_104, int_12_105); - fullAdd_x FA_8400_3696(int_21_105, int_20_105, int_14_105, int_21_104, int_16_105); - fullAdd_x FA_8400_3912(int_23_105, int_22_105, int_23_104, int_18_105, int_20_105); - assign Sum[105] = int_25_104; - assign Carry[105] = int_22_105; - - // Hardware for column 106 - - r4bs r4bs_8480_0(yy[63], gnd, single[21], double[21], neg[21], pp_21_106); - halfAdd HA_8480_128(int_1_106, int_0_106, 1'b1, pp_21_106); - r4bs r4bs_8480_208(yy[61], yy[62], single[22], double[22], neg[22], pp_22_106); - r4bs r4bs_8480_336(yy[59], yy[60], single[23], double[23], neg[23], pp_23_106); - r4bs r4bs_8480_464(yy[57], yy[58], single[24], double[24], neg[24], pp_24_106); - fullAdd_x FA_8480_592(int_3_106, int_2_106, pp_22_106, pp_23_106, pp_24_106); - r4bs r4bs_8480_808(yy[55], yy[56], single[25], double[25], neg[25], pp_25_106); - r4bs r4bs_8480_936(yy[53], yy[54], single[26], double[26], neg[26], pp_26_106); - r4bs r4bs_8480_1064(yy[51], yy[52], single[27], double[27], neg[27], pp_27_106); - fullAdd_x FA_8480_1192(int_5_106, int_4_106, pp_25_106, pp_26_106, pp_27_106); - r4bs r4bs_8480_1408(yy[49], yy[50], single[28], double[28], neg[28], pp_28_106); - r4bs r4bs_8480_1536(yy[47], yy[48], single[29], double[29], neg[29], pp_29_106); - r4bs r4bs_8480_1664(yy[45], yy[46], single[30], double[30], neg[30], pp_30_106); - fullAdd_x FA_8480_1792(int_7_106, int_6_106, pp_28_106, pp_29_106, pp_30_106); - r4bs r4bs_8480_2008(yy[43], yy[44], single[31], double[31], neg[31], pp_31_106); - r4bs r4bs_8480_2136(yy[41], yy[42], single[32], double[32], neg[32], pp_32_106); - fullAdd_x FA_8480_2264(int_9_106, int_8_106, pp_31_106, pp_32_106, int_1_105); - fullAdd_x FA_8480_2480(int_11_106, int_10_106, int_3_105, int_5_105, int_7_105); - fullAdd_x FA_8480_2696(int_13_106, int_12_106, int_0_106, int_9_105, int_11_105); - fullAdd_x FA_8480_2912(int_15_106, int_14_106, int_2_106, int_4_106, int_6_106); - fullAdd_x FA_8480_3128(int_17_106, int_16_106, int_8_106, int_13_105, int_10_106); - fullAdd_x FA_8480_3344(int_19_106, int_18_106, int_15_105, int_17_105, int_12_106); - fullAdd_x FA_8480_3560(int_21_106, int_20_106, int_14_106, int_19_105, int_16_106); - fullAdd_x FA_8480_3776(int_23_106, int_22_106, int_21_105, int_18_106, int_20_106); - assign Sum[106] = int_23_105; - assign Carry[106] = int_22_106; - - // Hardware for column 107 - - r4bs r4bs_8560_0(yy[62], yy[63], single[22], double[22], neg[22], pp_22_107); - r4bs r4bs_8560_128(yy[60], yy[61], single[23], double[23], neg[23], pp_23_107); - fullAdd_x FA_8560_256(int_1_107, int_0_107, negbar[21], pp_22_107, pp_23_107); - r4bs r4bs_8560_472(yy[58], yy[59], single[24], double[24], neg[24], pp_24_107); - r4bs r4bs_8560_600(yy[56], yy[57], single[25], double[25], neg[25], pp_25_107); - r4bs r4bs_8560_728(yy[54], yy[55], single[26], double[26], neg[26], pp_26_107); - fullAdd_x FA_8560_856(int_3_107, int_2_107, pp_24_107, pp_25_107, pp_26_107); - r4bs r4bs_8560_1072(yy[52], yy[53], single[27], double[27], neg[27], pp_27_107); - r4bs r4bs_8560_1200(yy[50], yy[51], single[28], double[28], neg[28], pp_28_107); - r4bs r4bs_8560_1328(yy[48], yy[49], single[29], double[29], neg[29], pp_29_107); - fullAdd_x FA_8560_1456(int_5_107, int_4_107, pp_27_107, pp_28_107, pp_29_107); - r4bs r4bs_8560_1672(yy[46], yy[47], single[30], double[30], neg[30], pp_30_107); - r4bs r4bs_8560_1800(yy[44], yy[45], single[31], double[31], neg[31], pp_31_107); - r4bs r4bs_8560_1928(yy[42], yy[43], single[32], double[32], neg[32], pp_32_107); - fullAdd_x FA_8560_2056(int_7_107, int_6_107, pp_30_107, pp_31_107, pp_32_107); - fullAdd_x FA_8560_2272(int_9_107, int_8_107, int_1_106, int_3_106, int_5_106); - fullAdd_x FA_8560_2488(int_11_107, int_10_107, int_7_106, int_9_106, int_11_106); - fullAdd_x FA_8560_2704(int_13_107, int_12_107, int_0_107, int_2_107, int_4_107); - fullAdd_x FA_8560_2920(int_15_107, int_14_107, int_6_107, int_13_106, int_15_106); - fullAdd_x FA_8560_3136(int_17_107, int_16_107, int_8_107, int_17_106, int_10_107); - fullAdd_x FA_8560_3352(int_19_107, int_18_107, int_12_107, int_19_106, int_14_107); - fullAdd_x FA_8560_3568(int_21_107, int_20_107, int_21_106, int_16_107, int_18_107); - assign Sum[107] = int_23_106; - assign Carry[107] = int_20_107; - - // Hardware for column 108 - - r4bs r4bs_8640_0(yy[63], gnd, single[22], double[22], neg[22], pp_22_108); - halfAdd HA_8640_128(int_1_108, int_0_108, 1'b1, pp_22_108); - r4bs r4bs_8640_208(yy[61], yy[62], single[23], double[23], neg[23], pp_23_108); - r4bs r4bs_8640_336(yy[59], yy[60], single[24], double[24], neg[24], pp_24_108); - r4bs r4bs_8640_464(yy[57], yy[58], single[25], double[25], neg[25], pp_25_108); - fullAdd_x FA_8640_592(int_3_108, int_2_108, pp_23_108, pp_24_108, pp_25_108); - r4bs r4bs_8640_808(yy[55], yy[56], single[26], double[26], neg[26], pp_26_108); - r4bs r4bs_8640_936(yy[53], yy[54], single[27], double[27], neg[27], pp_27_108); - r4bs r4bs_8640_1064(yy[51], yy[52], single[28], double[28], neg[28], pp_28_108); - fullAdd_x FA_8640_1192(int_5_108, int_4_108, pp_26_108, pp_27_108, pp_28_108); - r4bs r4bs_8640_1408(yy[49], yy[50], single[29], double[29], neg[29], pp_29_108); - r4bs r4bs_8640_1536(yy[47], yy[48], single[30], double[30], neg[30], pp_30_108); - r4bs r4bs_8640_1664(yy[45], yy[46], single[31], double[31], neg[31], pp_31_108); - fullAdd_x FA_8640_1792(int_7_108, int_6_108, pp_29_108, pp_30_108, pp_31_108); - r4bs r4bs_8640_2008(yy[43], yy[44], single[32], double[32], neg[32], pp_32_108); - fullAdd_x FA_8640_2136(int_9_108, int_8_108, pp_32_108, int_1_107, int_3_107); - fullAdd_x FA_8640_2352(int_11_108, int_10_108, int_5_107, int_7_107, int_0_108); - fullAdd_x FA_8640_2568(int_13_108, int_12_108, int_9_107, int_2_108, int_4_108); - fullAdd_x FA_8640_2784(int_15_108, int_14_108, int_6_108, int_11_107, int_13_107); - fullAdd_x FA_8640_3000(int_17_108, int_16_108, int_8_108, int_10_108, int_15_107); - fullAdd_x FA_8640_3216(int_19_108, int_18_108, int_12_108, int_17_107, int_14_108); - fullAdd_x FA_8640_3432(int_21_108, int_20_108, int_16_108, int_19_107, int_18_108); - assign Sum[108] = int_21_107; - assign Carry[108] = int_20_108; - - // Hardware for column 109 - - r4bs r4bs_8720_0(yy[62], yy[63], single[23], double[23], neg[23], pp_23_109); - r4bs r4bs_8720_128(yy[60], yy[61], single[24], double[24], neg[24], pp_24_109); - fullAdd_x FA_8720_256(int_1_109, int_0_109, negbar[22], pp_23_109, pp_24_109); - r4bs r4bs_8720_472(yy[58], yy[59], single[25], double[25], neg[25], pp_25_109); - r4bs r4bs_8720_600(yy[56], yy[57], single[26], double[26], neg[26], pp_26_109); - r4bs r4bs_8720_728(yy[54], yy[55], single[27], double[27], neg[27], pp_27_109); - fullAdd_x FA_8720_856(int_3_109, int_2_109, pp_25_109, pp_26_109, pp_27_109); - r4bs r4bs_8720_1072(yy[52], yy[53], single[28], double[28], neg[28], pp_28_109); - r4bs r4bs_8720_1200(yy[50], yy[51], single[29], double[29], neg[29], pp_29_109); - r4bs r4bs_8720_1328(yy[48], yy[49], single[30], double[30], neg[30], pp_30_109); - fullAdd_x FA_8720_1456(int_5_109, int_4_109, pp_28_109, pp_29_109, pp_30_109); - r4bs r4bs_8720_1672(yy[46], yy[47], single[31], double[31], neg[31], pp_31_109); - r4bs r4bs_8720_1800(yy[44], yy[45], single[32], double[32], neg[32], pp_32_109); - fullAdd_x FA_8720_1928(int_7_109, int_6_109, pp_31_109, pp_32_109, int_1_108); - fullAdd_x FA_8720_2144(int_9_109, int_8_109, int_3_108, int_5_108, int_7_108); - fullAdd_x FA_8720_2360(int_11_109, int_10_109, int_9_108, int_11_108, int_0_109); - fullAdd_x FA_8720_2576(int_13_109, int_12_109, int_2_109, int_4_109, int_6_109); - fullAdd_x FA_8720_2792(int_15_109, int_14_109, int_13_108, int_8_109, int_15_108); - fullAdd_x FA_8720_3008(int_17_109, int_16_109, int_10_109, int_12_109, int_17_108); - fullAdd_x FA_8720_3224(int_19_109, int_18_109, int_14_109, int_19_108, int_16_109); - assign Sum[109] = int_21_108; - assign Carry[109] = int_18_109; - - // Hardware for column 110 - - r4bs r4bs_8800_0(yy[63], gnd, single[23], double[23], neg[23], pp_23_110); - halfAdd HA_8800_128(int_1_110, int_0_110, 1'b1, pp_23_110); - r4bs r4bs_8800_208(yy[61], yy[62], single[24], double[24], neg[24], pp_24_110); - r4bs r4bs_8800_336(yy[59], yy[60], single[25], double[25], neg[25], pp_25_110); - r4bs r4bs_8800_464(yy[57], yy[58], single[26], double[26], neg[26], pp_26_110); - fullAdd_x FA_8800_592(int_3_110, int_2_110, pp_24_110, pp_25_110, pp_26_110); - r4bs r4bs_8800_808(yy[55], yy[56], single[27], double[27], neg[27], pp_27_110); - r4bs r4bs_8800_936(yy[53], yy[54], single[28], double[28], neg[28], pp_28_110); - r4bs r4bs_8800_1064(yy[51], yy[52], single[29], double[29], neg[29], pp_29_110); - fullAdd_x FA_8800_1192(int_5_110, int_4_110, pp_27_110, pp_28_110, pp_29_110); - r4bs r4bs_8800_1408(yy[49], yy[50], single[30], double[30], neg[30], pp_30_110); - r4bs r4bs_8800_1536(yy[47], yy[48], single[31], double[31], neg[31], pp_31_110); - r4bs r4bs_8800_1664(yy[45], yy[46], single[32], double[32], neg[32], pp_32_110); - fullAdd_x FA_8800_1792(int_7_110, int_6_110, pp_30_110, pp_31_110, pp_32_110); - fullAdd_x FA_8800_2008(int_9_110, int_8_110, int_1_109, int_3_109, int_5_109); - fullAdd_x FA_8800_2224(int_11_110, int_10_110, int_0_110, int_7_109, int_9_109); - fullAdd_x FA_8800_2440(int_13_110, int_12_110, int_2_110, int_4_110, int_6_110); - fullAdd_x FA_8800_2656(int_15_110, int_14_110, int_11_109, int_13_109, int_8_110); - fullAdd_x FA_8800_2872(int_17_110, int_16_110, int_10_110, int_12_110, int_15_109); - fullAdd_x FA_8800_3088(int_19_110, int_18_110, int_14_110, int_17_109, int_16_110); - assign Sum[110] = int_19_109; - assign Carry[110] = int_18_110; - - // Hardware for column 111 - - r4bs r4bs_8880_0(yy[62], yy[63], single[24], double[24], neg[24], pp_24_111); - r4bs r4bs_8880_128(yy[60], yy[61], single[25], double[25], neg[25], pp_25_111); - fullAdd_x FA_8880_256(int_1_111, int_0_111, negbar[23], pp_24_111, pp_25_111); - r4bs r4bs_8880_472(yy[58], yy[59], single[26], double[26], neg[26], pp_26_111); - r4bs r4bs_8880_600(yy[56], yy[57], single[27], double[27], neg[27], pp_27_111); - r4bs r4bs_8880_728(yy[54], yy[55], single[28], double[28], neg[28], pp_28_111); - fullAdd_x FA_8880_856(int_3_111, int_2_111, pp_26_111, pp_27_111, pp_28_111); - r4bs r4bs_8880_1072(yy[52], yy[53], single[29], double[29], neg[29], pp_29_111); - r4bs r4bs_8880_1200(yy[50], yy[51], single[30], double[30], neg[30], pp_30_111); - r4bs r4bs_8880_1328(yy[48], yy[49], single[31], double[31], neg[31], pp_31_111); - fullAdd_x FA_8880_1456(int_5_111, int_4_111, pp_29_111, pp_30_111, pp_31_111); - r4bs r4bs_8880_1672(yy[46], yy[47], single[32], double[32], neg[32], pp_32_111); - fullAdd_x FA_8880_1800(int_7_111, int_6_111, pp_32_111, int_1_110, int_3_110); - fullAdd_x FA_8880_2016(int_9_111, int_8_111, int_5_110, int_7_110, int_9_110); - fullAdd_x FA_8880_2232(int_11_111, int_10_111, int_0_111, int_2_111, int_4_111); - fullAdd_x FA_8880_2448(int_13_111, int_12_111, int_6_111, int_11_110, int_13_110); - fullAdd_x FA_8880_2664(int_15_111, int_14_111, int_8_111, int_15_110, int_10_111); - fullAdd_x FA_8880_2880(int_17_111, int_16_111, int_12_111, int_17_110, int_14_111); - assign Sum[111] = int_19_110; - assign Carry[111] = int_16_111; - - // Hardware for column 112 - - r4bs r4bs_8960_0(yy[63], gnd, single[24], double[24], neg[24], pp_24_112); - halfAdd HA_8960_128(int_1_112, int_0_112, 1'b1, pp_24_112); - r4bs r4bs_8960_208(yy[61], yy[62], single[25], double[25], neg[25], pp_25_112); - r4bs r4bs_8960_336(yy[59], yy[60], single[26], double[26], neg[26], pp_26_112); - r4bs r4bs_8960_464(yy[57], yy[58], single[27], double[27], neg[27], pp_27_112); - fullAdd_x FA_8960_592(int_3_112, int_2_112, pp_25_112, pp_26_112, pp_27_112); - r4bs r4bs_8960_808(yy[55], yy[56], single[28], double[28], neg[28], pp_28_112); - r4bs r4bs_8960_936(yy[53], yy[54], single[29], double[29], neg[29], pp_29_112); - r4bs r4bs_8960_1064(yy[51], yy[52], single[30], double[30], neg[30], pp_30_112); - fullAdd_x FA_8960_1192(int_5_112, int_4_112, pp_28_112, pp_29_112, pp_30_112); - r4bs r4bs_8960_1408(yy[49], yy[50], single[31], double[31], neg[31], pp_31_112); - r4bs r4bs_8960_1536(yy[47], yy[48], single[32], double[32], neg[32], pp_32_112); - fullAdd_x FA_8960_1664(int_7_112, int_6_112, pp_31_112, pp_32_112, int_1_111); - fullAdd_x FA_8960_1880(int_9_112, int_8_112, int_3_111, int_5_111, int_0_112); - fullAdd_x FA_8960_2096(int_11_112, int_10_112, int_7_111, int_2_112, int_4_112); - fullAdd_x FA_8960_2312(int_13_112, int_12_112, int_6_112, int_9_111, int_11_111); - fullAdd_x FA_8960_2528(int_15_112, int_14_112, int_8_112, int_13_111, int_10_112); - fullAdd_x FA_8960_2744(int_17_112, int_16_112, int_15_111, int_12_112, int_14_112); - assign Sum[112] = int_17_111; - assign Carry[112] = int_16_112; - - // Hardware for column 113 - - r4bs r4bs_9040_0(yy[62], yy[63], single[25], double[25], neg[25], pp_25_113); - r4bs r4bs_9040_128(yy[60], yy[61], single[26], double[26], neg[26], pp_26_113); - fullAdd_x FA_9040_256(int_1_113, int_0_113, negbar[24], pp_25_113, pp_26_113); - r4bs r4bs_9040_472(yy[58], yy[59], single[27], double[27], neg[27], pp_27_113); - r4bs r4bs_9040_600(yy[56], yy[57], single[28], double[28], neg[28], pp_28_113); - r4bs r4bs_9040_728(yy[54], yy[55], single[29], double[29], neg[29], pp_29_113); - fullAdd_x FA_9040_856(int_3_113, int_2_113, pp_27_113, pp_28_113, pp_29_113); - r4bs r4bs_9040_1072(yy[52], yy[53], single[30], double[30], neg[30], pp_30_113); - r4bs r4bs_9040_1200(yy[50], yy[51], single[31], double[31], neg[31], pp_31_113); - r4bs r4bs_9040_1328(yy[48], yy[49], single[32], double[32], neg[32], pp_32_113); - fullAdd_x FA_9040_1456(int_5_113, int_4_113, pp_30_113, pp_31_113, pp_32_113); - fullAdd_x FA_9040_1672(int_7_113, int_6_113, int_1_112, int_3_112, int_5_112); - fullAdd_x FA_9040_1888(int_9_113, int_8_113, int_7_112, int_9_112, int_0_113); - fullAdd_x FA_9040_2104(int_11_113, int_10_113, int_2_113, int_4_113, int_11_112); - fullAdd_x FA_9040_2320(int_13_113, int_12_113, int_6_113, int_13_112, int_8_113); - fullAdd_x FA_9040_2536(int_15_113, int_14_113, int_10_113, int_15_112, int_12_113); - assign Sum[113] = int_17_112; - assign Carry[113] = int_14_113; - - // Hardware for column 114 - - r4bs r4bs_9120_0(yy[63], gnd, single[25], double[25], neg[25], pp_25_114); - halfAdd HA_9120_128(int_1_114, int_0_114, 1'b1, pp_25_114); - r4bs r4bs_9120_208(yy[61], yy[62], single[26], double[26], neg[26], pp_26_114); - r4bs r4bs_9120_336(yy[59], yy[60], single[27], double[27], neg[27], pp_27_114); - r4bs r4bs_9120_464(yy[57], yy[58], single[28], double[28], neg[28], pp_28_114); - fullAdd_x FA_9120_592(int_3_114, int_2_114, pp_26_114, pp_27_114, pp_28_114); - r4bs r4bs_9120_808(yy[55], yy[56], single[29], double[29], neg[29], pp_29_114); - r4bs r4bs_9120_936(yy[53], yy[54], single[30], double[30], neg[30], pp_30_114); - r4bs r4bs_9120_1064(yy[51], yy[52], single[31], double[31], neg[31], pp_31_114); - fullAdd_x FA_9120_1192(int_5_114, int_4_114, pp_29_114, pp_30_114, pp_31_114); - r4bs r4bs_9120_1408(yy[49], yy[50], single[32], double[32], neg[32], pp_32_114); - fullAdd_x FA_9120_1536(int_7_114, int_6_114, pp_32_114, int_1_113, int_3_113); - fullAdd_x FA_9120_1752(int_9_114, int_8_114, int_5_113, int_0_114, int_7_113); - fullAdd_x FA_9120_1968(int_11_114, int_10_114, int_2_114, int_4_114, int_9_113); - fullAdd_x FA_9120_2184(int_13_114, int_12_114, int_6_114, int_8_114, int_11_113); - fullAdd_x FA_9120_2400(int_15_114, int_14_114, int_10_114, int_13_113, int_12_114); - assign Sum[114] = int_15_113; - assign Carry[114] = int_14_114; - - // Hardware for column 115 - - r4bs r4bs_9200_0(yy[62], yy[63], single[26], double[26], neg[26], pp_26_115); - r4bs r4bs_9200_128(yy[60], yy[61], single[27], double[27], neg[27], pp_27_115); - fullAdd_x FA_9200_256(int_1_115, int_0_115, negbar[25], pp_26_115, pp_27_115); - r4bs r4bs_9200_472(yy[58], yy[59], single[28], double[28], neg[28], pp_28_115); - r4bs r4bs_9200_600(yy[56], yy[57], single[29], double[29], neg[29], pp_29_115); - r4bs r4bs_9200_728(yy[54], yy[55], single[30], double[30], neg[30], pp_30_115); - fullAdd_x FA_9200_856(int_3_115, int_2_115, pp_28_115, pp_29_115, pp_30_115); - r4bs r4bs_9200_1072(yy[52], yy[53], single[31], double[31], neg[31], pp_31_115); - r4bs r4bs_9200_1200(yy[50], yy[51], single[32], double[32], neg[32], pp_32_115); - fullAdd_x FA_9200_1328(int_5_115, int_4_115, pp_31_115, pp_32_115, int_1_114); - fullAdd_x FA_9200_1544(int_7_115, int_6_115, int_3_114, int_5_114, int_7_114); - fullAdd_x FA_9200_1760(int_9_115, int_8_115, int_0_115, int_2_115, int_4_115); - fullAdd_x FA_9200_1976(int_11_115, int_10_115, int_9_114, int_6_115, int_11_114); - fullAdd_x FA_9200_2192(int_13_115, int_12_115, int_8_115, int_13_114, int_10_115); - assign Sum[115] = int_15_114; - assign Carry[115] = int_12_115; - - // Hardware for column 116 - - r4bs r4bs_9280_0(yy[63], gnd, single[26], double[26], neg[26], pp_26_116); - halfAdd HA_9280_128(int_1_116, int_0_116, 1'b1, pp_26_116); - r4bs r4bs_9280_208(yy[61], yy[62], single[27], double[27], neg[27], pp_27_116); - r4bs r4bs_9280_336(yy[59], yy[60], single[28], double[28], neg[28], pp_28_116); - r4bs r4bs_9280_464(yy[57], yy[58], single[29], double[29], neg[29], pp_29_116); - fullAdd_x FA_9280_592(int_3_116, int_2_116, pp_27_116, pp_28_116, pp_29_116); - r4bs r4bs_9280_808(yy[55], yy[56], single[30], double[30], neg[30], pp_30_116); - r4bs r4bs_9280_936(yy[53], yy[54], single[31], double[31], neg[31], pp_31_116); - r4bs r4bs_9280_1064(yy[51], yy[52], single[32], double[32], neg[32], pp_32_116); - fullAdd_x FA_9280_1192(int_5_116, int_4_116, pp_30_116, pp_31_116, pp_32_116); - fullAdd_x FA_9280_1408(int_7_116, int_6_116, int_1_115, int_3_115, int_0_116); - fullAdd_x FA_9280_1624(int_9_116, int_8_116, int_5_115, int_2_116, int_4_116); - fullAdd_x FA_9280_1840(int_11_116, int_10_116, int_7_115, int_9_115, int_6_116); - fullAdd_x FA_9280_2056(int_13_116, int_12_116, int_8_116, int_11_115, int_10_116); - assign Sum[116] = int_13_115; - assign Carry[116] = int_12_116; - - // Hardware for column 117 - - r4bs r4bs_9360_0(yy[62], yy[63], single[27], double[27], neg[27], pp_27_117); - r4bs r4bs_9360_128(yy[60], yy[61], single[28], double[28], neg[28], pp_28_117); - fullAdd_x FA_9360_256(int_1_117, int_0_117, negbar[26], pp_27_117, pp_28_117); - r4bs r4bs_9360_472(yy[58], yy[59], single[29], double[29], neg[29], pp_29_117); - r4bs r4bs_9360_600(yy[56], yy[57], single[30], double[30], neg[30], pp_30_117); - r4bs r4bs_9360_728(yy[54], yy[55], single[31], double[31], neg[31], pp_31_117); - fullAdd_x FA_9360_856(int_3_117, int_2_117, pp_29_117, pp_30_117, pp_31_117); - r4bs r4bs_9360_1072(yy[52], yy[53], single[32], double[32], neg[32], pp_32_117); - fullAdd_x FA_9360_1200(int_5_117, int_4_117, pp_32_117, int_1_116, int_3_116); - fullAdd_x FA_9360_1416(int_7_117, int_6_117, int_5_116, int_7_116, int_0_117); - fullAdd_x FA_9360_1632(int_9_117, int_8_117, int_2_117, int_4_117, int_9_116); - fullAdd_x FA_9360_1848(int_11_117, int_10_117, int_11_116, int_6_117, int_8_117); - assign Sum[117] = int_13_116; - assign Carry[117] = int_10_117; - - // Hardware for column 118 - - r4bs r4bs_9440_0(yy[63], gnd, single[27], double[27], neg[27], pp_27_118); - halfAdd HA_9440_128(int_1_118, int_0_118, 1'b1, pp_27_118); - r4bs r4bs_9440_208(yy[61], yy[62], single[28], double[28], neg[28], pp_28_118); - r4bs r4bs_9440_336(yy[59], yy[60], single[29], double[29], neg[29], pp_29_118); - r4bs r4bs_9440_464(yy[57], yy[58], single[30], double[30], neg[30], pp_30_118); - fullAdd_x FA_9440_592(int_3_118, int_2_118, pp_28_118, pp_29_118, pp_30_118); - r4bs r4bs_9440_808(yy[55], yy[56], single[31], double[31], neg[31], pp_31_118); - r4bs r4bs_9440_936(yy[53], yy[54], single[32], double[32], neg[32], pp_32_118); - fullAdd_x FA_9440_1064(int_5_118, int_4_118, pp_31_118, pp_32_118, int_1_117); - fullAdd_x FA_9440_1280(int_7_118, int_6_118, int_3_117, int_0_118, int_5_117); - fullAdd_x FA_9440_1496(int_9_118, int_8_118, int_2_118, int_4_118, int_7_117); - fullAdd_x FA_9440_1712(int_11_118, int_10_118, int_6_118, int_9_117, int_8_118); - assign Sum[118] = int_11_117; - assign Carry[118] = int_10_118; - - // Hardware for column 119 - - r4bs r4bs_9520_0(yy[62], yy[63], single[28], double[28], neg[28], pp_28_119); - r4bs r4bs_9520_128(yy[60], yy[61], single[29], double[29], neg[29], pp_29_119); - fullAdd_x FA_9520_256(int_1_119, int_0_119, negbar[27], pp_28_119, pp_29_119); - r4bs r4bs_9520_472(yy[58], yy[59], single[30], double[30], neg[30], pp_30_119); - r4bs r4bs_9520_600(yy[56], yy[57], single[31], double[31], neg[31], pp_31_119); - r4bs r4bs_9520_728(yy[54], yy[55], single[32], double[32], neg[32], pp_32_119); - fullAdd_x FA_9520_856(int_3_119, int_2_119, pp_30_119, pp_31_119, pp_32_119); - fullAdd_x FA_9520_1072(int_5_119, int_4_119, int_1_118, int_3_118, int_5_118); - fullAdd_x FA_9520_1288(int_7_119, int_6_119, int_0_119, int_2_119, int_7_118); - fullAdd_x FA_9520_1504(int_9_119, int_8_119, int_4_119, int_9_118, int_6_119); - assign Sum[119] = int_11_118; - assign Carry[119] = int_8_119; - - // Hardware for column 120 - - r4bs r4bs_9600_0(yy[63], gnd, single[28], double[28], neg[28], pp_28_120); - halfAdd HA_9600_128(int_1_120, int_0_120, 1'b1, pp_28_120); - r4bs r4bs_9600_208(yy[61], yy[62], single[29], double[29], neg[29], pp_29_120); - r4bs r4bs_9600_336(yy[59], yy[60], single[30], double[30], neg[30], pp_30_120); - r4bs r4bs_9600_464(yy[57], yy[58], single[31], double[31], neg[31], pp_31_120); - fullAdd_x FA_9600_592(int_3_120, int_2_120, pp_29_120, pp_30_120, pp_31_120); - r4bs r4bs_9600_808(yy[55], yy[56], single[32], double[32], neg[32], pp_32_120); - fullAdd_x FA_9600_936(int_5_120, int_4_120, pp_32_120, int_1_119, int_3_119); - fullAdd_x FA_9600_1152(int_7_120, int_6_120, int_0_120, int_2_120, int_5_119); - fullAdd_x FA_9600_1368(int_9_120, int_8_120, int_4_120, int_7_119, int_6_120); - assign Sum[120] = int_9_119; - assign Carry[120] = int_8_120; - - // Hardware for column 121 - - r4bs r4bs_9680_0(yy[62], yy[63], single[29], double[29], neg[29], pp_29_121); - r4bs r4bs_9680_128(yy[60], yy[61], single[30], double[30], neg[30], pp_30_121); - fullAdd_x FA_9680_256(int_1_121, int_0_121, negbar[28], pp_29_121, pp_30_121); - r4bs r4bs_9680_472(yy[58], yy[59], single[31], double[31], neg[31], pp_31_121); - r4bs r4bs_9680_600(yy[56], yy[57], single[32], double[32], neg[32], pp_32_121); - fullAdd_x FA_9680_728(int_3_121, int_2_121, pp_31_121, pp_32_121, int_1_120); - fullAdd_x FA_9680_944(int_5_121, int_4_121, int_3_120, int_5_120, int_0_121); - fullAdd_x FA_9680_1160(int_7_121, int_6_121, int_2_121, int_7_120, int_4_121); - assign Sum[121] = int_9_120; - assign Carry[121] = int_6_121; - - // Hardware for column 122 - - r4bs r4bs_9760_0(yy[63], gnd, single[29], double[29], neg[29], pp_29_122); - halfAdd HA_9760_128(int_1_122, int_0_122, 1'b1, pp_29_122); - r4bs r4bs_9760_208(yy[61], yy[62], single[30], double[30], neg[30], pp_30_122); - r4bs r4bs_9760_336(yy[59], yy[60], single[31], double[31], neg[31], pp_31_122); - r4bs r4bs_9760_464(yy[57], yy[58], single[32], double[32], neg[32], pp_32_122); - fullAdd_x FA_9760_592(int_3_122, int_2_122, pp_30_122, pp_31_122, pp_32_122); - fullAdd_x FA_9760_808(int_5_122, int_4_122, int_1_121, int_0_122, int_3_121); - fullAdd_x FA_9760_1024(int_7_122, int_6_122, int_2_122, int_5_121, int_4_122); - assign Sum[122] = int_7_121; - assign Carry[122] = int_6_122; - - // Hardware for column 123 - - r4bs r4bs_9840_0(yy[62], yy[63], single[30], double[30], neg[30], pp_30_123); - r4bs r4bs_9840_128(yy[60], yy[61], single[31], double[31], neg[31], pp_31_123); - fullAdd_x FA_9840_256(int_1_123, int_0_123, negbar[29], pp_30_123, pp_31_123); - r4bs r4bs_9840_472(yy[58], yy[59], single[32], double[32], neg[32], pp_32_123); - fullAdd_x FA_9840_600(int_3_123, int_2_123, pp_32_123, int_1_122, int_3_122); - fullAdd_x FA_9840_816(int_5_123, int_4_123, int_0_123, int_5_122, int_2_123); - assign Sum[123] = int_7_122; - assign Carry[123] = int_4_123; - - // Hardware for column 124 - - r4bs r4bs_9920_0(yy[63], gnd, single[30], double[30], neg[30], pp_30_124); - halfAdd HA_9920_128(int_1_124, int_0_124, 1'b1, pp_30_124); - r4bs r4bs_9920_208(yy[61], yy[62], single[31], double[31], neg[31], pp_31_124); - r4bs r4bs_9920_336(yy[59], yy[60], single[32], double[32], neg[32], pp_32_124); - fullAdd_x FA_9920_464(int_3_124, int_2_124, pp_31_124, pp_32_124, int_1_123); - fullAdd_x FA_9920_680(int_5_124, int_4_124, int_0_124, int_3_123, int_2_124); - assign Sum[124] = int_5_123; - assign Carry[124] = int_4_124; - - // Hardware for column 125 - - r4bs r4bs_10000_0(yy[62], yy[63], single[31], double[31], neg[31], pp_31_125); - r4bs r4bs_10000_128(yy[60], yy[61], single[32], double[32], neg[32], pp_32_125); - fullAdd_x FA_10000_256(int_1_125, int_0_125, negbar[30], pp_31_125, pp_32_125); - fullAdd_x FA_10000_472(int_3_125, int_2_125, int_1_124, int_3_124, int_0_125); - assign Sum[125] = int_5_124; - assign Carry[125] = int_2_125; - - // Hardware for column 126 - - r4bs r4bs_10080_0(yy[63], gnd, single[31], double[31], neg[31], pp_31_126); - halfAdd HA_10080_128(int_1_126, int_0_126, 1'b1, pp_31_126); - r4bs r4bs_10080_208(yy[61], yy[62], single[32], double[32], neg[32], pp_32_126); - fullAdd_x FA_10080_336(int_3_126, int_2_126, pp_32_126, int_1_125, int_0_126); - assign Sum[126] = int_3_125; - assign Carry[126] = int_2_126; - - // Hardware for column 127 - - r4bs r4bs_10160_0(yy[62], yy[63], single[32], double[32], neg[32], pp_32_127); - xor3 xor_10160_128(negbar[31], pp_32_127, int_1_126, int_0_127); - assign Sum[127] = int_3_126; - assign Carry[127] = int_0_127; - -endmodule // multiplier - -// Extra Modules - -module aaoi(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = !(in1&in2) & !(in3&in4); - -endmodule // aaoi - - -module halfAdd(cout,s,a,b); - - output cout; - output s; - input a; - input b; - - and2 carryComp0_0(cout,a,b); - xor2 sumComp_0_40(a,b,s); - -endmodule // halfAdd - - -// booth_encoder_r4 takes in X[2:0], which corresponds to X_(2n-1) to X_(2n+1) -// it outputs control signals to a Booth selector that cause the selector to -// send out the correct partial product - -module r4bs(y1,y0,sing,doub,neg,pp); - - input y1; - input y0; - input sing; - input doub; - input neg; - output pp; - - wire aaoiRes; - - aaoi usppgen_0_0(aaoiRes,doub,y1,sing,y0); - xnor2 ppinverter_0_40(aaoiRes,neg,pp); - -endmodule // r4bs - - -module r4be(x0,x1,x2,sing,doub,neg); - - input x0; - input x1; - input x2; - output sing; - output doub; - output neg; - - wire singRes; - wire doubRes; - - wire x0b; - wire x1b; - wire x2b; - - wire nandaRes; - wire nandbRes; - - assign neg = x2; - assign sing = x0^x1; - assign x0b = ~x0; - assign x1b = ~x1; - assign x2b = ~x2; - - // Nand structure = see Bewick - assign nandaRes = ~(x0 & x1 & x2b); - assign nandbRes = ~(x0b & x1b & x2); - assign doub = ~(nandaRes & nandbRes); - -endmodule // r4be - - -// Use maj and two xor2's, with cin being late -module fullAdd_xc(cout, s, a, b, cin); - - output cout; - output s; - input a; - input b; - input cin; - - wire xorRes; - - xor2 XOR1_0_0(a,b,xorRes); - xor2 XOR2_0_56(xorRes,cin,s); - maj MAJ_0_112(cout,a,b,cin); - -endmodule // fullAdd_xc - - -module maj(y, a, b, c); - - output y; - input a; - input b; - input c; - - wire min; - - min mincomp_0_0(min,a,b,c); - inverter outinv_0_32(y,min); - -endmodule // maj - -// 4:2 Weinberger compressor -module fourtwo_x(t, S, C, X, Y, Z, W, t_1); - - output t;//fast cout - output S; - output C;//slow cout - - input X;//two xor delays to s - input Y;//three xor delays to s - input Z;//three xor delays to s - input W;//two xor delays to s - input t_1;//two xor delayts to s - - wire intermediate; - - fullAdd_xc firstCSA_0_0(t,intermediate,Y,Z,X); - fullAdd_xc secondCSA_0_160(C,S,W,t_1,intermediate); - -endmodule // fourtwo_x - -module inverter(egress, in); - - output egress; - input in; - - assign egress = ~in; - -endmodule // inverter - -module buffer(egress, in); - - output egress; - input in; - - assign egress = in; - -endmodule // buffer - -module subxor(egress,in1,in1_b,in2,in2_b); - - output egress; - input in1; - input in1_b; - input in2; - input in2_b; - - assign egress = (~(in2_b&in1_b)) & (~(in2&in1)); - -endmodule // subxor - -module xnor2(a,b,y); - input a; - input b; - output y; - - assign y = ~(a^b); - -endmodule // xnor2 - -module xor2(a,b,y); - input a; - input b; - output y; - - wire a_b; - wire b_b; - - - inverter inva_0_0(a_b,a); - inverter invb_0_16(b_b,b); - - subxor sub_0_32(y,a,a_b,b,b_b); - -endmodule // xor2 - -module xor3(a,b,c,y); - - input a; - input b; - input c; - output y; - - assign y = a^b^c; - -endmodule // xor3 - -module xor3c(egress,in1,in2,in3,in4,in5,in6); - - output egress; - input in1; - input in2; - input in3; - input in4; - input in5; - input in6; - - assign egress = (~in6&~in4&~in2) | (~in5&~in3&~in2) | (~in5&~in4&~in1) | - (~in6&~in3&~in1); - -endmodule // xor3c - -module fullAdd_x(cout,sum,a,b,c); - - output cout; - output sum; - input a; - input b; - input c; - - wire ab; - wire bb; - wire cb; - - inverter ainv_0_0(ab,a); - inverter binv_0_16(bb,b); - inverter cinv_0_32(cb,c); - - xor3c sumcomp_0_48(sum,a,ab,b,bb,c,cb); - maj majcomp_0_144(cout,a,b,c); - -endmodule // fullAdd_x - -module nand2(egress,in1,in2); - - output egress; - input in1; - input in2; - - assign egress = ~(in1&in2); - -endmodule // nand2 - -module nand3(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - wire a,b; - - assign egress = ~(in1&in2&in3); - -endmodule // nand3 - -module and3(y,a,b,c); - - output y; - input a; - input b; - input c; - - assign y = a&b&c; - -endmodule // and3 - -module and2(y,a,b); - - output y; - input a; - input b; - - assign y = a&b; - -endmodule // and2 - -module nor2(egress,in1,in2); - - output egress; - input in1; - input in2; - - assign egress = ~(in1|in2); - -endmodule // nor2 - -module or2(y,a,b); - - output y; - input a; - input b; - - assign y = a|b; - -endmodule // or2 - -module nor3(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in1|in2|in3); - -endmodule // nor3 - -module nand5(egress,in1,in2,in3,in4,in5); - - output egress; - input in1; - input in2; - input in3; - input in4; - input in5; - - assign egress = ~(in1&in2&in3&in4&in5); - -endmodule // nand5 - -module and5(y,a,b,c,d,e); - - output y; - input a; - input b; - input c; - input d; - input e; - - assign y = a&b&c&d&e; - -endmodule // and5 - -module nand4(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = ~(in1&in2&in3&in4); - -endmodule // nand4 - -module and4(y,a,b,c,d); - - output y; - input a; - input b; - input c; - input d; - - assign y = a&b&c&d; - -endmodule // and4 - -module oai(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in3 & (in1|in2)); - -endmodule // oai - -module aoi(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~(in3 | (in1&in2)); - -endmodule // aoi - -module min(egress,in1,in2,in3); - - output egress; - input in1; - input in2; - input in3; - - assign egress = ~in3&~in2 | ~in3&~in1 | ~in2&~in1; - -endmodule // min - -module sum_b(egress,in1,in2,in3,in4); - - output egress; - input in1; - input in2; - input in3; - input in4; - - assign egress = ~in4&(~(in3&in2&in1)) | ~(in3|in2|in1); - -endmodule // sum_b - -module fullAdd_i(cout_b,sum_b,a,b,c); - - output cout_b; - output sum_b; - input a; - input b; - input c; - - min carry_0_0(cout_b,a,b,c); - sum_b sum_0_32(sum_b,a,b,c,cout_b); - -endmodule // fullAdd_i - -module fullAdd(cout,s,a,b,c); - - output cout; - output s; - input a; - input b; - input c; - wire cout_b; - wire sum_b; - - fullAdd_i adder_0_0(cout_b,sum_b,a,b,c); - inverter couti_0_96(cout,cout_b); - inverter sumi_0_112(s,sum_b); - -endmodule // fullAdd - -module blackCell(g_i_j, p_i_j, g_i_k, p_i_k, g_kneg1_j, p_kneg1_j); - - output g_i_j; - output p_i_j; - input g_i_k; - input p_i_k; - input g_kneg1_j; - input p_kneg1_j; - - grayCell grayCell_0_0(g_i_j, g_i_k, p_i_k, g_kneg1_j); - and2 and_0_48(p_i_j, p_i_k, p_kneg1_j); - -endmodule // blackCell - -module grayCell(g_i_j, g_i_k, p_i_k, g_kneg1_j); - - output g_i_j; - input g_i_k; - input p_i_k; - input g_kneg1_j; - - wire intermediate; - - aoi andorinv_0_0(intermediate,p_i_k,g_kneg1_j,g_i_k); - inverter inv_0_32(g_i_j,intermediate); - -endmodule // grayCell - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/rounder_div.sv b/wally-pipelined/src/fpu/fpdivsqrt/rounder_div.sv deleted file mode 100755 index de0076cb6..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/rounder_div.sv +++ /dev/null @@ -1,187 +0,0 @@ -// -// The rounder takes as inputs a 64-bit value to be rounded, A, the -// exponent of the value to be rounded, the sign of the final result, Sign, -// the precision of the results, P, and the two-bit rounding mode, rm. -// It produces a rounded 52-bit result, Z, the exponent of the rounded -// result, Z_exp, and a flag that indicates if the result was rounded, -// Inexact. The rounding mode has the following values. -// rm Modee -// 00 round-to-nearest-even -// 01 round-toward-zero -// 10 round-toward-plus infinity -// 11 round-toward-minus infinity -// - -module rounder_div (Result, DenormIO, Flags, rm, P, OvEn, - UnEn, exp_diff, sel_inv, Invalid, DenormIn, - SignR, q1, qm1, qp1, q0, qm0, qp0, regr_out); - - input [1:0] rm; - input P; - input OvEn; - input UnEn; - input [12:0] exp_diff; - input [2:0] sel_inv; - input Invalid; - input DenormIn; - input SignR; - - input logic [63:0] q1; - input logic [63:0] qm1; - input logic [63:0] qp1; - input logic [63:0] q0; - input logic [63:0] qm0; - input logic [63:0] qp0; - input logic [127:0] regr_out; - - output logic [63:0] Result; - output logic DenormIO; - output logic [4:0] Flags; - - supply1 vdd; - supply0 vss; - - logic Rsign; - logic [10:0] Rexp; - logic [12:0] Texp; - logic [51:0] Rmant; - logic [63:0] Tmant; - logic [51:0] Smant; - logic Rzero; - logic Gdp, Gsp, G; - logic UnFlow_SP, UnFlow_DP, UnderFlow; - logic OvFlow_SP, OvFlow_DP, OverFlow; - logic Inexact; - logic Round_zero; - logic Infinite; - logic VeryLarge; - logic Largest; - logic Div0; - logic Adj_exp; - logic Valid; - logic NaN; - logic Texp_l7z; - logic Texp_l7o; - logic OvCon; - logic [1:0] mux_mant; - logic sign_rem; - logic [63:0] q, qm, qp; - logic exp_ovf, exp_ovfSP, exp_ovfDP; - - // Remainder = 0? - assign zero_rem = ~(|regr_out); - // Remainder Sign - assign sign_rem = ~regr_out[127]; - // choose correct Guard bit [1,2) or [0,1) - assign Gdp = q1[63] ? q1[10] : q0[10]; - assign Gsp = q1[63] ? q1[39] : q0[39]; - assign G = P ? Gsp : Gdp; - // Selection of Rounding (from logic/switching) - assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) | - (!rm[1]&!rm[0]&G&!sign_rem) | - (SignR&rm[1]&rm[0]&!zero_rem&!sign_rem) | - (!SignR&rm[1]&!rm[0]&!zero_rem&!sign_rem); - assign mux_mant[0] = (!SignR&rm[0]&!G&!zero_rem&sign_rem) | - (!rm[1]&rm[0]&!G&!zero_rem&sign_rem) | - (SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem); - - // Which Q? - mux2 #(64) mx1 (q0, q1, q1[63], q); - mux2 #(64) mx2 (qm0, qm1, q1[63], qm); - mux2 #(64) mx3 (qp0, qp1, q1[63], qp); - // Choose Q, Q+1, Q-1 - mux3 #(64) mx4 (q, qm, qp, mux_mant, Tmant); - assign Smant = Tmant[62:11]; - // Compute the value of the exponent - // exponent is modified if we choose: - // 1.) we choose any qm0, qp0, q0 (since we shift mant) - // 2.) we choose qp and we overflow (for RU) - assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})}; - assign Texp = exp_diff - {{13{vss}}, ~q1[63]} + {{13{vss}}, mux_mant[1]&qp1[63]&~exp_ovf}; - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = (~Texp[12]&Texp[11]) | (Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o); - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11]/Texp[10] is one) or - // Texp[10] to Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = (Texp[12]&Texp[11]) | ~Texp[11]&~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = ~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z); - - // Set the overflow and underflow flags. They should not be set if - // the input was infinite or NaN or the output of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]); - assign NaN = ~sel_inv[1]& sel_inv[0]; - assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid; - assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid; - assign Div0 = sel_inv[2]&sel_inv[1]&~sel_inv[0]; - - // The DenormIO is set if underflow has occurred or if their was a - // denormalized input. - assign DenormIO = DenormIn | UnderFlow; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (G|~zero_rem|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {Inexact, UnderFlow, OverFlow, Div0, Invalid}; - - // Determine sign - assign Rzero = UnderFlow | (~sel_inv[2]&sel_inv[1]&sel_inv[0]); - assign Rsign = SignR; - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~SignR&rm[0] | SignR&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | sel_inv[1]; - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = {51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}}); - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - assign OvCon = OverFlow & OvEn; - assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{vss}}} - : {Rsign, Rexp, Rmant}; - -endmodule // rounder - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/run_results.sh b/wally-pipelined/src/fpu/fpdivsqrt/run_results.sh deleted file mode 100755 index bfd06259b..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/run_results.sh +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh -echo 'f64 DIV RNE' > run_results.txt -cat f64_div_rne.out | grep '_0$' >> run_results.txt -echo 'f64 DIV RD' >> run_results.txt -cat f64_div_rd.out | grep '_0$' >> run_results.txt -echo 'f64 DIV RU' >> run_results.txt -cat f64_div_ru.out | grep '_0$' >> run_results.txt -echo 'f64 DIV RZ' >> run_results.txt -cat f64_div_rz.out | grep '_0$' >> run_results.txt - -echo 'f32 DIV RNE' >> run_results.txt -cat f32_div_rne.out | grep '_0$' >> run_results.txt -echo 'f32 DIV RD' >> run_results.txt -cat f32_div_rd.out | grep '_0$' >> run_results.txt -echo 'f32 DIV RU' >> run_results.txt -cat f32_div_ru.out | grep '_0$' >> run_results.txt -echo 'f32 DIV RZ' >> run_results.txt -cat f32_div_rz.out | grep '_0$' >> run_results.txt - -echo 'f64 SQRT RNE' >> run_results.txt -cat f64_sqrt_rne.out | grep '_0$' >> run_results.txt -echo 'f64 SQRT RD' >> run_results.txt -cat f64_sqrt_rd.out | grep '_0$' >> run_results.txt -echo 'f64 SQRT RU' >> run_results.txt -cat f64_sqrt_ru.out | grep '_0$' >> run_results.txt -echo 'f64 SQRT RZ' >> run_results.txt -cat f64_sqrt_rz.out | grep '_0$' >> run_results.txt - -echo 'f32 SQRT RNE' >> run_results.txt -cat f32_sqrt_rne.out | grep '_0$' >> run_results.txt -echo 'f32 SQRT RD' >> run_results.txt -cat f32_sqrt_rd.out | grep '_0$' >> run_results.txt -echo 'f32 SQRT RU' >> run_results.txt -cat f32_sqrt_ru.out | grep '_0$' >> run_results.txt -echo 'f32 SQRT RZ' >> run_results.txt -cat f32_sqrt_rz.out | grep '_0$' >> run_results.txt diff --git a/wally-pipelined/src/fpu/fpdivsqrt/run_results.txt b/wally-pipelined/src/fpu/fpdivsqrt/run_results.txt deleted file mode 100755 index e2ffa9963..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/run_results.txt +++ /dev/null @@ -1,940 +0,0 @@ -f64 DIV RNE -0010000000000000_3fffffffffffffff_0000000000000000_11000_1 | 0008000000000000_0 -0010000000000000_4000000000000000_0000000000000000_11000_1 | 0008000000000000_0 -0010000000000000_4000000000000001_0000000000000000_11100_1 | 0008000000000000_0 -0010000000000000_400fffffffffffff_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000000_400ffffffffffffe_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000000_4010000000000000_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000000_4010000000000001_0000000000000000_11000_1 | 0004000000000000_0 -0010000000000000_401fffffffffffff_0000000000000000_11000_1 | 0002000000000000_0 -0010000000000000_401ffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0 -0010000000000000_bfffffffffffffff_8000000000000000_11000_1 | 8008000000000000_0 -0010000000000000_c000000000000000_8000000000000000_11000_1 | 8008000000000000_0 -0010000000000000_c000000000000001_8000000000000000_11100_1 | 8008000000000000_0 -0010000000000000_c00fffffffffffff_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000000_c00ffffffffffffe_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000000_c010000000000000_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000000_c010000000000001_8000000000000000_11000_1 | 8004000000000000_0 -0010000000000000_c01fffffffffffff_8000000000000000_11000_1 | 8002000000000000_0 -0010000000000000_c01ffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0 -0010000000000001_4000000000000000_0000000000000000_11000_1 | 0008000000000000_0 -0010000000000001_4000000000000001_0000000000000000_11000_1 | 0008000000000000_0 -0010000000000001_400fffffffffffff_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000001_4010000000000000_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000001_4010000000000001_0000000000000000_11100_1 | 0004000000000000_0 -0010000000000001_401fffffffffffff_0000000000000000_11000_1 | 0002000000000000_0 -0010000000000001_401ffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0 -0010000000000001_c000000000000000_8000000000000000_11000_1 | 8008000000000000_0 -0010000000000001_c000000000000001_8000000000000000_11000_1 | 8008000000000000_0 -0010000000000001_c00fffffffffffff_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000001_c010000000000000_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000001_c010000000000001_8000000000000000_11100_1 | 8004000000000000_0 -0010000000000001_c01fffffffffffff_8000000000000000_11000_1 | 8002000000000000_0 -0010000000000001_c01ffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0 -001fffffffffffff_4000000000000000_0000000000000000_11000_1 | 0010000000000000_0 -001fffffffffffff_400fffffffffffff_0000000000000000_11000_1 | 0008000000000000_0 -001fffffffffffff_400ffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0 -001fffffffffffff_4010000000000000_0000000000000000_11100_1 | 0008000000000000_0 -001fffffffffffff_401fffffffffffff_0000000000000000_11100_1 | 0004000000000000_0 -001fffffffffffff_401ffffffffffffe_0000000000000000_11100_1 | 0004000000000000_0 -001fffffffffffff_c000000000000000_8000000000000000_11000_1 | 8010000000000000_0 -001fffffffffffff_c00fffffffffffff_8000000000000000_11000_1 | 8008000000000000_0 -001fffffffffffff_c00ffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0 -001fffffffffffff_c010000000000000_8000000000000000_11100_1 | 8008000000000000_0 -001fffffffffffff_c01fffffffffffff_8000000000000000_11100_1 | 8004000000000000_0 -001fffffffffffff_c01ffffffffffffe_8000000000000000_11100_1 | 8004000000000000_0 -001ffffffffffffe_400fffffffffffff_0000000000000000_11100_1 | 0008000000000000_0 -001ffffffffffffe_400ffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0 -001ffffffffffffe_4010000000000000_0000000000000000_11100_1 | 0008000000000000_0 -001ffffffffffffe_401fffffffffffff_0000000000000000_11000_1 | 0004000000000000_0 -001ffffffffffffe_401ffffffffffffe_0000000000000000_11100_1 | 0004000000000000_0 -001ffffffffffffe_c00fffffffffffff_8000000000000000_11100_1 | 8008000000000000_0 -001ffffffffffffe_c00ffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0 -001ffffffffffffe_c010000000000000_8000000000000000_11100_1 | 8008000000000000_0 -001ffffffffffffe_c01fffffffffffff_8000000000000000_11000_1 | 8004000000000000_0 -001ffffffffffffe_c01ffffffffffffe_8000000000000000_11100_1 | 8004000000000000_0 -3fd0000000000000_7fe0000000000000_0000000000000000_11000_1 | 0002000000000000_0 -3fd0000000000000_7fe0000000000001_0000000000000000_11000_1 | 0002000000000000_0 -3fd0000000000000_7fefffffffffffff_0000000000000000_11000_1 | 0001000000000000_0 -3fd0000000000000_7feffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0 -3fd0000000000000_ffe0000000000000_8000000000000000_11000_1 | 8002000000000000_0 -3fd0000000000000_ffe0000000000001_8000000000000000_11000_1 | 8002000000000000_0 -3fd0000000000000_ffefffffffffffff_8000000000000000_11000_1 | 8001000000000000_0 -3fd0000000000000_ffeffffffffffffe_8000000000000000_11000_1 | 8001000000000000_0 -3fd0000000000001_7fe0000000000000_0000000000000000_11000_1 | 0002000000000000_0 -3fd0000000000001_7fe0000000000001_0000000000000000_11000_1 | 0002000000000000_0 -3fd0000000000001_7fefffffffffffff_0000000000000000_11000_1 | 0001000000000000_0 -3fd0000000000001_7feffffffffffffe_0000000000000000_11000_1 | 0001000000000000_0 -3fd0000000000001_ffe0000000000000_8000000000000000_11000_1 | 8002000000000000_0 -3fd0000000000001_ffe0000000000001_8000000000000000_11000_1 | 8002000000000000_0 -3fd0000000000001_ffefffffffffffff_8000000000000000_11000_1 | 8001000000000000_0 -3fd0000000000001_ffeffffffffffffe_8000000000000000_11000_1 | 8001000000000000_0 -3fdfffffffffffff_7fe0000000000000_0000000000000000_11000_1 | 0004000000000000_0 -3fdfffffffffffff_7fe0000000000001_0000000000000000_11000_1 | 0004000000000000_0 -3fdfffffffffffff_7fefffffffffffff_0000000000000000_11000_1 | 0002000000000000_0 -3fdfffffffffffff_7feffffffffffffe_0000000000000000_11000_1 | 0002000000000000_0 -3fdfffffffffffff_ffe0000000000000_8000000000000000_11000_1 | 8004000000000000_0 -3fdfffffffffffff_ffe0000000000001_8000000000000000_11000_1 | 8004000000000000_0 -3fdfffffffffffff_ffefffffffffffff_8000000000000000_11000_1 | 8002000000000000_0 -3fdfffffffffffff_ffeffffffffffffe_8000000000000000_11000_1 | 8002000000000000_0 -3fdffffffffffffe_7fe0000000000000_0000000000000000_11000_1 | 0004000000000000_0 -3fdffffffffffffe_7fe0000000000001_0000000000000000_11000_1 | 0004000000000000_0 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-bfeffffffffffffe_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0 -bfeffffffffffffe_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0 -bff0000000000000_7fe0000000000000_8000000000000000_11000_1 | 8008000000000000_0 -bff0000000000000_7fefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0 -bff0000000000000_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0 -bff0000000000000_ffe0000000000000_0000000000000000_11000_1 | 0008000000000000_0 -bff0000000000000_ffefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0 -bff0000000000000_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0 -bff0000000000001_7fe0000000000000_8000000000000000_11000_1 | 8008000000000000_0 -bff0000000000001_7fe0000000000001_8000000000000000_11000_1 | 8008000000000000_0 -bff0000000000001_7fefffffffffffff_800fffffffffffff_11100_1 | 8004000000000000_0 -bff0000000000001_7feffffffffffffe_800fffffffffffff_11100_1 | 8004000000000000_0 -bff0000000000001_ffe0000000000000_0000000000000000_11000_1 | 0008000000000000_0 -bff0000000000001_ffe0000000000001_0000000000000000_11000_1 | 0008000000000000_0 -bff0000000000001_ffefffffffffffff_000fffffffffffff_11100_1 | 0004000000000000_0 -bff0000000000001_ffeffffffffffffe_000fffffffffffff_11100_1 | 0004000000000000_0 -bfffffffffffffff_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0 -bfffffffffffffff_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0 -bfffffffffffffff_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0 -bfffffffffffffff_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0 -bffffffffffffffe_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0 -bffffffffffffffe_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0 -c000000000000000_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0 -c000000000000000_7feffffffffffffe_8000000000000000_11000_1 | 8008000000000000_0 -c000000000000000_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0 -c000000000000000_ffeffffffffffffe_0000000000000000_11000_1 | 0008000000000000_0 -c000000000000001_7fefffffffffffff_8000000000000000_11000_1 | 8008000000000000_0 -c000000000000001_ffefffffffffffff_0000000000000000_11000_1 | 0008000000000000_0 -f32 DIV RNE -f32 DIV RD -f32 DIV RU -f32 DIV RZ -f64 SQRT RNE -f64 SQRT RD -f64 SQRT RU -f64 SQRT RZ -f32 SQRT RNE -f32 SQRT RD -f32 SQRT RU -f32 SQRT RZ diff --git a/wally-pipelined/src/fpu/fpdivsqrt/runme.csh b/wally-pipelined/src/fpu/fpdivsqrt/runme.csh deleted file mode 100755 index 970d4b4b4..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/runme.csh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh -vsim -do fpdiv.do -c -tail fpdiv.out diff --git a/wally-pipelined/src/fpu/fpdivsqrt/runme_f32div.csh b/wally-pipelined/src/fpu/fpdivsqrt/runme_f32div.csh deleted file mode 100755 index bba6fb532..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/runme_f32div.csh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh -vsim -do f32_div_rne.do -c -vsim -do f32_div_rz.do -c -vsim -do f32_div_rd.do -c -vsim -do f32_div_ru.do -c diff --git a/wally-pipelined/src/fpu/fpdivsqrt/runme_f32sqrt.csh b/wally-pipelined/src/fpu/fpdivsqrt/runme_f32sqrt.csh deleted file mode 100755 index aeee76981..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/runme_f32sqrt.csh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh -vsim -do f32_sqrt_rne.do -c -vsim -do f32_sqrt_rz.do -c -vsim -do f32_sqrt_rd.do -c -vsim -do f32_sqrt_ru.do -c diff --git a/wally-pipelined/src/fpu/fpdivsqrt/runme_f64div.csh b/wally-pipelined/src/fpu/fpdivsqrt/runme_f64div.csh deleted file mode 100755 index ad18b47df..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/runme_f64div.csh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh -vsim -do f64_div_rne.do -c -vsim -do f64_div_rz.do -c -vsim -do f64_div_rd.do -c -vsim -do f64_div_ru.do -c diff --git a/wally-pipelined/src/fpu/fpdivsqrt/runme_f64sqrt.csh b/wally-pipelined/src/fpu/fpdivsqrt/runme_f64sqrt.csh deleted file mode 100755 index 203c3adba..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/runme_f64sqrt.csh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh -vsim -do f64_sqrt_rne.do -c -vsim -do f64_sqrt_rz.do -c -vsim -do f64_sqrt_rd.do -c -vsim -do f64_sqrt_ru.do -c diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm.sv deleted file mode 100755 index 7a4fefc03..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm.sv +++ /dev/null @@ -1,33 +0,0 @@ -module sbtm (input logic [11:0] a, output logic [10:0] ia_out); - - // bit partitions - logic [3:0] x0; - logic [2:0] x1; - logic [3:0] x2; - logic [2:0] x2_1cmp; - // mem outputs - logic [12:0] y0; - logic [4:0] y1; - // input to CPA - logic [14:0] op1; - logic [14:0] op2; - logic [14:0] p; - - assign x0 = a[10:7]; - assign x1 = a[6:4]; - assign x2 = a[3:0]; - - sbtm_a0 mem1 ({x0, x1}, y0); - // 1s cmp per sbtm/stam - assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; - sbtm_a1 mem2 ({x0, x2_1cmp}, y1); - assign op1 = {1'b0, y0, 1'b0}; - // 1s cmp per sbtm/stam - assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} : - {1'b0, 8'b0, y1, 1'b1}; - // CPA - adder #(15) cp1 (op1, op2, 1'b0, p, cout); - //assign ia_out = {p[14:4], {53{1'b0}}}; - assign ia_out = p[14:4]; - -endmodule // sbtm diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm3.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm3.sv deleted file mode 100755 index f333d2851..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm3.sv +++ /dev/null @@ -1,39 +0,0 @@ -module sbtm2 (input logic [11:0] a, output logic [10:0] y); - - // bit partitions - logic [4:0] x0; - logic [2:0] x1; - logic [3:0] x2; - logic [2:0] x2_1cmp; - // mem outputs - logic [13:0] y0; - logic [5:0] y1; - // input to CPA - logic [14:0] op1; - logic [14:0] op2; - logic [14:0] p; - - assign x0 = a[11:7]; - assign x1 = a[6:4]; - assign x2 = a[3:0]; - - sbtm_a2 mem1 ({x0, x1}, y0); - assign op1 = {y0, 1'b0}; - - // 1s cmp per sbtm/stam - assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; - sbtm_a3 mem2 ({x0, x2_1cmp}, y1); - // 1s cmp per sbtm/stam - assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} : - {8'b0, y1, 1'b1}; - - // CPA - adder #(15) cp1 (op1, op2, 1'b0, p, cout); - assign y = p[14:4]; - -endmodule // sbtm2 - - - - - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a0.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a0.sv deleted file mode 100755 index 381e4a820..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a0.sv +++ /dev/null @@ -1,140 +0,0 @@ -module sbtm_a0 (input logic [6:0] a, - output logic [12:0] y); - always_comb - case(a) - 7'b0000000: y = 13'b1111111100010; - 7'b0000001: y = 13'b1111110100011; - 7'b0000010: y = 13'b1111101100101; - 7'b0000011: y = 13'b1111100101000; - 7'b0000100: y = 13'b1111011101100; - 7'b0000101: y = 13'b1111010110000; - 7'b0000110: y = 13'b1111001110110; - 7'b0000111: y = 13'b1111000111100; - 7'b0001000: y = 13'b1111000000100; - 7'b0001001: y = 13'b1110111001100; - 7'b0001010: y = 13'b1110110010101; - 7'b0001011: y = 13'b1110101011110; - 7'b0001100: y = 13'b1110100101001; - 7'b0001101: y = 13'b1110011110100; - 7'b0001110: y = 13'b1110011000000; - 7'b0001111: y = 13'b1110010001101; - 7'b0010000: y = 13'b1110001011010; - 7'b0010001: y = 13'b1110000101000; - 7'b0010010: y = 13'b1101111110111; - 7'b0010011: y = 13'b1101111000110; - 7'b0010100: y = 13'b1101110010111; - 7'b0010101: y = 13'b1101101100111; - 7'b0010110: y = 13'b1101100111001; - 7'b0010111: y = 13'b1101100001011; - 7'b0011000: y = 13'b1101011011101; - 7'b0011001: y = 13'b1101010110001; - 7'b0011010: y = 13'b1101010000100; - 7'b0011011: y = 13'b1101001011001; - 7'b0011100: y = 13'b1101000101110; - 7'b0011101: y = 13'b1101000000011; - 7'b0011110: y = 13'b1100111011001; - 7'b0011111: y = 13'b1100110101111; - 7'b0100000: y = 13'b1100110000110; - 7'b0100001: y = 13'b1100101011110; - 7'b0100010: y = 13'b1100100110110; - 7'b0100011: y = 13'b1100100001111; - 7'b0100100: y = 13'b1100011101000; - 7'b0100101: y = 13'b1100011000001; - 7'b0100110: y = 13'b1100010011011; - 7'b0100111: y = 13'b1100001110101; - 7'b0101000: y = 13'b1100001010000; - 7'b0101001: y = 13'b1100000101011; - 7'b0101010: y = 13'b1100000000111; - 7'b0101011: y = 13'b1011111100011; - 7'b0101100: y = 13'b1011111000000; - 7'b0101101: y = 13'b1011110011101; - 7'b0101110: y = 13'b1011101111010; - 7'b0101111: y = 13'b1011101011000; - 7'b0110000: y = 13'b1011100110110; - 7'b0110001: y = 13'b1011100010101; - 7'b0110010: y = 13'b1011011110011; - 7'b0110011: y = 13'b1011011010011; - 7'b0110100: y = 13'b1011010110010; - 7'b0110101: y = 13'b1011010010010; - 7'b0110110: y = 13'b1011001110011; - 7'b0110111: y = 13'b1011001010011; - 7'b0111000: y = 13'b1011000110100; - 7'b0111001: y = 13'b1011000010110; - 7'b0111010: y = 13'b1010111110111; - 7'b0111011: y = 13'b1010111011001; - 7'b0111100: y = 13'b1010110111100; - 7'b0111101: y = 13'b1010110011110; - 7'b0111110: y = 13'b1010110000001; - 7'b0111111: y = 13'b1010101100100; - 7'b1000000: y = 13'b1010101001000; - 7'b1000001: y = 13'b1010100101100; - 7'b1000010: y = 13'b1010100010000; - 7'b1000011: y = 13'b1010011110100; - 7'b1000100: y = 13'b1010011011001; - 7'b1000101: y = 13'b1010010111110; - 7'b1000110: y = 13'b1010010100011; - 7'b1000111: y = 13'b1010010001001; - 7'b1001000: y = 13'b1010001101111; - 7'b1001001: y = 13'b1010001010101; - 7'b1001010: y = 13'b1010000111011; - 7'b1001011: y = 13'b1010000100001; - 7'b1001100: y = 13'b1010000001000; - 7'b1001101: y = 13'b1001111101111; - 7'b1001110: y = 13'b1001111010111; - 7'b1001111: y = 13'b1001110111110; - 7'b1010000: y = 13'b1001110100110; - 7'b1010001: y = 13'b1001110001110; - 7'b1010010: y = 13'b1001101110110; - 7'b1010011: y = 13'b1001101011111; - 7'b1010100: y = 13'b1001101000111; - 7'b1010101: y = 13'b1001100110000; - 7'b1010110: y = 13'b1001100011001; - 7'b1010111: y = 13'b1001100000010; - 7'b1011000: y = 13'b1001011101100; - 7'b1011001: y = 13'b1001011010110; - 7'b1011010: y = 13'b1001011000000; - 7'b1011011: y = 13'b1001010101010; - 7'b1011100: y = 13'b1001010010100; - 7'b1011101: y = 13'b1001001111111; - 7'b1011110: y = 13'b1001001101001; - 7'b1011111: y = 13'b1001001010100; - 7'b1100000: y = 13'b1001000111111; - 7'b1100001: y = 13'b1001000101011; - 7'b1100010: y = 13'b1001000010110; - 7'b1100011: y = 13'b1001000000010; - 7'b1100100: y = 13'b1000111101110; - 7'b1100101: y = 13'b1000111011010; - 7'b1100110: y = 13'b1000111000110; - 7'b1100111: y = 13'b1000110110010; - 7'b1101000: y = 13'b1000110011111; - 7'b1101001: y = 13'b1000110001011; - 7'b1101010: y = 13'b1000101111000; - 7'b1101011: y = 13'b1000101100101; - 7'b1101100: y = 13'b1000101010010; - 7'b1101101: y = 13'b1000101000000; - 7'b1101110: y = 13'b1000100101101; - 7'b1101111: y = 13'b1000100011011; - 7'b1110000: y = 13'b1000100001001; - 7'b1110001: y = 13'b1000011110110; - 7'b1110010: y = 13'b1000011100101; - 7'b1110011: y = 13'b1000011010011; - 7'b1110100: y = 13'b1000011000001; - 7'b1110101: y = 13'b1000010110000; - 7'b1110110: y = 13'b1000010011110; - 7'b1110111: y = 13'b1000010001101; - 7'b1111000: y = 13'b1000001111100; - 7'b1111001: y = 13'b1000001101011; - 7'b1111010: y = 13'b1000001011010; - 7'b1111011: y = 13'b1000001001010; - 7'b1111100: y = 13'b1000000111001; - 7'b1111101: y = 13'b1000000101001; - 7'b1111110: y = 13'b1000000011001; - 7'b1111111: y = 13'b1000000001001; - default: y = 13'bxxxxxxxxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - \ No newline at end of file diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a1.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a1.sv deleted file mode 100755 index df1e600a9..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a1.sv +++ /dev/null @@ -1,140 +0,0 @@ -module sbtm_a1 (input logic [6:0] a, - output logic [4:0] y); - always_comb - case(a) - 7'b0000000: y = 5'b11100; - 7'b0000001: y = 5'b11000; - 7'b0000010: y = 5'b10100; - 7'b0000011: y = 5'b10000; - 7'b0000100: y = 5'b01101; - 7'b0000101: y = 5'b01001; - 7'b0000110: y = 5'b00101; - 7'b0000111: y = 5'b00001; - 7'b0001000: y = 5'b11001; - 7'b0001001: y = 5'b10101; - 7'b0001010: y = 5'b10010; - 7'b0001011: y = 5'b01111; - 7'b0001100: y = 5'b01011; - 7'b0001101: y = 5'b01000; - 7'b0001110: y = 5'b00101; - 7'b0001111: y = 5'b00001; - 7'b0010000: y = 5'b10110; - 7'b0010001: y = 5'b10011; - 7'b0010010: y = 5'b10000; - 7'b0010011: y = 5'b01101; - 7'b0010100: y = 5'b01010; - 7'b0010101: y = 5'b00111; - 7'b0010110: y = 5'b00100; - 7'b0010111: y = 5'b00001; - 7'b0011000: y = 5'b10100; - 7'b0011001: y = 5'b10001; - 7'b0011010: y = 5'b01110; - 7'b0011011: y = 5'b01100; - 7'b0011100: y = 5'b01001; - 7'b0011101: y = 5'b00110; - 7'b0011110: y = 5'b00100; - 7'b0011111: y = 5'b00001; - 7'b0100000: y = 5'b10010; - 7'b0100001: y = 5'b01111; - 7'b0100010: y = 5'b01101; - 7'b0100011: y = 5'b01010; - 7'b0100100: y = 5'b01000; - 7'b0100101: y = 5'b00110; - 7'b0100110: y = 5'b00011; - 7'b0100111: y = 5'b00001; - 7'b0101000: y = 5'b10000; - 7'b0101001: y = 5'b01110; - 7'b0101010: y = 5'b01100; - 7'b0101011: y = 5'b01001; - 7'b0101100: y = 5'b00111; - 7'b0101101: y = 5'b00101; - 7'b0101110: y = 5'b00011; - 7'b0101111: y = 5'b00001; - 7'b0110000: y = 5'b01111; - 7'b0110001: y = 5'b01101; - 7'b0110010: y = 5'b01011; - 7'b0110011: y = 5'b01001; - 7'b0110100: y = 5'b00111; - 7'b0110101: y = 5'b00101; - 7'b0110110: y = 5'b00011; - 7'b0110111: y = 5'b00001; - 7'b0111000: y = 5'b01101; - 7'b0111001: y = 5'b01100; - 7'b0111010: y = 5'b01010; - 7'b0111011: y = 5'b01000; - 7'b0111100: y = 5'b00110; - 7'b0111101: y = 5'b00100; - 7'b0111110: y = 5'b00010; - 7'b0111111: y = 5'b00000; - 7'b1000000: y = 5'b01100; - 7'b1000001: y = 5'b01011; - 7'b1000010: y = 5'b01001; - 7'b1000011: y = 5'b00111; - 7'b1000100: y = 5'b00101; - 7'b1000101: y = 5'b00100; - 7'b1000110: y = 5'b00010; - 7'b1000111: y = 5'b00000; - 7'b1001000: y = 5'b01011; - 7'b1001001: y = 5'b01010; - 7'b1001010: y = 5'b01000; - 7'b1001011: y = 5'b00111; - 7'b1001100: y = 5'b00101; - 7'b1001101: y = 5'b00011; - 7'b1001110: y = 5'b00010; - 7'b1001111: y = 5'b00000; - 7'b1010000: y = 5'b01010; - 7'b1010001: y = 5'b01001; - 7'b1010010: y = 5'b01000; - 7'b1010011: y = 5'b00110; - 7'b1010100: y = 5'b00101; - 7'b1010101: y = 5'b00011; - 7'b1010110: y = 5'b00010; - 7'b1010111: y = 5'b00000; - 7'b1011000: y = 5'b01010; - 7'b1011001: y = 5'b01000; - 7'b1011010: y = 5'b00111; - 7'b1011011: y = 5'b00110; - 7'b1011100: y = 5'b00100; - 7'b1011101: y = 5'b00011; - 7'b1011110: y = 5'b00010; - 7'b1011111: y = 5'b00000; - 7'b1100000: y = 5'b01001; - 7'b1100001: y = 5'b01000; - 7'b1100010: y = 5'b00110; - 7'b1100011: y = 5'b00101; - 7'b1100100: y = 5'b00100; - 7'b1100101: y = 5'b00011; - 7'b1100110: y = 5'b00001; - 7'b1100111: y = 5'b00000; - 7'b1101000: y = 5'b01000; - 7'b1101001: y = 5'b00111; - 7'b1101010: y = 5'b00110; - 7'b1101011: y = 5'b00101; - 7'b1101100: y = 5'b00100; - 7'b1101101: y = 5'b00010; - 7'b1101110: y = 5'b00001; - 7'b1101111: y = 5'b00000; - 7'b1110000: y = 5'b01000; - 7'b1110001: y = 5'b00111; - 7'b1110010: y = 5'b00110; - 7'b1110011: y = 5'b00100; - 7'b1110100: y = 5'b00011; - 7'b1110101: y = 5'b00010; - 7'b1110110: y = 5'b00001; - 7'b1110111: y = 5'b00000; - 7'b1111000: y = 5'b00111; - 7'b1111001: y = 5'b00110; - 7'b1111010: y = 5'b00101; - 7'b1111011: y = 5'b00100; - 7'b1111100: y = 5'b00011; - 7'b1111101: y = 5'b00010; - 7'b1111110: y = 5'b00001; - 7'b1111111: y = 5'b00000; - default: y = 5'bxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - \ No newline at end of file diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a4.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a4.sv deleted file mode 100755 index 1553c80dd..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a4.sv +++ /dev/null @@ -1,204 +0,0 @@ -module sbtm_a2 (input logic [7:0] a, - output logic [13:0] y); - always_comb - case(a) - 8'b01000000: y = 14'b10110100010111; - 8'b01000001: y = 14'b10110010111111; - 8'b01000010: y = 14'b10110001101000; - 8'b01000011: y = 14'b10110000010011; - 8'b01000100: y = 14'b10101111000001; - 8'b01000101: y = 14'b10101101110000; - 8'b01000110: y = 14'b10101100100001; - 8'b01000111: y = 14'b10101011010011; - 8'b01001000: y = 14'b10101010000111; - 8'b01001001: y = 14'b10101000111101; - 8'b01001010: y = 14'b10100111110100; - 8'b01001011: y = 14'b10100110101101; - 8'b01001100: y = 14'b10100101100111; - 8'b01001101: y = 14'b10100100100010; - 8'b01001110: y = 14'b10100011011111; - 8'b01001111: y = 14'b10100010011101; - 8'b01010000: y = 14'b10100001011100; - 8'b01010001: y = 14'b10100000011100; - 8'b01010010: y = 14'b10011111011110; - 8'b01010011: y = 14'b10011110100001; - 8'b01010100: y = 14'b10011101100100; - 8'b01010101: y = 14'b10011100101001; - 8'b01010110: y = 14'b10011011101111; - 8'b01010111: y = 14'b10011010110110; - 8'b01011000: y = 14'b10011001111110; - 8'b01011001: y = 14'b10011001000110; - 8'b01011010: y = 14'b10011000010000; - 8'b01011011: y = 14'b10010111011011; - 8'b01011100: y = 14'b10010110100110; - 8'b01011101: y = 14'b10010101110011; - 8'b01011110: y = 14'b10010101000000; - 8'b01011111: y = 14'b10010100001110; - 8'b01100000: y = 14'b10010011011100; - 8'b01100001: y = 14'b10010010101100; - 8'b01100010: y = 14'b10010001111100; - 8'b01100011: y = 14'b10010001001101; - 8'b01100100: y = 14'b10010000011111; - 8'b01100101: y = 14'b10001111110001; - 8'b01100110: y = 14'b10001111000100; - 8'b01100111: y = 14'b10001110011000; - 8'b01101000: y = 14'b10001101101100; - 8'b01101001: y = 14'b10001101000001; - 8'b01101010: y = 14'b10001100010110; - 8'b01101011: y = 14'b10001011101100; - 8'b01101100: y = 14'b10001011000011; - 8'b01101101: y = 14'b10001010011010; - 8'b01101110: y = 14'b10001001110010; - 8'b01101111: y = 14'b10001001001010; - 8'b01110000: y = 14'b10001000100011; - 8'b01110001: y = 14'b10000111111101; - 8'b01110010: y = 14'b10000111010111; - 8'b01110011: y = 14'b10000110110001; - 8'b01110100: y = 14'b10000110001100; - 8'b01110101: y = 14'b10000101100111; - 8'b01110110: y = 14'b10000101000011; - 8'b01110111: y = 14'b10000100011111; - 8'b01111000: y = 14'b10000011111100; - 8'b01111001: y = 14'b10000011011001; - 8'b01111010: y = 14'b10000010110111; - 8'b01111011: y = 14'b10000010010101; - 8'b01111100: y = 14'b10000001110011; - 8'b01111101: y = 14'b10000001010010; - 8'b01111110: y = 14'b10000000110001; - 8'b01111111: y = 14'b10000000010001; - 8'b10000000: y = 14'b01111111110001; - 8'b10000001: y = 14'b01111111010001; - 8'b10000010: y = 14'b01111110110010; - 8'b10000011: y = 14'b01111110010011; - 8'b10000100: y = 14'b01111101110101; - 8'b10000101: y = 14'b01111101010110; - 8'b10000110: y = 14'b01111100111001; - 8'b10000111: y = 14'b01111100011011; - 8'b10001000: y = 14'b01111011111110; - 8'b10001001: y = 14'b01111011100001; - 8'b10001010: y = 14'b01111011000100; - 8'b10001011: y = 14'b01111010101000; - 8'b10001100: y = 14'b01111010001100; - 8'b10001101: y = 14'b01111001110000; - 8'b10001110: y = 14'b01111001010101; - 8'b10001111: y = 14'b01111000111010; - 8'b10010000: y = 14'b01111000011111; - 8'b10010001: y = 14'b01111000000100; - 8'b10010010: y = 14'b01110111101010; - 8'b10010011: y = 14'b01110111010000; - 8'b10010100: y = 14'b01110110110110; - 8'b10010101: y = 14'b01110110011101; - 8'b10010110: y = 14'b01110110000100; - 8'b10010111: y = 14'b01110101101011; - 8'b10011000: y = 14'b01110101010010; - 8'b10011001: y = 14'b01110100111001; - 8'b10011010: y = 14'b01110100100001; - 8'b10011011: y = 14'b01110100001001; - 8'b10011100: y = 14'b01110011110001; - 8'b10011101: y = 14'b01110011011010; - 8'b10011110: y = 14'b01110011000010; - 8'b10011111: y = 14'b01110010101011; - 8'b10100000: y = 14'b01110010010100; - 8'b10100001: y = 14'b01110001111110; - 8'b10100010: y = 14'b01110001100111; - 8'b10100011: y = 14'b01110001010001; - 8'b10100100: y = 14'b01110000111011; - 8'b10100101: y = 14'b01110000100101; - 8'b10100110: y = 14'b01110000001111; - 8'b10100111: y = 14'b01101111111010; - 8'b10101000: y = 14'b01101111100101; - 8'b10101001: y = 14'b01101111010000; - 8'b10101010: y = 14'b01101110111011; - 8'b10101011: y = 14'b01101110100110; - 8'b10101100: y = 14'b01101110010001; - 8'b10101101: y = 14'b01101101111101; - 8'b10101110: y = 14'b01101101101001; - 8'b10101111: y = 14'b01101101010101; - 8'b10110000: y = 14'b01101101000001; - 8'b10110001: y = 14'b01101100101101; - 8'b10110010: y = 14'b01101100011010; - 8'b10110011: y = 14'b01101100000110; - 8'b10110100: y = 14'b01101011110011; - 8'b10110101: y = 14'b01101011100000; - 8'b10110110: y = 14'b01101011001101; - 8'b10110111: y = 14'b01101010111010; - 8'b10111000: y = 14'b01101010101000; - 8'b10111001: y = 14'b01101010010101; - 8'b10111010: y = 14'b01101010000011; - 8'b10111011: y = 14'b01101001110001; - 8'b10111100: y = 14'b01101001011111; - 8'b10111101: y = 14'b01101001001101; - 8'b10111110: y = 14'b01101000111100; - 8'b10111111: y = 14'b01101000101010; - 8'b11000000: y = 14'b01101000011001; - 8'b11000001: y = 14'b01101000000111; - 8'b11000010: y = 14'b01100111110110; - 8'b11000011: y = 14'b01100111100101; - 8'b11000100: y = 14'b01100111010100; - 8'b11000101: y = 14'b01100111000011; - 8'b11000110: y = 14'b01100110110011; - 8'b11000111: y = 14'b01100110100010; - 8'b11001000: y = 14'b01100110010010; - 8'b11001001: y = 14'b01100110000010; - 8'b11001010: y = 14'b01100101110010; - 8'b11001011: y = 14'b01100101100001; - 8'b11001100: y = 14'b01100101010010; - 8'b11001101: y = 14'b01100101000010; - 8'b11001110: y = 14'b01100100110010; - 8'b11001111: y = 14'b01100100100011; - 8'b11010000: y = 14'b01100100010011; - 8'b11010001: y = 14'b01100100000100; - 8'b11010010: y = 14'b01100011110101; - 8'b11010011: y = 14'b01100011100101; - 8'b11010100: y = 14'b01100011010110; - 8'b11010101: y = 14'b01100011000111; - 8'b11010110: y = 14'b01100010111001; - 8'b11010111: y = 14'b01100010101010; - 8'b11011000: y = 14'b01100010011011; - 8'b11011001: y = 14'b01100010001101; - 8'b11011010: y = 14'b01100001111110; - 8'b11011011: y = 14'b01100001110000; - 8'b11011100: y = 14'b01100001100010; - 8'b11011101: y = 14'b01100001010100; - 8'b11011110: y = 14'b01100001000110; - 8'b11011111: y = 14'b01100000111000; - 8'b11100000: y = 14'b01100000101010; - 8'b11100001: y = 14'b01100000011100; - 8'b11100010: y = 14'b01100000001111; - 8'b11100011: y = 14'b01100000000001; - 8'b11100100: y = 14'b01011111110100; - 8'b11100101: y = 14'b01011111100110; - 8'b11100110: y = 14'b01011111011001; - 8'b11100111: y = 14'b01011111001100; - 8'b11101000: y = 14'b01011110111111; - 8'b11101001: y = 14'b01011110110010; - 8'b11101010: y = 14'b01011110100101; - 8'b11101011: y = 14'b01011110011000; - 8'b11101100: y = 14'b01011110001011; - 8'b11101101: y = 14'b01011101111110; - 8'b11101110: y = 14'b01011101110010; - 8'b11101111: y = 14'b01011101100101; - 8'b11110000: y = 14'b01011101011001; - 8'b11110001: y = 14'b01011101001100; - 8'b11110010: y = 14'b01011101000000; - 8'b11110011: y = 14'b01011100110100; - 8'b11110100: y = 14'b01011100101000; - 8'b11110101: y = 14'b01011100011100; - 8'b11110110: y = 14'b01011100010000; - 8'b11110111: y = 14'b01011100000100; - 8'b11111000: y = 14'b01011011111000; - 8'b11111001: y = 14'b01011011101100; - 8'b11111010: y = 14'b01011011100000; - 8'b11111011: y = 14'b01011011010101; - 8'b11111100: y = 14'b01011011001001; - 8'b11111101: y = 14'b01011010111101; - 8'b11111110: y = 14'b01011010110010; - 8'b11111111: y = 14'b01011010100111; - default: y = 14'bxxxxxxxxxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - \ No newline at end of file diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a5.sv b/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a5.sv deleted file mode 100755 index ff0aaa4b6..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sbtm_a5.sv +++ /dev/null @@ -1,200 +0,0 @@ -module sbtm_a3 (input logic [7:0] a, - output logic [5:0] y); - always_comb - case(a) - 8'b01000000: y = 6'b100110; - 8'b01000001: y = 6'b100001; - 8'b01000010: y = 6'b011100; - 8'b01000011: y = 6'b010111; - 8'b01000100: y = 6'b010010; - 8'b01000101: y = 6'b001100; - 8'b01000110: y = 6'b000111; - 8'b01000111: y = 6'b000010; - 8'b01001000: y = 6'b100000; - 8'b01001001: y = 6'b011100; - 8'b01001010: y = 6'b011000; - 8'b01001011: y = 6'b010011; - 8'b01001100: y = 6'b001111; - 8'b01001101: y = 6'b001010; - 8'b01001110: y = 6'b000110; - 8'b01001111: y = 6'b000010; - 8'b01010000: y = 6'b011100; - 8'b01010001: y = 6'b011000; - 8'b01010010: y = 6'b010100; - 8'b01010011: y = 6'b010000; - 8'b01010100: y = 6'b001101; - 8'b01010101: y = 6'b001001; - 8'b01010110: y = 6'b000101; - 8'b01010111: y = 6'b000001; - 8'b01011000: y = 6'b011000; - 8'b01011001: y = 6'b010101; - 8'b01011010: y = 6'b010010; - 8'b01011011: y = 6'b001110; - 8'b01011100: y = 6'b001011; - 8'b01011101: y = 6'b001000; - 8'b01011110: y = 6'b000100; - 8'b01011111: y = 6'b000001; - 8'b01100000: y = 6'b010101; - 8'b01100001: y = 6'b010010; - 8'b01100010: y = 6'b001111; - 8'b01100011: y = 6'b001101; - 8'b01100100: y = 6'b001010; - 8'b01100101: y = 6'b000111; - 8'b01100110: y = 6'b000100; - 8'b01100111: y = 6'b000001; - 8'b01101000: y = 6'b010011; - 8'b01101001: y = 6'b010000; - 8'b01101010: y = 6'b001110; - 8'b01101011: y = 6'b001011; - 8'b01101100: y = 6'b001001; - 8'b01101101: y = 6'b000110; - 8'b01101110: y = 6'b000011; - 8'b01101111: y = 6'b000001; - 8'b01110000: y = 6'b010001; - 8'b01110001: y = 6'b001111; - 8'b01110010: y = 6'b001100; - 8'b01110011: y = 6'b001010; - 8'b01110100: y = 6'b001000; - 8'b01110101: y = 6'b000101; - 8'b01110110: y = 6'b000011; - 8'b01110111: y = 6'b000001; - 8'b01111000: y = 6'b001111; - 8'b01111001: y = 6'b001101; - 8'b01111010: y = 6'b001011; - 8'b01111011: y = 6'b001001; - 8'b01111100: y = 6'b000111; - 8'b01111101: y = 6'b000101; - 8'b01111110: y = 6'b000011; - 8'b01111111: y = 6'b000001; - 8'b10000000: y = 6'b001110; - 8'b10000001: y = 6'b001100; - 8'b10000010: y = 6'b001010; - 8'b10000011: y = 6'b001000; - 8'b10000100: y = 6'b000110; - 8'b10000101: y = 6'b000100; - 8'b10000110: y = 6'b000010; - 8'b10000111: y = 6'b000000; - 8'b10001000: y = 6'b001101; - 8'b10001001: y = 6'b001011; - 8'b10001010: y = 6'b001001; - 8'b10001011: y = 6'b000111; - 8'b10001100: y = 6'b000110; - 8'b10001101: y = 6'b000100; - 8'b10001110: y = 6'b000010; - 8'b10001111: y = 6'b000000; - 8'b10010000: y = 6'b001100; - 8'b10010001: y = 6'b001010; - 8'b10010010: y = 6'b001000; - 8'b10010011: y = 6'b000111; - 8'b10010100: y = 6'b000101; - 8'b10010101: y = 6'b000100; - 8'b10010110: y = 6'b000010; - 8'b10010111: y = 6'b000000; - 8'b10011000: y = 6'b001011; - 8'b10011001: y = 6'b001001; - 8'b10011010: y = 6'b001000; - 8'b10011011: y = 6'b000110; - 8'b10011100: y = 6'b000101; - 8'b10011101: y = 6'b000011; - 8'b10011110: y = 6'b000010; - 8'b10011111: y = 6'b000000; - 8'b10100000: y = 6'b001010; - 8'b10100001: y = 6'b001000; - 8'b10100010: y = 6'b000111; - 8'b10100011: y = 6'b000110; - 8'b10100100: y = 6'b000100; - 8'b10100101: y = 6'b000011; - 8'b10100110: y = 6'b000010; - 8'b10100111: y = 6'b000000; - 8'b10101000: y = 6'b001001; - 8'b10101001: y = 6'b001000; - 8'b10101010: y = 6'b000111; - 8'b10101011: y = 6'b000101; - 8'b10101100: y = 6'b000100; - 8'b10101101: y = 6'b000011; - 8'b10101110: y = 6'b000001; - 8'b10101111: y = 6'b000000; - 8'b10110000: y = 6'b001000; - 8'b10110001: y = 6'b000111; - 8'b10110010: y = 6'b000110; - 8'b10110011: y = 6'b000101; - 8'b10110100: y = 6'b000100; - 8'b10110101: y = 6'b000010; - 8'b10110110: y = 6'b000001; - 8'b10110111: y = 6'b000000; - 8'b10111000: y = 6'b001000; - 8'b10111001: y = 6'b000111; - 8'b10111010: y = 6'b000110; - 8'b10111011: y = 6'b000101; - 8'b10111100: y = 6'b000011; - 8'b10111101: y = 6'b000010; - 8'b10111110: y = 6'b000001; - 8'b10111111: y = 6'b000000; - 8'b11000000: y = 6'b000111; - 8'b11000001: y = 6'b000110; - 8'b11000010: y = 6'b000101; - 8'b11000011: y = 6'b000100; - 8'b11000100: y = 6'b000011; - 8'b11000101: y = 6'b000010; - 8'b11000110: y = 6'b000001; - 8'b11000111: y = 6'b000000; - 8'b11001000: y = 6'b000111; - 8'b11001001: y = 6'b000110; - 8'b11001010: y = 6'b000101; - 8'b11001011: y = 6'b000100; - 8'b11001100: y = 6'b000011; - 8'b11001101: y = 6'b000010; - 8'b11001110: y = 6'b000001; - 8'b11001111: y = 6'b000000; - 8'b11010000: y = 6'b000111; - 8'b11010001: y = 6'b000110; - 8'b11010010: y = 6'b000101; - 8'b11010011: y = 6'b000100; - 8'b11010100: y = 6'b000011; - 8'b11010101: y = 6'b000010; - 8'b11010110: y = 6'b000001; - 8'b11010111: y = 6'b000000; - 8'b11011000: y = 6'b000110; - 8'b11011001: y = 6'b000101; - 8'b11011010: y = 6'b000100; - 8'b11011011: y = 6'b000011; - 8'b11011100: y = 6'b000011; - 8'b11011101: y = 6'b000010; - 8'b11011110: y = 6'b000001; - 8'b11011111: y = 6'b000000; - 8'b11100000: y = 6'b000110; - 8'b11100001: y = 6'b000101; - 8'b11100010: y = 6'b000100; - 8'b11100011: y = 6'b000011; - 8'b11100100: y = 6'b000010; - 8'b11100101: y = 6'b000010; - 8'b11100110: y = 6'b000001; - 8'b11100111: y = 6'b000000; - 8'b11101000: y = 6'b000101; - 8'b11101001: y = 6'b000101; - 8'b11101010: y = 6'b000100; - 8'b11101011: y = 6'b000011; - 8'b11101100: y = 6'b000010; - 8'b11101101: y = 6'b000001; - 8'b11101110: y = 6'b000001; - 8'b11101111: y = 6'b000000; - 8'b11110000: y = 6'b000101; - 8'b11110001: y = 6'b000100; - 8'b11110010: y = 6'b000100; - 8'b11110011: y = 6'b000011; - 8'b11110100: y = 6'b000010; - 8'b11110101: y = 6'b000001; - 8'b11110110: y = 6'b000001; - 8'b11110111: y = 6'b000000; - 8'b11111000: y = 6'b000101; - 8'b11111001: y = 6'b000100; - 8'b11111010: y = 6'b000011; - 8'b11111011: y = 6'b000011; - 8'b11111100: y = 6'b000010; - 8'b11111101: y = 6'b000001; - 8'b11111110: y = 6'b000001; - 8'b11111111: y = 6'b000000; - default: y = 6'bxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 diff --git a/wally-pipelined/src/fpu/fpdivsqrt/sim.csh b/wally-pipelined/src/fpu/fpdivsqrt/sim.csh deleted file mode 100755 index a70ee2d06..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/sim.csh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -./runme_f64div.csh -./runme_f32div.csh -./runme_f64sqrt.csh -./runme_f32sqrt.csh -echo "Simulation Ended, Go Pokes!..." diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rd.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rd.sv deleted file mode 100755 index f71a83650..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rd.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_div_rd.out"); - $readmemh("f32_div_rd.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b1; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (31605) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rne.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rne.sv deleted file mode 100755 index 7f19e7d57..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rne.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_div_rne.out"); - $readmemh("f32_div_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b1; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (39509) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_ru.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_ru.sv deleted file mode 100755 index 77485f8e2..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_ru.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_div_ru.out"); - $readmemh("f32_div_ru.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b1; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (31614) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rz.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rz.sv deleted file mode 100755 index dfa980058..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_div_rz.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [31:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [103:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, {op2, 32'h0}, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_div_rz.out"); - $readmemh("f32_div_rz.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b1; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (31792) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rd.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rd.sv deleted file mode 100755 index 2a63c3173..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rd.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [71:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_sqrt_rd.out"); - $readmemh("f32_sqrt_rd.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b1; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (19538) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rne.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rne.sv deleted file mode 100755 index a566fcc0a..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rne.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [71:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_sqrt_rne.out"); - $readmemh("f32_sqrt_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b1; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (19538) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_ru.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_ru.sv deleted file mode 100755 index 44c41fada..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_ru.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [71:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_sqrt_ru.out"); - $readmemh("f32_sqrt_ru.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b1; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (19538) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rz.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rz.sv deleted file mode 100755 index 0c4a61d71..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f32_sqrt_rz.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [31:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [31:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [71:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, {op1, 32'h0}, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f32_sqrt_rz.out"); - $readmemh("f32_sqrt_rz.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b1; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (19538) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result[63:32]==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rd.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rd.sv deleted file mode 100755 index 7f72a9a98..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rd.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_div_rd.out"); - $readmemh("f64_div_rd.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b0; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (39050) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rne.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rne.sv deleted file mode 100755 index 99351b039..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rne.sv +++ /dev/null @@ -1,82 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_div_rne.out"); - $readmemh("f64_div_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b0; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (39509) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_ru.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_ru.sv deleted file mode 100755 index 816a4132a..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_ru.sv +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_div_ru.out"); - $readmemh("f64_div_ru.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b0; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (39020) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rz.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rz.sv deleted file mode 100755 index bf6cac539..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_div_rz.sv +++ /dev/null @@ -1,82 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_div_rz.out"); - $readmemh("f64_div_rz.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b0; - #0 P = 1'b0; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (39515) - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb - - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rd.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rd.sv deleted file mode 100755 index d67275a0f..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rd.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [135:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_sqrt_rd.out"); - $readmemh("f64_sqrt_rd.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b0; - #0 rm = 2'b11; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (363) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rne.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rne.sv deleted file mode 100755 index e2f7d40d8..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rne.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [135:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_sqrt_rne.out"); - $readmemh("f64_sqrt_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b0; - #0 rm = 2'b00; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (363) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_ru.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_ru.sv deleted file mode 100755 index e01490c13..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_ru.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [135:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_sqrt_ru.out"); - $readmemh("f64_sqrt_ru.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b0; - #0 rm = 2'b10; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (363) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rz.sv b/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rz.sv deleted file mode 100755 index d43bebea3..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/tb_f64_sqrt_rz.sv +++ /dev/null @@ -1,79 +0,0 @@ -`timescale 1ps/1ps -module tb (); - - logic [63:0] op1; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [135:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - fpdiv dut (done, AS_Result, Flags, Denorm, op1, 64'h0, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - - initial - begin - handle3 = $fopen("f64_sqrt_rz.out"); - $readmemh("f64_sqrt_rz.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - #0 op_type = 1'b1; - #0 P = 1'b0; - #0 rm = 2'b01; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - repeat (363) - if (~reset) - begin - #0; {op1, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (15) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%b_%b | %h_%b", op1, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - end // if (~reset) - $display("%d vectors processed", vectornum); - $finish; - end // always @ (posedge clk) - -endmodule // tb diff --git a/wally-pipelined/src/fpu/fpdivsqrt/test_divconvDP.sv b/wally-pipelined/src/fpu/fpdivsqrt/test_divconvDP.sv deleted file mode 100755 index 3efab2d1a..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/test_divconvDP.sv +++ /dev/null @@ -1,72 +0,0 @@ -module tb; - - logic [52:0] d, n; - logic reset; - - logic [63:0] q, qm, qp, rega_out, regb_out, regc_out; - logic [127:0] regr_out; - - logic start; - logic error; - logic op_type; - - logic done; - logic load_rega; - logic load_regb; - logic load_regc; - logic load_regr; - logic [1:0] sel_muxa; - logic [1:0] sel_muxb; - logic sel_muxr; - - logic clk; - integer handle3; - integer desc3; - - divconv dut (q, qm, qp, rega_out, regb_out, regc_out, regr_out, - d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk, - load_rega, load_regb, load_regc, load_regr); - fsm control (done, load_rega, load_regb, load_regc, load_regr, - sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); - - initial - begin - clk = 1'b1; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("divconvDP.out"); - #700 $finish; - end - - always - begin - desc3 = handle3; - #5 $fdisplay(desc3, "%b %b %b | %h %h | %h %h %h | %h %h %h %h", sel_muxa, - sel_muxb, sel_muxr, d, n, q, qm, qp, rega_out, regb_out, regc_out, regr_out); - end - - initial - begin - #0 start = 1'b0; - #0 n = 53'h1C_0000_0000_0000; // 1.75 - #0 d = 53'h1E_0000_0000_0000; // 1.875 - #0 reset = 1'b1; - - #20 reset = 1'b0; - #20 start = 1'b1; - #40 start = 1'b0; - - - end - - -endmodule // tb - - - - - diff --git a/wally-pipelined/src/fpu/fpdivsqrt/test_fpdiv.sv b/wally-pipelined/src/fpu/fpdivsqrt/test_fpdiv.sv deleted file mode 100755 index 9cc92d979..000000000 --- a/wally-pipelined/src/fpu/fpdivsqrt/test_fpdiv.sv +++ /dev/null @@ -1,176 +0,0 @@ -`timescale 1ps/1ps -module tb; - - logic [63:0] op1; - logic [63:0] op2; - logic [1:0] rm; - logic op_type; - logic P; - logic OvEn; - logic UnEn; - - logic start; - logic reset; - logic clk; - - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - integer handle3; - integer desc3; - - fpdiv dut (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn, - start, reset, clk); - - initial - begin - clk = 1'b1; - forever #333 clk = ~clk; - end - - initial - begin - handle3 = $fopen("fpdiv.out"); - end - - always - begin - desc3 = handle3; - #5 $fdisplay(desc3, "%h %h | %h %h %h", - op1, op2, AS_Result, Flags, Denorm); - end - - initial - begin - #0 start = 1'b0; - #0 P = 1'b0; - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - // 00 round-to-nearest-even - // 01 round-toward-zero - // 10 round-toward-plus infinity - // 11 round-toward-minus infinity - #0 rm = 2'b00; - #0 op_type = 1'b0; - - #0 op1 = 64'h3ffc_0000_0000_0000; // 1.75 - #0 op2 = 64'h3ffe_0000_0000_0000; // 1.875 - - #0 op1 = 64'h4020_5fff_ffff_ffff; - #0 op2 = 64'hbcaf_ffff_ffff_ffff; - - #0 op1 = 64'h0010_0000_0000_0001; - #0 op2 = 64'hc8cf_ffff_ffff_c001; - - //#0 op1 = 64'h3ffe_e219_652b_d3c3; // 1.9302 - //#0 op2 = 64'h3ff7_346d_c5d6_3886; // 1.4503 - //#0 op1 = 64'h404f_b1d4_9518_2a99; // 63.3893 - //#0 op2 = 64'h4020_9b94_d940_7896; // 8.30387 - //#0 op1 = 64'h3ff6_3d98_4781_6b47; // 1.390037803 - //#0 op2 = 64'h3fd7_b540_56e5_c87a; // 0.370437703 - //#0 op1 = 64'h3fed_c505_fada_95fd; // 0.930300703 - //#0 op2 = 64'h4029_dc59_e3a1_24a8; // 12.9303733 - //#0 op1 = 64'h41E0_0003_FFFB_FFFF; - //#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF; - //#0 op1 = 64'h41E0_0003_FFFB_FFFF; - //#0 op2 = 64'h3FDF_FFFF_FFEF_FFFF; - //#0 op1 = 64'hB68F_FFF8_0000_00FF; - //#0 op2 = 64'h3F90_8000_0007_FFFF; - //#0 op1 = 64'h0000_0000_0000_0000; - //#0 op2 = 64'hA57F_319E_DE38_F755; - //#0 op1 = 64'hC1DF_FFFF_FFE0_0080; - //#0 op2 = 64'h3FA4_8EDF_3623_F076; - //#0 op1 = 64'hC030_00FF_FFFF_FFE0; - //#0 op2 = 64'h47EF_FDFF_FDFF_FFFF; - //#0 op1 = 64'h4030_00FF_FFFF_FFE0; - //#0 op2 = 64'h47EF_FDFF_FDFF_FFFF; - //#0 op1 = 64'h5555_5555_5555_5555; // 1.75 - //#0 op2 = 64'haaaa_aaaa_aaaa_aaaa; // 1.875 - //#0 op1 = 64'h3ffc_0000_0000_0000; // 1.75 - //#0 op2 = 64'h0000_0000_0000_0000; // 0.00 (Div0 exception) - //#0 op1 = 64'h3ff7_10cb_0000_0000; - //#0 op2 = 64'h3fb9_a36e_0000_0000; - //#0 op1 = 64'h37e0_0000_0000_0001; - //#0 op2 = 64'h3be6_a09e_667f_3bce; - - //#0 op1 = 64'h37e0_0000_0000_0001; - //#0 op1 = 64'h43d3_6fa3_cad3_f59e; - //#0 op1 = 64'h2470_0000_ffff_ffef; - //#0 op1 = 64'h7ff0_0000_0000_0000; - //#0 op1 = 64'h7fef_ffff_ffff_ffff; - //#0 op1 = 64'hffe0_0000_0000_0000; - //#0 op2 = 64'h7fe0_0000_0000_0001; - //#0 op1 = 64'h69ff_ff7f_0000_0000; - //#0 op2 = 64'h0; - //#0 op1 = 64'h3f7f_ffff_0000_0000; - //#0 op1 = 64'h4180_0000_0000_0000; - - - //#0 op1 = 64'h3fe0_0000_0000_0000; // 1.75 (SP) - //#0 op2 = 64'h3ff0_0000_0000_0000; // 1.875 (SP) - //#0 op1 = 64'h3ff7_10cb_0000_0000; // 1.75 (SP) - //#0 op2 = 64'h3fb9_a36e_0000_0000; // 1.875 (SP) - //#0 op1 = 64'h427d_8ea5_0000_0000; // 1.75 (SP) - //#0 op2 = 64'h4104_dca7_0000_0000; // 1.875 (SP) - //#0 op1 = 64'h3fb1_ecc2_0000_0000; // 1.75 (SP) - //#0 op2 = 64'h3ebd_aa03_0000_0000; // 1.875 (SP) - //#0 op1 = 64'h3f6e_2830_0000_0000; - //#0 op2 = 64'h414e_e2cf_0000_0000; - //#0 op1 = 64'h8683_f7ff_0000_0000; - //#0 op2 = 64'hc07f_3fff_0000_0000; - //#0 op1 = 64'h0100_0000_0000_0000; - //#0 op2 = 64'h3400_00ef_0000_0000; - //#0 op1 = 64'hbed5_6444_0000_0000; - //#0 op2 = 64'h3e7f_f400_0000_0000; - //#0 op1 = 64'h0100_087f_0000_0000; - //#0 op2 = 64'hfe80_4fff_0000_0000; - - - //#0 op1 = 64'hc513_492f_a359_69e3; - //#0 op2 = 64'hbfcf_fdff_ffff_ffef; - //#0 op1 = 64'h41E0_0003_FFFB_FFFF; - //#0 op2 = 64'hBFDF_FFFF_FFEF_FFFF; - //#0 op1 = 64'hf17ffffffff7fff0; - //#0 op2 = 64'h001ffffffffffffe; - //#0 op1 = 64'hC040_0000_0000_1000; - //#0 op2 = 64'h802f_ff7f_ffff_ffc0; - //#0 op1 = 64'h3800008000000002; - //#0 op2 = 64'h7ff0000000000000; - //#0 op1 = 64'h8020200007fffffe; - //#0 op2 = 64'hc59000000000083f; - //#0 op1 = 64'h0140008000fffffe; - //#0 op2 = 64'hd2e0001ffffffffb; - //#0 op1 = 64'h4013_95a7_515b_e3d9; - //#0 op2 = 64'h8010_0000_0004_0007; - //#0 op1 = 64'h0010_0000_0000_0000; - //#0 op2 = 64'h3fff_ffff_ffff_ffff; - //#0 op1 = 64'h0010_0000_0000_0000; - //#0 op2 = 64'h4000_0000_0000_0001; - //#0 op1 = 64'h4000000000000001; - //#0 op2 = 64'h403000004007fffe; // _3fbfffff7ff00207_00000_0 | 3fbfffff7ff00206_0 - //#0 op1 = 64'hffe0_0000_0000_0000; - //#0 op2 = 64'hc0a0_0000_4008_0000; - //#0 op1 = 64'hffe0_0000_0000_0001; - //#0 op2 = 64'hbfd0_0000_0000_0000; - - //#0 op1 = 64'h801f_ffff_ffff_ffff; - //#0 op2 = 64'h4000_0000_0000_0000; - - - #0 reset = 1'b1; - #1000 reset = 1'b0; - #3000 start = 1'b1; - #800 start = 1'b0; - - - end - - -endmodule // tb - - - - - diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 2888c8bcd..2d1351ec5 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -44,7 +44,9 @@ module fpu ( output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction output logic [4:0] SetFflagsM); // FPU result // *** change FMA to do 16 - 32 - 64 - 128 FEXPBITS - +// *** folder at same level of src for tests fpu tests +// qa.b +// u1.52 - u sunsigned, q signed generate if (`F_SUPPORTED | `D_SUPPORTED) begin // control logic signal instantiation @@ -188,16 +190,18 @@ module fpu ( // capture the inputs for div/sqrt flopenrc #(64) reg_input1 (.d(FSrcXE), .q(DivInput1E), - .en(~HoldInputs), .clear(FDivSqrtDoneE), - .reset(reset), .clk(clk)); + .en(1'b1), .clear(FDivSqrtDoneE), + .reset(reset), .clk(HoldInputs)); flopenrc #(64) reg_input2 (.d(FSrcYE), .q(DivInput2E), - .en(~HoldInputs), .clear(FDivSqrtDoneE), - .reset(reset), .clk(clk)); - - // fpdiv fdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E, - // .FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM, - // .FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset); - assign FDivBusyE = 0; + .en(1'b1), .clear(FDivSqrtDoneE), + .reset(reset), .clk(HoldInputs)); + //*** add round to nearest ties to max magnitude + fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .done(FDivSqrtDoneE), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), .P(~FmtE), .FDivBusyE, .HoldInputs, + .OvEn(1'b1), .UnEn(1'b1), .start(FDivStartE), .reset, .clk(~clk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM)); + // .DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E, + // .FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM, + // .FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset); + // assign FDivBusyE = 0; // first of two-stage instance of floating-point add/cvt unit faddcvt faddcvt (.clk, .reset, .FlushM, .StallM, .FrmM, .FOpCtrlM, .FmtE, .FmtM, .FSrcXE, .FSrcYE, .FOpCtrlE, .FAddResM, .FAddFlgM); @@ -215,7 +219,6 @@ module fpu ( fcvt fcvt (.XSgnE, .XExpE, .XFracE, .XAssumed1E, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); // output for store instructions - // mux2 #(`XLEN) FWriteDataMux({{`XLEN-32{1'b0}}, FSrcYE[63:32]}, FSrcYE[63:64-`XLEN], FmtE, FWriteDataE); assign FWriteDataE = FSrcYE[`XLEN-1:0]; //***************** diff --git a/wally-pipelined/src/fpu/fsm.sv b/wally-pipelined/src/fpu/fsm.sv index 7500eeaae..26efe10ac 100755 --- a/wally-pipelined/src/fpu/fsm.sv +++ b/wally-pipelined/src/fpu/fsm.sv @@ -81,7 +81,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; - holdInputs = 1'b0; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -97,7 +97,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; - holdInputs = 1'b0; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; diff --git a/wally-pipelined/src/fpu/fsm_div.v b/wally-pipelined/src/fpu/fsm_div.v index f9f338776..5c6cc7edf 100755 --- a/wally-pipelined/src/fpu/fsm_div.v +++ b/wally-pipelined/src/fpu/fsm_div.v @@ -1,461 +1,461 @@ -`timescale 1ps/1ps -module fsm_div (done, load_rega, load_regb, load_regc, - load_regd, load_regr, load_regs, - sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, error, op_type); +// `timescale 1ps/1ps +// module fsm_div (done, load_rega, load_regb, load_regc, +// load_regd, load_regr, load_regs, +// sel_muxa, sel_muxb, sel_muxr, +// clk, reset, start, error, op_type); - input clk; - input reset; - input start; - input error; - input op_type; +// input clk; +// input reset; +// input start; +// input error; +// input op_type; - output done; - output load_rega; - output load_regb; - output load_regc; - output load_regd; - output load_regr; - output load_regs; +// output done; +// output load_rega; +// output load_regb; +// output load_regc; +// output load_regd; +// output load_regr; +// output load_regs; - output [2:0] sel_muxa; - output [2:0] sel_muxb; - output sel_muxr; +// output [2:0] sel_muxa; +// output [2:0] sel_muxb; +// output sel_muxr; - reg done; // End of cycles - reg load_rega; // enable for regA - reg load_regb; // enable for regB - reg load_regc; // enable for regC - reg load_regd; // enable for regD - reg load_regr; // enable for rem - reg load_regs; // enable for q,qm,qp - reg [2:0] sel_muxa; // Select muxA - reg [2:0] sel_muxb; // Select muxB - reg sel_muxr; // Select rem mux +// reg done; // End of cycles +// reg load_rega; // enable for regA +// reg load_regb; // enable for regB +// reg load_regc; // enable for regC +// reg load_regd; // enable for regD +// reg load_regr; // enable for rem +// reg load_regs; // enable for q,qm,qp +// reg [2:0] sel_muxa; // Select muxA +// reg [2:0] sel_muxb; // Select muxB +// reg sel_muxr; // Select rem mux - reg [4:0] CURRENT_STATE; - reg [4:0] NEXT_STATE; +// reg [4:0] CURRENT_STATE; +// reg [4:0] NEXT_STATE; - parameter [4:0] - S0=5'd0, S1=5'd1, S2=5'd2, - S3=5'd3, S4=5'd4, S5=5'd5, - S6=5'd6, S7=5'd7, S8=5'd8, - S9=5'd9, S10=5'd10, - S13=5'd13, S14=5'd14, S15=5'd15, - S16=5'd16, S17=5'd17, S18=5'd18, - S19=5'd19, S20=5'd20, S21=5'd21, - S22=5'd22, S23=5'd23, S24=5'd24, - S25=5'd25, S26=5'd26, S27=5'd27, - S28=5'd28, S29=5'd29, S30=5'd30; +// parameter [4:0] +// S0=5'd0, S1=5'd1, S2=5'd2, +// S3=5'd3, S4=5'd4, S5=5'd5, +// S6=5'd6, S7=5'd7, S8=5'd8, +// S9=5'd9, S10=5'd10, +// S13=5'd13, S14=5'd14, S15=5'd15, +// S16=5'd16, S17=5'd17, S18=5'd18, +// S19=5'd19, S20=5'd20, S21=5'd21, +// S22=5'd22, S23=5'd23, S24=5'd24, +// S25=5'd25, S26=5'd26, S27=5'd27, +// S28=5'd28, S29=5'd29, S30=5'd30; - always @(posedge clk) - begin - if(reset==1'b1) - CURRENT_STATE<=S0; - else - CURRENT_STATE<=NEXT_STATE; - end +// always @(posedge clk) +// begin +// if(reset==1'b1) +// CURRENT_STATE<=S0; +// else +// CURRENT_STATE<=NEXT_STATE; +// end - always @(*) - begin - case(CURRENT_STATE) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - else if (start==1'b1 && op_type==1'b0) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S1; - end // if (start==1'b1 && op_type==1'b0) - else if (start==1'b1 && op_type==1'b1) - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S13; - end - end // case: S0 - S1: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S2; - end - S2: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S3; - end - S3: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S4; - end - S4: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S5; - end - S5: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; // add - NEXT_STATE <= S6; - end - S6: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end - S7: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S8; - end // case: S7 - S8: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S9; - end - S9: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - NEXT_STATE <= S10; - end - S10: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - S13: // start of sqrt path - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - NEXT_STATE <= S14; - end - S14: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - NEXT_STATE <= S15; - end - S15: // iteration 1 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S16; - end - S16: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S17; - end - S17: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S18; - end - S18: // iteration 2 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S19; - end - S19: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S20; - end - S20: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S21; - end - S21: // iteration 3 - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S22; - end - S22: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - NEXT_STATE <= S23; - end - S23: - begin - done = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - NEXT_STATE <= S24; - end - S24: // q,qm,qp - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S25; - end - S25: // rem - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - NEXT_STATE <= S26; - end - S26: // done - begin - done = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - default: - begin - done = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - NEXT_STATE <= S0; - end - endcase // case(CURRENT_STATE) - end // always @ (CURRENT_STATE or X) +// always @(*) +// begin +// case(CURRENT_STATE) +// S0: // iteration 0 +// begin +// if (start==1'b0) +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S0; +// end +// else if (start==1'b1 && op_type==1'b0) +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b001; +// sel_muxb = 3'b001; +// sel_muxr = 1'b0; +// NEXT_STATE <= S1; +// end // if (start==1'b1 && op_type==1'b0) +// else if (start==1'b1 && op_type==1'b1) +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b010; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S13; +// end +// end // case: S0 +// S1: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b010; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S2; +// end +// S2: // iteration 1 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S3; +// end +// S3: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; +// NEXT_STATE <= S4; +// end +// S4: // iteration 2 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S5; +// end +// S5: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; // add +// NEXT_STATE <= S6; +// end +// S6: // iteration 3 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S8; +// end +// S7: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; +// NEXT_STATE <= S8; +// end // case: S7 +// S8: // q,qm,qp +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b1; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S9; +// end +// S9: // rem +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b1; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b1; +// NEXT_STATE <= S10; +// end +// S10: // done +// begin +// done = 1'b1; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S0; +// end +// S13: // start of sqrt path +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b1; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b010; +// sel_muxb = 3'b001; +// sel_muxr = 1'b0; +// NEXT_STATE <= S14; +// end +// S14: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b001; +// sel_muxb = 3'b100; +// sel_muxr = 1'b0; +// NEXT_STATE <= S15; +// end +// S15: // iteration 1 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S16; +// end +// S16: +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b1; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S17; +// end +// S17: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b100; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; +// NEXT_STATE <= S18; +// end +// S18: // iteration 2 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S19; +// end +// S19: +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b1; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S20; +// end +// S20: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b100; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; +// NEXT_STATE <= S21; +// end +// S21: // iteration 3 +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b1; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S22; +// end +// S22: +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b1; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b011; +// sel_muxr = 1'b0; +// NEXT_STATE <= S23; +// end +// S23: +// begin +// done = 1'b0; +// load_rega = 1'b1; +// load_regb = 1'b0; +// load_regc = 1'b1; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b100; +// sel_muxb = 3'b010; +// sel_muxr = 1'b0; +// NEXT_STATE <= S24; +// end +// S24: // q,qm,qp +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b1; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S25; +// end +// S25: // rem +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b1; +// load_regs = 1'b0; +// sel_muxa = 3'b011; +// sel_muxb = 3'b110; +// sel_muxr = 1'b1; +// NEXT_STATE <= S26; +// end +// S26: // done +// begin +// done = 1'b1; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S0; +// end +// default: +// begin +// done = 1'b0; +// load_rega = 1'b0; +// load_regb = 1'b0; +// load_regc = 1'b0; +// load_regd = 1'b0; +// load_regr = 1'b0; +// load_regs = 1'b0; +// sel_muxa = 3'b000; +// sel_muxb = 3'b000; +// sel_muxr = 1'b0; +// NEXT_STATE <= S0; +// end +// endcase // case(CURRENT_STATE) +// end // always @ (CURRENT_STATE or X) -endmodule // fsm +// endmodule // fsm diff --git a/wally-pipelined/src/fpu/rounder_div.sv b/wally-pipelined/src/fpu/rounder_div.sv index de0076cb6..f855edef0 100755 --- a/wally-pipelined/src/fpu/rounder_div.sv +++ b/wally-pipelined/src/fpu/rounder_div.sv @@ -63,6 +63,7 @@ module rounder_div (Result, DenormIO, Flags, rm, P, OvEn, logic Texp_l7z; logic Texp_l7o; logic OvCon; + logic zero_rem; logic [1:0] mux_mant; logic sign_rem; logic [63:0] q, qm, qp; @@ -180,7 +181,7 @@ module rounder_div (Result, DenormIO, Flags, rm, P, OvEn, // overflow has occurred, the overflow trap is enabled, and a conversion // is being performed. assign OvCon = OverFlow & OvEn; - assign Result = (P&~OvCon) ? {Rsign, Rexp[7:0], Rmant[51:29], {32{vss}}} + assign Result = (P&~OvCon) ? { {32{1'b1}}, Rsign, Rexp[7:0], Rmant[51:29]} : {Rsign, Rexp, Rmant}; endmodule // rounder diff --git a/wally-pipelined/src/fpu/sbtm.sv b/wally-pipelined/src/fpu/sbtm.sv index abd1bba77..5c12f7b21 100644 --- a/wally-pipelined/src/fpu/sbtm.sv +++ b/wally-pipelined/src/fpu/sbtm.sv @@ -1,33 +1,35 @@ -// module sbtm (input logic [11:0] a, output logic [10:0] ia_out); +module sbtm (input logic [11:0] a, output logic [10:0] ia_out); -// // bit partitions -// logic [3:0] x0; -// logic [2:0] x1; -// logic [3:0] x2; -// logic [2:0] x2_1cmp; -// // mem outputs -// logic [12:0] y0; -// logic [4:0] y1; -// // input to CPA -// logic [14:0] op1; -// logic [14:0] op2; -// logic [14:0] p; + // bit partitions + logic [3:0] x0; + logic [2:0] x1; + logic [3:0] x2; + logic [2:0] x2_1cmp; + // mem outputs + logic [12:0] y0; + logic [4:0] y1; + // input to CPA + logic [14:0] op1; + logic [14:0] op2; + logic [14:0] p; + logic cout; -// assign x0 = a[10:7]; -// assign x1 = a[6:4]; -// assign x2 = a[3:0]; + assign x0 = a[10:7]; + assign x1 = a[6:4]; + assign x2 = a[3:0]; -// sbtm_a0 mem1 ({x0, x1}, y0); -// // 1s cmp per sbtm/stam -// assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; -// sbtm_a1 mem2 ({x0, x2_1cmp}, y1); -// assign op1 = {1'b0, y0, 1'b0}; -// // 1s cmp per sbtm/stam -// assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} : -// {1'b0, 8'b0, y1, 1'b1}; -// // CPA + sbtm_a0 mem1 ({x0, x1}, y0); + // 1s cmp per sbtm/stam + assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; + sbtm_a1 mem2 ({x0, x2_1cmp}, y1); + assign op1 = {1'b0, y0, 1'b0}; + // 1s cmp per sbtm/stam + assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} : + {1'b0, 8'b0, y1, 1'b1}; + // CPA // adder #(15) cp1 (op1, op2, 1'b0, p, cout); -// //assign ia_out = {p[14:4], {53{1'b0}}}; -// assign ia_out = p[14:4]; + assign {cout, p} = op1 + op2; + //assign ia_out = {p[14:4], {53{1'b0}}}; + assign ia_out = p[14:4]; -// endmodule // sbtm +endmodule // sbtm diff --git a/wally-pipelined/src/fpu/sbtm2.sv b/wally-pipelined/src/fpu/sbtm2.sv index e7b9b6c2f..3052f60f1 100644 --- a/wally-pipelined/src/fpu/sbtm2.sv +++ b/wally-pipelined/src/fpu/sbtm2.sv @@ -1,39 +1,39 @@ -// module sbtm2 (input logic [11:0] a, output logic [10:0] y); +module sbtm2 (input logic [11:0] a, output logic [10:0] y); -// // bit partitions -// logic [4:0] x0; -// logic [2:0] x1; -// logic [3:0] x2; -// logic [2:0] x2_1cmp; -// // mem outputs -// logic [12:0] y0; -// logic [5:0] y1; -// // input to CPA -// logic [14:0] op1; -// logic [14:0] op2; -// logic [14:0] p; -// logic cout; + // bit partitions + logic [4:0] x0; + logic [2:0] x1; + logic [3:0] x2; + logic [2:0] x2_1cmp; + // mem outputs + logic [12:0] y0; + logic [5:0] y1; + // input to CPA + logic [14:0] op1; + logic [14:0] op2; + logic [14:0] p; + logic cout; -// assign x0 = a[11:7]; -// assign x1 = a[6:4]; -// assign x2 = a[3:0]; + assign x0 = a[11:7]; + assign x1 = a[6:4]; + assign x2 = a[3:0]; -// sbtm_a2 mem1 ({x0[3:0], x1}, y0); -// assign op1 = {1'b0, y0, 1'b0}; + sbtm_a2 mem1 ({x0[3:0], x1}, y0); + assign op1 = {1'b0, y0, 1'b0}; -// // 1s cmp per sbtm/stam -// assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; -// sbtm_a3 mem2 ({x0, x2_1cmp}, y1); -// // 1s cmp per sbtm/stam -// assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} : -// {8'b0, y1, 1'b1}; + // 1s cmp per sbtm/stam + assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; + sbtm_a3 mem2 ({x0, x2_1cmp}, y1); + // 1s cmp per sbtm/stam + assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} : + {8'b0, y1, 1'b1}; -// // CPA -// bk15 cp1 (cout, p, op1, op2, 1'b0); -// assign y = p[14:4]; + // CPA + bk15 cp1 (cout, p, op1, op2, 1'b0); + assign y = p[14:4]; -// endmodule // sbtm2 +endmodule // sbtm2 diff --git a/wally-pipelined/src/fpu/unpacking.sv b/wally-pipelined/src/fpu/unpacking.sv index b22d1896f..2280f3803 100644 --- a/wally-pipelined/src/fpu/unpacking.sv +++ b/wally-pipelined/src/fpu/unpacking.sv @@ -15,7 +15,7 @@ module unpacking ( output logic XInfE, YInfE, ZInfE, output logic XExpMaxE ); - + //***rename to make significand = 1.frac m = significand logic XFracZero, YFracZero, ZFracZero; // input fraction zero logic XExpZero, YExpZero, ZExpZero; // input exponent zero logic [63:0] Addend; // value to add (Z or zero) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 648b3594e..980248b6d 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -98,7 +98,7 @@ string tests32f[] = '{ "rv64f/I-FCVT-LU-S-01", "2000", "rv64f/I-FCVT-W-S-01", "2000", "rv64f/I-FCVT-WU-S-01", "2000", - // "rv64f/I-FDIV-S-01", "2000", + "rv64f/I-FDIV-S-01", "2000", "rv64f/I-FEQ-S-01", "2000", "rv64f/I-FLE-S-01", "2000", "rv64f/I-FLT-S-01", "2000", @@ -112,7 +112,7 @@ string tests32f[] = '{ "rv64f/I-FSGNJ-S-01", "2000", "rv64f/I-FSGNJN-S-01", "2000", "rv64f/I-FSGNJX-S-01", "2000", - // "rv64f/I-FSQRT-S-01", "2000", + "rv64f/I-FSQRT-S-01", "2000", "rv64f/I-FSUB-S-01", "2000" }; @@ -124,14 +124,14 @@ string tests32f[] = '{ // "rv64d/I-FDIV-D-01", "2000", "rv64d/I-FCVT-D-L-01", "2000", "rv64d/I-FCVT-D-LU-01", "2000", - "rv64d/I-FCVT-D-S-01", "2000", //the number to be converted is in the lower 32 bits need to change the test + "rv64d/I-FCVT-D-S-01", "2000", "rv64d/I-FCVT-D-W-01", "2000", "rv64d/I-FCVT-D-WU-01", "2000", "rv64d/I-FCVT-L-D-01", "2000", "rv64d/I-FCVT-LU-D-01", "2000", - "rv64d/I-FCVT-S-D-01", "2000", //the result is in the lower 32 bits needs to be changed in the imperas test + "rv64d/I-FCVT-S-D-01", "2000", "rv64d/I-FCVT-W-D-01", "2000", - "rv64d/I-FCVT-WU-D-01", "2000", //this test needs to be fixed it expects 2^64-1 rather then 2^32-1 (specified in spec) + "rv64d/I-FCVT-WU-D-01", "2000", "rv64d/I-FNMADD-D-01", "2000", "rv64d/I-FNMSUB-D-01", "2000", "rv64d/I-FMSUB-D-01", "2000", @@ -147,7 +147,7 @@ string tests32f[] = '{ "rv64d/I-FSGNJ-D-01", "2000", "rv64d/I-FSGNJN-D-01", "2000", "rv64d/I-FSGNJX-D-01", "2000", - // "rv64d/I-FSQRTD-01", "2000", + // "rv64d/I-FSQRT-D-01", "2000", "rv64d/I-FSUB-D-01", "2000" };