From 3523318acba41aa6648779708ced3df3cb100794 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 13:51:05 -0800 Subject: [PATCH] Synthesis with memories --- src/generic/mem/ram1p1rwbe.sv | 16 +++------------- src/generic/mem/ram1p1rwbe_64x128.sv | 3 ++- src/generic/mem/ram1p1rwbe_64x22.sv | 10 ++++++---- src/generic/mem/ram1p1rwbe_64x44.sv | 9 +++++---- src/generic/mem/ram2p1r1wbe.sv | 6 +++--- src/generic/mem/ram2p1r1wbe_1024x36.sv | 8 ++++++-- src/generic/mem/ram2p1r1wbe_1024x68.sv | 6 ++++-- src/generic/mem/ram2p1r1wbe_64x32.sv | 7 +++++-- src/generic/mem/rom1p1r.sv | 4 ++-- synthDC/.synopsys_dc.setup | 2 ++ synthDC/extractSummary.py | 14 +++++++------- synthDC/wallySynth.py | 2 +- 12 files changed, 46 insertions(+), 41 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f1e784c13..7a7dadbed 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -49,7 +49,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 64) begin + if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -59,7 +59,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag genvar index; // 64 x 44-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -69,17 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin - genvar index; - // 64 x 128-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); - - end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin + end else if (`USE_SRAM == 1 & WIDTH == 22 & DEPTH == 32) begin // RV32 cache tag genvar index; // 64 x 22-bit SRAM logic [WIDTH-1:0] BitWriteMask; diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index fa8e32f0b..a28b64e9a 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -35,6 +35,7 @@ module ram1p1rwbe_64x128( ); // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor - generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + //generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + ts1n28hpcpsvtb64x128m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 84c8d1b75..8b04c7979 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -29,12 +29,14 @@ module ram1p1rwbe_64x22( input logic CEB, input logic WEB, input logic [5:0] A, - input logic [127:0] D, - input logic [127:0] BWEB, - output logic [127:0] Q + input logic [21:0] D, + input logic [21:0] BWEB, + output logic [21:0] Q ); // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor - generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + // use part of a larger RAM to avoid generating more flavors of RAM + ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); + //generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 7fa71f312..080dd9977 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -29,12 +29,13 @@ module ram1p1rwbe_64x44( input logic CEB, input logic WEB, input logic [5:0] A, - input logic [127:0] D, - input logic [127:0] BWEB, - output logic [127:0] Q + input logic [43:0] D, + input logic [43:0] BWEB, + output logic [43:0] Q ); // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor - generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + // generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index da099cdc7..d285dbe16 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( // TRUE Smem macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 68 && DEPTH == 1024) begin + if (`USE_SRAM == 1 & WIDTH == 68 & DEPTH == 1024) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 & WIDTH == 36 & DEPTH == 1024) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -76,7 +76,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 & WIDTH == 2 & DEPTH == 1024) begin logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 0aad7db4a..7ceef23c0 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -42,7 +42,11 @@ module ram2p1r1wbe_1024x36( ); // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor - generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // use part of a larger RAM to avoid generating more flavors of RAM + tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]), + .BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0])); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index e6a6b6257..c6c0f01af 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -42,7 +42,9 @@ module ram2p1r1wbe_1024x68( ); // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor - generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 8bc19637d..da080b2cd 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -42,7 +42,10 @@ module ram2p1r1wbe_64x32( ); // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor - generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + tsdn28hpcpa64x32m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - endmodule diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 64cb9224b..c5c1f8b0a 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -38,10 +38,10 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // Core Memory logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; - if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin + if ((`USE_SRAM == 1) & (DATA_WIDTH == 64)) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); - end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin + end if ((`USE_SRAM == 1) & (DATA_WIDTH == 32)) begin rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); end else begin diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 15367d707..3c8b566a7 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -72,6 +72,8 @@ if {$tech == "tsmc28"} { lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db + lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db + lappend target_library $memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db } # Set up User Information diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 3d939644a..5aeb5aa9f 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -103,7 +103,7 @@ def freqPlot(tech, width, config): freqs = freqsL[ind] freqs, delays, areas = noOutliers(median, freqs, delays, areas) - c = 'blue' if ind else 'green' + c = 'blue' if ind else 'gray' targs = [1000/f for f in freqs] ax1.scatter(targs, delays, color=c) @@ -113,7 +113,7 @@ def freqPlot(tech, width, config): delays = list(flatten(delaysL)) areas = list(flatten(areasL)) - legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + legend_elements = [lines.Line2D([0], [0], color='gray', ls='', marker='o', label='timing achieved'), lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] ax1.legend(handles=legend_elements) @@ -246,8 +246,8 @@ if __name__ == '__main__': TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") techdict = {} - techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) - techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + techdict['sky90'] = TechSpec('gray', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) + techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) current_directory = os.getcwd() final_directory = os.path.join(current_directory, 'wallyplots') @@ -256,10 +256,10 @@ if __name__ == '__main__': synthsintocsv() synthsfromcsv('Summary.csv') - freqPlot('tsmc28', 'rv32', 'e') + freqPlot('tsmc28psyn', 'rv32', 'e') freqPlot('sky90', 'rv32', 'e') plotFeatures('sky90', 'rv64', 'gc') - plotFeatures('tsmc28', 'rv64', 'gc') + plotFeatures('tsmc28psyn', 'rv64', 'gc') plotConfigs('sky90', mod='orig') - plotConfigs('tsmc28', mod='orig') + plotConfigs('tsmc28psyn', mod='orig') normAreaDelay(mod='orig') diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index e2918620a..ef93da7fe 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -19,7 +19,7 @@ if __name__ == '__main__': techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] - freqVaryPct = [0, 10] +# freqVaryPct = [-20, -10, 0, 10, 20] pool = Pool()