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https://github.com/openhwgroup/cvw
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Add all working mcause tests
This commit is contained in:
Domenico Ottolia
parent
a659cfec3f
commit
351c71e812
@ -2,7 +2,7 @@
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##################################
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# testgen-ADD-SUB.py
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#
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# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021
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# dottolia@hmc.edu 1 Mar 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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@ -29,84 +29,164 @@ from random import getrandbits
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# # exit(1)
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def randRegs():
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reg1 = randint(1,31)
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reg2 = randint(1,31)
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reg3 = randint(1,31)
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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reg3 = randint(1,20)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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return str(reg1), str(reg2), str(reg3)
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def writeVector(a, b, storecmd):
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def writeVectors(storecmd):
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global testnum
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#expected = computeExpected(a, b, test)
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#expected = expected % 2**xlen # drop carry if necessary
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#if (expected < 0): # take twos complement
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# expected = 2**xlen + expected
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csr = "mscratch"
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reg1, reg2, reg3 = randRegs()
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lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n"
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
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#lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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#lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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expected = a
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#lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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#lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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if test == "csrrw":
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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# User Software Interrupt: True, 0
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# Supervisor Software Interrupt: True, 1
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# Machine Software Interrupt: True, 2
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# User Timer Interrupt: True, 4
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# writeTest(storecmd, f, r, f"""
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# la x21, 0x2004000
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# """, False, 4)
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# Supervior timer interrupt: True, 5
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# Machine timer interrupt: True, 7
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# User external input: True, 8
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# Supervisor external input: True, 9
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# Machine externa input: True, 11
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elif test == "csrrs": # at some point, try writing a non-zero value first
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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# Instruction address misaligned: False, 0
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# Instruction access fault: False, 1
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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elif test == "csrrc": # at some point, try writing a non-one value first
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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.fill 1, 4, 0
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""", False, 2)
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
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lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
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# Breakpoint
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writeTest(storecmd, f, r, f"""
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ebreak
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""", False, 3)
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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# Load Address Misaligned
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writeTest(storecmd, f, r, f"""
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lw x0, 11(x0)
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""", False, 4)
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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# Load Access fault: False, 5
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expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
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elif test == "csrrwi":
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a = a & 0x1F # imm is only 5 bits
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# Store/AMO address misaligned
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writeTest(storecmd, f, r, f"""
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sw x0, 11(x0)
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""", False, 6)
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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# Environment call from u-mode: only for when only M and U mode enabled?
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# writeTest(storecmd, f, r, f"""
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# ecall
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# """, False, 8, "u")
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expected = a
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elif test == "csrrsi": # at some point, try writing a non-zero value first
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a = a & 0x1F
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# # Environment call from s-mode
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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# ??? BUG ??? Code should be 9, but ends up being 8
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# writeTest(storecmd, f, r, f"""
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# ecall
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# """, False, 8, "s")
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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# Environment call from m-mode
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 11, "m")
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expected = a
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elif test == "csrrci": # at some point, try writing a non-one value first
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a = a & 0x1F
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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# Instruction page fault: 12
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# Load page fault: 13
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# Store/AMO page fault: 15
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
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lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"):
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global testnum
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expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
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expected = code
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if(interrupt):
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expected+=(1 << (wordsize - 1))
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lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
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lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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trapEnd = ""
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before = ""
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if mode != "m":
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before = f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b{"01" if mode == "s" else "00"}0000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrrw x27, mepc, x1
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mret
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# We're now in {mode} mode...
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"""
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trapEnd = f"""j _jend{testnum}"""
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# Setup
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# TODO: Adding 8 to x30 won't work for 32 bit?
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# x31: Old mtvec value
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# x30: trap handler address
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# x29: Old mtvec value for user/supervisor mode
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# x28: Old mstatus value
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# x27: Old mepc value
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# x26: 0 if we should execute mret normally. 1 otherwise. This allows us to stay in machine
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# x25: mcause
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# mode for the next tests
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lines = f"""
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# Testcase {testnum}
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csrrs x31, mtvec, x0
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auipc x30, 0
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addi x30, x30, 12
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j _jtest{testnum}
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# Machine trap vector
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csrrs x25, mcause, x0
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csrrs x1, mepc, x0
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addi x1, x1, 4
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csrrw x0, mepc, x1
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{trapEnd}
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mret
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# Actual test
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_jtest{testnum}:
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csrrw x0, mtvec, x30
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# Start test code
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{before}
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{test}
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# Finished test. Reset to old mtvec
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_jend{testnum}:
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csrrw x0, mtvec, x31
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"""
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#expected = 42
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lines += storecmd + " x25, " + str(wordsize*testnum) + "(x6)\n"
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#lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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@ -115,16 +195,25 @@ def writeVector(a, b, storecmd):
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r.write(line)
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testnum = testnum+1
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# lines += storecmd + " x0" + ", " + str(wordsize*testnum) + "(x6)\n"
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# #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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# f.write(lines)
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# if (xlen == 32):
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# line = formatrefstr.format(expected)+"\n"
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# else:
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# line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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# r.write(line)
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# testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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tests = ["csrrw"]
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author = "ushakya@hmc.edu & dottolia@hmc.edu"
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 60;
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numrand = 30;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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@ -140,54 +229,48 @@ for xlen in xlens:
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else:
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storecmd = "sd"
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wordsize = 8
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for test in tests:
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corners = [
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0, 1, 2, 0x1E, 0x1F, 0xFF,
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-CAUSE"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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corners = [
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-CAUSE"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# print directed and random test vectors
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for a in corners:
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for b in corners:
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writeVector(a, b, storecmd)
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for i in range(0,numrand):
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a = getrandbits(xlen)
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b = getrandbits(xlen)
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writeVector(a, b, storecmd)
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# print directed and random test vectors
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for i in range(0,numrand):
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writeVectors(storecmd)
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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