diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 4d90185c3..50f3e68f0 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -81,8 +81,8 @@ module fdivsqrtpreproc (
   assign PreprocX = Xm[`NF-1:0]<<L;
   assign PreprocY = Ym[`NF-1:0]<<m;
 
-  // assign ZeroDiff = m - L;
-  // assign p = ZeroDiff[`DIVBLEN] ? '0 : ZeroDiff;
+  assign ZeroDiff = m - L;
+  assign p = ZeroDiff[`DIVBLEN] ? '0 : ZeroDiff;
 
   // assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
   // assign pPrTrunc = pPlusr[`LOGRK-1:0];