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https://github.com/openhwgroup/cvw
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Minor dcache cleanup.
This commit is contained in:
Ross Thompson
parent
243728d089
commit
34c11ca8d5
13
wally-pipelined/src/cache/dcache.sv
vendored
13
wally-pipelined/src/cache/dcache.sv
vendored
@ -55,13 +55,7 @@ module dcache
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output logic [`PA_BITS-1:0] BasePAdrM,
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output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
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// temp
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//output logic SelUncached,
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output logic SelFlush,
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//input logic FetchCountFlag,
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//output logic CntEn,
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//output logic CntReset,
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input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData,
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@ -303,26 +297,19 @@ module dcache
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.CPUBusy,
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.CacheableM,
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.IgnoreRequest,
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.AHBAck, // from ahb
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.CacheHit,
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.FetchCountFlag(1'b0),
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.VictimDirty,
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.DCacheStall,
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.CommittedM,
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.DCacheMiss,
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.DCacheAccess,
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.AHBRead(),
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.AHBWrite(),
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.SelAdrM,
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.CntEn(),
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.SetValid,
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.ClearValid,
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.SetDirty,
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.ClearDirty,
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.SRAMWordWriteEnableM,
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.SRAMBlockWriteEnableM,
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.CntReset(),
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.SelUncached(),
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.SelEvict,
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.SelFlush,
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.FlushAdrCntEn,
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97
wally-pipelined/src/cache/dcachefsm.sv
vendored
97
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -40,10 +40,9 @@ module dcachefsm
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// hptw inputs
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input logic IgnoreRequest,
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// Bus inputs
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input logic AHBAck, // from ahb
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input logic BUSACK,
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// dcache internals
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input logic CacheHit,
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input logic FetchCountFlag,
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input logic VictimDirty,
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input logic FlushAdrFlag,
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@ -54,24 +53,18 @@ module dcachefsm
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output logic DCacheMiss,
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output logic DCacheAccess,
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// Bus outputs
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output logic AHBRead,
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output logic AHBWrite,
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output logic DCWriteLine,
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output logic DCFetchLine,
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input logic BUSACK,
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// dcache internals
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output logic [1:0] SelAdrM,
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output logic CntEn,
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output logic SetValid,
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output logic ClearValid,
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output logic SetDirty,
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output logic ClearDirty,
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output logic SRAMWordWriteEnableM,
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output logic SRAMBlockWriteEnableM,
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output logic CntReset,
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output logic SelUncached,
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output logic SelEvict,
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output logic LRUWriteEn,
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output logic SelFlush,
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@ -83,7 +76,6 @@ module dcachefsm
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);
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logic PreCntEn;
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logic AnyCPUReqM;
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typedef enum {STATE_READY,
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@ -96,11 +88,6 @@ module dcachefsm
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STATE_MISS_READ_WORD_DELAY,
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STATE_MISS_WRITE_WORD,
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STATE_UNCACHED_WRITE,
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STATE_UNCACHED_WRITE_DONE,
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STATE_UNCACHED_READ,
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STATE_UNCACHED_READ_DONE,
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STATE_CPU_BUSY,
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STATE_CPU_BUSY_FINISH_AMO,
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@ -111,7 +98,6 @@ module dcachefsm
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(* mark_debug = "true" *) statetype CurrState, NextState;
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assign AnyCPUReqM = |MemRWM | (|AtomicM);
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assign CntEn = PreCntEn & AHBAck;
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// outputs for the performance counters.
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assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
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@ -125,18 +111,13 @@ module dcachefsm
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always_comb begin
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DCacheStall = 1'b0;
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SelAdrM = 2'b00;
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PreCntEn = 1'b0;
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SetValid = 1'b0;
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ClearValid = 1'b0;
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SetDirty = 1'b0;
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ClearDirty = 1'b0;
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SRAMWordWriteEnableM = 1'b0;
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SRAMBlockWriteEnableM = 1'b0;
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CntReset = 1'b0;
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AHBRead = 1'b0;
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AHBWrite = 1'b0;
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CommittedM = 1'b0;
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SelUncached = 1'b0;
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SelEvict = 1'b0;
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LRUWriteEn = 1'b0;
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SelFlush = 1'b0;
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@ -152,10 +133,7 @@ module dcachefsm
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case (CurrState)
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STATE_READY: begin
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CntReset = 1'b0;
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DCacheStall = 1'b0;
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AHBRead = 1'b0;
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AHBWrite = 1'b0;
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SelAdrM = 2'b00;
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SRAMWordWriteEnableM = 1'b0;
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SetDirty = 1'b0;
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@ -231,35 +209,17 @@ module dcachefsm
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// read or write miss valid cached
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else if((|MemRWM) & CacheableM & ~CacheHit) begin
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NextState = STATE_MISS_FETCH_WDV;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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DCFetchLine = 1'b1;
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end
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// uncached write
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else if(MemRWM[0] & ~CacheableM) begin
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NextState = STATE_UNCACHED_WRITE;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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end
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// uncached read
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else if(MemRWM[1] & ~CacheableM) begin
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NextState = STATE_UNCACHED_READ;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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AHBRead = 1'b1;
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end
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else NextState = STATE_READY;
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end
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STATE_MISS_FETCH_WDV: begin
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DCacheStall = 1'b1;
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PreCntEn = 1'b1;
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AHBRead = 1'b1;
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SelAdrM = 2'b10;
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CommittedM = 1'b1;
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//if (FetchCountFlag & AHBAck) begin
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if (BUSACK) begin
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NextState = STATE_MISS_FETCH_DONE;
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end else begin
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@ -270,7 +230,6 @@ module dcachefsm
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STATE_MISS_FETCH_DONE: begin
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DCacheStall = 1'b1;
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SelAdrM = 2'b10;
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CntReset = 1'b1;
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CommittedM = 1'b1;
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if(VictimDirty) begin
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NextState = STATE_MISS_EVICT_DIRTY;
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@ -350,12 +309,9 @@ module dcachefsm
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STATE_MISS_EVICT_DIRTY: begin
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DCacheStall = 1'b1;
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PreCntEn = 1'b1;
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AHBWrite = 1'b1;
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SelAdrM = 2'b10;
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CommittedM = 1'b1;
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SelEvict = 1'b1;
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//if(FetchCountFlag & AHBAck) begin
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if(BUSACK) begin
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NextState = STATE_MISS_WRITE_CACHE_BLOCK;
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end else begin
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@ -393,53 +349,6 @@ module dcachefsm
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end
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end
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STATE_UNCACHED_WRITE : begin
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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CommittedM = 1'b1;
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if(AHBAck) begin
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NextState = STATE_UNCACHED_WRITE_DONE;
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end else begin
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NextState = STATE_UNCACHED_WRITE;
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end
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end
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STATE_UNCACHED_READ: begin
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DCacheStall = 1'b1;
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AHBRead = 1'b1;
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CommittedM = 1'b1;
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if(AHBAck) begin
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NextState = STATE_UNCACHED_READ_DONE;
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end else begin
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NextState = STATE_UNCACHED_READ;
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end
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end
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STATE_UNCACHED_WRITE_DONE: begin
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CommittedM = 1'b1;
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SelAdrM = 2'b00;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b10;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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STATE_UNCACHED_READ_DONE: begin
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CommittedM = 1'b1;
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SelUncached = 1'b1;
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SelAdrM = 2'b00;
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if(CPUBusy) begin
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NextState = STATE_CPU_BUSY;
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SelAdrM = 2'b10;
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end
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else begin
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NextState = STATE_READY;
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end
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end
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STATE_FLUSH: begin
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DCacheStall = 1'b1;
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CommittedM = 1'b1;
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@ -447,7 +356,6 @@ module dcachefsm
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SelFlush = 1'b1;
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FlushAdrCntEn = 1'b1;
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FlushWayCntEn = 1'b1;
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CntReset = 1'b1;
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if(VictimDirty) begin
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NextState = STATE_FLUSH_WRITE_BACK;
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FlushAdrCntEn = 1'b0;
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@ -465,12 +373,9 @@ module dcachefsm
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STATE_FLUSH_WRITE_BACK: begin
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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SelAdrM = 2'b11;
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CommittedM = 1'b1;
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SelFlush = 1'b1;
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PreCntEn = 1'b1;
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//if(FetchCountFlag & AHBAck) begin
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if(BUSACK) begin
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NextState = STATE_FLUSH_CLEAR_DIRTY;
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end else begin
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@ -357,13 +357,8 @@ module lsu
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.BasePAdrM,
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.ReadDataBlockSetsM,
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// temp
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//.SelUncached,
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.SelFlush,
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.DCacheMemWriteData,
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//.FetchCountFlag,
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//.CntEn,
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//.CntReset,
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.DCFetchLine,
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.DCWriteLine,
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.BUSACK,
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@ -443,9 +438,7 @@ module lsu
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typedef enum {STATE_BUS_READY,
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STATE_BUS_FETCH_WDV,
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STATE_BUS_FETCH_DONE,
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STATE_BUS_EVICT_DIRTY,
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STATE_BUS_WRITE_CACHE_BLOCK,
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STATE_BUS_WRITE_WDV,
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STATE_BUS_UNCACHED_WRITE,
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STATE_BUS_UNCACHED_WRITE_DONE,
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STATE_BUS_UNCACHED_READ,
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@ -495,7 +488,7 @@ module lsu
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end
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// D$ Write Line
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else if(DCWriteLine) begin
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BusNextState = STATE_BUS_EVICT_DIRTY;
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BusNextState = STATE_BUS_WRITE_WDV;
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CntReset = 1'b1;
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BusStall = 1'b1;
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end
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@ -547,7 +540,7 @@ module lsu
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end
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end
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STATE_BUS_EVICT_DIRTY: begin
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STATE_BUS_WRITE_WDV: begin
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BusStall = 1'b1;
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PreCntEn = 1'b1;
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DCtoAHBWriteM = 1'b1;
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@ -556,7 +549,7 @@ module lsu
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BusNextState = STATE_BUS_READY;
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BUSACK = 1'b1;
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end else begin
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BusNextState = STATE_BUS_EVICT_DIRTY;
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BusNextState = STATE_BUS_WRITE_WDV;
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end
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end
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endcase
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