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Minor dcache cleanup.

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This commit is contained in:
Ross Thompson 2021-12-28 11:29:16 -06:00
parent 243728d089
commit 34c11ca8d5
3 changed files with 5 additions and 120 deletions
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13
wally-pipelined/src/cache/dcache.sv vendored
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@ -55,13 +55,7 @@ module dcache
output logic [`PA_BITS-1:0] BasePAdrM, output logic [`PA_BITS-1:0] BasePAdrM,
output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
// temp
//output logic SelUncached,
output logic SelFlush, output logic SelFlush,
//input logic FetchCountFlag,
//output logic CntEn,
//output logic CntReset,
input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData,
@ -303,26 +297,19 @@ module dcache
.CPUBusy, .CPUBusy,
.CacheableM, .CacheableM,
.IgnoreRequest, .IgnoreRequest,
.AHBAck, // from ahb
.CacheHit, .CacheHit,
.FetchCountFlag(1'b0),
.VictimDirty, .VictimDirty,
.DCacheStall, .DCacheStall,
.CommittedM, .CommittedM,
.DCacheMiss, .DCacheMiss,
.DCacheAccess, .DCacheAccess,
.AHBRead(),
.AHBWrite(),
.SelAdrM, .SelAdrM,
.CntEn(),
.SetValid, .SetValid,
.ClearValid, .ClearValid,
.SetDirty, .SetDirty,
.ClearDirty, .ClearDirty,
.SRAMWordWriteEnableM, .SRAMWordWriteEnableM,
.SRAMBlockWriteEnableM, .SRAMBlockWriteEnableM,
.CntReset(),
.SelUncached(),
.SelEvict, .SelEvict,
.SelFlush, .SelFlush,
.FlushAdrCntEn, .FlushAdrCntEn,

97
wally-pipelined/src/cache/dcachefsm.sv vendored
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@ -40,10 +40,9 @@ module dcachefsm
// hptw inputs // hptw inputs
input logic IgnoreRequest, input logic IgnoreRequest,
// Bus inputs // Bus inputs
input logic AHBAck, // from ahb input logic BUSACK,
// dcache internals // dcache internals
input logic CacheHit, input logic CacheHit,
input logic FetchCountFlag,
input logic VictimDirty, input logic VictimDirty,
input logic FlushAdrFlag, input logic FlushAdrFlag,
@ -54,24 +53,18 @@ module dcachefsm
output logic DCacheMiss, output logic DCacheMiss,
output logic DCacheAccess, output logic DCacheAccess,
// Bus outputs // Bus outputs
output logic AHBRead,
output logic AHBWrite,
output logic DCWriteLine, output logic DCWriteLine,
output logic DCFetchLine, output logic DCFetchLine,
input logic BUSACK,
// dcache internals // dcache internals
output logic [1:0] SelAdrM, output logic [1:0] SelAdrM,
output logic CntEn,
output logic SetValid, output logic SetValid,
output logic ClearValid, output logic ClearValid,
output logic SetDirty, output logic SetDirty,
output logic ClearDirty, output logic ClearDirty,
output logic SRAMWordWriteEnableM, output logic SRAMWordWriteEnableM,
output logic SRAMBlockWriteEnableM, output logic SRAMBlockWriteEnableM,
output logic CntReset,
output logic SelUncached,
output logic SelEvict, output logic SelEvict,
output logic LRUWriteEn, output logic LRUWriteEn,
output logic SelFlush, output logic SelFlush,
@ -83,7 +76,6 @@ module dcachefsm
); );
logic PreCntEn;
logic AnyCPUReqM; logic AnyCPUReqM;
typedef enum {STATE_READY, typedef enum {STATE_READY,
@ -96,11 +88,6 @@ module dcachefsm
STATE_MISS_READ_WORD_DELAY, STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD, STATE_MISS_WRITE_WORD,
STATE_UNCACHED_WRITE,
STATE_UNCACHED_WRITE_DONE,
STATE_UNCACHED_READ,
STATE_UNCACHED_READ_DONE,
STATE_CPU_BUSY, STATE_CPU_BUSY,
STATE_CPU_BUSY_FINISH_AMO, STATE_CPU_BUSY_FINISH_AMO,
@ -111,7 +98,6 @@ module dcachefsm
(* mark_debug = "true" *) statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
assign AnyCPUReqM = |MemRWM | (|AtomicM); assign AnyCPUReqM = |MemRWM | (|AtomicM);
assign CntEn = PreCntEn & AHBAck;
// outputs for the performance counters. // outputs for the performance counters.
assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY; assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
@ -125,18 +111,13 @@ module dcachefsm
always_comb begin always_comb begin
DCacheStall = 1'b0; DCacheStall = 1'b0;
SelAdrM = 2'b00; SelAdrM = 2'b00;
PreCntEn = 1'b0;
SetValid = 1'b0; SetValid = 1'b0;
ClearValid = 1'b0; ClearValid = 1'b0;
SetDirty = 1'b0; SetDirty = 1'b0;
ClearDirty = 1'b0; ClearDirty = 1'b0;
SRAMWordWriteEnableM = 1'b0; SRAMWordWriteEnableM = 1'b0;
SRAMBlockWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0;
CntReset = 1'b0;
AHBRead = 1'b0;
AHBWrite = 1'b0;
CommittedM = 1'b0; CommittedM = 1'b0;
SelUncached = 1'b0;
SelEvict = 1'b0; SelEvict = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
SelFlush = 1'b0; SelFlush = 1'b0;
@ -152,10 +133,7 @@ module dcachefsm
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
CntReset = 1'b0;
DCacheStall = 1'b0; DCacheStall = 1'b0;
AHBRead = 1'b0;
AHBWrite = 1'b0;
SelAdrM = 2'b00; SelAdrM = 2'b00;
SRAMWordWriteEnableM = 1'b0; SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0; SetDirty = 1'b0;
@ -231,35 +209,17 @@ module dcachefsm
// read or write miss valid cached // read or write miss valid cached
else if((|MemRWM) & CacheableM & ~CacheHit) begin else if((|MemRWM) & CacheableM & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
CntReset = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
DCFetchLine = 1'b1; DCFetchLine = 1'b1;
end end
// uncached write
else if(MemRWM[0] & ~CacheableM) begin
NextState = STATE_UNCACHED_WRITE;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBWrite = 1'b1;
end
// uncached read
else if(MemRWM[1] & ~CacheableM) begin
NextState = STATE_UNCACHED_READ;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBRead = 1'b1;
end
else NextState = STATE_READY; else NextState = STATE_READY;
end end
STATE_MISS_FETCH_WDV: begin STATE_MISS_FETCH_WDV: begin
DCacheStall = 1'b1; DCacheStall = 1'b1;
PreCntEn = 1'b1;
AHBRead = 1'b1;
SelAdrM = 2'b10; SelAdrM = 2'b10;
CommittedM = 1'b1; CommittedM = 1'b1;
//if (FetchCountFlag & AHBAck) begin
if (BUSACK) begin if (BUSACK) begin
NextState = STATE_MISS_FETCH_DONE; NextState = STATE_MISS_FETCH_DONE;
end else begin end else begin
@ -270,7 +230,6 @@ module dcachefsm
STATE_MISS_FETCH_DONE: begin STATE_MISS_FETCH_DONE: begin
DCacheStall = 1'b1; DCacheStall = 1'b1;
SelAdrM = 2'b10; SelAdrM = 2'b10;
CntReset = 1'b1;
CommittedM = 1'b1; CommittedM = 1'b1;
if(VictimDirty) begin if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
@ -350,12 +309,9 @@ module dcachefsm
STATE_MISS_EVICT_DIRTY: begin STATE_MISS_EVICT_DIRTY: begin
DCacheStall = 1'b1; DCacheStall = 1'b1;
PreCntEn = 1'b1;
AHBWrite = 1'b1;
SelAdrM = 2'b10; SelAdrM = 2'b10;
CommittedM = 1'b1; CommittedM = 1'b1;
SelEvict = 1'b1; SelEvict = 1'b1;
//if(FetchCountFlag & AHBAck) begin
if(BUSACK) begin if(BUSACK) begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK; NextState = STATE_MISS_WRITE_CACHE_BLOCK;
end else begin end else begin
@ -393,53 +349,6 @@ module dcachefsm
end end
end end
STATE_UNCACHED_WRITE : begin
DCacheStall = 1'b1;
AHBWrite = 1'b1;
CommittedM = 1'b1;
if(AHBAck) begin
NextState = STATE_UNCACHED_WRITE_DONE;
end else begin
NextState = STATE_UNCACHED_WRITE;
end
end
STATE_UNCACHED_READ: begin
DCacheStall = 1'b1;
AHBRead = 1'b1;
CommittedM = 1'b1;
if(AHBAck) begin
NextState = STATE_UNCACHED_READ_DONE;
end else begin
NextState = STATE_UNCACHED_READ;
end
end
STATE_UNCACHED_WRITE_DONE: begin
CommittedM = 1'b1;
SelAdrM = 2'b00;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
else begin
NextState = STATE_READY;
end
end
STATE_UNCACHED_READ_DONE: begin
CommittedM = 1'b1;
SelUncached = 1'b1;
SelAdrM = 2'b00;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
else begin
NextState = STATE_READY;
end
end
STATE_FLUSH: begin STATE_FLUSH: begin
DCacheStall = 1'b1; DCacheStall = 1'b1;
CommittedM = 1'b1; CommittedM = 1'b1;
@ -447,7 +356,6 @@ module dcachefsm
SelFlush = 1'b1; SelFlush = 1'b1;
FlushAdrCntEn = 1'b1; FlushAdrCntEn = 1'b1;
FlushWayCntEn = 1'b1; FlushWayCntEn = 1'b1;
CntReset = 1'b1;
if(VictimDirty) begin if(VictimDirty) begin
NextState = STATE_FLUSH_WRITE_BACK; NextState = STATE_FLUSH_WRITE_BACK;
FlushAdrCntEn = 1'b0; FlushAdrCntEn = 1'b0;
@ -465,12 +373,9 @@ module dcachefsm
STATE_FLUSH_WRITE_BACK: begin STATE_FLUSH_WRITE_BACK: begin
DCacheStall = 1'b1; DCacheStall = 1'b1;
AHBWrite = 1'b1;
SelAdrM = 2'b11; SelAdrM = 2'b11;
CommittedM = 1'b1; CommittedM = 1'b1;
SelFlush = 1'b1; SelFlush = 1'b1;
PreCntEn = 1'b1;
//if(FetchCountFlag & AHBAck) begin
if(BUSACK) begin if(BUSACK) begin
NextState = STATE_FLUSH_CLEAR_DIRTY; NextState = STATE_FLUSH_CLEAR_DIRTY;
end else begin end else begin

15
wally-pipelined/src/lsu/lsu.sv
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@ -357,13 +357,8 @@ module lsu
.BasePAdrM, .BasePAdrM,
.ReadDataBlockSetsM, .ReadDataBlockSetsM,
// temp
//.SelUncached,
.SelFlush, .SelFlush,
.DCacheMemWriteData, .DCacheMemWriteData,
//.FetchCountFlag,
//.CntEn,
//.CntReset,
.DCFetchLine, .DCFetchLine,
.DCWriteLine, .DCWriteLine,
.BUSACK, .BUSACK,
@ -443,9 +438,7 @@ module lsu
typedef enum {STATE_BUS_READY, typedef enum {STATE_BUS_READY,
STATE_BUS_FETCH_WDV, STATE_BUS_FETCH_WDV,
STATE_BUS_FETCH_DONE, STATE_BUS_WRITE_WDV,
STATE_BUS_EVICT_DIRTY,
STATE_BUS_WRITE_CACHE_BLOCK,
STATE_BUS_UNCACHED_WRITE, STATE_BUS_UNCACHED_WRITE,
STATE_BUS_UNCACHED_WRITE_DONE, STATE_BUS_UNCACHED_WRITE_DONE,
STATE_BUS_UNCACHED_READ, STATE_BUS_UNCACHED_READ,
@ -495,7 +488,7 @@ module lsu
end end
// D$ Write Line // D$ Write Line
else if(DCWriteLine) begin else if(DCWriteLine) begin
BusNextState = STATE_BUS_EVICT_DIRTY; BusNextState = STATE_BUS_WRITE_WDV;
CntReset = 1'b1; CntReset = 1'b1;
BusStall = 1'b1; BusStall = 1'b1;
end end
@ -547,7 +540,7 @@ module lsu
end end
end end
STATE_BUS_EVICT_DIRTY: begin STATE_BUS_WRITE_WDV: begin
BusStall = 1'b1; BusStall = 1'b1;
PreCntEn = 1'b1; PreCntEn = 1'b1;
DCtoAHBWriteM = 1'b1; DCtoAHBWriteM = 1'b1;
@ -556,7 +549,7 @@ module lsu
BusNextState = STATE_BUS_READY; BusNextState = STATE_BUS_READY;
BUSACK = 1'b1; BUSACK = 1'b1;
end else begin end else begin
BusNextState = STATE_BUS_EVICT_DIRTY; BusNextState = STATE_BUS_WRITE_WDV;
end end
end end
endcase endcase