From 348187ea70c74b17bc7f43f90c174e8c9055d68e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 16 Sep 2021 17:12:51 -0500
Subject: [PATCH] Added counters to walk through d cache flush.

---
 wally-pipelined/src/cache/dcache.sv | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 31130d387..7aff773ef 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -126,7 +126,16 @@ module dcache
   logic [TAGLEN-1:0] 	       VictimTag;
 
   logic [INDEXLEN-1:0] 	       FlushAdr;
+  logic [INDEXLEN-1:0] 	       FlushAdrP1;
+  logic 		       FlushAdrCntEn;
+  logic 		       FlushAdrCntRst;
+  logic 		       FlushAdrFlag;
+  
   logic [NUMWAYS-1:0] 	       FlushWay;
+  logic [NUMWAYS-1:0] 	       NextFlushWay;
+  logic 		       FlushWayCntEn;
+  logic 		       FlushWayCntRst;  
+  
   logic 		       SelFlush;
   
   logic AnyCPUReqM;
@@ -299,6 +308,23 @@ module dcache
 
   assign NextFetchCount = FetchCount + 1'b1;
 
+  // flush address and way generation.
+  flopenr #(INDEXLEN)
+  FlushAdrReg(.clk,
+	      .reset(reset | FlushAdrCntRst),
+	      .en(FlushAdrCntEn),
+	      .d(FlushAdrP1),
+	      .q(FlushAdr));
+
+  flopenl #(NUMWAYS)
+  FlushWayReg(.clk,
+	      .load(reset | FlushWayCntRst),
+	      .en(FlushWayCntEn),
+	      .val({{NUMWAYS-1{1'b0}}, 1'b1}),
+	      .d(NextFlushWay),
+	      .q(FlushWay));
+  
+
   assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
 
   // controller