Get's the fpga building again after the git history rewrite.

This commit is contained in:
Rose Thompson 2023-12-14 17:08:25 -06:00
parent bb712d6860
commit 34631c54d3
3 changed files with 11 additions and 29 deletions

View File

@ -7,6 +7,3 @@ lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW
privileged/csr.sv: logic MENVCFG_REGW
privileged/csr.sv: logic SENVCFG_REGW

File diff suppressed because one or more lines are too long

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@ -6,17 +6,17 @@ dst := IP
#export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108
#export XILINX_PART := xcvu095-ffva2104-2-e
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
#export board := vcu108
# Arty A7
# export XILINX_PART := xc7a100tcsg324-1
# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
# export board := ArtyA7
export XILINX_PART := xc7a100tcsg324-1
export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
export board := ArtyA7
# for Arty A7 and S7 boards
all: FPGA_VCU
all: FPGA_Arty
# VCU 108 and VCU 118 boards
#all: FPGA_VCU
@ -54,7 +54,7 @@ PreProcessFiles:
cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
./insert_debug_comment.sh
# modify config *** RT: eventually setup for variably defined sized memory
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh