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Divider mostly cleaned up
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@ -53,7 +53,7 @@ module intdivrestoring (
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flopenrc #(1) SignedDivideMReg(clk, reset, FlushM, ~StallM, SignedDivideE, SignedDivideM);
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flopenrc #(1) SignedDivideMReg(clk, reset, FlushM, ~StallM, SignedDivideE, SignedDivideM);
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assign SignD = DSavedE[`XLEN-1]; // *** do some of these need pipelining for consecutive divides?
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assign SignD = DSavedE[`XLEN-1]; // *** do some of these need pipelining for consecutive divides?
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assign SignX = XSavedE[`XLEN-1];
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assign SignX = XSavedE[`XLEN-1];
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assign div0 = (DSavedE == 0); // *** eventually replace with just the negedge saved D
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assign div0 = (DSavedE == 0);
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// Take absolute value for signed operations
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// Take absolute value for signed operations
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neg #(`XLEN) negd(DSavedE, DnE);
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neg #(`XLEN) negd(DSavedE, DnE);
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@ -72,7 +72,7 @@ module intdivrestoring (
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intdivrestoringstep step1(Win, XQin, DAbsB, W1, XQ1);
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intdivrestoringstep step1(Win, XQin, DAbsB, W1, XQ1);
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intdivrestoringstep step2(W1, XQ1, DAbsB, Wnext, XQnext);
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intdivrestoringstep step2(W1, XQ1, DAbsB, Wnext, XQnext);
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flopen #(`XLEN) wreg(clk, BusyE, Wnext, W); // *** could become just busy once start moves to its own cycle
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flopen #(`XLEN) wreg(clk, BusyE, Wnext, W);
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flopen #(`XLEN) xreg(clk, BusyE, XQnext, XQ);
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flopen #(`XLEN) xreg(clk, BusyE, XQnext, XQ);
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// Output selection logic in Memory Stage
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// Output selection logic in Memory Stage
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@ -106,23 +106,7 @@ module intdivrestoring (
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done = 0;
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done = 0;
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BusyE = 0;
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BusyE = 0;
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end
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end
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//assign init = (step == 0);
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endmodule // muldiv
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module intdivrestoringstep(
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input logic [`XLEN-1:0] W, XQ, DAbsB,
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output logic [`XLEN-1:0] WOut, XQOut);
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logic [`XLEN-1:0] WShift, WPrime;
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logic qi, qib;
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assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
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assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
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assign qi = ~qib;
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mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
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endmodule
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endmodule
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// *** clean up internal signals
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// *** clean up internal signals
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40
wally-pipelined/src/muldiv/intdivrestoringstep.sv
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40
wally-pipelined/src/muldiv/intdivrestoringstep.sv
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@ -0,0 +1,40 @@
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///////////////////////////////////////////
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// intdivrestoringstep.sv
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//
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// Written: David_Harris@hmc.edu 2 October 2021
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// Modified:
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//
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// Purpose: Restoring integer division using a shift register and subtractor
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module intdivrestoringstep(
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input logic [`XLEN-1:0] W, XQ, DAbsB,
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output logic [`XLEN-1:0] WOut, XQOut);
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logic [`XLEN-1:0] WShift, WPrime;
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logic qi, qib;
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assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
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assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} + 1; // subtractor, carry out determines quotient bit ***replace with add
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assign qi = ~qib;
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mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
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endmodule
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