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Rearranged uart_logger block to only generate if UART is supported

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slmnemo 2024-04-12 21:30:33 -07:00
parent 90040a6a21
commit 342c99d6ea
1 changed files with 8 additions and 6 deletions
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14
testbench/testbench.sv
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@ -580,12 +580,14 @@ module testbench;
end
// Append UART output to file for tests
always @(posedge clk) begin
if (P.UART_SUPPORTED & TEST == "buildroot") begin
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
$fclose(memFile);
if (P.UART_SUPPORTED) begin: uart_logger
always @(posedge clk) begin
if (TEST == "buildroot") begin
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
$fclose(memFile);
end
end
end
end