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Rearranged uart_logger block to only generate if UART is supported

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slmnemo 2024-04-12 21:30:33 -07:00
parent 90040a6a21
commit 342c99d6ea
1 changed files with 8 additions and 6 deletions
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testbench/testbench.sv
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@ -580,8 +580,9 @@ module testbench;
end end
// Append UART output to file for tests // Append UART output to file for tests
if (P.UART_SUPPORTED) begin: uart_logger
always @(posedge clk) begin always @(posedge clk) begin
if (P.UART_SUPPORTED & TEST == "buildroot") begin if (TEST == "buildroot") begin
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
memFile = $fopen(uartoutfilename, "ab"); memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
@ -589,6 +590,7 @@ module testbench;
end end
end end
end end
end
// Termination condition // Termination condition
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed