From 5b4d3f49b02de7b507e335a3242b0760916fc796 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 26 Mar 2024 12:26:03 -0500 Subject: [PATCH] Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv. --- src/cache/cacheLRU.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 865ebc74d..0af178c94 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -149,8 +149,8 @@ module cacheLRU for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize else if(CacheEn) begin // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value - if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = #1 NextLRU; - else CurrLRU = #1 LRUMemory[CacheSetTag]; + if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU; + else CurrLRU = LRUMemory[CacheSetTag]; if(LRUWriteEn) LRUMemory[PAdr] = NextLRU; end end