Crypto formatting cleanup

src/ieu/aes_common/aesinvmixcolumns.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvmixcolumns(input logic [31:0] in, output logic [31:0] out);
+module aesinvmixcolumns(
+   input  logic [31:0] in, 
+   output logic [31:0] out
+);
 
    logic [7:0] in0, in1, in2, in3, temp;
    logic [10:0] xor0, xor1, xor2, xor3;
@@ -42,5 +45,4 @@ module aesinvmixcolumns(input logic [31:0] in, output logic [31:0] out);
    galoismultinverse gm1 (xor1, out[15:8]);
    galoismultinverse gm2 (xor2, out[23:16]);
    galoismultinverse gm3 (xor3, out[31:24]);
-
 endmodule 

src/ieu/aes_common/aesinvsbox.sv

@@ -25,10 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvsbox(input logic [7:0] in, output logic [7:0] out);
+module aesinvsbox(
+	input  logic [7:0] in, 
+	output logic [7:0] out
+);
 
    always_comb
-     begin
 	case(in)
 	  8'h00 : out = 8'h52;
 	  8'h01 : out = 8'h09;
@@ -287,6 +289,4 @@ module aesinvsbox(input logic [7:0] in, output logic [7:0] out);
 	  8'hFE : out = 8'h0C;
 	  8'hFF : out = 8'h7D;
 	endcase
-     end
-
 endmodule

src/ieu/aes_common/aesinvsboxword.sv

@@ -25,14 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvsboxword(input logic [31:0] in, output logic [31:0] out);
+module aesinvsboxword(
+   input  logic [31:0] in, 
+   output logic [31:0] out
+);
    
-   // Declare the SBOX for (least significant) byte 0 of the input
+   // inverse substitutions boxes for each byte of the word
    aesinvsbox sboxb0(.in(in[7:0]),   .out(out[7:0]));
-   // Declare the SBOX for byte 1 of the input
    aesinvsbox sboxb1(.in(in[15:8]),  .out(out[15:8]));
-   // Declare the SBOX for byte 2 of the input
    aesinvsbox sboxb2(.in(in[23:16]), .out(out[23:16]));	
-   // Declare the SBOX for byte 3 of the input	
    aesinvsbox sboxb3(.in(in[31:24]), .out(out[31:24]));   
 endmodule

src/ieu/aes_common/aesinvshiftrow.sv

@@ -25,11 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvshiftrow(input logic [127:0]  DataIn, output logic [127:0] DataOut);
+module aesinvshiftrow(
+   input  logic [127:0] DataIn, 
+   output logic [127:0] DataOut
+);
 
    assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96],
                      DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64],
                      DataIn[95:88], DataIn[119:112], DataIn[15:8], DataIn[39:32],
                      DataIn[63:56], DataIn[87:80], DataIn[111:104], DataIn[7:0]};
-   
 endmodule

src/ieu/aes_common/aesmixcolumns.sv

@@ -26,7 +26,10 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-module aesmixcolumns(input  logic [31:0] in, output logic [31:0] out);
+module aesmixcolumns(
+   input  logic [31:0] in, 
+   output logic [31:0] out
+);
 
    logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp;
 
@@ -44,5 +47,4 @@ module aesmixcolumns(input  logic [31:0] in, output logic [31:0] out);
    assign out3 = in3 ^ temp ^ t2;
    
    assign out = {out0, out1, out2, out3};
-
 endmodule

src/ieu/aes_common/aessbox.sv

@@ -25,11 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aessbox(input logic [7:0] in, output logic [7:0] out);
+module aessbox(
+	input  logic [7:0] in, 
+    output logic [7:0] out
+);
 
    // case statement to lookup the value in the rijndael table
    always_comb 
-     begin
 	case(in)
 	  8'h00 : out = 8'h63;
 	  8'h01 : out = 8'h7C;
@@ -288,6 +290,4 @@ module aessbox(input logic [7:0] in, output logic [7:0] out);
 	  8'hFE : out = 8'hBB;
 	  8'hFF : out = 8'h16;
 	endcase
-     end
-
 endmodule

src/ieu/aes_common/aessboxword.sv

@@ -25,14 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aessboxword(input logic [31:0] in, output logic [31:0] out);   
+module aessboxword(
+   input  logic [31:0] in, 
+   output logic [31:0] out
+);   
    
-   // Declare the SBOX for (least significant) byte 0 of the input
+   // substitutions boxes for each byte of the word
    aessbox sboxb0(.in(in[7:0]), .out(out[7:0]));
-   // Declare the SBOX for byte 1 of the input
    aessbox sboxb1(.in(in[15:8]), .out(out[15:8]));
-   // Declare the SBOX for byte 2 of the input
    aessbox sboxb2(.in(in[23:16]), .out(out[23:16]));	
-   // Declare the SBOX for byte 3 of the input	
    aessbox sboxb3(.in(in[31:24]), .out(out[31:24]));   
 endmodule

src/ieu/aes_common/aesshiftrow.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesshiftrow(input  logic [127:0] DataIn, output logic [127:0] DataOut);
+module aesshiftrow(
+   input  logic [127:0] DataIn, 
+   output logic [127:0] DataOut
+);
 		    
    assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
                      DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],

src/ieu/aes_common/galoismultforward.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module galoismultforward(input logic [7:0] in, output logic [7:0] out);
+module galoismultforward(
+   input  logic [7:0] in, 
+   output logic [7:0] out
+);
 
    logic [7:0] leftshift;
 

src/ieu/aes_common/galoismultinverse.sv

@@ -25,12 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module galoismultinverse(input logic [10:0] in, output logic [7:0] out);
+module galoismultinverse(
+   input  logic [10:0] in, 
+   output logic [7:0]  out
+);
 
    logic [7:0] temp0, temp1;
 
    assign temp0 = in[8]  ? (in[7:0] ^ 8'b00011011) : in[7:0];
    assign temp1 = in[9]  ? (temp0 ^ 8'b00110110)   : temp0;
    assign out   = in[10] ? (temp1 ^ 8'b01101100)   : temp1;
-
 endmodule

src/ieu/aes_instructions/aes32dsi.sv

@@ -25,12 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes32dsi(input logic [1:0] bs,
+module aes32dsi(
+   input  logic [1:0]  bs,
    input  logic [31:0] rs1,
    input  logic [31:0] rs2,
-                output logic [31:0] DataOut);
+   output logic [31:0] DataOut
+);
 
-   // Declare Intermediary logic
    logic [4:0] 			 shamt;
    logic [31:0] 		    SboxIn32;
    logic [7:0] 			 SboxIn;

src/ieu/aes_instructions/aes32dsmi.sv

@@ -25,12 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes32dsmi(input logic [1:0] bs,
+module aes32dsmi(
+   input  logic [1:0]  bs,
    input  logic [31:0] rs1,
    input  logic [31:0] rs2,
-                 output logic [31:0] DataOut);
+   output logic [31:0] DataOut
+);
 
-   // Declare Intermediary logic
    logic [4:0] 			  shamt;
    logic [31:0] 		     SboxIn32;
    logic [7:0] 			  SboxIn;

src/ieu/aes_instructions/aes32esi.sv

@@ -25,12 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes32esi(input logic [1:0] bs,
+module aes32esi(
+   input  logic [1:0]  bs,
    input  logic [31:0] rs1,
    input  logic [31:0] rs2,
-                output logic [31:0] DataOut);                
+   output logic [31:0] DataOut
+);                
                 
-   // Declare Intermediary logic
    logic [4:0] 			 shamt;
    logic [31:0] 		    SboxIn32;
    logic [7:0] 			 SboxIn;

src/ieu/aes_instructions/aes32esmi.sv

@@ -25,12 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes32esmi(input logic [1:0]   bs,
+module aes32esmi(
+   input  logic [1:0]  bs,
    input  logic [31:0] rs1,
    input  logic [31:0] rs2,
-                 output logic [31:0] DataOut);                
+   output logic [31:0] DataOut
+);                
                 
-   // Declare Intermediary logic
    logic [4:0] 			  shamt;
    logic [31:0] 		     SboxIn32;
    logic [7:0] 			  SboxIn;

src/ieu/aes_instructions/aes64ds.sv

@@ -25,14 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64ds(input logic [63:0] rs1,
+module aes64ds(
+   input  logic [63:0] rs1,
    input  logic [63:0] rs2,
-               output logic [63:0] DataOut);
+   output logic [63:0] DataOut
+);
    
-   // Intermediary Logic
    logic [127:0] 		   ShiftRowOut;
-   logic [31:0] 		   SboxOut0;
-   logic [31:0] 		   SboxOut1;    
+   logic [31:0] 		   SboxOut0, SboxOut1;
    
    // Apply inverse shiftrows to rs2 and rs1
    aesinvshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));

src/ieu/aes_instructions/aes64dsm.sv

@@ -25,16 +25,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64dsm(input logic [63:0] rs1,
+module aes64dsm(
+   input  logic [63:0] rs1,
    input  logic [63:0] rs2,
-                output logic [63:0] DataOut);
+   output logic [63:0] DataOut
+);
    
-   // Intermediary Logic
    logic [127:0] 		    ShiftRowOut;
-   logic [31:0] 		    SboxOut0;
-   logic [31:0] 		    SboxOut1;
-   logic [31:0] 		    MixcolOut0;
-   logic [31:0] 		    MixcolOut1;    
+   logic [31:0] 		    SboxOut0, SboxOut1;
+   logic [31:0] 		    MixcolOut0, MixcolOut1;
    
    // Apply inverse shiftrows to rs2 and rs1
    aesinvshiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRowOut));

src/ieu/aes_instructions/aes64es.sv

@@ -25,11 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64es(input logic [63:0]  rs1,
+module aes64es(
+   input  logic [63:0] rs1,
    input  logic [63:0] rs2,
-               output logic [63:0] DataOut);
+   output logic [63:0] DataOut
+);
                 
-   // Intermediary Signals
    logic [127:0] 		   ShiftRowOut;
    
    // AES shiftrow unit

src/ieu/aes_instructions/aes64esm.sv

@@ -25,11 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64esm(input logic [63:0]  rs1,
+module aes64esm(
+    input  logic [63:0] rs1,
     input  logic [63:0] rs2,
-                output logic [63:0] DataOut);
+    output logic [63:0] DataOut
+);
    
-    // Intermediary Signals
     logic [127:0] ShiftRowOut;
     logic [63:0]  SboxOut;
                 

src/ieu/aes_instructions/aes64im.sv

@@ -25,8 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64im(input logic [63:0] rs1,
-               output logic [63:0] DataOut);
+module aes64im(
+   input  logic [63:0] rs1,
+   output logic [63:0] DataOut
+);
 
    aesinvmixcolumns inv_mw_0(.in(rs1[31:0]), .out(DataOut[31:0]));
    aesinvmixcolumns inv_mw_1(.in(rs1[63:32]), .out(DataOut[63:32]));

src/ieu/aes_instructions/aes64ks1i.sv

@@ -25,11 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64ks1i(input logic [3:0] roundnum,
+module aes64ks1i(
+   input  logic [3:0]  roundnum,
    input  logic [63:0] rs1,
-                 output logic [63:0] rd);                 
+   output logic [63:0] rd
+);                 
                  
-   // Instantiate intermediary logic signals             
    logic [7:0] 			  rconPreShift;
    logic [31:0] 		     rcon;
    logic 			        lastRoundFlag;

src/ieu/aes_instructions/aes64ks2.sv

@@ -25,13 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aes64ks2(input logic [63:0] rs2,
+module aes64ks2(
+   input  logic [63:0] rs2,
    input  logic [63:0] rs1,
-                output logic [63:0] rd);
+   output logic [63:0] rd
+);
    
-   // Instantiate Intermediary logic
-   logic [31:0] 		    w0;
-   logic [31:0] 		    w1;
+   logic [31:0] 		    w0, w1;
    
    assign w0 = rs1[63:32] ^ rs2[31:0];
    assign w1 = rs1[63:32] ^ rs2[31:0] ^ rs2[63:32];   

src/ieu/aes_instructions/rconlut128.sv

@@ -25,11 +25,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module rconlut128(input logic [3:0] RD,
-		  output logic [7:0] rconOut);
+module rconlut128(
+	input  logic [3:0] RD,
+	output logic [7:0] rconOut
+);
 	
    always_comb
-     begin
 	case(RD)
 	  4'h0 : rconOut = 8'h01;
 	  4'h1 : rconOut = 8'h02;
@@ -44,5 +45,4 @@ module rconlut128(input logic [3:0] RD,
 	  4'hA : rconOut = 8'h00;
 	  default : rconOut = 8'h00;
 	endcase	
-     end
 endmodule

src/ieu/kmu/packer.sv

@@ -28,15 +28,14 @@
 module packer #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, B,
   input  logic [2:0] 	  PackSelect, 
-  output logic [WIDTH-1:0] PackResult);
+  output logic [WIDTH-1:0] PackResult
+);
    
    logic [WIDTH/2-1:0] 	   lowhalf, highhalf;
    logic [7:0] 		   lowhalfh, highhalfh;
    logic [15:0] 	        lowhalfw, highhalfw;
    
-   logic [WIDTH-1:0] 	   Pack;
-   logic [WIDTH-1:0] 	   PackH;
-   logic [WIDTH-1:0] 	   PackW;
+   logic [WIDTH-1:0] 	   Pack, PackH, PackW;
    
    assign lowhalf = A[WIDTH/2-1:0];
    assign highhalf = B[WIDTH/2-1:0];
@@ -50,9 +49,7 @@ module packer #(parameter WIDTH=32) (
    assign PackW = {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw}; 
    
    always_comb 
-     begin
 	if      (PackSelect[1:0] == 2'b11) PackResult = PackH;
 	else if (PackSelect[2]   == 1'b0)  PackResult = Pack;
 	else                               PackResult = PackW;
-     end
 endmodule

src/ieu/kmu/zbkb.sv

@@ -25,12 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zbkb #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] A, B, RevA,
+module zbkb #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B, RevA,
    input  logic 	          W64,
    input  logic [2:0] 	    Funct3,
    input  logic [2:0] 	    ZBKBSelect,
-    output logic [WIDTH-1:0] ZBKBResult);
+   output logic [WIDTH-1:0] ZBKBResult
+);
    
    logic [WIDTH-1:0] 	     ByteResult;   // rev8, brev8
    logic [WIDTH-1:0] 	     PackResult;   // pack, packh, packw (RB64 only)

src/ieu/kmu/zbkx.sv

@@ -25,10 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zbkx #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] A, B,
+module zbkx #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B,
    input  logic [2:0] 	    ZBKXSelect,
-    output logic [WIDTH-1:0] ZBKXResult);
+   output logic [WIDTH-1:0] ZBKXResult
+);
    
    logic [WIDTH-1:0] 	     xpermlookup;
    integer 		     i;

src/ieu/kmu/zipper.sv

@@ -25,13 +25,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zipper #(parameter WIDTH=64) 
-   (input  logic [WIDTH-1:0] A,
+module zipper #(parameter WIDTH=64) (
+   input  logic [WIDTH-1:0] A,
    input  logic 	          ZipSelect,
-    output logic [WIDTH-1:0] ZipResult);
+   output logic [WIDTH-1:0] ZipResult
+);
    
-   logic [WIDTH-1:0] 	     zip;
-   logic [WIDTH-1:0] 	     unzip;
+   logic [WIDTH-1:0] 	     zip, unzip;
    genvar 		     i;
    
    for (i=0; i<WIDTH/2; i+=1) begin: loop

src/ieu/kmu/zknd32.sv

@@ -26,14 +26,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zknd32 #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] A, B,
+module zknd32 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B,
    input  logic [6:0] 	    Funct7,
    input  logic [2:0] 	    ZKNDSelect,
-    output logic [WIDTH-1:0] ZKNDResult);
+   output logic [WIDTH-1:0] ZKNDResult
+);
    
-   logic [31:0] 	     aes32dsiRes;
-   logic [31:0] 	     aes32dsmiRes;
+   logic [31:0] 	     aes32dsiRes, aes32dsmiRes;
   
    // RV32
    aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));

src/ieu/kmu/zknd64.sv

@@ -26,18 +26,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zknd64 #(parameter WIDTH=32) 
-   (input logic [WIDTH-1:0]  A, B,
+module zknd64 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B,
    input  logic [6:0] 	    Funct7,
    input  logic [3:0] 	    RNUM,
    input  logic [2:0] 	    ZKNDSelect,
-    output logic [WIDTH-1:0] ZKNDResult);
+   output logic [WIDTH-1:0] ZKNDResult
+);
    
-   logic [63:0] 	     aes64dsRes;
-   logic [63:0] 	     aes64dsmRes;
-   logic [63:0] 	     aes64imRes;
-   logic [63:0] 	     aes64ks1iRes;
-   logic [63:0] 	     aes64ks2Res;
+   logic [63:0] 	     aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res;
    
    // RV64
    aes64ds aes64ds (.rs1(A), .rs2(B), .DataOut(aes64dsRes));

src/ieu/kmu/zkne32.sv

@@ -26,14 +26,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zkne32 #(parameter WIDTH=32) 
-   (input logic [WIDTH-1:0]  A, B,
+module zkne32 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B,
    input  logic [6:0] 	    Funct7,
    input  logic [2:0] 	    ZKNESelect,
    output logic [WIDTH-1:0] ZKNEResult);
    
-   logic [31:0] 	     aes32esiRes;
-   logic [31:0] 	     aes32esmiRes;
+   logic [31:0] 	     aes32esiRes, aes32esmiRes;
    
    // RV32
    aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));

src/ieu/kmu/zkne64.sv

@@ -26,17 +26,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zkne64 #(parameter WIDTH=32) 
-   (input logic [WIDTH-1:0]  A, B,
+module zkne64 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] A, B,
    input  logic [6:0] 	    Funct7,
    input  logic [3:0] 	    RNUM,
    input  logic [2:0] 	    ZKNESelect,
-    output logic [WIDTH-1:0] ZKNEResult);
+   output logic [WIDTH-1:0] ZKNEResult
+);
    
-   logic [63:0] 	     aes64esRes;
-   logic [63:0] 	     aes64esmRes;
-   logic [63:0] 	     aes64ks1iRes;
-   logic [63:0] 	     aes64ks2Res;
+   logic [63:0] 	     aes64esRes, aes64esmRes, aes64ks1iRes, aes64ks2Res;
    
    // RV64
    aes64es aes64es (.rs1(A), .rs2(B), .DataOut(aes64esRes));

src/ieu/kmu/zknh32.sv

@@ -25,21 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zknh32 (input  logic [31:0] A, B,
+module zknh32 (
+   input  logic [31:0] A, B,
 	input  logic [3:0]  ZKNHSelect,
-	       output logic [31:0] ZKNHResult);
+	output logic [31:0] ZKNHResult
+);
    
-   logic [31:0] 		   sha256sig0res;
-   logic [31:0] 		   sha256sig1res;
-   logic [31:0] 		   sha256sum0res;
-   logic [31:0] 		   sha256sum1res;
-   
-   logic [31:0] 		   sha512sig0hres;
-   logic [31:0] 		   sha512sig0lres;
-   logic [31:0] 		   sha512sig1hres;
-   logic [31:0] 		   sha512sig1lres;
-   logic [31:0] 		   sha512sum0rres;
-   logic [31:0] 		   sha512sum1rres;
+   logic [31:0] 		   sha256sig0res, sha256sig1res, sha256sum0res, sha256sum1res;
+   logic [31:0] 		   sha512sig0hres, sha512sig0lres, sha512sig1hres, sha512sig1lres, sha512sum0rres, sha512sum1rres;
    
    sha256sig0 #(32) sha256sig0(A, sha256sig0res);
    sha256sig1 #(32) sha256sig1(A, sha256sig1res);
@@ -53,7 +46,7 @@ module zknh32 (input  logic [31:0] A, B,
    sha512sum1r sha512sum1r(A, B, sha512sum1rres);
    
    // Result Select Mux
-   always_comb begin
+   always_comb 
       casez(ZKNHSelect)
          4'b0000: ZKNHResult = sha256sig0res;
          4'b0001: ZKNHResult = sha256sig1res;
@@ -65,7 +58,6 @@ module zknh32 (input  logic [31:0] A, B,
          4'b0111: ZKNHResult = sha512sig1lres;
          4'b1000: ZKNHResult = sha512sum0rres;
          4'b1001: ZKNHResult = sha512sum1rres;
-	default ZKNHResult = 0;
+         default: ZKNHResult = 0;
       endcase
-   end
 endmodule

src/ieu/kmu/zknh64.sv

@@ -25,18 +25,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zknh64 (input  logic [63:0] A, B, input  logic [3:0]  ZKNHSelect,
-	       output logic [63:0] ZKNHResult);
+module zknh64 (
+   input  logic [63:0] A, B, 
+   input  logic [3:0]  ZKNHSelect,
+	output logic [63:0] ZKNHResult
+);
 
-   logic [63:0] 		   sha256sig0res;
-   logic [63:0] 		   sha256sig1res;
-   logic [63:0] 		   sha256sum0res;
-   logic [63:0] 		   sha256sum1res;
-   
-   logic [63:0] 		   sha512sig0res;
-   logic [63:0] 		   sha512sig1res;
-   logic [63:0] 		   sha512sum0res;
-   logic [63:0] 		   sha512sum1res;   
+   logic [63:0] 		   sha256sig0res, sha256sig1res, sha256sum0res, sha256sum1res;   
+   logic [63:0] 		   sha512sig0res, sha512sig1res, sha512sum0res, sha512sum1res;
    
    sha256sig0 #(64) sha256sig0(A, sha256sig0res);
    sha256sig1 #(64) sha256sig1(A, sha256sig1res);
@@ -48,7 +44,7 @@ module zknh64 (input  logic [63:0] A, B, input  logic [3:0]  ZKNHSelect,
    sha512sum1 sha512sum1(A, sha512sum1res);
    
    // Result Select Mux
-   always_comb begin
+   always_comb 
       casez(ZKNHSelect)
          4'b0000: ZKNHResult = sha256sig0res;
          4'b0001: ZKNHResult = sha256sig1res;
@@ -58,7 +54,6 @@ module zknh64 (input  logic [63:0] A, B, input  logic [3:0]  ZKNHSelect,
          4'b1011: ZKNHResult = sha512sig1res;
          4'b1100: ZKNHResult = sha512sum0res;
          4'b1101: ZKNHResult = sha512sum1res;
-	default ZKNHResult = 0;
+         default: ZKNHResult = 0;
       endcase
-   end
 endmodule

src/ieu/sha_instructions/sha256sig0.sv

@@ -25,9 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha256sig0 #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] rs1,
-    output logic [WIDTH-1:0] result);
+module sha256sig0 #(parameter WIDTH=32) (
+  input  logic [WIDTH-1:0] rs1,
+  output logic [WIDTH-1:0] result
+);
 
    logic [31:0] 	   ror7;
    logic [31:0] 	   ror18;
@@ -40,9 +41,8 @@ module sha256sig0 #(parameter WIDTH=32)
    
    // Assign output to xor of 3 rotates
    assign exts = ror7 ^ ror18 ^ sh3;   
-   if (WIDTH==32) 
-     assign result = exts;
-   else 
-     assign result = {{32{exts[31]}}, exts};
 
+   // Sign-extend for RV64
+   if (WIDTH==32) assign result = exts;
+   else           assign result = {{32{exts[31]}}, exts};
 endmodule

src/ieu/sha_instructions/sha256sig1.sv

@@ -25,9 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha256sig1 #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] rs1,
-    output logic [WIDTH-1:0] result);
+module sha256sig1 #(parameter WIDTH=32) (
+  input  logic [WIDTH-1:0] rs1,
+  output logic [WIDTH-1:0] result
+);
    
    logic [31:0] 	     ror17;
    logic [31:0] 	     ror19;
@@ -40,9 +41,8 @@ module sha256sig1 #(parameter WIDTH=32)
    
    // Assign output to xor of 3 rotates
    assign exts = ror17 ^ ror19 ^ sh10;
-   if (WIDTH==32)
-     assign result = exts;
-   else 
-     assign result = {{32{exts[31]}}, exts};
 
+   // Sign-extend for RV64
+   if (WIDTH==32) assign result = exts;
+   else           assign result = {{32{exts[31]}}, exts};
 endmodule

src/ieu/sha_instructions/sha256sum0.sv

@@ -25,9 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha256sum0 #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] rs1,
-    output logic [WIDTH-1:0] result);
+module sha256sum0 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] rs1,
+   output logic [WIDTH-1:0] result
+);
    
    logic [31:0] 	     ror2;
    logic [31:0] 	     ror13;
@@ -40,9 +41,8 @@ module sha256sum0 #(parameter WIDTH=32)
    
    // Assign output to xor of 3 rotates
    assign exts = ror2 ^ ror13 ^ ror22;
-   if (WIDTH==32) 
-      assign result = exts;
-   else 
-     assign result = {{32{exts[31]}}, exts};
 
+   // Sign-extend for RV64
+   if (WIDTH==32) assign result = exts;
+   else           assign result = {{32{exts[31]}}, exts};
 endmodule

src/ieu/sha_instructions/sha256sum1.sv

@@ -25,9 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha256sum1 #(parameter WIDTH=32) 
-   (input  logic [WIDTH-1:0] rs1, 
-    output logic [WIDTH-1:0] result);
+module sha256sum1 #(parameter WIDTH=32) (
+   input  logic [WIDTH-1:0] rs1, 
+   output logic [WIDTH-1:0] result
+);
 
    logic [31:0] 	     ror6;
    logic [31:0] 	     ror11;
@@ -40,9 +41,8 @@ module sha256sum1 #(parameter WIDTH=32)
    
    // Assign output to xor of 3 rotates
    assign exts = ror6 ^ ror11 ^ ror25;
-   if (WIDTH==32)
-      assign result = exts;
-   else 
-     assign result = {{32{exts[31]}}, exts};
 
+   // Sign-extend for RV64
+   if (WIDTH==32) assign result = exts;
+   else           assign result = {{32{exts[31]}}, exts};
 endmodule

src/ieu/sha_instructions/sha512sig0.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig0(input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sig0(
+   input  logic [63:0] rs1, 
+   output logic [63:0] result
+);
 
    logic [63:0] ror1;
    logic [63:0] ror8;
@@ -37,5 +40,4 @@ module sha512sig0(input  logic [63:0] rs1, output logic [63:0] result);
    
    // Assign output to xor of 3 rotates
    assign result = ror1 ^ ror8 ^ sh7;  
-   
 endmodule

src/ieu/sha_instructions/sha512sig0h.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig0h(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);
+module sha512sig0h(
+   input  logic [31:0] rs1, 
+   input  logic [31:0] rs2,
+   output logic [31:0] DataOut
+);
    
    // RS1 Shifts
    logic [31:0] 		       shift1;
@@ -48,5 +51,4 @@ module sha512sig0h(input logic [31:0] rs1, input logic [31:0]  rs2,
    
    // XOR to get result
    assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
-    
 endmodule

src/ieu/sha_instructions/sha512sig0l.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig0l(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);
+module sha512sig0l(
+   input  logic [31:0] rs1, 
+   input  logic [31:0] rs2,
+   output logic [31:0] DataOut
+);
    
    // rs1 operations                   
    logic [31:0] 		       shift1;
@@ -49,5 +52,4 @@ module sha512sig0l(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift24 = rs2 << 24;
    
    assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
-   
 endmodule

src/ieu/sha_instructions/sha512sig1.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig1(input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sig1(
+   input  logic [63:0] rs1, 
+   output logic [63:0] result
+);
 
    logic [63:0] ror19;
    logic [63:0] ror61;
@@ -37,5 +40,4 @@ module sha512sig1(input  logic [63:0] rs1, output logic [63:0] result);
    
    // Assign output to xor of 3 rotates
    assign result = ror19 ^ ror61 ^ sh6;
-   
 endmodule

src/ieu/sha_instructions/sha512sig1h.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig1h(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);
+module sha512sig1h(
+   input  logic [31:0] rs1, 
+   input  logic [31:0] rs2,
+   output logic [31:0] DataOut
+);
    
    // rs1 shifts             
    logic [31:0] 		       shift3;
@@ -46,6 +49,5 @@ module sha512sig1h(input logic [31:0] rs1, input logic [31:0]  rs2,
    
    // XOR Shifted registers for output
    assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
-    
 endmodule
     

src/ieu/sha_instructions/sha512sig1l.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sig1l(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);
+module sha512sig1l(
+   input  logic [31:0] rs1, 
+   input  logic [31:0] rs2,
+   output logic [31:0] DataOut
+);
                   
    // rs1 shift logic
    logic [31:0] 		       shift3;
@@ -49,5 +52,4 @@ module sha512sig1l(input logic [31:0] rs1, input logic [31:0]  rs2,
    assign shift13 = rs2 << 13;
    
    assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;                 
-                            
 endmodule

src/ieu/sha_instructions/sha512sum0.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum0(input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sum0(
+   input  logic [63:0] rs1, 
+   output logic [63:0] result
+);
 
    logic [63:0] ror28;
    logic [63:0] ror34;
@@ -37,5 +40,4 @@ module sha512sum0(input  logic [63:0] rs1, output logic [63:0] result);
    
    // Assign output to xor of 3 rotates
    assign result = ror28 ^ ror34 ^ ror39;
-   
 endmodule

src/ieu/sha_instructions/sha512sum0r.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum0r(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);
+module sha512sum0r(
+   input  logic [31:0] rs1, 
+   input  logic [31:0]  rs2,
+   output logic [31:0] DataOut
+);
    
    // RS1 shifts
    logic [31:0] 		       shift25;
@@ -50,5 +53,4 @@ module sha512sum0r(input logic [31:0] rs1, input logic [31:0]  rs2,
    
    // Set output to XOR of shifted values
    assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
-   
 endmodule

src/ieu/sha_instructions/sha512sum1.sv

@@ -25,7 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum1(input  logic [63:0] rs1, output logic [63:0] result);
+module sha512sum1(
+   input  logic [63:0] rs1, 
+   output logic [63:0] result
+);
 
    logic [63:0] ror14;
    logic [63:0] ror18;
@@ -37,5 +40,4 @@ module sha512sum1(input  logic [63:0] rs1, output logic [63:0] result);
    
    // Assign output to xor of 3 rotates
    assign result = ror14 ^ ror18 ^ ror41;
-   
 endmodule

src/ieu/sha_instructions/sha512sum1r.sv

@@ -25,8 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module sha512sum1r(input logic [31:0] rs1, input logic [31:0]  rs2,
-                   output logic [31:0] DataOut);   
+module sha512sum1r(
+   input  logic [31:0] rs1, 
+   input  logic [31:0] rs2,
+   output logic [31:0] DataOut
+);   
    
    // Declare logic for rs1 shifts
    logic [31:0] 		       shift1by23;
@@ -50,5 +53,4 @@ module sha512sum1r(input logic [31:0] rs1, input logic [31:0]  rs2,
    
    // Assign output to xor of shifts
    assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14;
-    
 endmodule