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Fixed wally-periph, regression is now working

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This commit is contained in:
slmnemo 2022-06-23 13:08:15 -07:00
parent 4ff866b39e
commit 33c78e2404
2 changed files with 22 additions and 19 deletions
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30
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output
View File

@ -254,12 +254,12 @@ FFFFEE00
FFFFEE00 FFFFEE00
00000000 00000000
00000000 00000000
02BEEF10 02BEEF10 # Something here is failing
0000000B 0000000B
80000000 80000000
00000003 00000003
000000FF 000000FF
FFFFFFFF 00000000
000000FF 000000FF
00000000 00000000
00000000 00000000
@ -270,20 +270,20 @@ FFFFFFFF
FFFFFF00 FFFFFF00
00000000 00000000
00000000 00000000
02BEEF11 02BEEF11 # this might be wrong
0000000B 0000000B
80000000 80000000
00000003 00000003
000000CC 00000033 # input
CCCCCCCC 00000000 # output
00000000 # rise ip
00000000 # serviced rise ip
000000CC # fall ip
00000000 00000000
00000000 000000FF # high ip
00000033 00000033 # why is this 0x33?
00000000 FFFFFFCC # low ip
000000FF FFFFFFCC # serviced low ip
000000CC
FFFFFF33
FFFFFF33
00000000 00000000
00000000 00000000
03BEEF12 03BEEF12
@ -454,9 +454,9 @@ FFFFFF33
00080000 00080000
00080000 00080000
00000000 00000000
00000000 # is it this one that's failing?
00000000 00000000
00000000 00080000 # failing
00080000
00080000 00080000
FFFFFFFF FFFFFFFF
FFF7FFFF FFF7FFFF
@ -478,7 +478,7 @@ FFFFFFFF
FFFFFFFE FFFFFFFE
00000000 00000000
00000000 00000000
04BEEF1E 04BEEF1E # this might also be wrong
00000009 00000009
80000000 80000000
0000000A 0000000A

7
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S
View File

@ -271,7 +271,7 @@ main_code: #####
sw t1, 0x04(t0) sw t1, 0x04(t0)
# raise all output_en # raise all output_en
sw t1, 0x08(t0) sw t1, 0x08(t0)
# raise all input_en # raise all rise_en
sw t1, 0x18(t0) sw t1, 0x18(t0)
# ========== Execute Test ========== # ========== Execute Test ==========
# set MEIE # set MEIE
@ -616,6 +616,9 @@ Intr02BEEF11:
sw t1, 0x08(t0) sw t1, 0x08(t0)
# set initial output state # set initial output state
sw x0, 0x0C(t0) sw x0, 0x0C(t0)
# clear XOR
li t1, 0x00000000
sw t1, 0x40(t0)
# clear all pending interrupts # clear all pending interrupts
li t1, 0xFFFFFFFF li t1, 0xFFFFFFFF
sw t1, 0x1C(t0) sw t1, 0x1C(t0)
@ -843,7 +846,7 @@ Intr03BEEF1A:
sw t1, 0x04(t0) sw t1, 0x04(t0)
# raise all output_en # raise all output_en
sw t1, 0x08(t0) sw t1, 0x08(t0)
# raise all input_en # raise all rise_en
sw t1, 0x18(t0) sw t1, 0x18(t0)
# ========== Execute Test ========== # ========== Execute Test ==========
# set MEIE and SEIE # set MEIE and SEIE