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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed wally-periph, regression is now working
This commit is contained in:
parent
4ff866b39e
commit
33c78e2404
@ -254,12 +254,12 @@ FFFFEE00
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FFFFEE00
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FFFFEE00
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00000000
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00000000
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00000000
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00000000
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02BEEF10
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02BEEF10 # Something here is failing
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0000000B
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0000000B
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80000000
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80000000
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00000003
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00000003
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000000FF
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000000FF
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FFFFFFFF
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00000000
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000000FF
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000000FF
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00000000
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00000000
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00000000
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00000000
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@ -270,20 +270,20 @@ FFFFFFFF
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FFFFFF00
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FFFFFF00
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00000000
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00000000
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00000000
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00000000
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02BEEF11
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02BEEF11 # this might be wrong
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0000000B
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0000000B
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80000000
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80000000
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00000003
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00000003
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000000CC
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00000033 # input
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CCCCCCCC
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00000000 # output
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00000000 # rise ip
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00000000 # serviced rise ip
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000000CC # fall ip
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00000000
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00000000
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00000000
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000000FF # high ip
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00000033
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00000033 # why is this 0x33?
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00000000
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FFFFFFCC # low ip
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000000FF
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FFFFFFCC # serviced low ip
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000000CC
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FFFFFF33
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FFFFFF33
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00000000
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00000000
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00000000
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00000000
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03BEEF12
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03BEEF12
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@ -454,9 +454,9 @@ FFFFFF33
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00080000
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00080000
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00080000
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00080000
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00000000
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00000000
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00000000 # is it this one that's failing?
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00000000
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00000000
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00000000
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00080000 # failing
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00080000
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00080000
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00080000
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FFFFFFFF
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FFFFFFFF
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FFF7FFFF
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FFF7FFFF
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@ -478,7 +478,7 @@ FFFFFFFF
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FFFFFFFE
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FFFFFFFE
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00000000
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00000000
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00000000
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00000000
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04BEEF1E
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04BEEF1E # this might also be wrong
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00000009
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00000009
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80000000
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80000000
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0000000A
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0000000A
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@ -271,7 +271,7 @@ main_code: #####
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sw t1, 0x04(t0)
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sw t1, 0x04(t0)
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# raise all output_en
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# raise all output_en
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sw t1, 0x08(t0)
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sw t1, 0x08(t0)
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# raise all input_en
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# raise all rise_en
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sw t1, 0x18(t0)
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sw t1, 0x18(t0)
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# ========== Execute Test ==========
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# ========== Execute Test ==========
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# set MEIE
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# set MEIE
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@ -616,6 +616,9 @@ Intr02BEEF11:
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sw t1, 0x08(t0)
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sw t1, 0x08(t0)
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# set initial output state
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# set initial output state
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sw x0, 0x0C(t0)
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sw x0, 0x0C(t0)
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# clear XOR
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li t1, 0x00000000
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sw t1, 0x40(t0)
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# clear all pending interrupts
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# clear all pending interrupts
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li t1, 0xFFFFFFFF
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li t1, 0xFFFFFFFF
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sw t1, 0x1C(t0)
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sw t1, 0x1C(t0)
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@ -843,7 +846,7 @@ Intr03BEEF1A:
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sw t1, 0x04(t0)
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sw t1, 0x04(t0)
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# raise all output_en
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# raise all output_en
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sw t1, 0x08(t0)
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sw t1, 0x08(t0)
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# raise all input_en
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# raise all rise_en
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sw t1, 0x18(t0)
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sw t1, 0x18(t0)
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# ========== Execute Test ==========
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# ========== Execute Test ==========
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# set MEIE and SEIE
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# set MEIE and SEIE
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