From 33aca5d35ec78ceffba43c8297d00431e29aba3d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Dec 2022 06:37:55 -0800 Subject: [PATCH] Added IDIV_ON_FPU flag to control whether integer division uses FPU --- pipelined/config/buildroot/wally-config.vh | 1 + pipelined/config/fpga/wally-config.vh | 1 + pipelined/config/rv32e/wally-config.vh | 1 + pipelined/config/rv32gc/wally-config.vh | 1 + pipelined/config/rv32i/wally-config.vh | 1 + pipelined/config/rv32ic/wally-config.vh | 1 + pipelined/config/rv64BP/wally-config.vh | 1 + pipelined/config/rv64fpquad/wally-config.vh | 1 + pipelined/config/rv64gc/wally-config.vh | 1 + pipelined/config/rv64i/wally-config.vh | 1 + pipelined/src/ieu/datapath.sv | 6 +++++- pipelined/src/muldiv/muldiv.sv | 2 +- 12 files changed, 16 insertions(+), 2 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index defbf458d..6b5490354 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -72,6 +72,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 8d9ff7e15..97b43c5b4 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -74,6 +74,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 8b6dea7e7..99f61c12a 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -73,6 +73,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 1 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 69b256ad1..bafe35e6d 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -72,6 +72,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 4eaa116a0..46e493cbf 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -73,6 +73,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index ba47915de..d6ca045ea 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -72,6 +72,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 8591ab1c9..85456e2c9 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -76,6 +76,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Address space `define RESET_VECTOR 64'h0000000000001000 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 13df811c4..eeba56990 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -74,6 +74,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 630dfdb6f..a469a2552 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -74,6 +74,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 098755cd2..5c34b96a1 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -74,6 +74,7 @@ // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 `define DIV_BITSPERCYCLE 4 +`define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index abc232651..7c05986d5 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -126,7 +126,11 @@ module datapath ( if (`F_SUPPORTED) begin:fpmux mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW); - mux2 #(`XLEN) divresultmuxW(MDUResultW, FPIntDivResultW, DivW, MulDivResultW); + if (`IDIV_ON_FPU) begin + mux2 #(`XLEN) divresultmuxW(MDUResultW, FPIntDivResultW, DivW, MulDivResultW); + end else begin + assign MulDivResultW = MDUResultW; + end end else begin:fpmux assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; assign MulDivResultW = MDUResultW; diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv index c41ec4592..d6bc26de4 100644 --- a/pipelined/src/muldiv/muldiv.sv +++ b/pipelined/src/muldiv/muldiv.sv @@ -60,7 +60,7 @@ module muldiv ( // Divide // Start a divide when a new division instruction is received and the divider isn't already busy or finishing // When F extensions are supported, use the FPU divider instead - if (`F_SUPPORTED) begin + if (`IDIV_ON_FPU) begin assign QuotM = 0; assign RemM = 0; assign DivBusyE = 0;