Added 2 bits to C to initialize properly

pipelined/src/fpu/fdivsqrt.sv

@@ -59,7 +59,7 @@ module fdivsqrt(
   logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVN-2:0] Dpreproc;
   logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
-  logic [`DIVb-1:0] FirstC;
+  logic [`DIVb+1:0] FirstC;
   logic Firstqn;
   logic WZero;
 

pipelined/src/fpu/fdivsqrtiter.sv

@@ -44,7 +44,7 @@ module fdivsqrtiter(
   output logic [`DIVb+3:0]  NextWSN, NextWCN,
   output logic [`DIVb:0] FirstS, FirstSM,
   output logic [`DIVb:0] FirstQ, FirstQM,
-  output logic [`DIVb-1:0] FirstC,
+  output logic [`DIVb+1:0] FirstC,
   output logic             Firstqn,
   output logic [`DIVb+3:0]  FirstWS, FirstWC
 );
@@ -69,8 +69,8 @@ module fdivsqrtiter(
   logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b
   logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b
   logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVb-1:0] C[`DIVCOPIES:0]; // 0.b
-  logic [`DIVb-1:0] initC; // 0.b
+  logic [`DIVb+1:0] C[`DIVCOPIES:0]; // Q2.b
+  logic [`DIVb+1:0] initC; // Q2.b
   logic [`DIVCOPIES-1:0] qn; 
 
 
@@ -78,8 +78,8 @@ module fdivsqrtiter(
   logic [`DIVb+3:0]  WSN, WCN; // Q4.N-1
   logic [`DIVb+3:0]  DBar, D2, DBar2; // Q4.N-1
   logic [`DIVb:0] QMMux;
-  logic [`DIVb-1:0] NextC;
-  logic [`DIVb-1:0] CMux;
+  logic [`DIVb+1:0] NextC;
+  logic [`DIVb+1:0] CMux;
   logic [`DIVb:0] SMux;
 
   // Top Muxes and Registers
@@ -97,15 +97,22 @@ module fdivsqrtiter(
     assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
     assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
   end
-  assign initC = 0;
+
+  // Initialize C to -1 for sqrt and -R for division
+  logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper;
+  assign initCSqrt = 2'b11;
+  assign initCDiv2 = 2'b10;
+  assign initCDiv4 = 2'b00;
+  assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2;
+  assign initC = {initCUpper, {`DIVb{1'b0}}};
 
   mux2   #(`DIVb+4) wsmux(NextWSN, X, DivStart, WSN);
   flopen   #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
   mux2   #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
   flopen   #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
   flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
-  mux2 #(`DIVb) Cmux(C[`DIVCOPIES], initC, DivStart, CMux); 
-  flopen #(`DIVb) cflop(clk, DivStart|DivBusy, CMux, C[0]);
+  mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStart, CMux); 
+  flopen #(`DIVb+2) cflop(clk, DivStart|DivBusy, CMux, C[0]);
 
   // Divisor Selections
   //  - choose the negitive version of what's being selected

pipelined/src/fpu/fdivsqrtpostproc.sv

@@ -34,7 +34,7 @@ module fdivsqrtpostproc(
   input logic [`DIVb+3:0] WS, WC,
   input logic [`DIVN-2:0]  D, // U0.N-1
   input logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM,
-  input logic [`DIVb-1:0] FirstC,
+  input logic [`DIVb+1:0] FirstC,
   input logic  Firstqn,
   input logic SqrtM,
   output logic [`DIVb-(`RADIX/4):0] QmM,
@@ -55,7 +55,7 @@ module fdivsqrtpostproc(
     logic wfeq0;
     logic [`DIVb+3:0] WCF, WSF;
 
-    assign FirstK = ({3'b111, FirstC} & ~({3'b111, FirstC} << 1));
+    assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
     assign FZero = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
     csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);

pipelined/src/fpu/fdivsqrtstage2.sv

@@ -37,11 +37,11 @@ module fdivsqrtstage2 (
   input logic [`DIVb:0] Q, QM,
   input logic [`DIVb:0] S, SM,
   input logic [`DIVb+3:0]  WS, WC,
-  input logic [`DIVb-1:0] C,
+  input logic [`DIVb+1:0] C,
   input logic SqrtM,
   output logic [`DIVb:0] QNext, QMNext, 
   output logic qn,
-  output logic [`DIVb-1:0] CNext,
+  output logic [`DIVb+1:0] CNext,
   output logic [`DIVb:0] SNext, SMNext, 
   output logic [`DIVb+3:0]  WSA, WCA
 );
@@ -52,7 +52,7 @@ module fdivsqrtstage2 (
   logic [`DIVb+3:0] F;
   logic [`DIVb+3:0] AddIn;
 
-  assign CNext = {1'b1, C[`DIVb-1:1]};
+  assign CNext = {1'b1, C[`DIVb+1:1]};
 
   // Qmient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)

pipelined/src/fpu/fdivsqrtstage4.sv

@@ -37,8 +37,8 @@ module fdivsqrtstage4 (
   input logic [`DIVb:0] Q, QM,
   input logic [`DIVb:0] S, SM,
   input logic [`DIVb+3:0]  WS, WC,
-  input logic [`DIVb-1:0] C,
-  output logic [`DIVb-1:0] CNext,
+  input logic [`DIVb+1:0] C,
+  output logic [`DIVb+1:0] CNext,
   input logic SqrtM, j1,
   output logic [`DIVb:0] QNext, QMNext, 
   output logic qn,
@@ -54,7 +54,7 @@ module fdivsqrtstage4 (
   logic [4:0] Smsbs;
   logic CarryIn;
 
-  assign CNext = {2'b11, C[`DIVb-1:2]};
+  assign CNext = {2'b11, C[`DIVb+1:2]};
 
   // Qmient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
@@ -66,7 +66,7 @@ module fdivsqrtstage4 (
 	// 0001 = -2
   assign Smsbs = S[`DIVb:`DIVb-4];
   qsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q);
-  fgen4 fgen4(.s(q), .C({4'b1111, CNext}), .S({3'b000, S}), .SM({3'b000, SM}), .F);
+  fgen4 fgen4(.s(q), .C({2'b11, CNext}), .S({3'b000, S}), .SM({3'b000, SM}), .F);
 
   always_comb
   case (q)
@@ -85,7 +85,7 @@ module fdivsqrtstage4 (
   csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
  
   otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
-  sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C({1'b1, CNext}), .S, .SM, .SNext, .SMNext);
+  sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .S, .SM, .SNext, .SMNext);
 endmodule
 
 

pipelined/src/fpu/otfc.sv

@@ -63,7 +63,7 @@ endmodule
 ///////////////////////////////
 module sotfc2(
   input  logic         sp, sz,
-  input  logic [`DIVb-1:0] C,
+  input  logic [`DIVb+1:0] C,
   input logic [`DIVb:0] S, SM,
   output logic [`DIVb:0] SNext, SMNext
 );
@@ -72,7 +72,7 @@ module sotfc2(
   //  Use this otfc for division and square root.
   logic [`DIVb:0] CExt;
 
-  assign CExt = {1'b1, C};
+  assign CExt = {1'b1, C[`DIVb-1:0]};
 
   always_comb begin
     if (sp) begin

pipelined/src/fpu/qsel.sv

@@ -67,7 +67,7 @@ endmodule
 ////////////////////////////////////
 module fgen2 (
   input  logic sp, sz,
-  input  logic [`DIVb-1:0] C,
+  input  logic [`DIVb+1:0] C,
   input  logic [`DIVb:0] S, SM,
   output logic [`DIVb+3:0] F
 );
@@ -76,7 +76,7 @@ module fgen2 (
 
   assign SExt = {3'b0, S};
   assign SMExt = {3'b0, SM};
-  assign CExt = {4'hf, C}; // extend C from U0.k to Q4.k
+  assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k
 
   // Generate for both positive and negative bits
   assign FP = ~(SExt << 1) & CExt;