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intentionally breaking commit
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@ -76,7 +76,7 @@ module wallypipelinedsoc (
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synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
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synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
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// instantiate processor and memories
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// instantiate processor and memories
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wallypipelinedhart hart(.clk, .reset,
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wallypipelinedhart hart(.clk, .syntaxerror,
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.TimerIntM, .ExtIntM, .SwIntM,
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.TimerIntM, .ExtIntM, .SwIntM,
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.MTIME_CLINT, .MTIMECMP_CLINT,
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.MTIME_CLINT, .MTIMECMP_CLINT,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
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.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
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