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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.

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This commit is contained in:
cturek 2022-11-06 22:08:18 +00:00
parent b893d9249d
commit 333da5c945
4 changed files with 7 additions and 4 deletions
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5
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -64,11 +64,11 @@ module fdivsqrt(
logic Firstun; logic Firstun;
logic WZero; logic WZero;
logic SpecialCaseM; logic SpecialCaseM;
logic [`DIVBLEN:0] n; logic [`DIVBLEN:0] n, p, m;
fdivsqrtpreproc fdivsqrtpreproc( fdivsqrtpreproc fdivsqrtpreproc(
.clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
.Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .n, .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .n, .p, .m,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE, .clk, .reset, .FmtE, .XsE, .SqrtE,
@ -83,5 +83,6 @@ module fdivsqrt(
fdivsqrtpostproc fdivsqrtpostproc( fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
.n, .p, .m,
.QmM, .WZero, .DivSM); .QmM, .WZero, .DivSM);
endmodule endmodule

1
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -39,6 +39,7 @@ module fdivsqrtpostproc(
input logic SqrtM, input logic SqrtM,
input logic SpecialCaseM, input logic SpecialCaseM,
input logic RemOp, input logic RemOp,
input logic [`DIVBLEN:0] n, p, m,
output logic [`DIVb:0] QmM, output logic [`DIVb:0] QmM,
output logic WZero, output logic WZero,
output logic DivSM output logic DivSM

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -41,7 +41,7 @@ module fdivsqrtpreproc (
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
input logic [2:0] Funct3E, Funct3M, input logic [2:0] Funct3E, Funct3M,
input logic MDUE, W64E, input logic MDUE, W64E,
output logic [`DIVBLEN:0] n, output logic [`DIVBLEN:0] n, p, m,
output logic [`NE+1:0] QeM, output logic [`NE+1:0] QeM,
output logic [`DIVb+3:0] X, output logic [`DIVb+3:0] X,
output logic [`DIVN-2:0] Dpreproc output logic [`DIVN-2:0] Dpreproc
@ -58,7 +58,7 @@ module fdivsqrtpreproc (
logic [`XLEN-1:0] PosA, PosB; logic [`XLEN-1:0] PosA, PosB;
logic As, Bs; logic As, Bs;
logic [`XLEN-1:0] A64, B64; logic [`XLEN-1:0] A64, B64;
logic [`DIVBLEN:0] p, ZeroDiff, IntBits, RightShiftX; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
logic [`DIVBLEN:0] pPlusr, pPrTrunc, pPrCeil; logic [`DIVBLEN:0] pPlusr, pPrTrunc, pPrCeil;
logic [`DIVb+3:0] PreShiftX; logic [`DIVb+3:0] PreShiftX;

1
pipelined/testbench/testbench-fp.sv
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@ -718,6 +718,7 @@ module testbenchfp;
if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart),
.MDUE(1'b0), .W64E(1'b0),
.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
.QmM(Quot), .DivDone); .QmM(Quot), .DivDone);
end end