From 3322ff915e5c59696f2497bc2b178136d08e7e5d Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 24 Oct 2023 23:05:12 -0500 Subject: [PATCH] Cleaned up the implementation changes for wfi. --- src/hazard/hazard.sv | 6 ------ src/privileged/csr.sv | 2 -- src/privileged/privdec.sv | 6 +++--- src/privileged/privileged.sv | 4 ++-- 4 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 94c967f32..cb70605c0 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -27,7 +27,6 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module hazard ( - input logic clk, reset, // Detect hazards input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, @@ -46,10 +45,8 @@ module hazard ( logic FlushDCause, FlushECause, FlushMCause, FlushWCause; logic WFIStallM, WFIInterruptedM; - logic wfiW; // WFI logic - flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); assign WFIStallM = wfiM & ~IntPendingM; // WFI waiting for an interrupt or timeout assign WFIInterruptedM = wfiM & IntPendingM; // WFI detects a pending interrupt. Retire WFI; trap if interrupt is enabled. @@ -77,7 +74,6 @@ module hazard ( assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; assign FlushWCause = TrapM & ~WFIInterruptedM; - //assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage @@ -91,12 +87,10 @@ module hazard ( assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; - //assign StallMCause = '0; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); - //assign StallWCause = (IFUStallF & ~FlushDCause) | ((LSUStallM | WFIStallM) & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled // coverage off: StallFCause is always 0 diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index ccd06a1ea..b25c3b905 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -39,7 +39,6 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic CSRReadM, CSRWriteM, // read or write CSR input logic TrapM, // trap is occurring input logic mretM, sretM, wfiM, // return or WFI instruction - output logic wfiW, input logic IntPendingM, // at least one interrupt is pending and could occur if enabled input logic InterruptM, // interrupt is occurring input logic ExceptionM, // interrupt is occurring @@ -201,7 +200,6 @@ module csr import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// // CSR Write values /////////////////////////////////////////// - flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM; diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index e6edbb086..eb17b8d04 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -39,7 +39,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( output logic IllegalInstrFaultM, // Illegal instruction output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs output logic sretM, mretM, // return instructions - output logic wfiM, sfencevmaM // wfi / sfence.vma / sinval.vma instructions + output logic wfiM, wfiW, sfencevmaM // wfi / sfence.vma / sinval.vma instructions ); logic rs1zeroM; // rs1 field = 0 @@ -75,8 +75,6 @@ module privdec import cvw::*; #(parameter cvw_t P) ( /////////////////////////////////////////// // WFI timeout Privileged Spec 3.1.6.5 /////////////////////////////////////////// - logic wfiW; // *** need to merge with others - flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); // *** remove if (P.U_SUPPORTED) begin:wfi logic [P.WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; @@ -88,6 +86,8 @@ module privdec import cvw::*; #(parameter cvw_t P) ( // coverage on end else assign WFITimeoutM = 0; + flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW); + /////////////////////////////////////////// // Extract exceptions by name and handle them /////////////////////////////////////////// diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c338d2475..d777e0bf9 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -125,12 +125,12 @@ module privileged import cvw::*; #(parameter cvw_t P) ( privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]), .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, - .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM); + .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM); // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF, - .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .wfiW, .IntPendingM, .InterruptM, + .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,