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Simplify FSM

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This commit is contained in:
David Harris 2021-07-17 04:12:31 -04:00
parent 03ef3f7f17
commit 330e500442
1 changed files with 16 additions and 35 deletions
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51
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -156,6 +156,9 @@ module pagetablewalker
assign PageTableEntryF = PageTableEntry; assign PageTableEntryF = PageTableEntry;
assign PageTableEntryM = PageTableEntry; assign PageTableEntryM = PageTableEntry;
assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
// *** is there a way to speed up HPTW? // *** is there a way to speed up HPTW?
// TranslationPAdr mux // TranslationPAdr mux
@ -216,7 +219,6 @@ module pagetablewalker
// State transition logic // State transition logic
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
// TranslationPAdr = '0;
HPTWRead = 1'b0; HPTWRead = 1'b0;
PageTableEntry = '0; PageTableEntry = '0;
PageType = '0; PageType = '0;
@ -227,46 +229,27 @@ module pagetablewalker
WalkerLoadPageFaultM = 1'b0; WalkerLoadPageFaultM = 1'b0;
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
SelPTW = 1'b1; // SelPTW = 1'b1;
case (WalkerState) case (WalkerState)
IDLE: begin IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE;
SelPTW = 1'b0; else NextWalkerState = IDLE;
if (AnyTLBMissM & SvMode == `SV32) begin LEVEL1_SET_ADRE: NextWalkerState = LEVEL1_WDV;
NextWalkerState = LEVEL1_SET_ADRE;
end else begin
NextWalkerState = IDLE;
end
end
LEVEL1_SET_ADRE: begin
NextWalkerState = LEVEL1_WDV;
//TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
end
LEVEL1_WDV: begin LEVEL1_WDV: begin
//TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
HPTWRead = 1'b1; HPTWRead = 1'b1;
if (HPTWStall) begin if (HPTWStall) NextWalkerState = LEVEL1_WDV;
NextWalkerState = LEVEL1_WDV; else begin
end else begin
NextWalkerState = LEVEL1; NextWalkerState = LEVEL1;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL1: begin LEVEL1: begin
if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) begin if (ValidPTE && LeafPTE && ~(MegapageMisaligned | ADPageFault)) NextWalkerState = LEAF;
NextWalkerState = LEAF;
//TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this
end
else if (ValidPTE && ~LeafPTE) begin else if (ValidPTE && ~LeafPTE) begin
NextWalkerState = LEVEL0_SET_ADRE; NextWalkerState = LEVEL0_SET_ADRE;
//TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; HPTWRead = 1'b1;
HPTWRead = 1'b1; end else NextWalkerState = FAULT;
end else begin
NextWalkerState = FAULT;
end
end end
LEVEL0_SET_ADRE: begin LEVEL0_SET_ADRE: begin
@ -304,7 +287,7 @@ module pagetablewalker
end end
FAULT: begin FAULT: begin
SelPTW = 1'b0; //SelPTW = 1'b0;
NextWalkerState = IDLE; NextWalkerState = IDLE;
WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
@ -356,11 +339,9 @@ module pagetablewalker
WalkerLoadPageFaultM = 1'b0; WalkerLoadPageFaultM = 1'b0;
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
SelPTW = 1'b1;
case (WalkerState) case (WalkerState)
IDLE: begin IDLE: begin
SelPTW = 1'b0; //SelPTW = 1'b0;
if (AnyTLBMissM & SvMode == `SV48) begin if (AnyTLBMissM & SvMode == `SV48) begin
NextWalkerState = LEVEL3_SET_ADRE; NextWalkerState = LEVEL3_SET_ADRE;
end else if (AnyTLBMissM & SvMode == `SV39) begin end else if (AnyTLBMissM & SvMode == `SV39) begin
@ -505,7 +486,7 @@ module pagetablewalker
end end
FAULT: begin FAULT: begin
SelPTW = 1'b0; //SelPTW = 1'b0;
NextWalkerState = IDLE; NextWalkerState = IDLE;
WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;