diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv
new file mode 100644
index 000000000..42702d89c
--- /dev/null
+++ b/src/ieu/kmu/packer.sv
@@ -0,0 +1,67 @@
+///////////////////////////////////////////
+// packer.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 5 October 2023
+//
+// Purpose: RISCV kbitmanip pack operation unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module packer #(parameter WIDTH=32) (
+  input logic [WIDTH-1:0]  A, B,
+  input logic [2:0] 	   PackSelect, 
+  output logic [WIDTH-1:0] PackResult);
+   
+   logic [WIDTH/2-1:0] 	   low_half, high_half;
+   logic [7:0] 		   low_halfh, high_halfh;
+   logic [15:0] 	   low_halfw, high_halfw;
+   
+   logic [WIDTH-1:0] 	   Pack;
+   logic [WIDTH-1:0] 	   PackH;
+   logic [WIDTH-1:0] 	   PackW;
+   logic [1:0] 		   MuxSelect;
+   
+   assign low_half = A[WIDTH/2-1:0];
+   assign high_half = B[WIDTH/2-1:0];
+   assign low_halfh = A[7:0];
+   assign high_halfh = B[7:0];
+   assign low_halfw = A[15:0];
+   assign high_halfw = B[15:0];   
+   
+   assign Pack = {high_half, low_half}; 
+   assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh}; 
+   assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw}; 
+   
+   // TODO: FIX THIS ... this is completely incorrect way to use if statements
+   // Solution for now:
+   always_comb 
+     begin
+	if (PackSelect[1:0] == 2'b11) 
+	  MuxSelect = 2'b01;
+	else if (PackSelect[2] == 1'b0) 
+	  MuxSelect = 2'b00;
+	else 
+	  MuxSelect = 2'b10;
+     end
+   
+  mux3 #(WIDTH) PackMux(Pack, PackH, PackW, MuxSelect, PackResult);
+
+endmodule
diff --git a/src/ieu/kmu/revop.sv b/src/ieu/kmu/revop.sv
new file mode 100644
index 000000000..901e1532e
--- /dev/null
+++ b/src/ieu/kmu/revop.sv
@@ -0,0 +1,44 @@
+///////////////////////////////////////////
+// revop.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 5 October 2023
+//
+// Purpose: RISCV kbitmanip reverse byte-wise operation unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module revop #(parameter WIDTH=32) 
+   (input  logic [WIDTH-1:0] A,  // Operands
+    input logic [WIDTH-1:0]  RevA, // A Reversed
+    input logic 	     revType, // rev8 or brev8 (LSB of immediate)
+    output logic [WIDTH-1:0] RevResult); // results
+   
+   logic [WIDTH-1:0] 	     Rev8Result, Brev8Result;
+   genvar 		     i;
+   
+   for (i=0; i<WIDTH; i+=8) begin:loop
+      assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
+      assign Brev8Result[i+7:i] = RevA[WIDTH-1-i:WIDTH-i-8];
+   end
+   
+  mux2 #(WIDTH) revMux (Rev8Result, Brev8Result, revType, RevResult);
+   
+endmodule
diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv
new file mode 100644
index 000000000..9df27d490
--- /dev/null
+++ b/src/ieu/kmu/zbkb.sv
@@ -0,0 +1,46 @@
+///////////////////////////////////////////
+// zbkb.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 4 October 2023
+//
+// Purpose: RISC-V ZBKB top level unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zbkb #(parameter WIDTH=32) 
+   (input  logic [WIDTH-1:0] A, B, RevA,
+    input logic 	     W64,
+    input logic [2:0] 	     Funct3,
+    input logic [2:0] 	     ZBKBSelect,
+    output logic [WIDTH-1:0] ZBKBResult);
+   
+   logic [WIDTH-1:0] 	     RevResult;    // rev8, brev8
+   logic [WIDTH-1:0] 	     PackResult;   // pack, packh, packw (RB64 only)
+   logic [WIDTH-1:0] 	     ZipResult;    // zip, unzip
+   
+   revop #(WIDTH) rev(.A, .RevA, .revType(B[0]), .RevResult);
+   packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
+   zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
+   
+   // ZBKB Result Select Mux
+   mux3 #(WIDTH) zbkbresultmux(RevResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
+   
+endmodule
diff --git a/src/ieu/kmu/zbkc.sv b/src/ieu/kmu/zbkc.sv
new file mode 100644
index 000000000..66afe0e9a
--- /dev/null
+++ b/src/ieu/kmu/zbkc.sv
@@ -0,0 +1,55 @@
+///////////////////////////////////////////
+// zbkc.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 27 November 2023
+//
+// Purpose: RISC-V ZBKC top level unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zbkc #(parameter WIDTH=32) 
+   (input  logic [WIDTH-1:0] A, B,
+    input logic 	     ZBKCSelect,
+    output logic [WIDTH-1:0] ZBKCResult);
+   
+   logic [WIDTH-1:0] 	     temp, if_temp;
+   integer 		     i;
+   
+   always_comb begin
+      temp = 0;      
+      if (ZBKCSelect != 1'b0) begin   // clmulh
+	 for (i=1; i<WIDTH; i+=1) begin: clmulh
+            if_temp = (B >> i) & 1;
+            if(if_temp[0]) temp = temp ^ (A >> (WIDTH-i));
+            else temp = temp;
+	 end
+      end
+      else begin                      // clmul
+	 for (i=0; i<WIDTH; i+=1) begin: clmul
+            if_temp = (B >> i) & 1;
+            if(if_temp[0]) temp = temp ^ (A << i);
+            else temp = temp;
+	 end
+      end
+   end
+   assign ZBKCResult = temp;
+
+endmodule
diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv
new file mode 100644
index 000000000..9d42dd372
--- /dev/null
+++ b/src/ieu/kmu/zbkx.sv
@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// zbkx.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 1 February 2024
+//
+// Purpose: RISC-V ZBKX top level unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zbkx #(parameter WIDTH=32) 
+   (input  logic [WIDTH-1:0] A, B,
+    input logic [2:0] 	     ZBKXSelect,
+    output logic [WIDTH-1:0] ZBKXResult);
+   
+   logic [WIDTH-1:0] 	     xperm_lookup[0:WIDTH];
+   logic [WIDTH-1:0] 	     XPERM8_Result;
+   logic [WIDTH-1:0] 	     XPERM4_Result;
+   genvar 		     i;
+   
+   for(i=0; i<WIDTH; i=i+8) begin: xperm8
+      assign xperm_lookup[i] = A >> {B[i+7:i], 3'b0};
+      assign XPERM8_Result[i+7:i] = xperm_lookup[i][7:0];
+   end
+   
+   for(i=0; i<WIDTH; i=i+4) begin: xperm4
+      assign xperm_lookup[i+1] = A >> {B[i+3:i], 2'b0};
+      assign XPERM4_Result[i+3:i] = xperm_lookup[i+1][3:0];
+   end
+   
+   mux2 #(WIDTH) ZbkxMux (XPERM8_Result, XPERM4_Result, ZBKXSelect[0], ZBKXResult);
+   
+endmodule
diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv
new file mode 100644
index 000000000..acbd36355
--- /dev/null
+++ b/src/ieu/kmu/zipper.sv
@@ -0,0 +1,47 @@
+///////////////////////////////////////////
+// zipper.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 9 October 2023
+//
+// Purpose: RISCV kbitmanip zip operation unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zipper #(parameter WIDTH=64) 
+   (input  logic [WIDTH-1:0] A,
+    input logic 	     ZipSelect,
+    output logic [WIDTH-1:0] ZipResult);
+   
+   logic [WIDTH-1:0] 	     zip;
+   logic [WIDTH-1:0] 	     unzip;
+   genvar 		     i;
+   
+   for (i=0; i<WIDTH/2; i+=1) begin: loop
+      assign zip[2*i] = A[i];
+      assign zip [2*i+1] = A[i + WIDTH/2];
+      
+      assign unzip[i] = A[2*i];
+      assign unzip[i+WIDTH/2] = A[2*i+1];
+   end
+   
+   mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);
+   
+endmodule
diff --git a/src/ieu/kmu/zknd_32.sv b/src/ieu/kmu/zknd_32.sv
new file mode 100644
index 000000000..6ef6da9a9
--- /dev/null
+++ b/src/ieu/kmu/zknd_32.sv
@@ -0,0 +1,44 @@
+///////////////////////////////////////////
+// zknd_32.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 27 November 2023
+// Modified: 31 January 2024
+//
+// Purpose: RISC-V ZKND top level unit for 32-bit instructions
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zknd_32 #(parameter WIDTH=32) 
+   (input  logic [WIDTH-1:0] A, B,
+    input logic [6:0] 	     Funct7,
+    input logic [2:0] 	     ZKNDSelect,
+    output logic [WIDTH-1:0] ZKNDResult);
+   
+   logic [31:0] 	     aes32dsiRes;
+   logic [31:0] 	     aes32dsmiRes;
+   
+   // RV32
+   aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsiRes));
+   aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsmiRes));
+   
+   mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
+
+endmodule
diff --git a/src/ieu/kmu/zknd_64.sv b/src/ieu/kmu/zknd_64.sv
new file mode 100644
index 000000000..69e190ad3
--- /dev/null
+++ b/src/ieu/kmu/zknd_64.sv
@@ -0,0 +1,51 @@
+///////////////////////////////////////////
+// zknd_64.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 27 November 2023
+// Modified: 31 January 2024
+//
+// Purpose: RISC-V ZKND top level unit for 64-bit instructions
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zknd_64 #(parameter WIDTH=32) 
+   (input logic [WIDTH-1:0]  A, B,
+    input logic [6:0] 	     Funct7,
+    input logic [3:0] 	     RNUM,
+    input logic [2:0] 	     ZKNDSelect,
+    output logic [WIDTH-1:0] ZKNDResult);
+   
+   logic [63:0] 	     aes64dsRes;
+   logic [63:0] 	     aes64dsmRes;
+   logic [63:0] 	     aes64imRes;
+   logic [63:0] 	     aes64ks1iRes;
+   logic [63:0] 	     aes64ks2Res;
+   
+   // RV64
+   aes64ds aes64ds (.rs1(A), .rs2(B), .data_out(aes64dsRes));
+   aes64dsm aes64dsm (.rs1(A), .rs2(B), .data_out(aes64dsmRes));
+   aes64im aes64im (.rs1(A), .data_out(aes64imRes));
+   aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
+   aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
+   
+   mux5 #(WIDTH) zkndmux (aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
+
+endmodule
diff --git a/src/ieu/kmu/zkne_32.sv b/src/ieu/kmu/zkne_32.sv
new file mode 100644
index 000000000..c4ec0b78d
--- /dev/null
+++ b/src/ieu/kmu/zkne_32.sv
@@ -0,0 +1,44 @@
+///////////////////////////////////////////
+// zkne_32.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 21 November 2023
+// Modified: 31 January 2024
+//
+// Purpose: RISC-V ZKNE top level unit for 32-bit instructions
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zkne_32 #(parameter WIDTH=32) 
+   (input logic [WIDTH-1:0]  A, B,
+    input logic [6:0] 	     Funct7,
+    input logic [2:0] 	     ZKNESelect,
+    output logic [WIDTH-1:0] ZKNEResult);
+   
+   logic [31:0] 	     aes32esiRes;
+   logic [31:0] 	     aes32esmiRes;
+   
+   // RV32
+   aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esiRes));
+   aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esmiRes));
+   
+   mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
+
+endmodule
diff --git a/src/ieu/kmu/zkne_64.sv b/src/ieu/kmu/zkne_64.sv
new file mode 100644
index 000000000..84e45852f
--- /dev/null
+++ b/src/ieu/kmu/zkne_64.sv
@@ -0,0 +1,50 @@
+///////////////////////////////////////////
+// zkne_64.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 21 November 2023
+// Modified: 31 January 2024
+//
+// Purpose: RISC-V ZKNE top level unit for 64-bit instructions
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zkne_64 #(parameter WIDTH=32) 
+   (input logic [WIDTH-1:0]  A, B,
+    input logic [6:0] 	     Funct7,
+    input logic [3:0] 	     RNUM,
+    input logic [2:0] 	     ZKNESelect,
+    output logic [WIDTH-1:0] ZKNEResult);
+   
+   logic [63:0] 	     aes64esRes;
+   logic [63:0] 	     aes64esmRes;
+   logic [63:0] 	     aes64ks1iRes;
+   logic [63:0] 	     aes64ks2Res;
+   
+   // RV64
+   aes64es aes64es (.rs1(A), .rs2(B), .data_out(aes64esRes));
+   aes64esm aes64esm (.rs1(A), .rs2(B), .data_out(aes64esmRes));
+   aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
+   aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
+   
+   // 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
+   mux5 #(WIDTH) zknemux (aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
+   
+endmodule
diff --git a/src/ieu/kmu/zknh_32.sv b/src/ieu/kmu/zknh_32.sv
new file mode 100644
index 000000000..8c9cf79c8
--- /dev/null
+++ b/src/ieu/kmu/zknh_32.sv
@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// zknh_32.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 13 February 2024
+//
+// Purpose: RISC-V ZKNH 32-Bit top level unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zknh_32 (input  logic [31:0] A, B,
+		input logic [3:0] ZKNHSelect,
+		output logic [31:0] ZKNHResult);
+   
+   logic [31:0] 		    sha256sig0_res;
+   logic [31:0] 		    sha256sig1_res;
+   logic [31:0] 		    sha256sum0_res;
+   logic [31:0] 		    sha256sum1_res;
+   
+   logic [31:0] 		    sha512sig0h_res;
+   logic [31:0] 		    sha512sig0l_res;
+   logic [31:0] 		    sha512sig1h_res;
+   logic [31:0] 		    sha512sig1l_res;
+   logic [31:0] 		    sha512sum0r_res;
+   logic [31:0] 		    sha512sum1r_res;
+   
+   sha256sig0 #(32) sha256sig0(A, sha256sig0_res);
+   sha256sig1 #(32) sha256sig1(A, sha256sig1_res);
+   sha256sum0 #(32) sha256sum0(A, sha256sum0_res);
+   sha256sum1 #(32) sha256sum1(A, sha256sum1_res);
+   sha512sig0h sha512sig0h(A, B, sha512sig0h_res);
+   sha512sig0l sha512sig0l(A, B, sha512sig0l_res);
+   sha512sig1h sha512sig1h(A, B, sha512sig1h_res);
+   sha512sig1l sha512sig1l(A, B, sha512sig1l_res);
+   sha512sum0r sha512sum0r(A, B, sha512sum0r_res);
+   sha512sum1r sha512sum1r(A, B, sha512sum1r_res);
+   
+   // Result Select Mux
+   always_comb begin
+      casez(ZKNHSelect)
+	4'b0000: ZKNHResult = sha256sig0_res;
+	4'b0001: ZKNHResult = sha256sig1_res;
+	4'b0010: ZKNHResult = sha256sum0_res;
+	4'b0011: ZKNHResult = sha256sum1_res;
+	4'b0100: ZKNHResult = sha512sig0h_res;
+	4'b0101: ZKNHResult = sha512sig0l_res;
+	4'b0110: ZKNHResult = sha512sig1h_res;
+	4'b0111: ZKNHResult = sha512sig1l_res;
+	4'b1000: ZKNHResult = sha512sum0r_res;
+	4'b1001: ZKNHResult = sha512sum1r_res;
+	default ZKNHResult = 0;
+      endcase
+   end
+
+endmodule
diff --git a/src/ieu/kmu/zknh_64.sv b/src/ieu/kmu/zknh_64.sv
new file mode 100644
index 000000000..d090214aa
--- /dev/null
+++ b/src/ieu/kmu/zknh_64.sv
@@ -0,0 +1,65 @@
+///////////////////////////////////////////
+// zknh_64.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 13 February 2024
+//
+// Purpose: RISC-V ZKNH 64-Bit top level unit
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module zknh_64 (input  logic [63:0] A, B, input  logic [3:0]  ZKNHSelect,
+		output logic [63:0] ZKNHResult);
+
+   logic [63:0] 		    sha256sig0_res;
+   logic [63:0] 		    sha256sig1_res;
+   logic [63:0] 		    sha256sum0_res;
+   logic [63:0] 		    sha256sum1_res;
+   
+   logic [63:0] 		    sha512sig0_res;
+   logic [63:0] 		    sha512sig1_res;
+   logic [63:0] 		    sha512sum0_res;
+   logic [63:0] 		    sha512sum1_res;   
+   
+   sha256sig0 #(64) sha256sig0(A, sha256sig0_res);
+   sha256sig1 #(64) sha256sig1(A, sha256sig1_res);
+   sha256sum0 #(64) sha256sum0(A, sha256sum0_res);
+   sha256sum1 #(64) sha256sum1(A, sha256sum1_res);
+   sha512sig0 sha512sig0(A, sha512sig0_res);
+   sha512sig1 sha512sig1(A, sha512sig1_res);
+   sha512sum0 sha512sum0(A, sha512sum0_res);
+   sha512sum1 sha512sum1(A, sha512sum1_res);
+   
+   // Result Select Mux
+   always_comb begin
+      casez(ZKNHSelect)
+	4'b0000: ZKNHResult = sha256sig0_res;
+	4'b0001: ZKNHResult = sha256sig1_res;
+	4'b0010: ZKNHResult = sha256sum0_res;
+	4'b0011: ZKNHResult = sha256sum1_res;
+	4'b1010: ZKNHResult = sha512sig0_res;
+	4'b1011: ZKNHResult = sha512sig1_res;
+	4'b1100: ZKNHResult = sha512sum0_res;
+	4'b1101: ZKNHResult = sha512sum1_res;
+	default ZKNHResult = 0;
+      endcase
+   end
+
+endmodule