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https://github.com/openhwgroup/cvw
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Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
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@ -173,10 +173,10 @@ module fpu (
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mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
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mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
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mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
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mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
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// unpacking unit
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// unpack unit
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// - splits FP inputs into their various parts
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// - splits FP inputs into their various parts
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// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
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// - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
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unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE,
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unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE,
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.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
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.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
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.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
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.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
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@ -1,6 +1,6 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module unpacking (
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module unpack (
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input logic [63:0] X, Y, Z,
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input logic [63:0] X, Y, Z,
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input logic FmtE,
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input logic FmtE,
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input logic [2:0] FOpCtrlE,
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input logic [2:0] FOpCtrlE,
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@ -86,17 +86,17 @@ module datapath (
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logic [`XLEN-1:0] WriteDataE;
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logic [`XLEN-1:0] WriteDataE;
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// Memory stage signals
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// Memory stage signals
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] ResultM;
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logic [`XLEN-1:0] IFResultM;
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// Writeback stage signals
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// Writeback stage signals
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logic [`XLEN-1:0] SCResultW;
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logic [`XLEN-1:0] SCResultW;
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logic [`XLEN-1:0] WriteDataW;
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logic [`XLEN-1:0] ResultW;
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logic [`XLEN-1:0] ResultW;
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logic [`XLEN-1:0] IFResultW;
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// Decode stage
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// Decode stage
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assign Rs1D = InstrD[19:15];
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assign Rs1D = InstrD[19:15];
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assign Rs2D = InstrD[24:20];
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assign Rs2D = InstrD[24:20];
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assign RdD = InstrD[11:7];
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assign RdD = InstrD[11:7];
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regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, R1D, R2D);
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regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
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extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
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extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
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// Execute stage pipeline register and logic
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// Execute stage pipeline register and logic
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@ -107,8 +107,8 @@ module datapath (
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flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
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flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
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flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
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flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
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mux3 #(`XLEN) faemux(R1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
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mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
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mux3 #(`XLEN) fbemux(R2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
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mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
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@ -123,17 +123,17 @@ module datapath (
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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// Writeback stage pipeline register and logic
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// Writeback stage pipeline register and logic
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flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
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flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
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flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
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flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
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flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW);
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flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW);
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mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW);
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mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW);
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// floating point interactions: fcvt, fp stores
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// floating point interactions: fcvt, fp stores
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if (`F_SUPPORTED) begin:fpmux
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if (`F_SUPPORTED) begin:fpmux
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mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
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mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
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mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
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mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
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end else begin:fpmux
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end else begin:fpmux
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assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
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assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
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end
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end
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// handle Store Conditional result if atomic extension supported
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// handle Store Conditional result if atomic extension supported
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@ -83,7 +83,7 @@ module testbench;
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// Unpacker
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// Unpacker
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// Note: BiasE will probably get taken out eventually
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// Note: BiasE will probably get taken out eventually
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unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
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unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
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.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
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.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
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.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
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.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
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.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
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.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
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@ -51,7 +51,7 @@ module testbench ();
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integer desc3;
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integer desc3;
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// instantiate device under test
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// instantiate device under test
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unpacking unpacking(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE,
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unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE,
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.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
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.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
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.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
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.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
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