diff --git a/Makefile b/Makefile index 2c445fc46..877e69e52 100644 --- a/Makefile +++ b/Makefile @@ -40,7 +40,7 @@ imperasdv: iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m coverage: - cd ${WALLY}/sim; ./regresssion-wally -coverage -fp + cd ${WALLY}/sim; ./regression-wally -coverage -fp benchmarks: make coremark diff --git a/config/derivlist.txt b/config/derivlist.txt index 279fbd3c5..6851278b3 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -546,6 +546,10 @@ deriv fd_rv64gc rv64gc MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 +deriv fdh_rv64gc rv64gc +MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + deriv fdq_rv64gc rv64gc MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) ZFH_SUPPORTED 0 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 9f0056fad..5e1f883d4 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -179,6 +179,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 843f55530..d6fb995b1 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 81b25bc2b..490937558 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 931725cc4..357eba840 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -178,6 +178,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 7f038d87e..1d6c5e9f4 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 1; +localparam ZBKC_SUPPORTED = 1; +localparam ZBKX_SUPPORTED = 1; +localparam ZKND_SUPPORTED = 1; +localparam ZKNE_SUPPORTED = 1; +localparam ZKNH_SUPPORTED = 1; +localparam ZK_SUPPORTED = 1; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 4dd540a9f..a289003cc 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0; localparam ZCF_SUPPORTED = 0; localparam ZCD_SUPPORTED = 0; +// K extension instructions +localparam ZBKB_SUPPORTED = 0; +localparam ZBKC_SUPPORTED = 0; +localparam ZBKX_SUPPORTED = 0; +localparam ZKNE_SUPPORTED = 0; +localparam ZKND_SUPPORTED = 0; +localparam ZK_SUPPORTED = 0; +localparam ZKNH_SUPPORTED = 0; + // Memory synthesis configuration localparam USE_SRAM = 0; diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index dd766f2fd..6763f583c 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -29,6 +29,7 @@ localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1); localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1); localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1); localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1); +localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED)); localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1); localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1); localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1); diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 464e3c0f9..5635b286c 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -113,6 +113,13 @@ localparam cvw_t P = '{ ZCB_SUPPORTED : ZCB_SUPPORTED, ZCD_SUPPORTED : ZCD_SUPPORTED, ZCF_SUPPORTED : ZCF_SUPPORTED, + ZBKB_SUPPORTED: ZBKB_SUPPORTED, + ZBKC_SUPPORTED: ZBKC_SUPPORTED, + ZBKX_SUPPORTED: ZBKX_SUPPORTED, + ZKND_SUPPORTED: ZKND_SUPPORTED, + ZKNE_SUPPORTED: ZKNE_SUPPORTED, + ZKNH_SUPPORTED: ZKNH_SUPPORTED, + ZK_SUPPORTED : ZK_SUPPORTED, USE_SRAM : USE_SRAM, M_MODE : M_MODE, S_MODE : S_MODE, @@ -136,6 +143,7 @@ localparam cvw_t P = '{ E_SUPPORTED : E_SUPPORTED, F_SUPPORTED : F_SUPPORTED, I_SUPPORTED : I_SUPPORTED, + K_SUPPORTED : K_SUPPORTED, M_SUPPORTED : M_SUPPORTED, Q_SUPPORTED : Q_SUPPORTED, S_SUPPORTED : S_SUPPORTED, diff --git a/setup.csh b/setup.csh index 82728f57c..62a99f376 100755 --- a/setup.csh +++ b/setup.csh @@ -5,48 +5,20 @@ echo "Executing Wally setup.csh" -# Path to Wally repository -setenv WALLY $PWD -echo '$WALLY set to ' ${WALLY} # Extend alias which makes extending PATH much easier. alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;echo Added \!:2 to \!:1' alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1' -# License servers and commercial CAD tool paths -# Must edit these based on your local environment. Ask your sysadmin. -setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server -setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa -setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler - # Path to RISC-V Tools setenv RISCV /opt/riscv # change this if you installed the tools in a different location -# Tools -# Questa and Synopsys -extend PATH $QUESTAPATH -extend PATH $SNPSPATH -# GCC -prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib -prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib -extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools -extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools -# Spike -extend LD_LIBRARY_PATH $RISCV/lib -extend PATH $RISCV/bin +# Path to Wally repository +setenv WALLY $PWD +echo '$WALLY set to ' ${WALLY} # utility functions in Wally repository extend PATH $WALLY/bin -# Verilator -extend PATH /usr/local/bin/verilator # Change this for your path to Verilator -# ModelSim/Questa (vsim) -# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now -# Imperas; put this in if you are using it -#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) -#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas - -# Verilator needs a larger stack to simulate CORE-V Wally -limit stacksize unlimited +source $RISCV/site-setup.csh echo "setup done" diff --git a/setup.sh b/setup.sh old mode 100755 new mode 100644 index e1d4e6cd3..f609c1e3d --- a/setup.sh +++ b/setup.sh @@ -2,58 +2,31 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 -# Set up tools for rvw +# Set up tools for cvw + +# optionally have .bashrc or .bash_profile source this file with +#if [ -f ~/cvw/setup.sh ]; then +# source ~/cvw/setup.sh +#fi + # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 echo "Executing Wally setup.sh" +# Path to RISC-V Tools +export RISCV=/opt/riscv # change this if you installed the tools in a different location + # Path to Wally repository WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to ${WALLY} - -# License servers and commercial CAD tool paths -# Must edit these based on your local environment. Ask your sysadmin. -export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server -export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin -export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin - -# Path to RISC-V Tools -export RISCV=/opt/riscv # change this if you installed the tools in a different location - -# Tools -# Questa and Synopsys -export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH -# GCC -export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib -export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools -# Spike -export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH -export PATH=$PATH:$RISCV/bin # utility functions in Wally repository export PATH=$WALLY/bin:$PATH -# Verilator -export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator -# ModelSim/Questa (vsim) -# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks. Ues 2021.2 for now - -# Imperas; put this in if you are using it -#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH -#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas - -export IDV=$RISCV/ImperasDV-OpenHW -if [ -e "$IDV" ]; then -# echo "Imperas exists" - export IMPERAS_HOME=$IDV/Imperas - export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC - export ROOTDIR=~/ - source ${IMPERAS_HOME}/bin/setup.sh - setupImperas ${IMPERAS_HOME} - export PATH=$IDV/scripts/cvw:$PATH -fi # Verilator needs a larger stack to simulate CORE-V Wally ulimit -s 100000 -echo "setup done" \ No newline at end of file +# load site licenses and tool locations +source $RISCV/site-setup.sh + +echo "setup done" diff --git a/sim/regression-wally b/sim/regression-wally index 26543d067..42c54d016 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -89,7 +89,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad", +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad", #tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( @@ -128,7 +128,7 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", +tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh", "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working #tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", # "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"] @@ -272,13 +272,13 @@ if (nightly): ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], - ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma"]], - ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]], + ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]], ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], - ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma"]], - ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "wally64q"]], + ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]], ] diff --git a/site-setup.csh b/site-setup.csh new file mode 100644 index 000000000..d2a52e720 --- /dev/null +++ b/site-setup.csh @@ -0,0 +1,46 @@ +#!/bin/csh + +# site-setup.csh + +# License servers and commercial CAD tool paths +# Must edit these based on your local environment. Ask your sysadmin. +setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server +setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server +setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa +setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler + +# Tools +# Questa and Synopsys +extend PATH $QUESTAPATH +extend PATH $SNPSPATH + +# GCC +prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib +prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib +extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools +extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools + +# Spike +extend LD_LIBRARY_PATH $RISCV/lib +extend PATH $RISCV/bin + +# Verilator +extend PATH /usr/local/bin/verilator # Change this for your path to Verilator +# Verilator needs a larger stack to simulate CORE-V Wally +limit stacksize unlimited + +# Imperas; put this in if you are using it +#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) +#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas + +setenv IDV $RISCV/ImperasDV-OpenHW +if ($?IDV) then +# echo "Imperas exists" + setenv IMPERAS_HOME $IDV/Imperas + setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC + setenv ROOTDIR ~/ + source ${IMPERAS_HOME}/bin/setup.sh + setupImperas ${IMPERAS_HOME} + extend PATH $IDV/scripts/cvw +endfi + diff --git a/site-setup.sh b/site-setup.sh new file mode 100755 index 000000000..cf28a93f1 --- /dev/null +++ b/site-setup.sh @@ -0,0 +1,46 @@ +#!/bin/bash + +# site-setup.sh +# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 +# System Admin should install this into $RISCV/site-setup.sh +# $RISCV is typically /opt/riscv +# System Admin must update the licenses and paths for localization. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# license servers and commercial CAD tool paths +# Must edit these based on your local environment. +export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa +export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler +export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin +export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin + +# Tools +# Questa and Synopsys +export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH + +# GCC +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib +export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools + +# Spike +export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH +export PATH=$PATH:$RISCV/bin + +# Verilator +export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator + +# Imperas OVPsim; put this in if you are using it +#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH +#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH + +export IDV=$RISCV/ImperasDV-OpenHW +if [ -e "$IDV" ]; then +# echo "Imperas exists" + export IMPERAS_HOME=$IDV/Imperas + export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC + export ROOTDIR=~/ + source ${IMPERAS_HOME}/bin/setup.sh + setupImperas ${IMPERAS_HOME} + export PATH=$IDV/scripts/cvw:$PATH +fi + diff --git a/src/cvw.sv b/src/cvw.sv index 75f83f68b..21b55c55e 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -180,6 +180,15 @@ typedef struct packed { logic ZCD_SUPPORTED; logic ZCF_SUPPORTED; +// Cryptography + logic ZBKB_SUPPORTED; + logic ZBKC_SUPPORTED; + logic ZBKX_SUPPORTED; + logic ZKND_SUPPORTED; + logic ZKNE_SUPPORTED; + logic ZKNH_SUPPORTED; + logic ZK_SUPPORTED; + // Memory synthesis configuration logic USE_SRAM; @@ -214,6 +223,7 @@ typedef struct packed { logic E_SUPPORTED; logic F_SUPPORTED; logic I_SUPPORTED; + logic K_SUPPORTED; logic M_SUPPORTED; logic Q_SUPPORTED; logic S_SUPPORTED; diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 85a1a5494..1d44cef5d 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -41,14 +41,14 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( input logic StallM, input logic FlushE, input logic SqrtE, SqrtM, - input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src A/B outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, Funct3M, input logic IntDivE, W64E, output logic DivStickyM, output logic FDivBusyE, IFDivStartE, FDivDoneE, output logic [P.NE+1:0] UeM, // Exponent result output logic [P.DIVb:0] UmM, // Significand result - output logic [P.XLEN-1:0] FIntDivResultM + output logic [P.XLEN-1:0] FIntDivResultM // Integer division result (IntDivResult in figure) ); // Floating-point division and square root module, with optional integer division and remainder diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 032bb700e..55810665b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -33,7 +33,7 @@ module fdivsqrtuotfc2 import cvw::*; #(parameter cvw_t P) ( input logic up, un, input logic [P.DIVb+1:0] C, // Q2.DIVb - input logic [P.DIVb:0] U, UM, // U1.DIVb + input logic [P.DIVb:0] U, UM, // U1.DIVb UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer output logic [P.DIVb:0] UNext, UMNext // U1.DIVb ); // The on-the-fly converter transfers the divsqrt diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 19e322013..5a802934e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -29,7 +29,7 @@ module fdivsqrtuotfc4 import cvw::*; #(parameter cvw_t P) ( input logic [3:0] udigit, - input logic [P.DIVb:0] U, UM, // U1.DIVb + input logic [P.DIVb:0] U, UM, // U1.DIVb UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer input logic [P.DIVb:0] C, // Q1.DIVb output logic [P.DIVb:0] UNext, UMNext // U1.DIVb ); diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index fef26668c..fd1092497 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -48,10 +48,10 @@ module fdivsqrtuslc4cmp ( logic [6:0] mk2, mk1, mk0, mkm1; logic [6:0] mkj2, mkj1, mkj0, mkjm1; - logic [6:0] mks2[7:0], mks1[7:0]; + logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0]; logic sqrtspecial; - // Prepopulate table of mks0 + // Prepopulate table of mks for comparison assign mks2[0] = 12; assign mks2[1] = 14; assign mks2[2] = 16; @@ -68,6 +68,24 @@ module fdivsqrtuslc4cmp ( assign mks1[5] = 8; // is the logic any cheaper if this is a 6? assign mks1[6] = 8; assign mks1[7] = 8; + + assign mks0[0] = -4; + assign mks0[1] = -4; + assign mks0[2] = -6; + assign mks0[3] = -6; + assign mks0[4] = -6; + assign mks0[5] = -8; + assign mks0[6] = -8; + assign mks0[7] = -8; + assign mksm1[0] = -13; + assign mksm1[1] = -14; + assign mksm1[2] = -16; + assign mksm1[3] = -17; + assign mksm1[4] = -18; + assign mksm1[5] = -20; + assign mksm1[6] = -22; + assign mksm1[7] = -23; + // handles special case when j = 0 or j = 1 for sqrt assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7. @@ -85,8 +103,13 @@ module fdivsqrtuslc4cmp ( assign mk2 = sqrtspecial ? mkj2 : mks2[A]; assign mk1 = sqrtspecial ? mkj1 : mks1[A]; + assign mk0 = sqrtspecial ? -mkj1 : mks0[A]; + assign mkm1 = sqrtspecial ? -mkj2 : mksm1[A]; + +/* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000 assign mk0 = -mk1; assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path + */ // Compare residual W to selection constants to choose digit always_comb diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 5a4767c87..f07efeb5c 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -65,6 +65,15 @@ module mux6 #(parameter WIDTH = 8) ( output logic [WIDTH-1:0] y); assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); +endmodule // mux6 + +module mux7 #(parameter WIDTH = 8) ( + input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, + input logic [2:0] s, + output logic [WIDTH-1:0] y); + + assign y = s[2] ? (s[1] ? d6 : (s[0] ? d5 : d4)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); + endmodule /* verilator lint_on DECLFILENAME */ diff --git a/src/ieu/aes/aes32d.sv b/src/ieu/aes/aes32d.sv new file mode 100644 index 000000000..95b75fc80 --- /dev/null +++ b/src/ieu/aes/aes32d.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// aes32d.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32dsmi and aes32dsi instruction: RV32 middle and final round AES decryption +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32d( + input logic [7:0] SboxIn, + input logic finalround, + output logic [31:0] result +); + + logic [7:0] SboxOut; + logic [31:0] so, mixed; + + aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si + assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box + aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function + mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns +endmodule diff --git a/src/ieu/aes/aes32e.sv b/src/ieu/aes/aes32e.sv new file mode 100644 index 000000000..969f8a25f --- /dev/null +++ b/src/ieu/aes/aes32e.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// aes32e.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes32esmi and aes32esi instruction: RV32 middle and final round AES encryption +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes32e( + input logic [7:0] SboxIn, + input logic finalround, + output logic [31:0] result +); + + logic [7:0] SboxOut; + logic [31:0] so, mixed; + + aessbox sbox(SboxIn, SboxOut); // Substitute + assign so = {24'h0, SboxOut}; // Pad sbox output + aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component + mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns +endmodule diff --git a/src/ieu/aes/aes64d.sv b/src/ieu/aes/aes64d.sv new file mode 100644 index 000000000..6f6fc172f --- /dev/null +++ b/src/ieu/aes/aes64d.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// aes64d.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64dsm and aes64ds instruction: RV64 middle and final round AES decryption +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64d( + input logic [63:0] rs1, + input logic [63:0] rs2, + input logic finalround, aes64im, + output logic [63:0] result +); + + logic [127:0] ShiftRowOut; + logic [63:0] SboxOut, MixcolIn, MixcolOut; + + // Apply inverse shiftrows to rs2 and rs1 + aesinvshiftrow srow({rs2, rs1}, ShiftRowOut); + + // Apply full word inverse substitution to lower 2 words of shiftrow out + aesinvsboxword invsbox0(ShiftRowOut[31:0], SboxOut[31:0]); + aesinvsboxword invsbox1(ShiftRowOut[63:32], SboxOut[63:32]); + + mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn); + + // Apply inverse mixword to sbox outputs + aesinvmixcolumns invmw0(MixcolIn[31:0], MixcolOut[31:0]); + aesinvmixcolumns invmw1(MixcolIn[63:32], MixcolOut[63:32]); + + // Final round skips mixcolumns. + mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result); +endmodule diff --git a/src/ieu/aes/aes64e.sv b/src/ieu/aes/aes64e.sv new file mode 100644 index 000000000..98a18fa23 --- /dev/null +++ b/src/ieu/aes/aes64e.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// aes64e.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64esm and aes64es instruction: RV64 middle and final round AES encryption +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64e( + input logic [63:0] rs1, + input logic [63:0] rs2, + input logic finalround, + input logic [31:0] Sbox0Out, + output logic [31:0] SboxEIn, + output logic [63:0] result +); + + logic [127:0] ShiftRowOut; + logic [63:0] SboxOut, MixcolOut; + + // AES shiftrow unit + aesshiftrow srow({rs2,rs1}, ShiftRowOut); + + // Apply substitution box to 2 lower words + // Use the shared sbox in zknde64.sv for the first sbox + assign SboxEIn = ShiftRowOut[31:0]; + assign SboxOut[31:0] = Sbox0Out; + + aessboxword sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox + + // Apply mix columns operations + aesmixcolumns mw0(SboxOut[31:0], MixcolOut[31:0]); + aesmixcolumns mw1(SboxOut[63:32], MixcolOut[63:32]); + + // Skip mixcolumns on last round + mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result); +endmodule diff --git a/src/ieu/aes/aes64ks1i.sv b/src/ieu/aes/aes64ks1i.sv new file mode 100644 index 000000000..ef36e1cc6 --- /dev/null +++ b/src/ieu/aes/aes64ks1i.sv @@ -0,0 +1,52 @@ +/////////////////////////////////////////// +// aes64ks1i.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks1i instruction: part of AES keyschedule with involving sbox +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks1i( + input logic [3:0] round, + input logic [63:0] rs1, + input logic [31:0] Sbox0Out, + output logic [31:0] SboxKIn, + output logic [63:0] result +); + + logic finalround; + logic [7:0] rcon8; + logic [31:0] rcon, rs1Rotate; + + rconlut128 rc(round, rcon8); // Get rcon value from lookup table + assign rcon = {24'b0, rcon8}; // Zero-pad RCON + assign rs1Rotate = {rs1[39:32], rs1[63:40]}; // Get rotated value fo ruse in tmp2 + assign finalround = (round == 4'b1010); // round 10 is the last one + assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate; // Don't rotate on the last round + + // Share sbox with encryption in zknde64. This module just sends value to shared sbox and gets result back + // send out value as SboxKIn, get back subsittuted result as Sbox0Out + + assign result[31:0] = Sbox0Out ^ rcon; + assign result[63:32] = Sbox0Out ^ rcon; +endmodule + diff --git a/src/ieu/aes/aes64ks2.sv b/src/ieu/aes/aes64ks2.sv new file mode 100644 index 000000000..dac9ed50d --- /dev/null +++ b/src/ieu/aes/aes64ks2.sv @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// aes64ks2.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aes64ks2 instruction: part of AES keyschedule +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aes64ks2( + input logic [63:0] rs2, + input logic [63:0] rs1, + output logic [63:0] result +); + + logic [31:0] w0, w1; + + assign w0 = rs1[63:32] ^ rs2[31:0]; + assign w1 = w0 ^ rs2[63:32]; + assign result = {w1, w0}; +endmodule diff --git a/src/ieu/aes/aesinvmixcolumns.sv b/src/ieu/aes/aesinvmixcolumns.sv new file mode 100644 index 000000000..5ef6b2e9c --- /dev/null +++ b/src/ieu/aes/aesinvmixcolumns.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// aesinvmixcolumns.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 05 March 2024 +// +// Purpose: AES Inverted Mix Column Function for use with AES +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesinvmixcolumns( + input logic [31:0] a, + output logic [31:0] y +); + + logic [7:0] a0, a1, a2, a3, temp; + logic [10:0] xor0, xor1, xor2, xor3; + + assign {a0, a1, a2, a3} = a; + assign temp = a0 ^ a1 ^ a2 ^ a3; + + assign xor0 = {temp, 3'b0} ^ {1'b0, a3^a1, 2'b0} ^ {2'b0, a3^a2, 1'b0} ^ {3'b0, temp} ^ {3'b0, a3}; + assign xor1 = {temp, 3'b0} ^ {1'b0, a2^a0, 2'b0} ^ {2'b0, a2^a1, 1'b0} ^ {3'b0, temp} ^ {3'b0, a2}; + assign xor2 = {temp, 3'b0} ^ {1'b0, a1^a3, 2'b0} ^ {2'b0, a1^a0, 1'b0} ^ {3'b0, temp} ^ {3'b0, a1}; + assign xor3 = {temp, 3'b0} ^ {1'b0, a0^a2, 2'b0} ^ {2'b0, a0^a3, 1'b0} ^ {3'b0, temp} ^ {3'b0, a0}; + + galoismultinverse gm0 (xor0, y[7:0]); + galoismultinverse gm1 (xor1, y[15:8]); + galoismultinverse gm2 (xor2, y[23:16]); + galoismultinverse gm3 (xor3, y[31:24]); +endmodule diff --git a/src/ieu/aes/aesinvsbox.sv b/src/ieu/aes/aesinvsbox.sv new file mode 100644 index 000000000..3d62e30f2 --- /dev/null +++ b/src/ieu/aes/aesinvsbox.sv @@ -0,0 +1,292 @@ +/////////////////////////////////////////// +// aesinvsbox.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Rinjdael Inverted S-BOX in form of a LUT +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesinvsbox( + input logic [7:0] a, + output logic [7:0] y +); + + always_comb + case(a) + 8'h00 : y = 8'h52; + 8'h01 : y = 8'h09; + 8'h02 : y = 8'h6A; + 8'h03 : y = 8'hD5; + 8'h04 : y = 8'h30; + 8'h05 : y = 8'h36; + 8'h06 : y = 8'hA5; + 8'h07 : y = 8'h38; + 8'h08 : y = 8'hBF; + 8'h09 : y = 8'h40; + 8'h0A : y = 8'hA3; + 8'h0B : y = 8'h9E; + 8'h0C : y = 8'h81; + 8'h0D : y = 8'hF3; + 8'h0E : y = 8'hD7; + 8'h0F : y = 8'hFB; + 8'h10 : y = 8'h7C; + 8'h11 : y = 8'hE3; + 8'h12 : y = 8'h39; + 8'h13 : y = 8'h82; + 8'h14 : y = 8'h9B; + 8'h15 : y = 8'h2F; + 8'h16 : y = 8'hFF; + 8'h17 : y = 8'h87; + 8'h18 : y = 8'h34; + 8'h19 : y = 8'h8E; + 8'h1A : y = 8'h43; + 8'h1B : y = 8'h44; + 8'h1C : y = 8'hC4; + 8'h1D : y = 8'hDE; + 8'h1E : y = 8'hE9; + 8'h1F : y = 8'hCB; + 8'h20 : y = 8'h54; + 8'h21 : y = 8'h7B; + 8'h22 : y = 8'h94; + 8'h23 : y = 8'h32; + 8'h24 : y = 8'hA6; + 8'h25 : y = 8'hC2; + 8'h26 : y = 8'h23; + 8'h27 : y = 8'h3D; + 8'h28 : y = 8'hEE; + 8'h29 : y = 8'h4C; + 8'h2A : y = 8'h95; + 8'h2B : y = 8'h0B; + 8'h2C : y = 8'h42; + 8'h2D : y = 8'hFA; + 8'h2E : y = 8'hC3; + 8'h2F : y = 8'h4E; + 8'h30 : y = 8'h08; + 8'h31 : y = 8'h2E; + 8'h32 : y = 8'hA1; + 8'h33 : y = 8'h66; + 8'h34 : y = 8'h28; + 8'h35 : y = 8'hD9; + 8'h36 : y = 8'h24; + 8'h37 : y = 8'hB2; + 8'h38 : y = 8'h76; + 8'h39 : y = 8'h5B; + 8'h3A : y = 8'hA2; + 8'h3B : y = 8'h49; + 8'h3C : y = 8'h6D; + 8'h3D : y = 8'h8B; + 8'h3E : y = 8'hD1; + 8'h3F : y = 8'h25; + 8'h40 : y = 8'h72; + 8'h41 : y = 8'hF8; + 8'h42 : y = 8'hF6; + 8'h43 : y = 8'h64; + 8'h44 : y = 8'h86; + 8'h45 : y = 8'h68; + 8'h46 : y = 8'h98; + 8'h47 : y = 8'h16; + 8'h48 : y = 8'hD4; + 8'h49 : y = 8'hA4; + 8'h4A : y = 8'h5C; + 8'h4B : y = 8'hCC; + 8'h4C : y = 8'h5D; + 8'h4D : y = 8'h65; + 8'h4E : y = 8'hB6; + 8'h4F : y = 8'h92; + 8'h50 : y = 8'h6C; + 8'h51 : y = 8'h70; + 8'h52 : y = 8'h48; + 8'h53 : y = 8'h50; + 8'h54 : y = 8'hFD; + 8'h55 : y = 8'hED; + 8'h56 : y = 8'hB9; + 8'h57 : y = 8'hDA; + 8'h58 : y = 8'h5E; + 8'h59 : y = 8'h15; + 8'h5A : y = 8'h46; + 8'h5B : y = 8'h57; + 8'h5C : y = 8'hA7; + 8'h5D : y = 8'h8D; + 8'h5E : y = 8'h9D; + 8'h5F : y = 8'h84; + 8'h60 : y = 8'h90; + 8'h61 : y = 8'hD8; + 8'h62 : y = 8'hAB; + 8'h63 : y = 8'h00; + 8'h64 : y = 8'h8C; + 8'h65 : y = 8'hBC; + 8'h66 : y = 8'hD3; + 8'h67 : y = 8'h0A; + 8'h68 : y = 8'hF7; + 8'h69 : y = 8'hE4; + 8'h6A : y = 8'h58; + 8'h6B : y = 8'h05; + 8'h6C : y = 8'hB8; + 8'h6D : y = 8'hB3; + 8'h6E : y = 8'h45; + 8'h6F : y = 8'h06; + 8'h70 : y = 8'hD0; + 8'h71 : y = 8'h2C; + 8'h72 : y = 8'h1E; + 8'h73 : y = 8'h8F; + 8'h74 : y = 8'hCA; + 8'h75 : y = 8'h3F; + 8'h76 : y = 8'h0F; + 8'h77 : y = 8'h02; + 8'h78 : y = 8'hC1; + 8'h79 : y = 8'hAF; + 8'h7A : y = 8'hBD; + 8'h7B : y = 8'h03; + 8'h7C : y = 8'h01; + 8'h7D : y = 8'h13; + 8'h7E : y = 8'h8A; + 8'h7F : y = 8'h6B; + 8'h80 : y = 8'h3A; + 8'h81 : y = 8'h91; + 8'h82 : y = 8'h11; + 8'h83 : y = 8'h41; + 8'h84 : y = 8'h4F; + 8'h85 : y = 8'h67; + 8'h86 : y = 8'hDC; + 8'h87 : y = 8'hEA; + 8'h88 : y = 8'h97; + 8'h89 : y = 8'hF2; + 8'h8A : y = 8'hCF; + 8'h8B : y = 8'hCE; + 8'h8C : y = 8'hF0; + 8'h8D : y = 8'hB4; + 8'h8E : y = 8'hE6; + 8'h8F : y = 8'h73; + 8'h90 : y = 8'h96; + 8'h91 : y = 8'hAC; + 8'h92 : y = 8'h74; + 8'h93 : y = 8'h22; + 8'h94 : y = 8'hE7; + 8'h95 : y = 8'hAD; + 8'h96 : y = 8'h35; + 8'h97 : y = 8'h85; + 8'h98 : y = 8'hE2; + 8'h99 : y = 8'hF9; + 8'h9A : y = 8'h37; + 8'h9B : y = 8'hE8; + 8'h9C : y = 8'h1C; + 8'h9D : y = 8'h75; + 8'h9E : y = 8'hDF; + 8'h9F : y = 8'h6E; + 8'hA0 : y = 8'h47; + 8'hA1 : y = 8'hF1; + 8'hA2 : y = 8'h1A; + 8'hA3 : y = 8'h71; + 8'hA4 : y = 8'h1D; + 8'hA5 : y = 8'h29; + 8'hA6 : y = 8'hC5; + 8'hA7 : y = 8'h89; + 8'hA8 : y = 8'h6F; + 8'hA9 : y = 8'hB7; + 8'hAA : y = 8'h62; + 8'hAB : y = 8'h0E; + 8'hAC : y = 8'hAA; + 8'hAD : y = 8'h18; + 8'hAE : y = 8'hBE; + 8'hAF : y = 8'h1B; + 8'hB0 : y = 8'hFC; + 8'hB1 : y = 8'h56; + 8'hB2 : y = 8'h3E; + 8'hB3 : y = 8'h4B; + 8'hB4 : y = 8'hC6; + 8'hB5 : y = 8'hD2; + 8'hB6 : y = 8'h79; + 8'hB7 : y = 8'h20; + 8'hB8 : y = 8'h9A; + 8'hB9 : y = 8'hDB; + 8'hBA : y = 8'hC0; + 8'hBB : y = 8'hFE; + 8'hBC : y = 8'h78; + 8'hBD : y = 8'hCD; + 8'hBE : y = 8'h5A; + 8'hBF : y = 8'hF4; + 8'hC0 : y = 8'h1F; + 8'hC1 : y = 8'hDD; + 8'hC2 : y = 8'hA8; + 8'hC3 : y = 8'h33; + 8'hC4 : y = 8'h88; + 8'hC5 : y = 8'h07; + 8'hC6 : y = 8'hC7; + 8'hC7 : y = 8'h31; + 8'hC8 : y = 8'hB1; + 8'hC9 : y = 8'h12; + 8'hCA : y = 8'h10; + 8'hCB : y = 8'h59; + 8'hCC : y = 8'h27; + 8'hCD : y = 8'h80; + 8'hCE : y = 8'hEC; + 8'hCF : y = 8'h5F; + 8'hD0 : y = 8'h60; + 8'hD1 : y = 8'h51; + 8'hD2 : y = 8'h7F; + 8'hD3 : y = 8'hA9; + 8'hD4 : y = 8'h19; + 8'hD5 : y = 8'hB5; + 8'hD6 : y = 8'h4A; + 8'hD7 : y = 8'h0D; + 8'hD8 : y = 8'h2D; + 8'hD9 : y = 8'hE5; + 8'hDA : y = 8'h7A; + 8'hDB : y = 8'h9F; + 8'hDC : y = 8'h93; + 8'hDD : y = 8'hC9; + 8'hDE : y = 8'h9C; + 8'hDF : y = 8'hEF; + 8'hE0 : y = 8'hA0; + 8'hE1 : y = 8'hE0; + 8'hE2 : y = 8'h3B; + 8'hE3 : y = 8'h4D; + 8'hE4 : y = 8'hAE; + 8'hE5 : y = 8'h2A; + 8'hE6 : y = 8'hF5; + 8'hE7 : y = 8'hB0; + 8'hE8 : y = 8'hC8; + 8'hE9 : y = 8'hEB; + 8'hEA : y = 8'hBB; + 8'hEB : y = 8'h3C; + 8'hEC : y = 8'h83; + 8'hED : y = 8'h53; + 8'hEE : y = 8'h99; + 8'hEF : y = 8'h61; + 8'hF0 : y = 8'h17; + 8'hF1 : y = 8'h2B; + 8'hF2 : y = 8'h04; + 8'hF3 : y = 8'h7E; + 8'hF4 : y = 8'hBA; + 8'hF5 : y = 8'h77; + 8'hF6 : y = 8'hD6; + 8'hF7 : y = 8'h26; + 8'hF8 : y = 8'hE1; + 8'hF9 : y = 8'h69; + 8'hFA : y = 8'h14; + 8'hFB : y = 8'h63; + 8'hFC : y = 8'h55; + 8'hFD : y = 8'h21; + 8'hFE : y = 8'h0C; + 8'hFF : y = 8'h7D; + endcase +endmodule diff --git a/src/ieu/aes/aesinvsboxword.sv b/src/ieu/aes/aesinvsboxword.sv new file mode 100644 index 000000000..62b969852 --- /dev/null +++ b/src/ieu/aes/aesinvsboxword.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// aesinvsboxword.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: 4 sets of Rinjdael Inverse S-BOX for whole word look up +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesinvsboxword( + input logic [31:0] a, + output logic [31:0] y +); + + // inverse substitutions boxes for each byte of the word + aesinvsbox sboxb0(a[7:0], y[7:0]); + aesinvsbox sboxb1(a[15:8], y[15:8]); + aesinvsbox sboxb2(a[23:16], y[23:16]); + aesinvsbox sboxb3(a[31:24], y[31:24]); +endmodule diff --git a/src/ieu/aes/aesinvshiftrow.sv b/src/ieu/aes/aesinvshiftrow.sv new file mode 100644 index 000000000..54b11c82a --- /dev/null +++ b/src/ieu/aes/aesinvshiftrow.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// aesinvshiftrow.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: AES Shiftrow +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesinvshiftrow( + input logic [127:0] a, + output logic [127:0] y +); + + assign y = {a[31:24], a[55:48], a[79:72], a[103:96], + a[127:120], a[23:16], a[47:40], a[71:64], + a[95:88], a[119:112], a[15:8], a[39:32], + a[63:56], a[87:80], a[111:104], a[7:0]}; +endmodule diff --git a/src/ieu/aes/aesmixcolumns.sv b/src/ieu/aes/aesmixcolumns.sv new file mode 100644 index 000000000..517533f63 --- /dev/null +++ b/src/ieu/aes/aesmixcolumns.sv @@ -0,0 +1,50 @@ +/////////////////////////////////////////// +// aesmixcolumns.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operation to an individual 32-bit word +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + +module aesmixcolumns( + input logic [31:0] a, + output logic [31:0] y +); + + logic [7:0] a0, a1, a2, a3, y0, y1, y2, y3, t0, t1, t2, t3, temp; + + assign {a0, a1, a2, a3} = a; + assign temp = a0 ^ a1 ^ a2 ^ a3; + + galoismultforward gm0 (a0^a1, t0); + galoismultforward gm1 (a1^a2, t1); + galoismultforward gm2 (a2^a3, t2); + galoismultforward gm3 (a3^a0, t3); + + assign y0 = a0 ^ temp ^ t3; + assign y1 = a1 ^ temp ^ t0; + assign y2 = a2 ^ temp ^ t1; + assign y3 = a3 ^ temp ^ t2; + + assign y = {y0, y1, y2, y3}; +endmodule diff --git a/src/ieu/aes/aessbox.sv b/src/ieu/aes/aessbox.sv new file mode 100644 index 000000000..84eb61c4d --- /dev/null +++ b/src/ieu/aes/aessbox.sv @@ -0,0 +1,293 @@ +/////////////////////////////////////////// +// aessbox.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Rinjdael forward S-BOX in the form of a LUT +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aessbox( + input logic [7:0] a, + output logic [7:0] y +); + + // case statement to lookup the value in the rijndael table + always_comb + case(a) + 8'h00 : y = 8'h63; + 8'h01 : y = 8'h7C; + 8'h02 : y = 8'h77; + 8'h03 : y = 8'h7B; + 8'h04 : y = 8'hF2; + 8'h05 : y = 8'h6B; + 8'h06 : y = 8'h6F; + 8'h07 : y = 8'hC5; + 8'h08 : y = 8'h30; + 8'h09 : y = 8'h01; + 8'h0A : y = 8'h67; + 8'h0B : y = 8'h2B; + 8'h0C : y = 8'hFE; + 8'h0D : y = 8'hD7; + 8'h0E : y = 8'hAB; + 8'h0F : y = 8'h76; + 8'h10 : y = 8'hCA; + 8'h11 : y = 8'h82; + 8'h12 : y = 8'hC9; + 8'h13 : y = 8'h7D; + 8'h14 : y = 8'hFA; + 8'h15 : y = 8'h59; + 8'h16 : y = 8'h47; + 8'h17 : y = 8'hF0; + 8'h18 : y = 8'hAD; + 8'h19 : y = 8'hD4; + 8'h1A : y = 8'hA2; + 8'h1B : y = 8'hAF; + 8'h1C : y = 8'h9C; + 8'h1D : y = 8'hA4; + 8'h1E : y = 8'h72; + 8'h1F : y = 8'hC0; + 8'h20 : y = 8'hB7; + 8'h21 : y = 8'hFD; + 8'h22 : y = 8'h93; + 8'h23 : y = 8'h26; + 8'h24 : y = 8'h36; + 8'h25 : y = 8'h3F; + 8'h26 : y = 8'hF7; + 8'h27 : y = 8'hCC; + 8'h28 : y = 8'h34; + 8'h29 : y = 8'hA5; + 8'h2A : y = 8'hE5; + 8'h2B : y = 8'hF1; + 8'h2C : y = 8'h71; + 8'h2D : y = 8'hD8; + 8'h2E : y = 8'h31; + 8'h2F : y = 8'h15; + 8'h30 : y = 8'h04; + 8'h31 : y = 8'hC7; + 8'h32 : y = 8'h23; + 8'h33 : y = 8'hC3; + 8'h34 : y = 8'h18; + 8'h35 : y = 8'h96; + 8'h36 : y = 8'h05; + 8'h37 : y = 8'h9A; + 8'h38 : y = 8'h07; + 8'h39 : y = 8'h12; + 8'h3A : y = 8'h80; + 8'h3B : y = 8'hE2; + 8'h3C : y = 8'hEB; + 8'h3D : y = 8'h27; + 8'h3E : y = 8'hB2; + 8'h3F : y = 8'h75; + 8'h40 : y = 8'h09; + 8'h41 : y = 8'h83; + 8'h42 : y = 8'h2C; + 8'h43 : y = 8'h1A; + 8'h44 : y = 8'h1B; + 8'h45 : y = 8'h6E; + 8'h46 : y = 8'h5A; + 8'h47 : y = 8'hA0; + 8'h48 : y = 8'h52; + 8'h49 : y = 8'h3B; + 8'h4A : y = 8'hD6; + 8'h4B : y = 8'hB3; + 8'h4C : y = 8'h29; + 8'h4D : y = 8'hE3; + 8'h4E : y = 8'h2F; + 8'h4F : y = 8'h84; + 8'h50 : y = 8'h53; + 8'h51 : y = 8'hD1; + 8'h52 : y = 8'h00; + 8'h53 : y = 8'hED; + 8'h54 : y = 8'h20; + 8'h55 : y = 8'hFC; + 8'h56 : y = 8'hB1; + 8'h57 : y = 8'h5B; + 8'h58 : y = 8'h6A; + 8'h59 : y = 8'hCB; + 8'h5A : y = 8'hBE; + 8'h5B : y = 8'h39; + 8'h5C : y = 8'h4A; + 8'h5D : y = 8'h4C; + 8'h5E : y = 8'h58; + 8'h5F : y = 8'hCF; + 8'h60 : y = 8'hD0; + 8'h61 : y = 8'hEF; + 8'h62 : y = 8'hAA; + 8'h63 : y = 8'hFB; + 8'h64 : y = 8'h43; + 8'h65 : y = 8'h4D; + 8'h66 : y = 8'h33; + 8'h67 : y = 8'h85; + 8'h68 : y = 8'h45; + 8'h69 : y = 8'hF9; + 8'h6A : y = 8'h02; + 8'h6B : y = 8'h7F; + 8'h6C : y = 8'h50; + 8'h6D : y = 8'h3C; + 8'h6E : y = 8'h9F; + 8'h6F : y = 8'hA8; + 8'h70 : y = 8'h51; + 8'h71 : y = 8'hA3; + 8'h72 : y = 8'h40; + 8'h73 : y = 8'h8F; + 8'h74 : y = 8'h92; + 8'h75 : y = 8'h9D; + 8'h76 : y = 8'h38; + 8'h77 : y = 8'hF5; + 8'h78 : y = 8'hBC; + 8'h79 : y = 8'hB6; + 8'h7A : y = 8'hDA; + 8'h7B : y = 8'h21; + 8'h7C : y = 8'h10; + 8'h7D : y = 8'hFF; + 8'h7E : y = 8'hF3; + 8'h7F : y = 8'hD2; + 8'h80 : y = 8'hCD; + 8'h81 : y = 8'h0C; + 8'h82 : y = 8'h13; + 8'h83 : y = 8'hEC; + 8'h84 : y = 8'h5F; + 8'h85 : y = 8'h97; + 8'h86 : y = 8'h44; + 8'h87 : y = 8'h17; + 8'h88 : y = 8'hC4; + 8'h89 : y = 8'hA7; + 8'h8A : y = 8'h7E; + 8'h8B : y = 8'h3D; + 8'h8C : y = 8'h64; + 8'h8D : y = 8'h5D; + 8'h8E : y = 8'h19; + 8'h8F : y = 8'h73; + 8'h90 : y = 8'h60; + 8'h91 : y = 8'h81; + 8'h92 : y = 8'h4F; + 8'h93 : y = 8'hDC; + 8'h94 : y = 8'h22; + 8'h95 : y = 8'h2A; + 8'h96 : y = 8'h90; + 8'h97 : y = 8'h88; + 8'h98 : y = 8'h46; + 8'h99 : y = 8'hEE; + 8'h9A : y = 8'hB8; + 8'h9B : y = 8'h14; + 8'h9C : y = 8'hDE; + 8'h9D : y = 8'h5E; + 8'h9E : y = 8'h0B; + 8'h9F : y = 8'hDB; + 8'hA0 : y = 8'hE0; + 8'hA1 : y = 8'h32; + 8'hA2 : y = 8'h3A; + 8'hA3 : y = 8'h0A; + 8'hA4 : y = 8'h49; + 8'hA5 : y = 8'h06; + 8'hA6 : y = 8'h24; + 8'hA7 : y = 8'h5C; + 8'hA8 : y = 8'hC2; + 8'hA9 : y = 8'hD3; + 8'hAA : y = 8'hAC; + 8'hAB : y = 8'h62; + 8'hAC : y = 8'h91; + 8'hAD : y = 8'h95; + 8'hAE : y = 8'hE4; + 8'hAF : y = 8'h79; + 8'hB0 : y = 8'hE7; + 8'hB1 : y = 8'hC8; + 8'hB2 : y = 8'h37; + 8'hB3 : y = 8'h6D; + 8'hB4 : y = 8'h8D; + 8'hB5 : y = 8'hD5; + 8'hB6 : y = 8'h4E; + 8'hB7 : y = 8'hA9; + 8'hB8 : y = 8'h6C; + 8'hB9 : y = 8'h56; + 8'hBA : y = 8'hF4; + 8'hBB : y = 8'hEA; + 8'hBC : y = 8'h65; + 8'hBD : y = 8'h7A; + 8'hBE : y = 8'hAE; + 8'hBF : y = 8'h08; + 8'hC0 : y = 8'hBA; + 8'hC1 : y = 8'h78; + 8'hC2 : y = 8'h25; + 8'hC3 : y = 8'h2E; + 8'hC4 : y = 8'h1C; + 8'hC5 : y = 8'hA6; + 8'hC6 : y = 8'hB4; + 8'hC7 : y = 8'hC6; + 8'hC8 : y = 8'hE8; + 8'hC9 : y = 8'hDD; + 8'hCA : y = 8'h74; + 8'hCB : y = 8'h1F; + 8'hCC : y = 8'h4B; + 8'hCD : y = 8'hBD; + 8'hCE : y = 8'h8B; + 8'hCF : y = 8'h8A; + 8'hD0 : y = 8'h70; + 8'hD1 : y = 8'h3E; + 8'hD2 : y = 8'hB5; + 8'hD3 : y = 8'h66; + 8'hD4 : y = 8'h48; + 8'hD5 : y = 8'h03; + 8'hD6 : y = 8'hF6; + 8'hD7 : y = 8'h0E; + 8'hD8 : y = 8'h61; + 8'hD9 : y = 8'h35; + 8'hDA : y = 8'h57; + 8'hDB : y = 8'hB9; + 8'hDC : y = 8'h86; + 8'hDD : y = 8'hC1; + 8'hDE : y = 8'h1D; + 8'hDF : y = 8'h9E; + 8'hE0 : y = 8'hE1; + 8'hE1 : y = 8'hF8; + 8'hE2 : y = 8'h98; + 8'hE3 : y = 8'h11; + 8'hE4 : y = 8'h69; + 8'hE5 : y = 8'hD9; + 8'hE6 : y = 8'h8E; + 8'hE7 : y = 8'h94; + 8'hE8 : y = 8'h9B; + 8'hE9 : y = 8'h1E; + 8'hEA : y = 8'h87; + 8'hEB : y = 8'hE9; + 8'hEC : y = 8'hCE; + 8'hED : y = 8'h55; + 8'hEE : y = 8'h28; + 8'hEF : y = 8'hDF; + 8'hF0 : y = 8'h8C; + 8'hF1 : y = 8'hA1; + 8'hF2 : y = 8'h89; + 8'hF3 : y = 8'h0D; + 8'hF4 : y = 8'hBF; + 8'hF5 : y = 8'hE6; + 8'hF6 : y = 8'h42; + 8'hF7 : y = 8'h68; + 8'hF8 : y = 8'h41; + 8'hF9 : y = 8'h99; + 8'hFA : y = 8'h2D; + 8'hFB : y = 8'h0F; + 8'hFC : y = 8'hB0; + 8'hFD : y = 8'h54; + 8'hFE : y = 8'hBB; + 8'hFF : y = 8'h16; + endcase +endmodule diff --git a/src/ieu/aes/aessboxword.sv b/src/ieu/aes/aessboxword.sv new file mode 100644 index 000000000..55bf1bb99 --- /dev/null +++ b/src/ieu/aes/aessboxword.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// aessboxword.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aessboxword( + input logic [31:0] a, + output logic [31:0] y +); + + // substitutions boxes for each byte of the word + aessbox sboxb0(a[7:0], y[7:0]); + aessbox sboxb1(a[15:8], y[15:8]); + aessbox sboxb2(a[23:16], y[23:16]); + aessbox sboxb3(a[31:24], y[31:24]); +endmodule diff --git a/src/ieu/aes/aesshiftrow.sv b/src/ieu/aes/aesshiftrow.sv new file mode 100644 index 000000000..fa355458b --- /dev/null +++ b/src/ieu/aes/aesshiftrow.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// aesshiftrow.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: aesshiftrow for taking in first Data line +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesshiftrow( + input logic [127:0] a, + output logic [127:0] y +); + + assign y = {a[95:88], a[55:48], a[15:8], a[103:96], + a[63:56], a[23:16], a[111:104], a[71:64], + a[31:24], a[119:112], a[79:72], a[39:32], + a[127:120], a[87:80], a[47:40], a[7:0]}; +endmodule diff --git a/src/ieu/aes/galoismultforward.sv b/src/ieu/aes/galoismultforward.sv new file mode 100644 index 000000000..081605682 --- /dev/null +++ b/src/ieu/aes/galoismultforward.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// galoismultforward.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module galoismultforward( + input logic [7:0] a, + output logic [7:0] y +); + + logic [7:0] leftshift; + + assign leftshift = {a[6:0], 1'b0}; + assign y = a[7] ? (leftshift ^ 8'b00011011) : leftshift; +endmodule diff --git a/src/ieu/aes/galoismultinverse.sv b/src/ieu/aes/galoismultinverse.sv new file mode 100644 index 000000000..89c697584 --- /dev/null +++ b/src/ieu/aes/galoismultinverse.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// galoismultinverse.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operations for mix columns operation +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module galoismultinverse( + input logic [10:0] a, + output logic [7:0] y +); + + logic [7:0] temp0, temp1; + + assign temp0 = a[8] ? (a[7:0] ^ 8'b00011011) : a[7:0]; + assign temp1 = a[9] ? (temp0 ^ 8'b00110110) : temp0; + assign y = a[10] ? (temp1 ^ 8'b01101100) : temp1; +endmodule diff --git a/src/ieu/aes/rconlut128.sv b/src/ieu/aes/rconlut128.sv new file mode 100644 index 000000000..3360b9b51 --- /dev/null +++ b/src/ieu/aes/rconlut128.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// rconlut128.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: rcon lookup for aes64ks1i instruction +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rconlut128( + input logic [3:0] rd, + output logic [7:0] rconOut +); + + always_comb + case(rd) + 4'h0 : rconOut = 8'h01; + 4'h1 : rconOut = 8'h02; + 4'h2 : rconOut = 8'h04; + 4'h3 : rconOut = 8'h08; + 4'h4 : rconOut = 8'h10; + 4'h5 : rconOut = 8'h20; + 4'h6 : rconOut = 8'h40; + 4'h7 : rconOut = 8'h80; + 4'h8 : rconOut = 8'h1b; + 4'h9 : rconOut = 8'h36; + 4'hA : rconOut = 8'h00; + default : rconOut = 8'h00; + endcase +endmodule diff --git a/src/ieu/aes/rotate.sv b/src/ieu/aes/rotate.sv new file mode 100644 index 000000000..7f44f95f4 --- /dev/null +++ b/src/ieu/aes/rotate.sv @@ -0,0 +1,35 @@ +/////////////////////////////////////////// +// rotate.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu +// Created: 20 February 2024 +// +// Purpose: rotate a by shamt +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rotate #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] shamt, + output logic [WIDTH-1:0] y +); + + assign y = (a << shamt) | (a >> (WIDTH-shamt)); +endmodule diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 51cf00b97..ae573ca70 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,9 +33,11 @@ module alu import cvw::*; #(parameter cvw_t P) ( input logic W64, // W64-type instruction input logic SubArith, // Subtraction or arithmetic shift input logic [2:0] ALUSelect, // ALU mux select signal - input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // For BMU decoding + input logic [6:0] Funct7, // For ZKNE and ZKND computation + input logic [4:0] Rs2E, // For ZKNE and ZKND computation input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic BMUActive, // Bit manipulation instruction being executed input logic [1:0] CZero, // {czero.nez, czero.eqz} instructions active @@ -89,10 +91,10 @@ module alu import cvw::*; #(parameter cvw_t P) ( else assign PreALUResult = FullResult; // Bit manipulation muxing - if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu + if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu bitmanipalu #(P) balu( .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive, - .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, + .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin assign ALUResult = PreALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 3f7d0ae7a..244a5b446 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -1,18 +1,18 @@ /////////////////////////////////////////// // bitmanipalu.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 23 March 2023 -// Modified: 23 March 2023 +// Modified: 9 March 2024 // -// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension +// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension // // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -29,29 +29,37 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module bitmanipalu import cvw::*; #(parameter cvw_t P) ( - input logic [P.XLEN-1:0] A, B, // Operands - input logic W64, // W64-type instruction - input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform - input logic LT, // less than flag - input logic LTU, // less than unsigned flag - input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - input logic BMUActive, // Bit manipulation instruction being executed - input logic [P.XLEN-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals + input logic [P.XLEN-1:0] A, B, // Operands + input logic W64, // W64-type instruction + input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform + input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations + input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND + input logic LT, // less than flag + input logic LTU, // less than unsigned flag + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + input logic BMUActive, // Bit manipulation instruction being executed + input logic [P.XLEN-1:0] PreALUResult, // PreALUResult signals + input logic [P.XLEN-1:0] FullResult, // FullResult signals output logic [P.XLEN-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [P.XLEN-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions output logic [P.XLEN-1:0] ALUResult); // Result - logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result - logic [P.XLEN-1:0] MaskB; // BitMask of B - logic [P.XLEN-1:0] RevA; // Bit-reversed A - logic Rotate; // Indicates if it is Rotate instruction - logic Mask; // Indicates if it is ZBS instruction - logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction - logic [1:0] PreShiftAmt; // Amount to Pre-Shift A - logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal - logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity + logic [P.XLEN-1:0] ZBBResult; // ZBB Result + logic [P.XLEN-1:0] ZBCResult; // ZBC Result + logic [P.XLEN-1:0] ZBKBResult; // ZBKB Result + logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result + logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result + logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result + logic [P.XLEN-1:0] ZKNDEResult; // ZKNE or ZKND Result + logic [P.XLEN-1:0] MaskB; // BitMask of B + logic [P.XLEN-1:0] RevA; // Bit-reversed A + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A + logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal + logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity // gate data inputs to BMU to only operate when BMU is active assign ABMU = A & {P.XLEN{BMUActive}}; @@ -83,23 +91,50 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( bitreverse #(P.XLEN) brA(.A(ABMU), .RevA); end - // ZBC Unit - if (P.ZBC_SUPPORTED) begin: zbc + // ZBC and ZBKCUnit + if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); end else assign ZBCResult = 0; // ZBB Unit if (P.ZBB_SUPPORTED) begin: zbb - zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); + zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult); end else assign ZBBResult = 0; + // ZBKB Unit + if (P.ZBKB_SUPPORTED) begin: zbkb + zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult); + end else assign ZBKBResult = 0; + + // ZBKX Unit + if (P.ZBKX_SUPPORTED) begin: zbkx + zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult); + end else assign ZBKXResult = 0; + + // ZKND and ZKNE AES decryption and encryption + if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) + if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); + else zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); + + // ZKNH Unit + if (P.ZKNH_SUPPORTED) begin: zknh + if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + else zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult)); + end else assign ZKNHResult = 0; + // Result Select Mux always_comb case (BSelect) - // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: ALUResult = PreALUResult; - 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: ALUResult = ZBBResult; - 2'b11: ALUResult = ZBCResult; + // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX + // 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH... + 4'b0000: ALUResult = PreALUResult; + 4'b0001: ALUResult = FullResult; // NOTE: don't use ALUResult since ZBA/ZBS doesnt sext the MSB of RH word + 4'b0010: ALUResult = ZBBResult; + 4'b0011: ALUResult = ZBCResult; + 4'b0100: ALUResult = ZBKBResult; + 4'b0110: ALUResult = ZBKXResult; + 4'b0111: ALUResult = ZKNDEResult; + 4'b1000: ALUResult = ZKNHResult; + default: ALUResult = PreALUResult; endcase endmodule diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 3876c31e4..083033d53 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // bitreverse.sv // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 5b758f123..887ac0065 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // bmuctrl.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 16 February 2023 -// Modified: 6 March 2023 +// Modified: 6 March 2023, 9 March 2024 // // Purpose: Top level bit manipulation instruction decoder // @@ -12,7 +12,7 @@ // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -34,8 +34,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage input logic ALUOpD, // Regular ALU Operation - output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage - output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [3:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage @@ -44,8 +44,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectD, // ALU select - output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - output logic [2:0] ZBBSelectE, // ZBB mux select signal + output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [3:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE // Bit manipulation instruction being executed @@ -62,7 +62,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage - `define BMUCTRLW 17 + `define BMUCTRLW 20 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -78,92 +78,204 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction; if (P.ZBA_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh3add endcase if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw endcase end + if (P.ZBB_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0; // count instruction // // coverage off: This case can't occur in RV64 // 17'b0110011_0000100_100: if (P.XLEN == 32) // BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) // // coverage on - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // minu endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // zexth (rv32) endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_1_0_0_0_0_0; // zexth (rv64) 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction endcase end + if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction endcase + if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul + 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh + endcase + end + if (P.ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0; // bset endcase if (P.XLEN==32) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti endcase else if (P.XLEN==64) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti (rv64) endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw endcase + + if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip + casez({OpD,Funct7D, Funct3D}) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // pack + 17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // packh + 17'b0010011_0110100_101: if (Rs2D == 5'b00111) + BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0; // brev8 + endcase + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0000100_001: if (Rs2D == 5'b01111) + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //zip + 17'b0010011_0000100_101: if (Rs2D == 5'b01111) + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //unzip + endcase + else if (P.XLEN==64) + casez({OpD,Funct7D, Funct3D}) + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw + endcase + end + if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // ror + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // rev8 + endcase + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv32) + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_1_0_1_0_0_0; // roriw + endcase + end + + if (P.ZBKX_SUPPORTED) begin //ZBKX + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8 + 17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_1_0_0_0_0_0; // xperm4 + endcase + end + + if (P.ZKND_SUPPORTED) begin //ZKND + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes32dsi - final round decrypt + 17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes32dsmi - mid round decrypt + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes64ds - decrypt final round + 17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes64dsm - decrypt mid round + 17'b0010011_0011000_001: if (Rs2D == 5'b00000) + BMUControlsD = `BMUCTRLW'b000_0111_1000_1_1_0_1_0_0_0_0_0; // aes64im - decrypt keyschdule mixcolumns + endcase + end + + if (P.ZKNE_SUPPORTED) begin //ZKNE + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_1_0_0_0_0_0; // aes32esi - final round encrypt + 17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes32esmi - mid round encrypt + endcase + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_1_0_0_0_0_0; // aes64es - encrypt final round + 17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes64esm - encrypt mid round + endcase + end + + if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1) + BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 + 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 + endcase + end + + if (P.ZKNH_SUPPORTED) begin // ZKNH + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0001000_001: + if (Rs2D == 5'b00010) BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // sha256sig0 + else if (Rs2D == 5'b00011) BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // sha256sig1 + else if (Rs2D == 5'b00000) BMUControlsD = `BMUCTRLW'b000_1000_0010_1_0_0_1_0_0_0_0_0; // sha256sum0 + else if (Rs2D == 5'b00001) BMUControlsD = `BMUCTRLW'b000_1000_0011_1_0_0_1_0_0_0_0_0; // sha256sum1 + endcase + + if (P.XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0h + 17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig0l + 17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig1h + 17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1l + 17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0r + 17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0; // sha512sum1r + endcase + + else if (P.XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0001000_001: + if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0 + else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig1 + else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sum0 + else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sum1 + endcase + end end // Unpack Control Signals @@ -176,5 +288,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); // BMU Execute stage pipieline control register - flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); + flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE}); endmodule diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 191919ecc..980c6d586 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // byteop.sv // -// Written: Kevin Kim +// Written: Kevin Kim , kelvin.tran@okstate.edu // Created: 1 February 2023 -// Modified: 6 March 2023 +// Modified: 29 February 2024 // // Purpose: RISCV bitmanip byte-wise operation unit // @@ -12,7 +12,7 @@ // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw // -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University // // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // @@ -30,16 +30,24 @@ module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands - input logic ByteSelect, // LSB of Immediate + input logic [WIDTH-1:0] RevA, // Reversed A + input logic [1:0] ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result - logic [WIDTH-1:0] OrcBResult, Rev8Result; + logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result; genvar i; for (i=0;i diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 52ed8ef34..e96ed7acd 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -1,4 +1,3 @@ - /////////////////////////////////////////// // zbb.sv // @@ -46,7 +45,7 @@ module zbb #(parameter WIDTH=32) ( mux2 #(1) ltmux(LT, LTU, BUnsigned , lt); cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); - byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); + byteop #(WIDTH) bu(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult); ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); // ZBBSelect[2] differentiates between min(u) vs max(u) instruction diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d9c076dbd..9bb40af12 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -43,7 +43,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic StructuralStallD, // Structural stalls detected by controller output logic LoadStallD, // Structural stalls for load, sent to performance counters output logic StoreStallD, // load after store hazard - output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage + output logic [4:0] Rs1D, Rs2D, Rs2E, // Register sources to read in Decode or Execute stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] FlagsE, // Comparison flags ({eq, lt}) @@ -55,6 +55,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field + output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -63,8 +64,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic BranchE, // Branch instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction - output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage + output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [3:0] ZBBSelectE, // ZBB mux select signal in Execute stage output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active @@ -95,7 +96,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [4:0] RdW // Register destinations in Execute, Memory, or Writeback stage ); - logic [4:0] Rs1E, Rs2E; // pipelined register sources + logic [4:0] Rs1E; // pipelined register sources logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage @@ -138,8 +139,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction - logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage - logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [3:0] ZBBSelectD; // ZBB Mux Select Signal logic [1:0] CZeroD; logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions @@ -351,9 +352,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand // tie off unused bit manipulation signals - assign BSelectE = 2'b00; - assign BSelectD = 2'b00; - assign ZBBSelectE = 3'b000; + assign BSelectE = 4'b0000; + assign BSelectD = 4'b0000; + assign ZBBSelectE = 4'b0000; assign BALUControlE = 3'b0; assign BMUActiveE = 1'b0; end @@ -417,9 +418,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(37) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); + flopenrc #(44) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index eb6fd1d81..49da4e0cb 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -33,11 +33,12 @@ module datapath import cvw::*; #(parameter cvw_t P) ( // Decode stage signals input logic [2:0] ImmSrcD, // Selects type of immediate extension input logic [31:0] InstrD, // Instruction in Decode stage - input logic [4:0] Rs1D, Rs2D, // Source registers + input logic [4:0] Rs1D, Rs2D, Rs2E, // Source registers // Execute stage signals input logic [P.XLEN-1:0] PCE, // PC in Execute stage input logic [P.XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage + input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic W64E, // W64-type instruction @@ -47,8 +48,8 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelectE, // ZBB mux select signal + input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] ZBBSelectE, // ZBB mux select signal input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage input logic BMUActiveE, // Bit manipulation instruction being executed input logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active @@ -109,7 +110,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); + alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 438ca7534..38d50e3c3 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -90,13 +90,16 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [3:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage logic SubArithE; // Subtraction or arithmetic shift + logic [6:0] Funct7E; + // Forwarding signals - logic [4:0] Rs1D, Rs2D; // Source registers + logic [4:0] Rs1D, Rs2D; + logic [4:0] Rs2E; // Source registers logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction @@ -108,10 +111,10 @@ module ieu import cvw::*; #(parameter cvw_t P) ( controller #(P) c( .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, - .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, + .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, + .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, @@ -120,8 +123,8 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .RdW, .RdE, .RdM); datapath #(P) dp( - .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, - .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, + .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, + .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv new file mode 100644 index 000000000..fcf2f9eef --- /dev/null +++ b/src/ieu/kmu/packer.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// packer.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 5 October 2023 +// +// Purpose: RISCV kbitmanip pack operation unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module packer #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] PackSelect, + output logic [WIDTH-1:0] PackResult +); + + logic [WIDTH/2-1:0] lowhalf, highhalf; + logic [7:0] lowhalfh, highhalfh; + logic [15:0] lowhalfw, highhalfw; + logic [WIDTH-1:0] Pack, PackH, PackW; + + assign lowhalf = A[WIDTH/2-1:0]; + assign highhalf = B[WIDTH/2-1:0]; + assign lowhalfh = A[7:0]; + assign highhalfh = B[7:0]; + assign lowhalfw = A[15:0]; + assign highhalfw = B[15:0]; + + assign Pack = {highhalf, lowhalf}; + assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh}; + assign PackW = (WIDTH == 64) ? {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw} : Pack; // not implemented for RV32; treat as Pack to simplify logic in result mux + + always_comb + if (PackSelect[1:0] == 2'b11) PackResult = PackH; + else if (PackSelect[2] == 1'b0) PackResult = Pack; + else PackResult = PackW; +endmodule diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv new file mode 100644 index 000000000..90b774042 --- /dev/null +++ b/src/ieu/kmu/zbkb.sv @@ -0,0 +1,46 @@ +/////////////////////////////////////////// +// zbkb.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 4 October 2023 +// +// Purpose: RISC-V ZBKB top level unit: bit manipulation instructions for crypto +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module zbkb #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, RevA, + input logic W64, + input logic [2:0] Funct3, + input logic [2:0] ZBKBSelect, + output logic [WIDTH-1:0] ZBKBResult +); + + logic [WIDTH-1:0] ByteResult; // rev8, brev8 + logic [WIDTH-1:0] PackResult; // pack, packh, packw (RB64 only) + logic [WIDTH-1:0] ZipResult; // zip, unzip + + byteop #(WIDTH) rev(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult); + packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult); + zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult); + + // ZBKB Result Select Mux + mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult); +endmodule diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv new file mode 100644 index 000000000..dbbaf3d2d --- /dev/null +++ b/src/ieu/kmu/zbkx.sv @@ -0,0 +1,50 @@ +/////////////////////////////////////////// +// zbkx.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 1 February 2024 +// +// Purpose: RISC-V ZBKX top level unit: crossbar permutation instructions for crypto +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module zbkx #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ZBKXSelect, + output logic [WIDTH-1:0] ZBKXResult +); + + logic [WIDTH-1:0] xperm4, xperm4lookup; + logic [WIDTH-1:0] xperm8, xperm8lookup; + int i; + + always_comb begin + for(i=0; i> {B[i+:4], 2'b0}; + xperm4[i+:4] = xperm4lookup[3:0]; + end + for(i=0; i> {B[i+:8], 3'b0}; + xperm8[i+:8] = xperm8lookup[7:0]; + end + end + + assign ZBKXResult = ZBKXSelect[0] ? xperm4 : xperm8; +endmodule diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv new file mode 100644 index 000000000..2cc0a3a18 --- /dev/null +++ b/src/ieu/kmu/zipper.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// zipper.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 9 October 2023 +// +// Purpose: RISCV kbitmanip zip operation unit +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module zipper #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] A, + input logic ZipSelect, + output logic [WIDTH-1:0] ZipResult +); + + logic [WIDTH-1:0] zip, unzip; + genvar i; + + for (i=0; i> 1; + assign x[0][1] = A >> 7; + assign x[0][2] = A >> 8; + assign x[0][3] = B << 31; + assign x[0][4] = B << 24; + assign x[0][5] = 0; + + // sha512sig0l + assign x[1][0] = A >> 1; + assign x[1][1] = A >> 7; + assign x[1][2] = A >> 8; + assign x[1][3] = B << 31; + assign x[1][4] = B << 25; + assign x[1][5] = B << 24; + + // sha512sig1h + assign x[2][0] = A << 3; + assign x[2][1] = A >> 6; + assign x[2][2] = A >> 19; + assign x[2][3] = B >> 29; + assign x[2][4] = B << 13; + assign x[2][5] = 0; + + // sha512sig1l + assign x[3][0] = A << 3; + assign x[3][1] = A >> 6; + assign x[3][2] = A >> 19; + assign x[3][3] = B >> 29; + assign x[3][4] = B << 26; + assign x[3][5] = B << 13; + + // sha512sum0r + assign x[4][0] = A << 25; + assign x[4][1] = A << 30; + assign x[4][2] = A >> 28; + assign x[4][3] = B >> 7; + assign x[4][4] = B >> 2; + assign x[4][5] = B << 4; + + // sha512sum1r + assign x[5][0] = A << 23; + assign x[5][1] = A >> 14; + assign x[5][2] = A >> 18; + assign x[5][3] = B >> 9; + assign x[5][4] = B << 18; + assign x[5][5] = B << 14; + + // 32-bit muxes to select inputs to xor6 for sha512 + assign y[0] = x[ZKNHSelect[2:0]][0]; + assign y[1] = x[ZKNHSelect[2:0]][1]; + assign y[2] = x[ZKNHSelect[2:0]][2]; + assign y[3] = x[ZKNHSelect[2:0]][3]; + assign y[4] = x[ZKNHSelect[2:0]][4]; + assign y[5] = x[ZKNHSelect[2:0]][5]; + + // sha512 32-bit xor6 + assign result = y[0] ^ y[1] ^ y[2] ^ y[3] ^ y[4] ^ y[5]; +endmodule diff --git a/src/ieu/sha/sha512_64.sv b/src/ieu/sha/sha512_64.sv new file mode 100644 index 000000000..8707311e8 --- /dev/null +++ b/src/ieu/sha/sha512_64.sv @@ -0,0 +1,66 @@ +/////////////////////////////////////////// +// sha512_64.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 13 February 2024 +// +// Purpose: RISC-V (RV64) ZKNH 512-bit SHA: select shifted inputs and XOR3 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module sha512_64 ( + input logic [63:0] A, + input logic [1:0] ZKNHSelect, + output logic [63:0] result +); + + logic [63:0] x[4][3]; + logic [63:0] y[3]; + + // sha512{sig0/sig1/sum0/sum1} select shifted operands for 64-bit xor3 + + // sha512sig0 + assign x[0][0] = {A[0], A[63:1]}; + assign x[0][1] = {A[7:0], A[63:8]}; + assign x[0][2] = A >> 7; + + // sha512sig1 + assign x[1][0] = {A[18:0], A[63:19]}; + assign x[1][1] = {A[60:0], A[63:61]}; + assign x[1][2] = A >> 6; + + // sha512sum0 + assign x[2][0] = {A[27:0], A[63:28]}; + assign x[2][1] = {A[33:0], A[63:34]}; + assign x[2][2] = {A[38:0], A[63:39]}; + + // sha512sum1 + assign x[3][0] = {A[13:0], A[63:14]}; + assign x[3][1] = {A[17:0], A[63:18]}; + assign x[3][2] = {A[40:0], A[63:41]}; + + // 64-bit muxes to select inputs to xor3 for sha512 + assign y[0] = x[ZKNHSelect[1:0]][0]; + assign y[1] = x[ZKNHSelect[1:0]][1]; + assign y[2] = x[ZKNHSelect[1:0]][2]; + + // sha512 64-bit xor3 + assign result = y[0] ^ y[1] ^ y[2]; +endmodule diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index ee6cd6900..b433b2ed8 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -58,6 +58,17 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b010010) name = "BCLRI"; else if (funct7[6:1] == 6'b011010) name = "BINVI"; else if (funct7[6:1] == 6'b001010) name = "BSETI"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP"; + else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM"; + else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0"; + else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1"; else if (funct7 == 7'b0110000) begin case (rs2) 5'b00000: name = "CLZ"; @@ -77,6 +88,8 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b011000) name = "RORI"; else if (funct7[6:1] == 6'b010010) name = "BEXTI"; else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B"; + else if (imm == 12'b011010000111) name = "BREV8"; + else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP"; else name = "ILLEGAL"; 10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I"; else if (rd == 0 & rs2 == 1) name = "PREFETCH.R"; @@ -130,6 +143,21 @@ module instrNameDecTB( 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; else if (funct7 == 7'b0000001) name = "MUL"; else if (funct7 == 7'b0100000) name = "SUB"; + else if (funct7[4:0] == 5'b10101) name = "AES32DSI"; + else if (funct7[4:0] == 5'b10111) name = "AES32DSMI"; + else if (funct7 == 7'b0011101) name = "AES64DS"; + else if (funct7 == 7'b0011111) name = "AES64DSM"; + else if (funct7[4:0] == 5'b10001) name = "AES32ESI"; + else if (funct7[4:0] == 5'b10011) name = "AES32ESMI"; + else if (funct7 == 7'b0011001) name = "AES64ES"; + else if (funct7 == 7'b0011011) name = "AES64ESM"; + else if (funct7 == 7'b0111111) name = "AES64KS2"; + else if (funct7 == 7'b0101110) name = "SHA512SIG0H"; + else if (funct7 == 7'b0101010) name = "SHA512SIG0L"; + else if (funct7 == 7'b0101111) name = "SHA512SIG1H"; + else if (funct7 == 7'b0101011) name = "SHA512SIG1L"; + else if (funct7 == 7'b0101000) name = "SHA512SUM0R"; + else if (funct7 == 7'b0101001) name = "SHA512SUM1R"; else name = "ILLEGAL"; 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; else if (funct7 == 7'b0000001) name = "MULH"; @@ -153,7 +181,9 @@ module instrNameDecTB( else if (funct7 == 7'b0010000) name = "SH2ADD"; else if (funct7 == 7'b0000101) name = "MIN"; else if (funct7 == 7'b0100000) name = "ORN"; - else if (funct7 == 7'b0000100) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H"; + else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK"; + else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW"; else name = "ILLEGAL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; else if (funct7 == 7'b0000001) name = "DIVU"; @@ -311,10 +341,14 @@ module instrNameDecTB( else if (funct7 == 7'b1011011 & funct3 == 3'b000) name = "FMVP.Q.X"; else if (funct7 == 7'b1100001 & funct3 == 3'b001 & rs2 == 5'b01000) name = "FCVTMOD.W.D"; else name = "ILLEGAL"; + 10'b0000111_001: name = "FLH"; 10'b0000111_010: name = "FLW"; - 10'b0100111_010: name = "FSW"; 10'b0000111_011: name = "FLD"; + 10'b0000111_100: name = "FLQ"; + 10'b0100111_001: name = "FSH"; + 10'b0100111_010: name = "FSW"; 10'b0100111_011: name = "FSD"; + 10'b0100111_100: name = "FSQ"; default: name = "ILLEGAL"; endcase endmodule diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index b439b3d75..3f50d3f7c 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA"); assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F"); assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); + assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); end endmodule diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index 85b39e766..2e7db3d6e 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -129,6 +129,12 @@ module testbench; "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; "arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -159,6 +165,12 @@ module testbench; "arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb; "arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1a72d4f0f..b0255262f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -148,6 +148,12 @@ module testbench; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; "buildroot": tests = buildroot; + "arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb; + "arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc; + "arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx; + "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; + "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; + "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; endcase end else begin // RV32 case (TEST) @@ -190,6 +196,12 @@ module testbench; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; "arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad; + "arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb; + "arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc; + "arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx; + "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; + "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; + "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index afde1f2e6..1e676b8cb 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -994,6 +994,78 @@ string imperas32f[] = '{ "rv32i_m/B/src/bseti-01.S" }; + string arch32zbkc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S" + }; + + string arch32zbkx[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/xperm8-01.S", + "rv32i_m/K/src/xperm4-01.S" + }; + + string arch32zknd[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32dsi-01.S", + "rv32i_m/K/src/aes32dsmi-01.S" + }; + + string arch32zkne[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/aes32esi-01.S", + "rv32i_m/K/src/aes32esmi-01.S" + }; + + string arch32zknh[] = '{ + `RISCVARCHTEST, + "rv32i_m/K/src/sha256sig0-01.S", + "rv32i_m/K/src/sha256sig1-01.S", + "rv32i_m/K/src/sha256sum0-01.S", + "rv32i_m/K/src/sha256sum1-01.S", + "rv32i_m/K/src/sha512sig0h-01.S", + "rv32i_m/K/src/sha512sig0l-01.S", + "rv32i_m/K/src/sha512sig1h-01.S", + "rv32i_m/K/src/sha512sig1l-01.S", + "rv32i_m/K/src/sha512sum0r-01.S", + "rv32i_m/K/src/sha512sum1r-01.S" + }; + + string arch32zbkb[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/K/src/pack-01.S", + "rv32i_m/K/src/packh-01.S", + "rv32i_m/K/src/brev8_32-01.S", + "rv32i_m/K/src/zip-01.S", + "rv32i_m/K/src/unzip-01.S" + }; + + string arch64zbkb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/K/src/pack-01.S", + "rv64i_m/K/src/packh-01.S", + "rv64i_m/K/src/packw-01.S", + "rv64i_m/K/src/brev8-01.S" + }; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1752,6 +1824,47 @@ string arch64zbs[] = '{ "rv64i_m/B/src/bseti-01.S" }; +string arch64zbkc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S" +}; + +string arch64zbkx[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/xperm8-01.S", + "rv64i_m/K/src/xperm4-01.S" +}; + +string arch64zknd[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64ds-01.S", + "rv64i_m/K/src/aes64dsm-01.S", + "rv64i_m/K/src/aes64im-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zkne[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/aes64es-01.S", + "rv64i_m/K/src/aes64esm-01.S", + "rv64i_m/K/src/aes64ks1i-01.S", + "rv64i_m/K/src/aes64ks2-01.S" +}; + +string arch64zknh[] = '{ + `RISCVARCHTEST, + "rv64i_m/K/src/sha256sig0-01.S", + "rv64i_m/K/src/sha256sig1-01.S", + "rv64i_m/K/src/sha256sum0-01.S", + "rv64i_m/K/src/sha256sum1-01.S", + "rv64i_m/K/src/sha512sig0-01.S", + "rv64i_m/K/src/sha512sig1-01.S", + "rv64i_m/K/src/sha512sum0-01.S", + "rv64i_m/K/src/sha512sum1-01.S" +}; + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 5450f64df..f5b8ea317 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -131,6 +131,18 @@ class spike(pluginTemplate): self.isa += '_Zbc' if "Zbs" in ispec["ISA"]: self.isa += '_Zbs' + if "Zbkb" in ispec["ISA"]: + self.isa += '_Zbkb' + if "Zbkc" in ispec["ISA"]: + self.isa += '_Zbkc' + if "Zknd" in ispec["ISA"]: + self.isa += '_Zknd' + if "Zkne" in ispec["ISA"]: + self.isa += '_Zkne' + if "Zbkx" in ispec["ISA"]: + self.isa += '_Zbkx' + if "Zknh" in ispec["ISA"]: + self.isa += '_Zknh' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml index 9e9775a9b..ee0aeec11 100644 --- a/tests/riscof/spike/spike_rv32e_isa.yaml +++ b/tests/riscof/spike/spike_rv32e_isa.yaml @@ -1,6 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32EMCZicsr_Zifencei + ISA: RV32EMCZicsr_Zifencei_Zbkc physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index c2c95fbf4..1879440ed 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh +# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 7bbcaf9e5..f7e6b8c73 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,7 +2,7 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64]