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removed unused parameter.

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This commit is contained in:
Ross Thompson 2022-03-11 10:43:54 -06:00
parent 04dd2f0eb5
commit 326ecda060
3 changed files with 7 additions and 6 deletions
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2
pipelined/src/cache/cache.sv vendored
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@ -30,7 +30,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( module cache #(parameter LINELEN, NUMLINES, NUMWAYS) (
input logic clk, input logic clk,
input logic reset, input logic reset,
// cpu side // cpu side

2
pipelined/src/ifu/ifu.sv
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@ -212,7 +212,7 @@ module ifu (
if(CACHE_ENABLED) begin : icache if(CACHE_ENABLED) begin : icache
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0)) .NUMWAYS(`ICACHE_NUMWAYS))
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),

9
pipelined/src/lsu/lsu.sv
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@ -225,14 +225,11 @@ module lsu (
.s(SelUncachedAdr), .y(ReadDataWordMuxM)); .s(SelUncachedAdr), .y(ReadDataWordMuxM));
mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM),
.s(SelUncachedAdr), .y(LSUBusHWDATA)); .s(SelUncachedAdr), .y(LSUBusHWDATA));
mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM),
.d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit),
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
if(CACHE_ENABLED) begin : dcache if(CACHE_ENABLED) begin : dcache
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache( .NUMWAYS(`DCACHE_NUMWAYS)) dcache(
.clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM),
.FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM),
.ByteMask(ByteMaskM), .ByteMask(ByteMaskM),
@ -243,6 +240,10 @@ module lsu (
.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM),
.d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit),
.y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset.
subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache
.clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore,
.ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM));