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Removed more generate statements

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This commit is contained in:
David Harris 2022-01-05 16:25:08 +00:00
parent f04856ee94
commit 32590d484c
20 changed files with 562 additions and 651 deletions
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2
pipelined/fpu-testfloat/FMA/tbgen/tb.sv
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@ -153,7 +153,7 @@ fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZEx
.FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM);
// generate clock
// produce clock
always
begin
clk = 1; #5; clk = 0; #5;

2
pipelined/ppa/ppa.sv
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@ -45,14 +45,12 @@ endmodule
module INVX2(input logic a, output logic y);
generate
if (LIB == SKY130)
sky130_osu_sc_12T_ms__inv_2 inv(a, y);
else if (LIB == SKL90)
scc9gena_inv_2 inv(a, y)
else if (LIB == GF14)
INV_X2N_A10P5PP84TSL_C14(a, y)
endgenerate
endmodule
module driver #(parameter WDITH=1) (

11
pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -72,7 +72,6 @@ module cachereplacementpolicy
assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index;
generate
if(NUMWAYS == 2) begin : TwoWay
assign LRUEn[0] = 1'b0;
@ -125,10 +124,10 @@ module cachereplacementpolicy
assign LRUMask[0] = WayHit[1];
assign LRUMask[1] = WayHit[3];
assign LRUMask[2] = WayHit[3] | WayHit[2];
-----/\----- EXCLUDED -----/\----- */
-----/\----- EXCLUDED -----/\----- */
for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
/* -----\/----- EXCLUDED -----\/-----
assign EncVicWay[1] = LineReplacementBits[2];
@ -137,7 +136,7 @@ module cachereplacementpolicy
onehotdecoder #(2)
waydec(.bin(EncVicWay),
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
-----/\----- EXCLUDED -----/\----- */
-----/\----- EXCLUDED -----/\----- */
end else if (NUMWAYS == 8) begin : EightWay
@ -160,7 +159,7 @@ module cachereplacementpolicy
assign LRUMask[0] = WayHit[0];
for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign EncVicWay[2] = LineReplacementBits[6];
assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2];
@ -173,8 +172,6 @@ module cachereplacementpolicy
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end
endgenerate
endmodule

15
pipelined/src/cache/cacheway.sv vendored
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@ -72,16 +72,13 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
genvar words;
generate
for(words = 0; words < LINELEN/`XLEN; words++) begin : word
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end
endgenerate
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
CacheTagMem(.clk(clk),
@ -123,27 +120,21 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
assign Valid = ValidBits[RAdrD];
generate
// Dirty bits
if(DIRTY_BITS) begin:dirty
always_ff @(posedge clk) begin
if (reset)
DirtyBits <= {NUMLINES{1'b0}};
if (reset) DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
end
always_ff @(posedge clk) begin
SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty;
end
assign Dirty = DirtyBits[RAdrD];
end else begin:dirty
assign Dirty = 1'b0;
end
endgenerate
endmodule // DCacheMemWay

7
pipelined/src/cache/dcache.sv vendored
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@ -143,7 +143,6 @@ module dcache #(parameter integer LINELEN,
.WayHit, .VictimDirtyWay, .VictimTagWay,
.InvalidateAll(1'b0));
generate
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset,
@ -155,7 +154,6 @@ module dcache #(parameter integer LINELEN,
end else begin:vict
assign VictimWay = 1'b1; // one hot.
end
endgenerate
assign CacheHit = | WayHit;
assign VictimDirty = | VictimDirtyWay;
@ -172,11 +170,8 @@ module dcache #(parameter integer LINELEN,
// easily build a variable input mux.
// *** consider using a limited range shift to do this final muxing.
genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
for (index = 0; index < WORDSPERLINE; index++)
assign ReadDataLineSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
end
endgenerate
// variable input mux

7
pipelined/src/cache/icache.sv vendored
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@ -114,7 +114,6 @@ module icache #(parameter integer LINELEN,
.VictimDirtyWay(), .VictimTagWay(),
.InvalidateAll(InvalidateICacheM));
generate
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset,
@ -126,7 +125,6 @@ module icache #(parameter integer LINELEN,
end else begin:vict
assign VictimWay = 1'b1; // one hot.
end
endgenerate
assign hit = | WayHit;
@ -136,12 +134,9 @@ module icache #(parameter integer LINELEN,
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
genvar index;
generate
for(index = 0; index < LINELEN / 16 - 1; index++) begin:readlinesetsmux
for(index = 0; index < LINELEN / 16 - 1; index++)
assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)];
end
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadLineF[LINELEN-1:LINELEN-16]};
endgenerate
assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(LINELEN / 32) + 1 : 1]];

3
pipelined/src/ebu/amoalu.sv
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@ -56,7 +56,6 @@ module amoalu (
endcase
// sign extend if necessary
generate
if (`XLEN == 32) begin:sext
assign a = srca;
assign b = srcb;
@ -74,7 +73,5 @@ module amoalu (
result = y;
end
end
endgenerate
endmodule

4
pipelined/src/fpu/cvtfp.sv
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@ -157,7 +157,7 @@ module cvtfp (
// Result Selection
///////////////////////////////////////////////////////////////////////////////
generate if(`IEEE754) begin
if(`IEEE754) begin
// select the double to single precision result
assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} :
Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} :
@ -178,8 +178,6 @@ module cvtfp (
// select the final result based on the opperation
assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}};
end
endgenerate
endmodule // fpadd

2
pipelined/src/fpu/divconv_pipe.sv
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@ -185,11 +185,9 @@ module csa #(parameter WIDTH=8) (
/*
logic [WIDTH:0] carry_temp;
genvar i;
generate
for (i=0;i<WIDTH;i=i+1) begin : genbit
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
end
endgenerate
assign carry = {carry_temp[WIDTH-1:1], 1'b0};
*/
endmodule // csa

6
pipelined/src/fpu/fcvt.sv
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@ -173,7 +173,7 @@ module fcvt (
// - only set invalid flag for out-of-range vales
// - set inexact if in representable range and not exact
generate if(`IEEE754) begin // checks before rounding
if(`IEEE754) begin // checks before rounding
assign Invalid = (Of | Uf)&FOpCtrlE[0];
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
@ -182,10 +182,6 @@ module fcvt (
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
end
endgenerate
endmodule // fpadd

7
pipelined/src/fpu/fma.sv
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@ -814,20 +814,17 @@ module resultselect(
);
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
generate
if(`IEEE754) begin:nan
if(`IEEE754) begin
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
end else begin:nan
end else begin
assign XNaNResult = FmtM ? {1'b0, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpM[7:0], 1'b1, 22'b0};
assign YNaNResult = FmtM ? {1'b0, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpM[7:0], 1'b1, 22'b0};
assign ZNaNResult = FmtM ? {1'b0, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, ZExpM[7:0], 1'b1, 22'b0};
assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, 1'b0, 8'hff, 1'b1, 22'b0};
end
endgenerate
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :

2
pipelined/src/ieu/shifter.sv
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@ -39,7 +39,6 @@ module shifter (
// For RV64, 32 and 64-bit shifts are needed, with sign extension.
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
// generate
if (`XLEN==32) begin:shifter // RV32
always_comb // funnel mux
if (Right)
@ -62,7 +61,6 @@ module shifter (
end
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
end
// endgenerate
// opposite offset for right shfits
assign offset = Right ? amttrunc : ~amttrunc;

2
pipelined/src/ifu/bpred.sv
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@ -70,7 +70,6 @@ module bpred
// Part 1 branch direction prediction
generate
if (`BPTYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk(clk),
.reset(reset),
@ -137,7 +136,6 @@ module bpred
.PCSrcE(PCSrcE),
.UpdatePrediction(UpdateBPPredE));
end
endgenerate
// this predictor will have two pieces of data,

16
pipelined/src/ifu/ifu.sv
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@ -111,7 +111,6 @@ module ifu (
logic [31:0] PostSpillInstrRawF;
generate
if(`C_SUPPORTED) begin : SpillSupport
logic [`XLEN-1:0] PCFp2;
logic Spill;
@ -166,7 +165,6 @@ module ifu (
assign SelNextSpill = 0;
assign PostSpillInstrRawF = InstrRawF;
end
endgenerate
assign PCFExt = {2'b00, PCFMux};
@ -235,10 +233,6 @@ module ifu (
logic [`PA_BITS-1:0] ICacheBusAdr;
logic SelUncachedAdr;
generate
if(`MEM_ICACHE) begin : icache
logic [1:0] IfuRWF;
assign IfuRWF = CacheableF ? 2'b10 : 2'b00;
@ -280,17 +274,13 @@ module ifu (
.InvalidateCacheM(InvalidateICacheM));
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
end else begin : passthrough
end else begin
assign ICacheFetchLine = 0;
assign ICacheBusAdr = 0;
//assign CompressedF = 0; //?
assign ICacheStallF = 0;
assign FinalInstrRawF = 0;
end
endgenerate
// select between dcache and direct from the BUS. Always selected if no dcache.
// handled in the busfsm.
@ -301,14 +291,12 @@ module ifu (
// always present
genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk),
.en(IfuBusAck & IfuBusRead & (index == WordCount)),
.d(IfuBusHRDATA),
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end
endgenerate
assign LocalIfuBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr;
@ -382,7 +370,6 @@ module ifu (
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
// branch and jump predictor
generate
if (`BPRED_ENABLED == 1) begin : bpred
bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE,
@ -400,7 +387,6 @@ module ifu (
assign RASPredPCWrongE = 1'b0;
assign BPPredClassNonCFIWrongE = 1'b0;
end
endgenerate
// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
assign PCCorrectE = PCSrcE ? IEUAdrE : PCLinkE;

10
pipelined/src/ifu/localHistoryPredictor.sv
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@ -66,16 +66,10 @@ module localHistoryPredictor
// .BitWEN1(2'b11));
genvar index;
generate
for (index = 0; index < 2**m; index = index +1) begin:localhist
flopenr #(k) LocalHistoryRegister(.clk(clk),
.reset(reset),
.en(UpdateEN & (index == UpdatePCIndex)),
.d(LHRFNext),
.q(LHRNextF[index]));
flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
.d(LHRFNext), .q(LHRNextF[index]));
end
endgenerate
// need to forward when updating to the same address as reading.
// first we compare to see if the update and lookup addreses are the same

18
pipelined/src/lsu/lsu.sv
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@ -120,7 +120,6 @@ module lsu
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
assign IEUAdrExtM = {2'b00, IEUAdrM};
generate
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
logic AnyCPUReqM;
logic [`PA_BITS-1:0] HPTWAdr;
@ -188,7 +187,6 @@ module lsu
assign DTLBLoadPageFaultM = 1'b0;
assign DTLBStorePageFaultM = 1'b0;
end
endgenerate
// **** look into this confusing signal.
// This signal is confusing. CommittedM tells the CPU's trap unit the current instruction
@ -200,7 +198,6 @@ module lsu
// to flush the memory operation at that time.
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
generate
if(`ZICSR_SUPPORTED == 1) begin : dmmu
logic DataMisalignedM;
@ -249,14 +246,10 @@ module lsu
assign LoadMisalignedFaultM = 0;
assign StoreMisalignedFaultM = 0;
end
endgenerate
assign LSUStall = DCacheStall | InterlockStall | BusStall;
// Move generate from lrsc to outside this module.
// use PreLsu as prefix for lrsc
generate
if (`A_SUPPORTED) begin:lrsc
assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM,
@ -265,7 +258,6 @@ module lsu
assign SquashSCW = 0;
assign LsuRWM = PreLsuRWM;
end
endgenerate
// conditional
@ -304,7 +296,6 @@ module lsu
logic SelUncachedAdr;
generate
if(`MEM_DCACHE) begin : dcache
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
@ -327,7 +318,6 @@ module lsu
assign DCacheBusAdr = 0;
assign ReadDataLineSetsM[0] = 0;
end
endgenerate
// select between dcache and direct from the BUS. Always selected if no dcache.
@ -343,7 +333,6 @@ module lsu
.Funct3M(LsuFunct3M),
.ReadDataM);
generate
if (`A_SUPPORTED) begin : amo
logic [`XLEN-1:0] AMOResult;
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]),
@ -351,7 +340,6 @@ module lsu
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM);
end else
assign FinalAMOWriteDataM = WriteDataM;
endgenerate
// this might only get instantiated if there is a dcache or dtim.
// There is a copy in the ebu.
@ -368,24 +356,20 @@ module lsu
logic [LOGWPL-1:0] WordCount;
genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk),
flopen #(`XLEN) fb(.clk,
.en(LsuBusAck & LsuBusRead & (index == WordCount)),
.d(LsuBusHRDATA),
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end
endgenerate
assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ;
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
assign PreLsuBusHWDATA = ReadDataLineSetsM[WordCount];
assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work.
generate
if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010;
else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011;
endgenerate;
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine,

10
pipelined/src/uncore/ram.sv
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@ -49,11 +49,9 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic memwrite;
logic [3:0] busycount;
generate
if(`FPGA) begin:ram
initial begin
//$readmemh(PRELOAD, RAM);
// FPGA only
RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
@ -98,7 +96,6 @@ module ram #(parameter BASE=0, RANGE = 65535) (
RAM[41] = 64'h0000808210a7a023;
end // initial begin
end // if (FPGA)
endgenerate
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
@ -144,26 +141,23 @@ module ram #(parameter BASE=0, RANGE = 65535) (
-----/\----- EXCLUDED -----/\----- */
/* verilator lint_off WIDTH */
generate
if (`XLEN == 64) begin:ramrd
if (`XLEN == 64) begin:ramrw
always_ff @(posedge HCLK) begin
HWADDR <= #1 A;
HREADRam0 <= #1 RAM[A[31:3]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA;
end
end else begin
always_ff @(posedge HCLK) begin:ramrd
always_ff @(posedge HCLK) begin:ramrw
HWADDR <= #1 A;
HREADRam0 <= #1 RAM[A[31:2]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA;
end
end
endgenerate
/* verilator lint_on WIDTH */
//assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz;
// *** Ross Thompson: removed tristate as fpga synthesis removes.
assign HREADRam = HREADRam0;
endmodule

3
pipelined/src/uncore/subwordwrite.sv
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@ -35,7 +35,6 @@ module subwordwrite (
logic [`XLEN-1:0] WriteDataSubwordDuplicated;
generate
if (`XLEN == 64) begin:sww
logic [7:0] ByteMaskM;
// Compute write mask
@ -104,6 +103,4 @@ module subwordwrite (
end
end
endgenerate
endmodule

2
pipelined/src/uncore/uart.sv
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@ -54,7 +54,6 @@ module uart (
assign HRESPUART = 0; // OK
assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
generate
if (`XLEN == 64) begin:uart
always_comb begin
HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
@ -80,7 +79,6 @@ module uart (
endcase
end
end
endgenerate
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
// *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals

2
pipelined/testbench/testbench-linux.sv
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@ -36,7 +36,7 @@
// 4: print memory accesses whenever they happen
// 5: print everything
module testbench();
module testbench;
///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////// CONFIG ////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////