From 660da5545122715fb3e8eabf8b4c8497f6592274 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 8 Aug 2024 13:50:11 -0500 Subject: [PATCH 1/2] Turned off RVVI by default. --- fpga/src/fpgaTopArtyA7.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index fa2aa59a9..9133baa25 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -28,7 +28,7 @@ import cvw::*; -module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1) +module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (input default_100mhz_clk, (* mark_debug = "true" *) input resetn, input south_reset, From 6e8c210e09b604e7c950777ed0f076d896e81a66 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 8 Aug 2024 13:52:53 -0500 Subject: [PATCH 2/2] Commented out rvvi debug probes in wally.tcl. --- fpga/generator/wally.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index b2e1e359e..a5e60a3d5 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -89,8 +89,8 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - #source ../constraints/small-debug.xdc - source ../constraints/small-debug-rvvi.xdc + source ../constraints/small-debug.xdc + #source ../constraints/small-debug-rvvi.xdc } else { source ../constraints/vcu-small-debug.xdc }