diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 2c2ee7b4e..fa3eab16f 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -47,7 +47,7 @@ module ifu ( output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU - output logic [`XLEN-1:0] PCFSpill, // PCF with possible + 2 to handle spill to HPTW + output logic [`XLEN-1:0] PCSpillF, // PCF with possible + 2 to handle spill to HPTW // Execute output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic PCSrcE, // Executation stage branch is taken @@ -136,7 +136,7 @@ module ifu ( logic CacheCommittedF; // I$ memory operation started, delay interrupts logic SelIROM; // PMA indicates instruction address is in the IROM - assign PCFExt = {2'b00, PCFSpill}; + assign PCFExt = {2'b00, PCSpillF}; ///////////////////////////////////////////////////////////////////////////////////////////// // Spill Support @@ -144,10 +144,10 @@ module ifu ( if(`C_SUPPORTED) begin : Spill spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, - .InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); + .InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCSpillF, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCNextFSpill = PCNextF; - assign PCFSpill = PCF; + assign PCSpillF = PCF; assign PostSpillInstrRawF = InstrRawF; assign {SelNextSpillF, CompressedF} = 0; end diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 4d971cbae..d4e85faf0 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -44,7 +44,7 @@ module spill #( input logic ITLBMissF, // ITLB miss, ignore memory request input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) output logic [`XLEN-1:0] PCNextFSpill, // The next PCF for one of the two memory addresses of the spill - output logic [`XLEN-1:0] PCFSpill, // PCF for one of the two memory addresses of the spill + output logic [`XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill output logic SelNextSpillF, // During the transition between the two spill operations, the IFU should stall the pipeline output logic [31:0] PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction output logic CompressedF); // The fetched instruction is compressed @@ -69,7 +69,7 @@ module spill #( // select between PCNextF and PCF+2 mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~FlushD), .y(PCNextFSpill)); // select between PCF and PCF+2 - mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); + mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF)); //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9f11f7007..91ad694e9 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -80,7 +80,7 @@ module lsu ( input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege input logic [1:0] STATUS_MPP, // Machine previous privilege mode - input logic [`XLEN-1:0] PCFSpill, // Fetch PC + input logic [`XLEN-1:0] PCSpillF, // Fetch PC input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB @@ -152,7 +152,7 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, - .FlushW, .DCacheStallM, .SATP_REGW, .PCFSpill, + .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index f2df8ea92..aac0a606c 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -34,7 +34,7 @@ module hptw ( input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table - input logic [`XLEN-1:0] PCFSpill, // addresses to translate + input logic [`XLEN-1:0] PCSpillF, // addresses to translate input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate input logic [1:0] MemRWM, AtomicM, // system status @@ -111,7 +111,7 @@ module hptw ( assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF); // Determine which address to translate - mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); + mux2 #(`XLEN) vadrmux(PCSpillF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 6c2d5816b..a226c7839 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -63,7 +63,7 @@ module wallypipelinedcore ( logic [2:0] Funct3E; logic [31:0] InstrD; logic [31:0] InstrM; - logic [`XLEN-1:0] PCFSpill, PCE, PCLinkE; + logic [`XLEN-1:0] PCSpillF, PCE, PCLinkE; logic [`XLEN-1:0] PCM; logic [`XLEN-1:0] CSRReadValW, MDUResultW; logic [`XLEN-1:0] UnalignedPCNextF, PC2NextF; @@ -170,7 +170,7 @@ module wallypipelinedcore ( .InstrValidM, .InstrValidE, .InstrValidD, .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF, // Fetch - .HRDATA, .PCFSpill, .IFUHADDR, .PC2NextF, + .HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, // Execute @@ -241,7 +241,7 @@ module wallypipelinedcore ( .StoreAmoMisalignedFaultM, // connects to privilege .StoreAmoAccessFaultM, // connects to privilege .InstrUpdateDAF, - .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, + .PCSpillF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .LSUStallM); if(`BUS_SUPPORTED) begin : ebu