diff --git a/src/debug/dm.sv b/src/debug/dm.sv
index c5de29a53..b6c339fc8 100644
--- a/src/debug/dm.sv
+++ b/src/debug/dm.sv
@@ -25,6 +25,20 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+// TODO List:
+// fix CSR scanning
+// determine config/permissions of all CSRs
+// DCSR and DPC should exist even when not privileged_supported
+// test all combinations of XLEN/FLEN
+// improve halting / implement "debug mode"
+//// Debug Mode = M-mode with stalled pipe
+// Flush pipe with NOPs during halt?
+// implement better steps
+// Alias DPC to PCF/PCNextF?
+
+// (stretch) add system bus access?
+
+
 module dm import cvw::*; #(parameter cvw_t P) (
   input  logic            clk, 
   input  logic            rst,
diff --git a/src/debug/hartcontrol.sv b/src/debug/hartcontrol.sv
index 5f16efa68..9dccb074d 100644
--- a/src/debug/hartcontrol.sv
+++ b/src/debug/hartcontrol.sv
@@ -27,6 +27,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+// Note: This module controls all of the per-hart debug state.
+// In a multihart system, this module should be instantiated under wallypipelinedcore
+
 module hartcontrol(
   input  logic clk, rst,
   input  logic NdmReset,     // Triggers HaltOnReset behavior
diff --git a/src/debug/rad.sv b/src/debug/rad.sv
index 99801fda3..5363fdd7e 100644
--- a/src/debug/rad.sv
+++ b/src/debug/rad.sv
@@ -41,7 +41,6 @@ module rad import cvw::*; #(parameter cvw_t P) (
 );
   `include "debug.vh"
 
-  localparam MISALEN = P.ZICSR_SUPPORTED ? P.XLEN : 0;
   localparam TRAPMLEN = P.ZICSR_SUPPORTED ? 1 : 0;
   localparam PCMLEN = (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) ? P.XLEN : 0;
   localparam INSTRMLEN = (P.ZICSR_SUPPORTED | P.A_SUPPORTED) ? 32 : 0;
@@ -50,13 +49,12 @@ module rad import cvw::*; #(parameter cvw_t P) (
   localparam WRITEDATAMLEN = P.XLEN;
   localparam IEUADRMLEN = P.XLEN;
   localparam READDATAMLEN = P.LLEN;
-  localparam SCANCHAINLEN = P.XLEN - 1 
-    + MISALEN + TRAPMLEN + PCMLEN + INSTRMLEN
+  localparam SCANCHAINLEN = P.LLEN - 1 
+    + TRAPMLEN + PCMLEN + INSTRMLEN
     + MEMRWMLEN + INSTRVALIDMLEN + WRITEDATAMLEN
     + IEUADRMLEN + READDATAMLEN;
 
-  localparam MISA_IDX = MISALEN;
-  localparam TRAPM_IDX = MISA_IDX + TRAPMLEN;
+  localparam TRAPM_IDX = TRAPMLEN;
   localparam PCM_IDX = TRAPM_IDX + PCMLEN;
   localparam INSTRM_IDX = PCM_IDX + INSTRMLEN;
   localparam MEMRWM_IDX = INSTRM_IDX + MEMRWMLEN;
@@ -74,6 +72,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
   always_comb begin
     InvalidRegNo = 0;
     RegReadOnly = 0;
+    CSRegNo = 0;
     GPRegNo = 0;
     FPRegNo = 0;
     case (Regno) inside
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
index 18892525b..544eae317 100644
--- a/src/ieu/datapath.sv
+++ b/src/ieu/datapath.sv
@@ -111,7 +111,6 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
   logic [P.XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
   // Debug signals
-  logic              DSCR;
   logic [P.XLEN-1:0] DebugGPRWriteD;
 
   // Decode stage