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Removed unused UARCH configuration entries

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This commit is contained in:
David Harris 2023-01-06 05:11:14 -08:00
parent 34f8f2c47a
commit 31bffc305b
11 changed files with 4 additions and 50 deletions
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5
pipelined/config/buildroot/wally-config.vh
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@ -43,11 +43,6 @@
`define COUNTERS 32 `define COUNTERS 32
`define DESIGN_COMPILER 0 `define DESIGN_COMPILER 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1

5
pipelined/config/fpga/wally-config.vh
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@ -45,11 +45,6 @@
`define COUNTERS 32 `define COUNTERS 32
`define DESIGN_COMPILER 0 `define DESIGN_COMPILER 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1

4
pipelined/config/rv32e/wally-config.vh
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@ -45,10 +45,6 @@
`define ZICOUNTERS_SUPPORTED 0 `define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 0 `define DCACHE 0

6
pipelined/config/rv32gc/wally-config.vh
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@ -44,10 +44,6 @@
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1
@ -75,7 +71,7 @@
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 16
// Address space // Address space
`define RESET_VECTOR 32'h80000000 `define RESET_VECTOR 32'h80000000

4
pipelined/config/rv32i/wally-config.vh
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@ -45,10 +45,6 @@
`define ZICOUNTERS_SUPPORTED 0 `define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 0 `define BUS 0
`define DCACHE 0 `define DCACHE 0

4
pipelined/config/rv32ic/wally-config.vh
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@ -44,10 +44,6 @@
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 0 `define DCACHE 0

5
pipelined/config/rv64BP/wally-config.vh
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@ -38,7 +38,6 @@
// IEEE 754 compliance // IEEE 754 compliance
`define IEEE754 0 `define IEEE754 0
//`define MISA (32'h00000105)
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
`define ZICSR_SUPPORTED 1 `define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1
@ -46,10 +45,6 @@
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1

5
pipelined/config/rv64fpquad/wally-config.vh
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@ -45,11 +45,6 @@
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 1 `define ZFH_SUPPORTED 1
/// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1

7
pipelined/config/rv64gc/wally-config.vh
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@ -45,11 +45,6 @@
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
/// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 1
`define DCACHE 1 `define DCACHE 1
@ -77,7 +72,7 @@
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 16
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000

5
pipelined/config/rv64i/wally-config.vh
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@ -45,11 +45,6 @@
`define ZICOUNTERS_SUPPORTED 0 `define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features
`define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 0 `define BUS 0
`define DCACHE 0 `define DCACHE 0

4
pipelined/config/shared/wally-shared.vh
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@ -23,8 +23,8 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// division constants // division constants
`define RADIX 32'h2 `define RADIX 32'h4
`define DIVCOPIES 32'h1 `define DIVCOPIES 32'h2
// Memory synthesis configuration // Memory synthesis configuration
`define USE_SRAM 0 `define USE_SRAM 0